1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NGE_CHIP_H 28 #define _SYS_NGE_CHIP_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "nge.h" 35 36 #define VENDOR_ID_NVIDIA 0x10de 37 38 #define DEVICE_ID_MCP04_37 0x37 39 #define DEVICE_ID_MCP04_38 0x38 40 #define DEVICE_ID_CK804_56 0x56 41 #define DEVICE_ID_CK804_57 0x57 42 #define DEVICE_ID_MCP51_269 0x269 43 #define DEVICE_ID_MCP51_268 0x268 44 #define DEVICE_ID_MCP55_373 0x373 45 #define DEVICE_ID_MCP55_372 0x372 46 #define DEVICE_ID_MCP61_3EE 0x3ee 47 #define DEVICE_ID_MCP61_3EF 0x3ef 48 #define DEVICE_ID_NF3_E6 0xe6 49 #define DEVICE_ID_NF3_DF 0xdf 50 51 /* Private PCI configuration register for bus config of ck804/mcp55 */ 52 #define PCI_CONF_HT_INTERNAL 0x4c 53 54 typedef union _nge_interbus_conf { 55 uint32_t conf_val; 56 struct { 57 uint32_t unit_id:5; 58 uint32_t resv5_23:19; 59 uint32_t aux_val:3; 60 uint32_t resv27:1; 61 uint32_t msi_off:1; 62 uint32_t msix_off:1; /* mcp55 only */ 63 uint32_t resv30_31:2; 64 } conf_bits; 65 } nge_interbus_conf; 66 67 /* Private PCI configuration register for MSI mask of mcp55 */ 68 #define PCI_CONF_HT_MSI_MASK 0x60 69 70 typedef union _nge_msi_mask_conf { 71 uint32_t msi_mask_conf_val; 72 struct { 73 uint32_t vec0_off:1; 74 uint32_t vec1_off:1; 75 uint32_t vec2_off:1; 76 uint32_t vec3_off:1; 77 uint32_t vec4_off:1; 78 uint32_t vec5_off:1; 79 uint32_t vec6_off:1; 80 uint32_t vec7_off:1; 81 uint32_t resv8_31:24; 82 } msi_mask_bits; 83 } nge_msi_mask_conf; 84 85 /* Private PCI configuration register for MSI map capability of mcp55 */ 86 #define PCI_CONF_HT_MSI_MAP_CAP 0x6c 87 88 typedef union _nge_msi_map_cap_conf { 89 uint32_t msi_map_cap_conf_val; 90 struct { 91 uint32_t cap_id:8; 92 uint32_t next_ptr:8; 93 uint32_t map_en:1; 94 uint32_t map_fixed:1; 95 uint32_t resv18_26:9; 96 uint32_t cap_type:5; 97 } map_cap_conf_bits; 98 } nge_msi_map_cap_conf; 99 100 /* 101 * Master interrupt 102 */ 103 #define NGE_INTR_SRC 0x000 104 #define INTR_SRC_ALL 0x00007fff 105 typedef union _nge_intr_src { 106 uint32_t intr_val; 107 struct { 108 uint32_t reint:1; 109 uint32_t rcint:1; 110 uint32_t miss:1; 111 uint32_t teint:1; 112 uint32_t tcint:1; 113 uint32_t stint:1; 114 uint32_t mint:1; 115 uint32_t rfint:1; 116 uint32_t tfint:1; 117 uint32_t feint:1; 118 uint32_t resv10:1; 119 uint32_t resv11:1; 120 uint32_t resv12:1; 121 uint32_t resv13:1; 122 uint32_t phyint:1; 123 uint32_t resv15_31:17; 124 } int_bits; 125 } nge_intr_src; 126 127 /* 128 * Master interrupt Mask 129 */ 130 #define NGE_INTR_MASK 0x004 131 #define NGE_INTR_ALL_EN 0x00007fff 132 typedef union _nge_intr_mask { 133 uint32_t mask_val; 134 struct { 135 uint32_t reint:1; 136 uint32_t rcint:1; 137 uint32_t miss:1; 138 uint32_t teint:1; 139 uint32_t tcint:1; 140 uint32_t stint:1; 141 uint32_t mint:1; 142 uint32_t rfint:1; 143 uint32_t tfint:1; 144 uint32_t feint:1; 145 uint32_t resv10:1; 146 uint32_t resv11:1; 147 uint32_t resv12:1; 148 uint32_t resv13:1; 149 uint32_t phyint:1; 150 uint32_t resv15_31:17; 151 } mask_bits; 152 } nge_intr_mask; 153 154 /* 155 * Software timer control register 156 */ 157 #define NGE_SWTR_CNTL 0x008 158 typedef union _nge_swtr_cntl { 159 uint8_t ctrl_val; 160 struct { 161 uint8_t stren:1; 162 uint8_t sten:1; 163 uint8_t resv2_7:6; 164 } cntl_bits; 165 } nge_swtr_cntl; 166 167 /* 168 * Software Timer Interval 169 */ 170 #define NGE_SWTR_ITC 0x00c 171 172 /* Default timer interval, 97 would mean 1 ms */ 173 #define SWTR_ITC 0x8 174 typedef union _nge_itc { 175 uint32_t itc_val; 176 struct { 177 uint32_t sw_intv:16; 178 uint32_t sw_cur_val:16; 179 } itc_bits; 180 } nge_itc; 181 182 /* 183 * Fatal error register 184 */ 185 #define NGE_REG010 0x010 186 typedef union _nge_reg010 { 187 uint32_t reg010_val; 188 struct { 189 uint32_t resv0:1; 190 uint32_t resv1:1; 191 uint32_t resv2:1; 192 uint32_t resv3:1; 193 uint32_t resv4:1; 194 uint32_t resv5:1; 195 uint32_t resv6:1; 196 uint32_t resv7:1; 197 uint32_t resv8:1; 198 uint32_t resv9:1; 199 uint32_t resv10:1; 200 uint32_t resv11_31:21; 201 } reg010_bits; 202 } nge_reg010; 203 204 /* 205 * MSI vector map register 0 206 */ 207 #define NGE_MSI_MAP0 0x020 208 typedef union _nge_msi_map0_vec { 209 uint32_t msi_map0_val; 210 struct { 211 uint32_t reint_vec:4; 212 uint32_t rcint_vec:4; 213 uint32_t miss_vec:4; 214 uint32_t teint_vec:4; 215 uint32_t tcint_vec:4; 216 uint32_t stint_vec:4; 217 uint32_t mint_vec:4; 218 uint32_t rfint_vec:4; 219 } vecs_bits; 220 } nge_msi_map0_vec; 221 222 /* 223 * MSI vector map register 1 224 */ 225 #define NGE_MSI_MAP1 0x024 226 typedef union _nge_msi_map1_vec { 227 uint32_t msi_map1_val; 228 struct { 229 uint32_t tfint_vec:4; 230 uint32_t feint_vec:4; 231 uint32_t resv8_11:4; 232 uint32_t resv12_15:4; 233 uint32_t resv16_19:4; 234 uint32_t resv20_23:4; 235 uint32_t resv24_31:8; 236 } vecs_bits; 237 } nge_msi_map1_vec; 238 239 240 /* 241 * MSI vector map register 2 242 */ 243 #define NGE_MSI_MAP2 0x028 244 245 /* 246 * MSI vector map register 2 247 */ 248 #define NGE_MSI_MAP3 0x02c 249 250 /* 251 * MSI mask register for mcp55 252 */ 253 #define NGE_MSI_MASK 0x30 254 typedef union _nge_msi_mask { 255 uint32_t msi_mask_val; 256 struct { 257 uint32_t vec0:1; 258 uint32_t vec1:1; 259 uint32_t vec2:1; 260 uint32_t vec3:1; 261 uint32_t vec4:1; 262 uint32_t vec5:1; 263 uint32_t vec6:1; 264 uint32_t vec7:1; 265 uint32_t resv8_31:24; 266 }msi_msk_bits; 267 }nge_msi_mask; 268 269 /* 270 * Software misc register for mcp51 271 */ 272 #define NGE_SOFT_MISC 0x034 273 typedef union _nge_soft_misc { 274 uint32_t misc_val; 275 struct { 276 uint32_t rx_clk_vx_rst:1; 277 uint32_t tx_clk_vx_rst:1; 278 uint32_t clk12m_vx_rst:1; 279 uint32_t fpci_clk_vx_rst:1; 280 uint32_t rx_clk_vc_rst:1; 281 uint32_t tx_clk_vc_rst:1; 282 uint32_t fs_clk_vc_rst:1; 283 uint32_t rst_ex_m2pintf:1; 284 uint32_t resv8_31:24; 285 } misc_bits; 286 } nge_soft_misc; 287 288 /* 289 * DMA configuration 290 */ 291 #define NGE_DMA_CFG 0x040 292 typedef union _nge_dma_cfg { 293 uint32_t cfg_val; 294 struct { 295 uint32_t tx_start_pri:3; 296 uint32_t tx_start_pri_flag:1; 297 uint32_t tx_prd_rpri:3; 298 uint32_t tx_prd_rpri_flag:1; 299 uint32_t tx_prd_wpri:3; 300 uint32_t tx_prd_wpri_flag:1; 301 uint32_t rx_start_pri:3; 302 uint32_t rx_start_pri_flag:1; 303 uint32_t rx_prd_rpri:3; 304 uint32_t rx_prd_rpri_flag:1; 305 uint32_t rx_prd_wpri:3; 306 uint32_t rx_prd_wpri_flag:1; 307 uint32_t dma_max_pri:3; 308 uint32_t dma_wrr_disable:1; 309 uint32_t dma_pri_disable:1; 310 } cfg_bits; 311 } nge_dma_cfg; 312 313 /* 314 * Request DMA configuration 315 */ 316 #define NGE_DMA_RCFG 0x044 317 typedef union _nge_dma_rcfg { 318 uint32_t dma_rcfg_val; 319 struct { 320 uint32_t tx_prd_coh_state:2; 321 uint32_t tx_data_coh_state:2; 322 uint32_t rx_prd_coh_state:2; 323 uint32_t rx_data_coh_state:2; 324 uint32_t max_roffset:5; 325 uint32_t resv13_31:19; 326 } rcfg_bis; 327 } nge_dma_rcfg; 328 329 /* 330 * Hot DMA configuration 331 */ 332 #define NGE_DMA_HOT_CFG 0x048 333 typedef union _nge_dma_hcfg { 334 uint32_t dma_hcfg_val; 335 struct { 336 uint32_t resv0_3:4; 337 uint32_t noti_wstart_pri:3; 338 uint32_t noti_wstart_pri_flag:1; 339 uint32_t cmd_rstart_pri:3; 340 uint32_t cmd_rstart_pri_flag:1; 341 uint32_t cmd_wstart_pri:3; 342 uint32_t cmd_wstart_pri_flag:1; 343 uint32_t resv16_31:16; 344 } hcfg_bits; 345 } nge_dma_hcfg; 346 347 /* 348 * PMU control register 0 for mcp51 349 */ 350 #define NGE_PMU_CNTL0 0x060 351 #define NGE_PMU_CORE_SPD10_BUSY 0x8 352 #define NGE_PMU_CORE_SPD10_IDLE 0xB 353 #define NGE_PMU_CORE_SPD100_BUSY 0x4 354 #define NGE_PMU_CORE_SPD100_IDLE 0x7 355 #define NGE_PMU_CORE_SPD1000_BUSY 0x0 356 #define NGE_PMU_CORE_SPD1000_IDLE 0x3 357 358 typedef union _nge_pmu_cntl0 { 359 uint32_t cntl0_val; 360 struct { 361 uint32_t core_spd10_fp:4; 362 uint32_t core_spd10_idle:4; 363 uint32_t core_spd100_fp:4; 364 uint32_t core_spd100_idle:4; 365 uint32_t core_spd1000_fp:4; 366 uint32_t core_spd1000_idle:4; 367 uint32_t core_sts_cur:8; 368 } cntl0_bits; 369 } nge_pmu_cntl0; 370 371 /* 372 * PMU control register 1 for mcp51 373 */ 374 #define NGE_PMU_CNTL1 0x064 375 typedef union _nge_pmu_cntl1 { 376 uint32_t cntl1_val; 377 struct { 378 uint32_t dev_fp:4; 379 uint32_t dev_idle:4; 380 uint32_t resv8_27:20; 381 uint32_t dev_sts_cur:4; 382 } cntl1_bits; 383 } nge_pmu_cntl1; 384 385 /* 386 * PMU control register 2 for mcp51 387 */ 388 #define NGE_PMU_CNTL2 0x068 389 typedef union _nge_pmu_cntl2 { 390 uint32_t cntl2_val; 391 struct { 392 uint32_t core_override:4; 393 uint32_t resv4_7:4; 394 uint32_t dev_override:4; 395 uint32_t resv12_15:4; 396 uint32_t core_override_en:1; 397 uint32_t dev_override_en:1; 398 uint32_t core_enable:1; 399 uint32_t dev_enable:1; 400 uint32_t rx_wake_dis:1; 401 uint32_t cidle_timer:1; 402 uint32_t didle_timer:1; 403 uint32_t resv23_31:9; 404 } cntl2_bits; 405 } nge_pmu_cntl2; 406 407 /* 408 * PMU core idle limit register for mcp51 409 */ 410 #define NGE_PMU_CIDLE_LIMIT 0x06c 411 #define NGE_PMU_CIDLE_LIMIT_DEF 0xffff 412 413 /* 414 * PMU device idle limit register for mcp51 415 */ 416 #define NGE_PMU_DIDLE_LIMIT 0x070 417 #define NGE_PMU_DIDLE_LIMIT_DEF 0xffff 418 419 /* 420 * PMU core idle count value register for mcp51 421 */ 422 #define NGE_PMU_CIDLE_COUNT 0x074 423 #define NGE_PMU_CIDEL_COUNT_DEF 0xffff 424 425 /* 426 * PMU device idle count value register for mcp51 427 */ 428 #define NGE_PMU_DIDLE_COUNT 0x078 429 #define NGE_PMU_DIDEL_COUNT_DEF 0xffff 430 431 /* 432 * Transmit control 433 */ 434 #define NGE_TX_CNTL 0x080 435 typedef union _nge_tx_cntl { 436 uint32_t cntl_val; 437 struct { 438 uint32_t paen:1; /* only for mcp55, otherwise reserve */ 439 uint32_t resv1:1; 440 uint32_t retry_en:1; 441 uint32_t pad_en:1; 442 uint32_t fappend_en:1; 443 uint32_t two_def_en:1; 444 uint32_t resv6_7:2; 445 uint32_t max_retry:4; 446 uint32_t burst_en:1; 447 uint32_t resv13_15:3; 448 uint32_t retry_emask:1; 449 uint32_t exdef_mask:1; 450 uint32_t def_mask:1; 451 uint32_t lcar_mask:1; 452 uint32_t tlcol_mask:1; 453 uint32_t uflo_err_mask:1; 454 uint32_t resv22_23:2; 455 uint32_t jam_seq_en:1; 456 uint32_t resv25_31:7; 457 } cntl_bits; 458 } nge_tx_cntl; 459 460 /* 461 * Transmit enable 462 * Note: for ck804 or mcp51, this is 8-bit register; 463 * for mcp55, it is a 32-bit register. 464 */ 465 #define NGE_TX_EN 0x084 466 #define NGE_SMU_FREE 0x0 467 #define NGE_SMU_GET 0xf 468 typedef union _nge_tx_en { 469 uint32_t val; 470 struct { 471 uint32_t tx_en:1; 472 uint32_t resv1_7:7; 473 uint32_t smu2mac:4; 474 uint32_t mac2smu:4; 475 uint32_t resv16_31:16; 476 } bits; 477 } nge_tx_en; 478 479 /* 480 * Transmit status 481 */ 482 #define NGE_TX_STA 0x088 483 typedef union _nge_tx_sta { 484 uint32_t sta_val; 485 struct { 486 uint32_t tx_chan_sta:1; 487 uint32_t resv1_15:15; 488 uint32_t retry_err:1; 489 uint32_t exdef:1; 490 uint32_t def:1; 491 uint32_t lcar:1; 492 uint32_t tlcol:1; 493 uint32_t uflo:1; 494 uint32_t resv22_31:10; 495 } sta_bits; 496 } nge_tx_sta; 497 498 /* 499 * Receive control 500 */ 501 #define NGE_RX_CNTL0 0x08c 502 typedef union _nge_rx_cntrl0 { 503 uint32_t cntl_val; 504 struct { 505 uint32_t resv0:1; 506 uint32_t padsen:1; 507 uint32_t fcsren:1; 508 uint32_t paen:1; 509 uint32_t lben:1; 510 uint32_t afen:1; 511 uint32_t runten:1; 512 uint32_t brdis:1; 513 uint32_t rdfen:1; 514 uint32_t slfb:1; 515 uint32_t resv10_15:6; 516 uint32_t runtm:1; 517 uint32_t rlcolm:1; 518 uint32_t maxerm:1; 519 uint32_t lferm:1; 520 uint32_t crcm:1; 521 uint32_t ofolm:1; 522 uint32_t framerm:1; 523 uint32_t resv23_31:9; 524 } cntl_bits; 525 } nge_rx_cntrl0; 526 527 /* 528 * Maximum receive Frame size 529 */ 530 #define NGE_RX_CNTL1 0x090 531 typedef union _nge_rx_cntl1 { 532 uint32_t cntl_val; 533 struct { 534 uint32_t length:14; 535 uint32_t resv14_31:18; 536 } cntl_bits; 537 } nge_rx_cntl1; 538 539 /* 540 * Receive enable register 541 * Note: for ck804 and mcp51, this is a 8-bit register; 542 * for mcp55, it is a 32-bit register. 543 */ 544 #define NGE_RX_EN 0x094 545 typedef union _nge_rx_en { 546 uint8_t val; 547 struct { 548 uint8_t rx_en:1; 549 uint8_t resv1_7:7; 550 } bits; 551 } nge_rx_en; 552 553 /* 554 * Receive status register 555 */ 556 #define NGE_RX_STA 0x098 557 typedef union _nge_rx_sta { 558 uint32_t sta_val; 559 struct { 560 uint32_t rx_chan_sta:1; 561 uint32_t resv1_15:15; 562 uint32_t runt_sta:1; 563 uint32_t rlcol_sta:1; 564 uint32_t mlen_err:1; 565 uint32_t lf_err:1; 566 uint32_t crc_err:1; 567 uint32_t ofol_err:1; 568 uint32_t fram_err:1; 569 uint32_t resv23_31:9; 570 } sta_bits; 571 } nge_rx_sta; 572 573 /* 574 * Backoff Control 575 */ 576 #define NGE_BKOFF_CNTL 0x09c 577 #define BKOFF_RSEED 0x8 578 #define BKOFF_SLIM_GMII 0x3ff 579 #define BKOFF_SLIM_MII 0x7f 580 typedef union _nge_bkoff_cntl { 581 uint32_t cntl_val; 582 struct { 583 uint32_t rseed:8; 584 uint32_t sltm:10; 585 uint32_t resv18_30:13; 586 uint32_t leg_bk_en:1; 587 } bkoff_bits; 588 } nge_bkoff_cntl; 589 590 /* 591 * Transmit defferral timing 592 */ 593 #define NGE_TX_DEF 0x0a0 594 #define TX_TIFG_MII 0x15 595 #define TX_IFG_RGMII_1000_FD 0x14 596 #define TX_IFG_RGMII_OTHER 0x16 597 #define TX_IFG2_MII 0x5 598 #define TX_IFG2_RGMII_10_100 0x7 599 #define TX_IFG2_RGMII_1000 0x5 600 #define TX_IFG2_DEFAULT 0X0 601 #define TX_IFG1_DEFAULT 0xf 602 typedef union _nge_tx_def { 603 uint32_t def_val; 604 struct { 605 uint32_t ifg1_def:8; 606 uint32_t ifg2_def:8; 607 uint32_t if_def:8; 608 uint32_t resv24_31:8; 609 } def_bits; 610 } nge_tx_def; 611 612 /* 613 * Receive defferral timing 614 */ 615 #define NGE_RX_DEf 0x0a4 616 #define RX_DEF_DEFAULT 0x16 617 typedef union _nge_rx_def { 618 uint8_t def_val; 619 struct { 620 uint8_t rifg; 621 } def_bits; 622 } nge_rx_def; 623 624 /* 625 * Low 32 bit unicast address 626 */ 627 #define NGE_UNI_ADDR0 0x0a8 628 union { 629 uint32_t addr_val; 630 struct { 631 uint32_t addr; 632 } addr_bits; 633 } nge_uni_addr0; 634 635 /* 636 * High 32 bit unicast address 637 */ 638 #define NGE_UNI_ADDR1 0x0ac 639 typedef union _nge_uni_addr1 { 640 uint32_t addr_val; 641 struct { 642 uint32_t addr:16; 643 uint32_t resv16_31:16; 644 } addr_bits; 645 } nge_uni_addr1; 646 647 #define LOW_24BITS_MASK 0xffffffULL 648 #define REVERSE_MAC_ELITE 0x211900ULL 649 #define REVERSE_MAC_GIGABYTE 0xe61600ULL 650 #define REVERSE_MAC_ASUS 0x601d00ULL 651 652 /* 653 * Low 32 bit multicast address 654 */ 655 #define NGE_MUL_ADDR0 0x0b0 656 union { 657 uint32_t addr_val; 658 struct { 659 uint32_t addr; 660 }addr_bits; 661 }nge_mul_addr0; 662 663 /* 664 * High 32 bit multicast address 665 */ 666 #define NGE_MUL_ADDR1 0x0b4 667 typedef union _nge_mul_addr1 { 668 uint32_t addr_val; 669 struct { 670 uint32_t addr:16; 671 uint32_t resv16_31:16; 672 }addr_bits; 673 }nge_mul_addr1; 674 675 /* 676 * Low 32 bit multicast mask 677 */ 678 #define NGE_MUL_MASK 0x0b8 679 union { 680 uint32_t mask_val; 681 struct { 682 uint32_t mask; 683 } mask_bits; 684 } nge_mul_mask0; 685 686 /* 687 * High 32 bit multicast mask 688 */ 689 #define NGE_MUL_MASK1 0x0bc 690 union { 691 uint32_t mask_val; 692 struct { 693 uint32_t mask:16; 694 uint32_t resv16_31:16; 695 } mask_bits; 696 } nge_mul_mask1; 697 698 /* 699 * Mac-to Phy Interface 700 */ 701 #define NGE_MAC2PHY 0x0c0 702 #define low_speed 0x0 703 #define fast_speed 0x1 704 #define giga_speed 0x2 705 #define err_speed 0x4 706 #define MII_IN 0x0 707 #define RGMII_IN 0x1 708 #define ERR_IN1 0x3 709 #define ERR_IN2 0x4 710 typedef union _nge_mac2phy { 711 uint32_t m2p_val; 712 struct { 713 uint32_t speed:2; 714 uint32_t resv2_7:6; 715 uint32_t hdup_en:1; 716 uint32_t resv9:1; 717 uint32_t phyintr:1; /* for mcp55 only */ 718 uint32_t phyintrlvl:1; /* for mcp55 only */ 719 uint32_t resv12_27:16; 720 uint32_t in_type:2; 721 uint32_t resv30_31:2; 722 } m2p_bits; 723 } nge_mac2phy; 724 725 /* 726 * Transmit Descriptor Ring address 727 */ 728 #define NGE_TX_DADR 0x100 729 typedef union _nge_tx_addr { 730 uint32_t addr_val; 731 struct { 732 uint32_t resv0_2:3; 733 uint32_t addr:29; 734 } addr_bits; 735 } nge_tx_addr; 736 737 /* 738 * Receive Descriptor Ring address 739 */ 740 #define NGE_RX_DADR 0x104 741 typedef union _nge_rx_addr { 742 uint32_t addr_val; 743 struct { 744 uint32_t resv0_2:3; 745 uint32_t addr:29; 746 } addr_bits; 747 } nge_rx_addr; 748 749 /* 750 * Rx/tx descriptor ring leng 751 * Note: for mcp55, tdlen/rdlen are 14 bit. 752 */ 753 #define NGE_RXTX_DLEN 0x108 754 typedef union _nge_rxtx_dlen { 755 uint32_t dlen_val; 756 struct { 757 uint32_t tdlen:14; 758 uint32_t resv14_15:2; 759 uint32_t rdlen:14; 760 uint32_t resv30_31:2; 761 } dlen_bits; 762 } nge_rxtx_dlen; 763 764 /* 765 * Transmit polling register 766 */ 767 #define NGE_TX_POLL 0x10c 768 #define TX_POLL_INTV_1G 10 769 #define TX_POLL_INTV_100M 100 770 #define TX_POLL_INTV_10M 1000 771 772 typedef union _nge_tx_poll { 773 uint32_t poll_val; 774 struct { 775 uint32_t tpi:16; 776 uint32_t tpen:1; 777 uint32_t resv17_31:15; 778 } poll_bits; 779 } nge_tx_poll; 780 781 /* 782 * Receive polling register 783 */ 784 #define NGE_RX_POLL 0x110 785 #define RX_POLL_INTV_1G 10 786 #define RX_POLL_INTV_100M 100 787 #define RX_POLL_INTV_10M 1000 788 typedef union _nge_rx_poll { 789 uint32_t poll_val; 790 struct { 791 uint32_t rpi:16; 792 uint32_t rpen:1; 793 uint32_t resv17_31:15; 794 } poll_bits; 795 } nge_rx_poll; 796 797 /* 798 * Transmit polling count 799 */ 800 #define NGE_TX_PCNT 0x114 801 union { 802 uint32_t cnt_val; 803 struct { 804 uint32_t pcnt:32; 805 } cnt_bits; 806 } nge_tx_pcnt; 807 808 /* 809 * Receive polling count 810 */ 811 #define NGE_RX_PCNT 0x118 812 union { 813 uint32_t cnt_val; 814 struct { 815 uint32_t pcnt:32; 816 } cnt_bits; 817 } nge_rx_pcnt; 818 819 820 /* 821 * Current tx's descriptor address 822 */ 823 #define NGE_TX_CUR_DADR 0x11c 824 union { 825 uint32_t addr_val; 826 struct { 827 uint32_t resv0_2:3; 828 uint32_t addr:29; 829 } addr_bits; 830 } nge_tx_cur_addr; 831 832 /* 833 * Current rx's descriptor address 834 */ 835 #define NGE_RX_CUR_DADR 0x120 836 union { 837 uint32_t addr_val; 838 struct { 839 uint32_t resv0_2:3; 840 uint32_t addr:29; 841 } addr_bits; 842 } nge_rx_cur_addr; 843 844 /* 845 * Current tx's data buffer address 846 */ 847 #define NGE_TX_CUR_PRD0 0x124 848 union { 849 uint32_t prd0_val; 850 struct { 851 uint32_t prd0:32; 852 } prd0_bits; 853 } nge_tx_cur_prd0; 854 855 /* 856 * Current tx's data buffer status 857 */ 858 #define NGE_TX_CUR_PRD1 0x128 859 union { 860 uint32_t prd1_val; 861 struct { 862 uint32_t rebytes:16; 863 uint32_t status:16; 864 } prd1_bits; 865 } nge_tx_cur_prd1; 866 867 /* 868 * Current rx's data buffer address 869 */ 870 #define NGE_RX_CUR_PRD0 0x12c 871 union { 872 uint32_t prd0_val; 873 struct { 874 uint32_t prd0:32; 875 }prd0_bits; 876 }nge_rx_cur_prd0; 877 878 /* 879 * Current rx's data buffer status 880 */ 881 #define NGE_RX_CUR_PRD1 0x130 882 883 /* 884 * Next tx's descriptor address 885 */ 886 #define NGE_TX_NXT_DADR 0x134 887 union { 888 uint32_t dadr_val; 889 struct { 890 uint32_t addr:32; 891 }addr_bits; 892 }nge_tx_nxt_dadr; 893 894 /* 895 * Next rx's descriptor address 896 */ 897 #define NGE_RX_NXT_DADR 0x138 898 union { 899 uint32_t dadr_val; 900 struct { 901 uint32_t addr:32; 902 } addr_bits; 903 } nge_rx_nxt_dadr; 904 905 /* 906 * Transmit fifo watermark 907 */ 908 #define NGE_TX_FIFO_WM 0x13c 909 #define TX_FIFO_TBFW 0 910 #define TX_FIFO_NOB_WM_MII 1 911 #define TX_FIFO_NOB_WM_GMII 8 912 #define TX_FIFO_DATA_LWM 0x20 913 #define TX_FIFO_PRD_LWM 0x8 914 #define TX_FIFO_PRD_HWM 0x38 915 typedef union _nge_tx_fifo_wm { 916 uint32_t wm_val; 917 struct { 918 uint32_t data_lwm:9; 919 uint32_t resv8_11:3; 920 uint32_t prd_lwm:6; 921 uint32_t uprd_hwm:6; 922 uint32_t nbfb_wm:4; 923 uint32_t fb_wm:4; 924 } wm_bits; 925 } nge_tx_fifo_wm; 926 927 /* 928 * Receive fifo watermark 929 */ 930 #define NGE_RX_FIFO_WM 0x140 931 typedef union _nge_rx_fifo_wm { 932 uint32_t wm_val; 933 struct { 934 uint32_t data_hwm:9; 935 uint32_t resv9_11:3; 936 uint32_t prd_lwm:4; 937 uint32_t resv16_17:2; 938 uint32_t prd_hwm:4; 939 uint32_t resv22_31:10; 940 } wm_bits; 941 } nge_rx_fifo_wm; 942 943 /* 944 * Chip mode control 945 */ 946 #define NGE_MODE_CNTL 0x144 947 #define DESC_MCP1 0x0 948 #define DESC_OFFLOAD 0x1 949 #define DESC_HOT 0x2 950 #define DESC_RESV 0x3 951 #define MACHINE_BUSY 0x0 952 #define MACHINE_IDLE 0x1 953 typedef union _nge_mode_cntl { 954 uint32_t mode_val; 955 struct { 956 uint32_t txdm:1; 957 uint32_t rxdm:1; 958 uint32_t dma_dis:1; 959 uint32_t dma_status:1; 960 uint32_t bm_reset:1; 961 uint32_t resv5:1; 962 uint32_t vlan_strip:1; /* mcp55 chip only */ 963 uint32_t vlan_ins:1; /* mcp55 chip only */ 964 uint32_t desc_type:2; 965 uint32_t rx_sum_en:1; 966 uint32_t tx_prd_cu_en:1; 967 uint32_t w64_dis:1; 968 uint32_t tx_rcom_en:1; 969 uint32_t rx_filter_en:1; 970 uint32_t resv15:1; 971 uint32_t resv16:1; /* ck804 and mcp51 only */ 972 uint32_t resv17:1; /* ck804 and mcp51 only */ 973 uint32_t resv18:1; /* ck804 and mcp51 only */ 974 uint32_t resv19_21:3; 975 uint32_t tx_fetch_prd:1; /* mcp51/mcp55 only */ 976 uint32_t rx_fetch_prd:1; /* mcp51/mcp55 only */ 977 uint32_t resv24_29:6; 978 uint32_t rx_status:1; 979 uint32_t tx_status:1; 980 } mode_bits; 981 } nge_mode_cntl; 982 983 #define NGE_TX_DADR_HI 0x148 984 #define NGE_RX_DADR_HI 0x14c 985 986 /* 987 * Mii interrupt register 988 * Note: for mcp55, this is a 32-bit register. 989 */ 990 #define NGE_MINTR_SRC 0x180 991 typedef union _nge_mintr_src { 992 uint8_t src_val; 993 struct { 994 uint8_t mrei:1; 995 uint8_t mcc2:1; 996 uint8_t mcc1:1; 997 uint8_t mapi:1; 998 uint8_t mpdi:1; 999 uint8_t resv5_7:3; 1000 } src_bits; 1001 } nge_mintr_src; 1002 1003 /* 1004 * Mii interrupt mask 1005 * Note: for mcp55, this is a 32-bit register. 1006 */ 1007 #define NGE_MINTR_MASK 0x184 1008 typedef union _nge_mintr_mask { 1009 uint8_t mask_val; 1010 struct { 1011 uint8_t mrei:1; 1012 uint8_t mcc2:1; 1013 uint8_t mcc1:1; 1014 uint8_t mapi:1; 1015 uint8_t mpdi:1; 1016 uint8_t resv5_7:3; 1017 } mask_bits; 1018 } nge_mintr_mask; 1019 1020 /* 1021 * Mii control and status 1022 */ 1023 #define NGE_MII_CS 0x188 1024 #define MII_POLL_INTV 0x4 1025 typedef union _nge_mii_cs { 1026 uint32_t cs_val; 1027 struct { 1028 uint32_t excap:1; 1029 uint32_t jab_dec:1; 1030 uint32_t lk_up:1; 1031 uint32_t ana_cap:1; 1032 uint32_t rfault:1; 1033 uint32_t auto_neg:1; 1034 uint32_t mfps:1; 1035 uint32_t resv7:1; 1036 uint32_t exst:1; 1037 uint32_t hdup_100m_t2:1; 1038 uint32_t fdup_100m_t2:1; 1039 uint32_t hdup_10m:1; 1040 uint32_t fdup_10m:1; 1041 uint32_t hdup_100m_x:1; 1042 uint32_t fdup_100m_x:1; 1043 uint32_t cap_100m_t4:1; 1044 uint32_t ap_intv:4; 1045 uint32_t ap_en:1; 1046 uint32_t resv21_23:3; 1047 uint32_t ap_paddr:5; 1048 uint32_t resv29_31:3; 1049 } cs_bits; 1050 } nge_mii_cs; 1051 1052 /* 1053 * Mii Clock timer register 1054 */ 1055 #define NGE_MII_TM 0x18c 1056 typedef union _nge_mii_tm { 1057 uint16_t tm_val; 1058 struct { 1059 uint16_t timer_interv:8; 1060 uint16_t timer_en:1; 1061 uint16_t resv9_14:6; 1062 uint16_t timer_status:1; 1063 } tm_bits; 1064 } nge_mii_tm; 1065 1066 /* 1067 * Mdio address 1068 */ 1069 #define NGE_MDIO_ADR 0x190 1070 typedef union _nge_mdio_adr { 1071 uint16_t adr_val; 1072 struct { 1073 uint16_t phy_reg:5; 1074 uint16_t phy_adr:5; 1075 uint16_t mdio_rw:1; 1076 uint16_t resv11_14:4; 1077 uint16_t mdio_clc:1; 1078 } adr_bits; 1079 } nge_mdio_adr; 1080 1081 /* 1082 * Mdio data 1083 */ 1084 #define NGE_MDIO_DATA 0x194 1085 1086 /* 1087 * Power Management and Control 1088 */ 1089 #define NGE_PM_CNTL 0x200 1090 typedef union _nge_pm_cntl { 1091 uint32_t cntl_val; 1092 struct { 1093 /* 1094 * mp_en: Magic Packet Enable 1095 * pm_en: Pattern Match Enable 1096 * lc_en: Link Change Enable 1097 */ 1098 uint32_t mp_en_d0:1; 1099 uint32_t pm_en_d0:1; 1100 uint32_t lc_en_d0:1; 1101 uint32_t resv3:1; 1102 uint32_t mp_en_d1:1; 1103 uint32_t pm_en_d1:1; 1104 uint32_t lc_en_d1:1; 1105 uint32_t resv7:1; 1106 uint32_t mp_en_d2:1; 1107 uint32_t pm_en_d2:1; 1108 uint32_t lc_en_d2:1; 1109 uint32_t resv11:1; 1110 uint32_t mp_en_d3:1; 1111 uint32_t pm_en_d3:1; 1112 uint32_t lc_en_d3:1; 1113 uint32_t resv15:1; 1114 uint32_t pat_match_en:5; 1115 uint32_t resv21_23:3; 1116 uint32_t pat_match_stat:5; 1117 uint32_t magic_status:1; 1118 uint32_t netman_status:1; 1119 uint32_t resv31:1; 1120 } cntl_bits; 1121 } nge_pm_cntl; 1122 1123 #define NGE_MPT_CRC0 0x204 1124 #define NGE_PMC_MK00 0x208 1125 #define NGE_PMC_MK01 0x20C 1126 #define NGE_PMC_MK02 0x210 1127 #define NGE_PMC_MK03 0x214 1128 #define NGE_MPT_CRC1 0x218 1129 #define NGE_PMC_MK10 0x21c 1130 #define NGE_PMC_MK11 0x220 1131 #define NGE_PMC_MK12 0x224 1132 #define NGE_PMC_MK13 0x228 1133 #define NGE_MPT_CRC2 0x22c 1134 #define NGE_PMC_MK20 0x230 1135 #define NGE_PMC_MK21 0x234 1136 #define NGE_PMC_MK22 0x238 1137 #define NGE_PMC_MK23 0x23c 1138 #define NGE_MPT_CRC3 0x240 1139 #define NGE_PMC_MK30 0x244 1140 #define NGE_PMC_MK31 0x248 1141 #define NGE_PMC_MK32 0x24c 1142 #define NGE_PMC_MK33 0x250 1143 #define NGE_MPT_CRC4 0x254 1144 #define NGE_PMC_MK40 0x258 1145 #define NGE_PMC_MK41 0x25c 1146 #define NGE_PMC_MK42 0x260 1147 #define NGE_PMC_MK43 0x264 1148 #define NGE_PMC_ALIAS 0x268 1149 #define NGE_PMCSR_ALIAS 0x26c 1150 1151 /* 1152 * Seeprom control 1153 */ 1154 #define NGE_EP_CNTL 0x500 1155 #define EEPROM_CLKDIV 249 1156 #define EEPROM_WAITCLK 0x7 1157 typedef union _nge_cp_cntl { 1158 uint32_t cntl_val; 1159 struct { 1160 uint32_t clkdiv:8; 1161 uint32_t rom_size:3; 1162 uint32_t resv11:1; 1163 uint32_t word_wid:1; 1164 uint32_t resv13_15:3; 1165 uint32_t wait_slots:4; 1166 uint32_t resv20_31:12; 1167 } cntl_bits; 1168 } nge_cp_cntl; 1169 1170 /* 1171 * Seeprom cmd control 1172 */ 1173 #define NGE_EP_CMD 0x504 1174 #define SEEPROM_CMD_READ 0x0 1175 #define SEEPROM_CMD_WRITE_ENABLE 0x1 1176 #define SEEPROM_CMD_ERASE 0x2 1177 #define SEEPROM_CMD_WRITE 0x3 1178 #define SEEPROM_CMD_ERALSE_ALL 0x4 1179 #define SEEPROM_CMD_WRITE_ALL 0x5 1180 #define SEEPROM_CMD_WRITE_DIS 0x6 1181 #define SEEPROM_READY 0x1 1182 typedef union _nge_ep_cmd { 1183 uint32_t cmd_val; 1184 struct { 1185 uint32_t addr:16; 1186 uint32_t cmd:3; 1187 uint32_t resv19_30:12; 1188 uint32_t sts:1; 1189 } cmd_bits; 1190 } nge_ep_cmd; 1191 1192 /* 1193 * Seeprom data register 1194 */ 1195 #define NGE_EP_DATA 0x508 1196 typedef union _nge_ep_data { 1197 uint32_t data_val; 1198 struct { 1199 uint32_t data:16; 1200 uint32_t resv16_31:16; 1201 } data_bits; 1202 } nge_ep_data; 1203 1204 /* 1205 * Power management control 2nd register (since MCP51) 1206 */ 1207 #define NGE_PM_CNTL2 0x600 1208 typedef union _nge_pm_cntl2 { 1209 uint32_t cntl_val; 1210 struct { 1211 uint32_t phy_coma_set:1; 1212 uint32_t phy_coma_status:1; 1213 uint32_t resv2_3:2; 1214 uint32_t resv4:1; 1215 uint32_t resv5_7:3; 1216 uint32_t resv8_11:4; 1217 uint32_t resv12_15:4; 1218 uint32_t pmt5_en:1; 1219 uint32_t pmt6_en:1; 1220 uint32_t pmt7_en:1; 1221 uint32_t resv19_23:5; 1222 uint32_t pmt5_status:1; 1223 uint32_t pmt6_status:1; 1224 uint32_t pmt7_status:1; 1225 uint32_t resv27_31:5; 1226 } cntl_bits; 1227 } nge_pm_cntl2; 1228 1229 1230 /* 1231 * ASF RAM 0x800-0xfff 1232 */ 1233 1234 /* 1235 * Hardware-defined Statistics Block Offsets 1236 * 1237 * These are given in the manual as addresses in NIC memory, starting 1238 * from the NIC statistics area base address of 0x2000; 1239 */ 1240 1241 #define KS_BASE 0x0280 1242 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint32_t)) 1243 1244 typedef enum { 1245 KS_ifHOutOctets = KS_ADDR(0x0280), 1246 KS_ifHOutZeroRetranCount, 1247 KS_ifHOutOneRetranCount, 1248 KS_ifHOutMoreRetranCount, 1249 KS_ifHOutColCount, 1250 KS_ifHOutFifoovCount, 1251 KS_ifHOutLOCCount, 1252 KS_ifHOutExDecCount, 1253 KS_ifHOutRetryCount, 1254 1255 KS_ifHInFrameErrCount, 1256 KS_ifHInExtraOctErrCount, 1257 KS_ifHInLColErrCount, 1258 KS_ifHInRuntCount, 1259 KS_ifHInOversizeErrCount, 1260 KS_ifHInFovErrCount, 1261 KS_ifHInFCSErrCount, 1262 KS_ifHInAlignErrCount, 1263 KS_ifHInLenErrCount, 1264 KS_ifHInUniPktsCount, 1265 KS_ifHInBroadPksCount, 1266 KS_ifHInMulPksCount, 1267 KS_STATS_SIZE = KS_ADDR(0x2d0) 1268 1269 } nge_stats_offset_t; 1270 1271 /* 1272 * Hardware-defined Statistics Block 1273 * 1274 * Another view of the statistic block, as a array and a structure ... 1275 */ 1276 1277 typedef union { 1278 uint64_t a[KS_STATS_SIZE]; 1279 struct { 1280 uint64_t OutOctets; 1281 uint64_t OutZeroRetranCount; 1282 uint64_t OutOneRetranCount; 1283 uint64_t OutMoreRetranCount; 1284 uint64_t OutColCount; 1285 uint64_t OutFifoovCount; 1286 uint64_t OutLOCCount; 1287 uint64_t OutExDecCount; 1288 uint64_t OutRetryCount; 1289 1290 uint64_t InFrameErrCount; 1291 uint64_t InExtraOctErrCount; 1292 uint64_t InLColErrCount; 1293 uint64_t InRuntCount; 1294 uint64_t InOversizeErrCount; 1295 uint64_t InFovErrCount; 1296 uint64_t InFCSErrCount; 1297 uint64_t InAlignErrCount; 1298 uint64_t InLenErrCount; 1299 uint64_t InUniPktsCount; 1300 uint64_t InBroadPksCount; 1301 uint64_t InMulPksCount; 1302 } s; 1303 } nge_hw_statistics_t; 1304 1305 /* 1306 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1307 */ 1308 1309 #define NGE_PHY_NUMBER 32 1310 #define MII_LP_ASYM_PAUSE 0x0800 1311 #define MII_LP_PAUSE 0x0400 1312 1313 #define MII_100BASE_T4 0x0200 1314 #define MII_100BASET_FD 0x0100 1315 #define MII_100BASET_HD 0x0080 1316 #define MII_10BASET_FD 0x0040 1317 #define MII_10BASET_HD 0x0020 1318 1319 #define MII_ID_MARVELL 0x5043 1320 #define MII_ID_CICADA 0x03f1 1321 #define MII_IDL_MASK 0xfc00 1322 #define MII_AN_LPNXTPG 8 1323 1324 1325 #define MII_IEEE_EXT_STATUS 15 1326 1327 /* 1328 * New bits in the MII_CONTROL register 1329 */ 1330 #define MII_CONTROL_1000MB 0x0040 1331 1332 /* 1333 * New bits in the MII_AN_ADVERT register 1334 */ 1335 #define MII_ABILITY_ASYM_PAUSE 0x0800 1336 #define MII_ABILITY_PAUSE 0x0400 1337 1338 /* 1339 * Values for the <selector> field of the MII_AN_ADVERT register 1340 */ 1341 #define MII_AN_SELECTOR_8023 0x0001 1342 1343 /* 1344 * Bits in the MII_1000BASE_T_CONTROL register 1345 * 1346 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1347 * (otherwise, roles are automatically negotiated). When this bit is set, 1348 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1349 */ 1350 #define MII_1000BASE_T_CONTROL 9 1351 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1352 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1353 #define MII_1000BT_CTL_ADV_FDX 0x0200 1354 #define MII_1000BT_CTL_ADV_HDX 0x0100 1355 1356 /* 1357 * Bits in the MII_1000BASE_T_STATUS register 1358 */ 1359 #define MII_1000BASE_T_STATUS 10 1360 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1361 #define MII_1000BT_STAT_MASTER_MODE 0x4000 1362 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1363 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1364 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1365 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1366 1367 #define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2) 1368 #define CICADA_125MHZ_CLOCK_ENABLE 0x0001 1369 1370 #define MII_CICADA_10BASET_CONTROL MII_VENDOR(6) 1371 #define MII_CICADA_DISABLE_ECHO_MODE 0x2000 1372 1373 #define MII_CICADA_EXT_CONTROL MII_VENDOR(7) 1374 #define MII_CICADA_MODE_SELECT_BITS 0xf000 1375 #define MII_CICADA_MODE_SELECT_RGMII 0x1000 1376 #define MII_CICADA_POWER_SUPPLY_BITS 0x0e00 1377 #define MII_CICADA_POWER_SUPPLY_3_3V 0x0000 1378 #define MII_CICADA_POWER_SUPPLY_2_5V 0x0200 1379 1380 #define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12) 1381 #define MII_CICADA_PIN_PRORITY_SETTING 0x0004 1382 #define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000 1383 1384 1385 #define NGE_REG_SIZE 0xfff 1386 #define NGE_MII_SIZE 0x20 1387 #define NGE_SEEROM_SIZE 0x800 1388 /* 1389 * Legacy rx's bd which does not support 1390 * any hardware offload 1391 */ 1392 typedef struct _legacy_rx_bd { 1393 uint32_t host_buf_addr; 1394 union { 1395 uint32_t cntl_val; 1396 struct { 1397 uint32_t bcnt:16; 1398 uint32_t end:1; 1399 uint32_t miss:1; 1400 uint32_t extra:1; 1401 uint32_t inten:1; 1402 uint32_t bam:1; 1403 uint32_t mam:1; 1404 uint32_t pam:1; 1405 uint32_t runt:1; 1406 uint32_t lcol:1; 1407 uint32_t max:1; 1408 uint32_t lfer:1; 1409 uint32_t crc:1; 1410 uint32_t ofol:1; 1411 uint32_t fram:1; 1412 uint32_t err:1; 1413 uint32_t own:1; 1414 } cntl_bits; 1415 } cntl_status; 1416 } legacy_rx_bd, *plegacy_rx_bd; 1417 1418 /* 1419 * Stand offload rx's bd which supports hareware checksum 1420 * for tcp/ip 1421 */ 1422 #define CK8G_NO_HSUM 0x0 1423 #define CK8G_TCP_SUM_ERR 0x1 1424 #define CK8G_UDP_SUM_ERR 0x2 1425 #define CK8G_IP_HSUM_ERR 0x3 1426 #define CK8G_IP_HSUM 0x4 1427 #define CK8G_TCP_SUM 0x5 1428 #define CK8G_UDP_SUM 0x6 1429 #define CK8G_RESV 0x7 1430 typedef struct _sum_rx_bd { 1431 uint32_t host_buf_addr; 1432 union { 1433 uint32_t cntl_val; 1434 struct { 1435 uint32_t bcnt:14; 1436 uint32_t resv14_29:16; 1437 uint32_t inten:1; 1438 uint32_t own:1; 1439 } control_bits; 1440 struct { 1441 uint32_t bcnt:14; 1442 uint32_t resv14:1; 1443 uint32_t bam:1; 1444 uint32_t mam:1; 1445 uint32_t pam:1; 1446 uint32_t runt:1; 1447 uint32_t lcol:1; 1448 uint32_t max:1; 1449 uint32_t lfer:1; 1450 uint32_t crc:1; 1451 uint32_t ofol:1; 1452 uint32_t fram:1; 1453 uint32_t extra:1; 1454 uint32_t l3_l4_sum:3; 1455 uint32_t rend:1; 1456 uint32_t err:1; 1457 uint32_t own:1; 1458 } status_bits; 1459 } cntl_status; 1460 } sum_rx_bd, *psum_rx_bd; 1461 /* 1462 * Hot offload rx's bd which support 64bit access and 1463 * full-tcp hardware offload 1464 */ 1465 typedef struct _hot_rx_bd { 1466 uint32_t host_buf_addr_hi; 1467 uint32_t host_buf_addr_lo; 1468 uint32_t sw_tag; 1469 union { 1470 uint32_t cntl_val; 1471 struct { 1472 uint32_t bcnt:14; 1473 uint32_t resv14_29:16; 1474 uint32_t inten:1; 1475 uint32_t own:1; 1476 } control_bits; 1477 1478 struct { 1479 uint32_t bcnt:14; 1480 uint32_t ctmach_rd:1; 1481 uint32_t bam:1; 1482 uint32_t mam:1; 1483 uint32_t pam:1; 1484 uint32_t runt:1; 1485 uint32_t lcol:1; 1486 uint32_t max:1; 1487 uint32_t lfer:1; 1488 uint32_t crc:1; 1489 uint32_t ofol:1; 1490 uint32_t fram:1; 1491 uint32_t extra:1; 1492 uint32_t l3_l4_sum:3; 1493 uint32_t rend:1; 1494 uint32_t err:1; 1495 uint32_t own:1; 1496 } status_bits_legacy; 1497 } cntl_status; 1498 } hot_rx_bd, *phot_rx_bd; 1499 1500 /* 1501 * Legacy tx's bd which does not support 1502 * any hardware offload 1503 */ 1504 typedef struct _legacy_tx_bd { 1505 uint32_t host_buf_addr; 1506 union { 1507 uint32_t cntl_val; 1508 struct { 1509 uint32_t bcnt:16; 1510 uint32_t end:1; 1511 uint32_t resv17_23:7; 1512 uint32_t inten:1; 1513 uint32_t resv25_30:6; 1514 uint32_t own:1; 1515 } control_bits; 1516 1517 struct { 1518 uint32_t bcnt:16; 1519 uint32_t end:1; 1520 uint32_t rtry:1; 1521 uint32_t trc:4; 1522 uint32_t inten:1; 1523 uint32_t exdef:1; 1524 uint32_t def:1; 1525 uint32_t lcar:1; 1526 uint32_t lcol:1; 1527 uint32_t uflo:1; 1528 uint32_t err:1; 1529 uint32_t own:1; 1530 } status_bits; 1531 } cntl_status; 1532 } legacy_tx_bd, *plegacy_tx_bd; 1533 1534 /* 1535 * Stand offload tx's bd which supports hareware checksum 1536 * for tcp/ip 1537 */ 1538 typedef struct _sum_tx_bd { 1539 uint32_t host_buf_addr; 1540 union { 1541 uint32_t cntl_val; 1542 struct { 1543 uint32_t bcnt:14; 1544 uint32_t resv14_25:12; 1545 uint32_t tcp_hsum:1; 1546 uint32_t ip_hsum:1; 1547 uint32_t segen:1; 1548 uint32_t end:1; 1549 uint32_t inten:1; 1550 uint32_t own:1; 1551 } control_sum_bits; 1552 1553 struct { 1554 uint32_t bcnt:14; 1555 uint32_t mss:14; 1556 uint32_t segen:1; 1557 uint32_t end:1; 1558 uint32_t inten:1; 1559 uint32_t own:1; 1560 } control_tso_bits; 1561 1562 struct { 1563 uint32_t bcnt:14; 1564 uint32_t resv14_17:4; 1565 uint32_t rtry:1; 1566 uint32_t trc:4; 1567 uint32_t inten:1; 1568 uint32_t exdef:1; 1569 uint32_t def:1; 1570 uint32_t lcar:1; 1571 uint32_t lcol:1; 1572 uint32_t uflo:1; 1573 uint32_t end:1; 1574 uint32_t err:1; 1575 uint32_t own:1; 1576 } status_bits; 1577 } control_status; 1578 } sum_tx_bd, *psum_tx_bd; 1579 1580 /* 1581 * Hot offload tx's bd which support 64bit access and 1582 * full-tcp hardware offload 1583 */ 1584 1585 typedef struct _hot_tx_bd { 1586 uint32_t host_buf_addr_hi; 1587 uint32_t host_buf_addr_lo; 1588 union { 1589 uint32_t parm_val; 1590 struct { 1591 uint32_t resv0_15:16; 1592 uint32_t resv16:1; 1593 uint32_t resv17:1; 1594 uint32_t resv18_31:14; 1595 } parm_bits; 1596 } hot_parms; 1597 1598 union { 1599 uint32_t cntl_val; 1600 struct { 1601 uint32_t bcnt:14; 1602 uint32_t resv14_25:12; 1603 uint32_t tcp_hsum:1; 1604 uint32_t ip_hsum:1; 1605 uint32_t segen:1; 1606 uint32_t end:1; 1607 uint32_t inten:1; 1608 uint32_t own:1; 1609 } control_sum_bits; 1610 1611 struct { 1612 uint32_t bcnt:14; 1613 uint32_t mss:14; 1614 uint32_t segen:1; 1615 uint32_t end:1; 1616 uint32_t inten:1; 1617 uint32_t own:1; 1618 } control_tso_bits; 1619 1620 struct { 1621 uint32_t bcnt:14; 1622 uint32_t resv14_17:4; 1623 uint32_t rtry:1; 1624 uint32_t trc:4; 1625 uint32_t inten:1; 1626 uint32_t exdef:1; 1627 uint32_t def:1; 1628 uint32_t lcar:1; 1629 uint32_t lcol:1; 1630 uint32_t uflo:1; 1631 uint32_t end:1; 1632 uint32_t err:1; 1633 uint32_t own:1; 1634 } status_bits; 1635 } control_status; 1636 } hot_tx_bd, *phot_tx_bd; 1637 1638 #ifdef __cplusplus 1639 } 1640 #endif 1641 1642 #endif /* _SYS_NGE_CHIP_H */ 1643