1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NGE_CHIP_H 28 #define _SYS_NGE_CHIP_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "nge.h" 35 36 #define VENDOR_ID_NVIDIA 0x10de 37 38 #define DEVICE_ID_MCP04_37 0x37 39 #define DEVICE_ID_MCP04_38 0x38 40 #define DEVICE_ID_CK804_56 0x56 41 #define DEVICE_ID_CK804_57 0x57 42 #define DEVICE_ID_MCP51_269 0x269 43 #define DEVICE_ID_MCP51_268 0x268 44 #define DEVICE_ID_MCP55_373 0x373 45 #define DEVICE_ID_MCP55_372 0x372 46 #define DEVICE_ID_MCP61_3EE 0x3ee 47 #define DEVICE_ID_MCP61_3EF 0x3ef 48 #define DEVICE_ID_MCP77_760 0x760 49 #define DEVICE_ID_NF3_E6 0xe6 50 #define DEVICE_ID_NF3_DF 0xdf 51 52 /* Private PCI configuration register for bus config of ck804/mcp55 */ 53 #define PCI_CONF_HT_INTERNAL 0x4c 54 55 typedef union _nge_interbus_conf { 56 uint32_t conf_val; 57 struct { 58 uint32_t unit_id:5; 59 uint32_t resv5_23:19; 60 uint32_t aux_val:3; 61 uint32_t resv27:1; 62 uint32_t msi_off:1; 63 uint32_t msix_off:1; /* mcp55 only */ 64 uint32_t resv30_31:2; 65 } conf_bits; 66 } nge_interbus_conf; 67 68 /* Private PCI configuration register for MSI mask of mcp55 */ 69 #define PCI_CONF_HT_MSI_MASK 0x60 70 71 typedef union _nge_msi_mask_conf { 72 uint32_t msi_mask_conf_val; 73 struct { 74 uint32_t vec0_off:1; 75 uint32_t vec1_off:1; 76 uint32_t vec2_off:1; 77 uint32_t vec3_off:1; 78 uint32_t vec4_off:1; 79 uint32_t vec5_off:1; 80 uint32_t vec6_off:1; 81 uint32_t vec7_off:1; 82 uint32_t resv8_31:24; 83 } msi_mask_bits; 84 } nge_msi_mask_conf; 85 86 /* Private PCI configuration register for MSI map capability of mcp55 */ 87 #define PCI_CONF_HT_MSI_MAP_CAP 0x6c 88 89 typedef union _nge_msi_map_cap_conf { 90 uint32_t msi_map_cap_conf_val; 91 struct { 92 uint32_t cap_id:8; 93 uint32_t next_ptr:8; 94 uint32_t map_en:1; 95 uint32_t map_fixed:1; 96 uint32_t resv18_26:9; 97 uint32_t cap_type:5; 98 } map_cap_conf_bits; 99 } nge_msi_map_cap_conf; 100 101 /* 102 * Master interrupt 103 */ 104 #define NGE_INTR_SRC 0x000 105 #define INTR_SRC_ALL 0x00007fff 106 typedef union _nge_intr_src { 107 uint32_t intr_val; 108 struct { 109 uint32_t reint:1; 110 uint32_t rcint:1; 111 uint32_t miss:1; 112 uint32_t teint:1; 113 uint32_t tcint:1; 114 uint32_t stint:1; 115 uint32_t mint:1; 116 uint32_t rfint:1; 117 uint32_t tfint:1; 118 uint32_t feint:1; 119 uint32_t resv10:1; 120 uint32_t resv11:1; 121 uint32_t resv12:1; 122 uint32_t resv13:1; 123 uint32_t phyint:1; 124 uint32_t resv15_31:17; 125 } int_bits; 126 } nge_intr_src; 127 128 /* 129 * Master interrupt Mask 130 */ 131 #define NGE_INTR_MASK 0x004 132 #define NGE_INTR_ALL_EN 0x00007fff 133 typedef union _nge_intr_mask { 134 uint32_t mask_val; 135 struct { 136 uint32_t reint:1; 137 uint32_t rcint:1; 138 uint32_t miss:1; 139 uint32_t teint:1; 140 uint32_t tcint:1; 141 uint32_t stint:1; 142 uint32_t mint:1; 143 uint32_t rfint:1; 144 uint32_t tfint:1; 145 uint32_t feint:1; 146 uint32_t resv10:1; 147 uint32_t resv11:1; 148 uint32_t resv12:1; 149 uint32_t resv13:1; 150 uint32_t phyint:1; 151 uint32_t resv15_31:17; 152 } mask_bits; 153 } nge_intr_mask; 154 155 /* 156 * Software timer control register 157 */ 158 #define NGE_SWTR_CNTL 0x008 159 typedef union _nge_swtr_cntl { 160 uint8_t ctrl_val; 161 struct { 162 uint8_t stren:1; 163 uint8_t sten:1; 164 uint8_t resv2_7:6; 165 } cntl_bits; 166 } nge_swtr_cntl; 167 168 /* 169 * Software Timer Interval 170 */ 171 #define NGE_SWTR_ITC 0x00c 172 173 /* Default timer interval, 97 would mean 1 ms */ 174 #define SWTR_ITC 0x8 175 typedef union _nge_itc { 176 uint32_t itc_val; 177 struct { 178 uint32_t sw_intv:16; 179 uint32_t sw_cur_val:16; 180 } itc_bits; 181 } nge_itc; 182 183 /* 184 * Fatal error register 185 */ 186 #define NGE_REG010 0x010 187 typedef union _nge_reg010 { 188 uint32_t reg010_val; 189 struct { 190 uint32_t resv0:1; 191 uint32_t resv1:1; 192 uint32_t resv2:1; 193 uint32_t resv3:1; 194 uint32_t resv4:1; 195 uint32_t resv5:1; 196 uint32_t resv6:1; 197 uint32_t resv7:1; 198 uint32_t resv8:1; 199 uint32_t resv9:1; 200 uint32_t resv10:1; 201 uint32_t resv11_31:21; 202 } reg010_bits; 203 } nge_reg010; 204 205 /* 206 * MSI vector map register 0 207 */ 208 #define NGE_MSI_MAP0 0x020 209 typedef union _nge_msi_map0_vec { 210 uint32_t msi_map0_val; 211 struct { 212 uint32_t reint_vec:4; 213 uint32_t rcint_vec:4; 214 uint32_t miss_vec:4; 215 uint32_t teint_vec:4; 216 uint32_t tcint_vec:4; 217 uint32_t stint_vec:4; 218 uint32_t mint_vec:4; 219 uint32_t rfint_vec:4; 220 } vecs_bits; 221 } nge_msi_map0_vec; 222 223 /* 224 * MSI vector map register 1 225 */ 226 #define NGE_MSI_MAP1 0x024 227 typedef union _nge_msi_map1_vec { 228 uint32_t msi_map1_val; 229 struct { 230 uint32_t tfint_vec:4; 231 uint32_t feint_vec:4; 232 uint32_t resv8_11:4; 233 uint32_t resv12_15:4; 234 uint32_t resv16_19:4; 235 uint32_t resv20_23:4; 236 uint32_t resv24_31:8; 237 } vecs_bits; 238 } nge_msi_map1_vec; 239 240 241 /* 242 * MSI vector map register 2 243 */ 244 #define NGE_MSI_MAP2 0x028 245 246 /* 247 * MSI vector map register 2 248 */ 249 #define NGE_MSI_MAP3 0x02c 250 251 /* 252 * MSI mask register for mcp55 253 */ 254 #define NGE_MSI_MASK 0x30 255 typedef union _nge_msi_mask { 256 uint32_t msi_mask_val; 257 struct { 258 uint32_t vec0:1; 259 uint32_t vec1:1; 260 uint32_t vec2:1; 261 uint32_t vec3:1; 262 uint32_t vec4:1; 263 uint32_t vec5:1; 264 uint32_t vec6:1; 265 uint32_t vec7:1; 266 uint32_t resv8_31:24; 267 }msi_msk_bits; 268 }nge_msi_mask; 269 270 /* 271 * Software misc register for mcp51 272 */ 273 #define NGE_SOFT_MISC 0x034 274 typedef union _nge_soft_misc { 275 uint32_t misc_val; 276 struct { 277 uint32_t rx_clk_vx_rst:1; 278 uint32_t tx_clk_vx_rst:1; 279 uint32_t clk12m_vx_rst:1; 280 uint32_t fpci_clk_vx_rst:1; 281 uint32_t rx_clk_vc_rst:1; 282 uint32_t tx_clk_vc_rst:1; 283 uint32_t fs_clk_vc_rst:1; 284 uint32_t rst_ex_m2pintf:1; 285 uint32_t resv8_31:24; 286 } misc_bits; 287 } nge_soft_misc; 288 289 /* 290 * DMA configuration 291 */ 292 #define NGE_DMA_CFG 0x040 293 typedef union _nge_dma_cfg { 294 uint32_t cfg_val; 295 struct { 296 uint32_t tx_start_pri:3; 297 uint32_t tx_start_pri_flag:1; 298 uint32_t tx_prd_rpri:3; 299 uint32_t tx_prd_rpri_flag:1; 300 uint32_t tx_prd_wpri:3; 301 uint32_t tx_prd_wpri_flag:1; 302 uint32_t rx_start_pri:3; 303 uint32_t rx_start_pri_flag:1; 304 uint32_t rx_prd_rpri:3; 305 uint32_t rx_prd_rpri_flag:1; 306 uint32_t rx_prd_wpri:3; 307 uint32_t rx_prd_wpri_flag:1; 308 uint32_t dma_max_pri:3; 309 uint32_t dma_wrr_disable:1; 310 uint32_t dma_pri_disable:1; 311 } cfg_bits; 312 } nge_dma_cfg; 313 314 /* 315 * Request DMA configuration 316 */ 317 #define NGE_DMA_RCFG 0x044 318 typedef union _nge_dma_rcfg { 319 uint32_t dma_rcfg_val; 320 struct { 321 uint32_t tx_prd_coh_state:2; 322 uint32_t tx_data_coh_state:2; 323 uint32_t rx_prd_coh_state:2; 324 uint32_t rx_data_coh_state:2; 325 uint32_t max_roffset:5; 326 uint32_t resv13_31:19; 327 } rcfg_bis; 328 } nge_dma_rcfg; 329 330 /* 331 * Hot DMA configuration 332 */ 333 #define NGE_DMA_HOT_CFG 0x048 334 typedef union _nge_dma_hcfg { 335 uint32_t dma_hcfg_val; 336 struct { 337 uint32_t resv0_3:4; 338 uint32_t noti_wstart_pri:3; 339 uint32_t noti_wstart_pri_flag:1; 340 uint32_t cmd_rstart_pri:3; 341 uint32_t cmd_rstart_pri_flag:1; 342 uint32_t cmd_wstart_pri:3; 343 uint32_t cmd_wstart_pri_flag:1; 344 uint32_t resv16_31:16; 345 } hcfg_bits; 346 } nge_dma_hcfg; 347 348 /* 349 * PMU control register 0 for mcp51 350 */ 351 #define NGE_PMU_CNTL0 0x060 352 #define NGE_PMU_CORE_SPD10_BUSY 0x8 353 #define NGE_PMU_CORE_SPD10_IDLE 0xB 354 #define NGE_PMU_CORE_SPD100_BUSY 0x4 355 #define NGE_PMU_CORE_SPD100_IDLE 0x7 356 #define NGE_PMU_CORE_SPD1000_BUSY 0x0 357 #define NGE_PMU_CORE_SPD1000_IDLE 0x3 358 359 typedef union _nge_pmu_cntl0 { 360 uint32_t cntl0_val; 361 struct { 362 uint32_t core_spd10_fp:4; 363 uint32_t core_spd10_idle:4; 364 uint32_t core_spd100_fp:4; 365 uint32_t core_spd100_idle:4; 366 uint32_t core_spd1000_fp:4; 367 uint32_t core_spd1000_idle:4; 368 uint32_t core_sts_cur:8; 369 } cntl0_bits; 370 } nge_pmu_cntl0; 371 372 /* 373 * PMU control register 1 for mcp51 374 */ 375 #define NGE_PMU_CNTL1 0x064 376 typedef union _nge_pmu_cntl1 { 377 uint32_t cntl1_val; 378 struct { 379 uint32_t dev_fp:4; 380 uint32_t dev_idle:4; 381 uint32_t resv8_27:20; 382 uint32_t dev_sts_cur:4; 383 } cntl1_bits; 384 } nge_pmu_cntl1; 385 386 /* 387 * PMU control register 2 for mcp51 388 */ 389 #define NGE_PMU_CNTL2 0x068 390 typedef union _nge_pmu_cntl2 { 391 uint32_t cntl2_val; 392 struct { 393 uint32_t core_override:4; 394 uint32_t resv4_7:4; 395 uint32_t dev_override:4; 396 uint32_t resv12_15:4; 397 uint32_t core_override_en:1; 398 uint32_t dev_override_en:1; 399 uint32_t core_enable:1; 400 uint32_t dev_enable:1; 401 uint32_t rx_wake_dis:1; 402 uint32_t cidle_timer:1; 403 uint32_t didle_timer:1; 404 uint32_t resv23_31:9; 405 } cntl2_bits; 406 } nge_pmu_cntl2; 407 408 /* 409 * PMU core idle limit register for mcp51 410 */ 411 #define NGE_PMU_CIDLE_LIMIT 0x06c 412 #define NGE_PMU_CIDLE_LIMIT_DEF 0xffff 413 414 /* 415 * PMU device idle limit register for mcp51 416 */ 417 #define NGE_PMU_DIDLE_LIMIT 0x070 418 #define NGE_PMU_DIDLE_LIMIT_DEF 0xffff 419 420 /* 421 * PMU core idle count value register for mcp51 422 */ 423 #define NGE_PMU_CIDLE_COUNT 0x074 424 #define NGE_PMU_CIDEL_COUNT_DEF 0xffff 425 426 /* 427 * PMU device idle count value register for mcp51 428 */ 429 #define NGE_PMU_DIDLE_COUNT 0x078 430 #define NGE_PMU_DIDEL_COUNT_DEF 0xffff 431 432 /* 433 * Transmit control 434 */ 435 #define NGE_TX_CNTL 0x080 436 typedef union _nge_tx_cntl { 437 uint32_t cntl_val; 438 struct { 439 uint32_t paen:1; /* only for mcp55, otherwise reserve */ 440 uint32_t resv1:1; 441 uint32_t retry_en:1; 442 uint32_t pad_en:1; 443 uint32_t fappend_en:1; 444 uint32_t two_def_en:1; 445 uint32_t resv6_7:2; 446 uint32_t max_retry:4; 447 uint32_t burst_en:1; 448 uint32_t resv13_15:3; 449 uint32_t retry_emask:1; 450 uint32_t exdef_mask:1; 451 uint32_t def_mask:1; 452 uint32_t lcar_mask:1; 453 uint32_t tlcol_mask:1; 454 uint32_t uflo_err_mask:1; 455 uint32_t resv22_23:2; 456 uint32_t jam_seq_en:1; 457 uint32_t resv25_31:7; 458 } cntl_bits; 459 } nge_tx_cntl; 460 461 /* 462 * Transmit enable 463 * Note: for ck804 or mcp51, this is 8-bit register; 464 * for mcp55, it is a 32-bit register. 465 */ 466 #define NGE_TX_EN 0x084 467 #define NGE_SMU_FREE 0x0 468 #define NGE_SMU_GET 0xf 469 typedef union _nge_tx_en { 470 uint32_t val; 471 struct { 472 uint32_t tx_en:1; 473 uint32_t resv1_7:7; 474 uint32_t smu2mac:4; 475 uint32_t mac2smu:4; 476 uint32_t resv16_31:16; 477 } bits; 478 } nge_tx_en; 479 480 /* 481 * Transmit status 482 */ 483 #define NGE_TX_STA 0x088 484 typedef union _nge_tx_sta { 485 uint32_t sta_val; 486 struct { 487 uint32_t tx_chan_sta:1; 488 uint32_t resv1_15:15; 489 uint32_t retry_err:1; 490 uint32_t exdef:1; 491 uint32_t def:1; 492 uint32_t lcar:1; 493 uint32_t tlcol:1; 494 uint32_t uflo:1; 495 uint32_t resv22_31:10; 496 } sta_bits; 497 } nge_tx_sta; 498 499 /* 500 * Receive control 501 */ 502 #define NGE_RX_CNTL0 0x08c 503 typedef union _nge_rx_cntrl0 { 504 uint32_t cntl_val; 505 struct { 506 uint32_t resv0:1; 507 uint32_t padsen:1; 508 uint32_t fcsren:1; 509 uint32_t paen:1; 510 uint32_t lben:1; 511 uint32_t afen:1; 512 uint32_t runten:1; 513 uint32_t brdis:1; 514 uint32_t rdfen:1; 515 uint32_t slfb:1; 516 uint32_t resv10_15:6; 517 uint32_t runtm:1; 518 uint32_t rlcolm:1; 519 uint32_t maxerm:1; 520 uint32_t lferm:1; 521 uint32_t crcm:1; 522 uint32_t ofolm:1; 523 uint32_t framerm:1; 524 uint32_t resv23_31:9; 525 } cntl_bits; 526 } nge_rx_cntrl0; 527 528 /* 529 * Maximum receive Frame size 530 */ 531 #define NGE_RX_CNTL1 0x090 532 typedef union _nge_rx_cntl1 { 533 uint32_t cntl_val; 534 struct { 535 uint32_t length:14; 536 uint32_t resv14_31:18; 537 } cntl_bits; 538 } nge_rx_cntl1; 539 540 /* 541 * Receive enable register 542 * Note: for ck804 and mcp51, this is a 8-bit register; 543 * for mcp55, it is a 32-bit register. 544 */ 545 #define NGE_RX_EN 0x094 546 typedef union _nge_rx_en { 547 uint8_t val; 548 struct { 549 uint8_t rx_en:1; 550 uint8_t resv1_7:7; 551 } bits; 552 } nge_rx_en; 553 554 /* 555 * Receive status register 556 */ 557 #define NGE_RX_STA 0x098 558 typedef union _nge_rx_sta { 559 uint32_t sta_val; 560 struct { 561 uint32_t rx_chan_sta:1; 562 uint32_t resv1_15:15; 563 uint32_t runt_sta:1; 564 uint32_t rlcol_sta:1; 565 uint32_t mlen_err:1; 566 uint32_t lf_err:1; 567 uint32_t crc_err:1; 568 uint32_t ofol_err:1; 569 uint32_t fram_err:1; 570 uint32_t resv23_31:9; 571 } sta_bits; 572 } nge_rx_sta; 573 574 /* 575 * Backoff Control 576 */ 577 #define NGE_BKOFF_CNTL 0x09c 578 #define BKOFF_RSEED 0x8 579 #define BKOFF_SLIM_GMII 0x3ff 580 #define BKOFF_SLIM_MII 0x7f 581 typedef union _nge_bkoff_cntl { 582 uint32_t cntl_val; 583 struct { 584 uint32_t rseed:8; 585 uint32_t sltm:10; 586 uint32_t resv18_30:13; 587 uint32_t leg_bk_en:1; 588 } bkoff_bits; 589 } nge_bkoff_cntl; 590 591 /* 592 * Transmit defferral timing 593 */ 594 #define NGE_TX_DEF 0x0a0 595 #define TX_TIFG_MII 0x15 596 #define TX_IFG_RGMII_1000_FD 0x14 597 #define TX_IFG_RGMII_OTHER 0x16 598 #define TX_IFG2_MII 0x5 599 #define TX_IFG2_RGMII_10_100 0x7 600 #define TX_IFG2_RGMII_1000 0x5 601 #define TX_IFG2_DEFAULT 0X0 602 #define TX_IFG1_DEFAULT 0xf 603 typedef union _nge_tx_def { 604 uint32_t def_val; 605 struct { 606 uint32_t ifg1_def:8; 607 uint32_t ifg2_def:8; 608 uint32_t if_def:8; 609 uint32_t resv24_31:8; 610 } def_bits; 611 } nge_tx_def; 612 613 /* 614 * Receive defferral timing 615 */ 616 #define NGE_RX_DEf 0x0a4 617 #define RX_DEF_DEFAULT 0x16 618 typedef union _nge_rx_def { 619 uint8_t def_val; 620 struct { 621 uint8_t rifg; 622 } def_bits; 623 } nge_rx_def; 624 625 /* 626 * Low 32 bit unicast address 627 */ 628 #define NGE_UNI_ADDR0 0x0a8 629 union { 630 uint32_t addr_val; 631 struct { 632 uint32_t addr; 633 } addr_bits; 634 } nge_uni_addr0; 635 636 /* 637 * High 32 bit unicast address 638 */ 639 #define NGE_UNI_ADDR1 0x0ac 640 typedef union _nge_uni_addr1 { 641 uint32_t addr_val; 642 struct { 643 uint32_t addr:16; 644 uint32_t resv16_31:16; 645 } addr_bits; 646 } nge_uni_addr1; 647 648 #define LOW_24BITS_MASK 0xffffffULL 649 #define REVERSE_MAC_ELITE 0x211900ULL 650 #define REVERSE_MAC_GIGABYTE 0xe61600ULL 651 #define REVERSE_MAC_ASUS 0x601d00ULL 652 653 /* 654 * Low 32 bit multicast address 655 */ 656 #define NGE_MUL_ADDR0 0x0b0 657 union { 658 uint32_t addr_val; 659 struct { 660 uint32_t addr; 661 }addr_bits; 662 }nge_mul_addr0; 663 664 /* 665 * High 32 bit multicast address 666 */ 667 #define NGE_MUL_ADDR1 0x0b4 668 typedef union _nge_mul_addr1 { 669 uint32_t addr_val; 670 struct { 671 uint32_t addr:16; 672 uint32_t resv16_31:16; 673 }addr_bits; 674 }nge_mul_addr1; 675 676 /* 677 * Low 32 bit multicast mask 678 */ 679 #define NGE_MUL_MASK 0x0b8 680 union { 681 uint32_t mask_val; 682 struct { 683 uint32_t mask; 684 } mask_bits; 685 } nge_mul_mask0; 686 687 /* 688 * High 32 bit multicast mask 689 */ 690 #define NGE_MUL_MASK1 0x0bc 691 union { 692 uint32_t mask_val; 693 struct { 694 uint32_t mask:16; 695 uint32_t resv16_31:16; 696 } mask_bits; 697 } nge_mul_mask1; 698 699 /* 700 * Mac-to Phy Interface 701 */ 702 #define NGE_MAC2PHY 0x0c0 703 #define low_speed 0x0 704 #define fast_speed 0x1 705 #define giga_speed 0x2 706 #define err_speed 0x4 707 #define MII_IN 0x0 708 #define RGMII_IN 0x1 709 #define ERR_IN1 0x3 710 #define ERR_IN2 0x4 711 typedef union _nge_mac2phy { 712 uint32_t m2p_val; 713 struct { 714 uint32_t speed:2; 715 uint32_t resv2_7:6; 716 uint32_t hdup_en:1; 717 uint32_t resv9:1; 718 uint32_t phyintr:1; /* for mcp55 only */ 719 uint32_t phyintrlvl:1; /* for mcp55 only */ 720 uint32_t resv12_27:16; 721 uint32_t in_type:2; 722 uint32_t resv30_31:2; 723 } m2p_bits; 724 } nge_mac2phy; 725 726 /* 727 * Transmit Descriptor Ring address 728 */ 729 #define NGE_TX_DADR 0x100 730 typedef union _nge_tx_addr { 731 uint32_t addr_val; 732 struct { 733 uint32_t resv0_2:3; 734 uint32_t addr:29; 735 } addr_bits; 736 } nge_tx_addr; 737 738 /* 739 * Receive Descriptor Ring address 740 */ 741 #define NGE_RX_DADR 0x104 742 typedef union _nge_rx_addr { 743 uint32_t addr_val; 744 struct { 745 uint32_t resv0_2:3; 746 uint32_t addr:29; 747 } addr_bits; 748 } nge_rx_addr; 749 750 /* 751 * Rx/tx descriptor ring leng 752 * Note: for mcp55, tdlen/rdlen are 14 bit. 753 */ 754 #define NGE_RXTX_DLEN 0x108 755 typedef union _nge_rxtx_dlen { 756 uint32_t dlen_val; 757 struct { 758 uint32_t tdlen:14; 759 uint32_t resv14_15:2; 760 uint32_t rdlen:14; 761 uint32_t resv30_31:2; 762 } dlen_bits; 763 } nge_rxtx_dlen; 764 765 /* 766 * Transmit polling register 767 */ 768 #define NGE_TX_POLL 0x10c 769 #define TX_POLL_INTV_1G 10 770 #define TX_POLL_INTV_100M 100 771 #define TX_POLL_INTV_10M 1000 772 773 typedef union _nge_tx_poll { 774 uint32_t poll_val; 775 struct { 776 uint32_t tpi:16; 777 uint32_t tpen:1; 778 uint32_t resv17_31:15; 779 } poll_bits; 780 } nge_tx_poll; 781 782 /* 783 * Receive polling register 784 */ 785 #define NGE_RX_POLL 0x110 786 #define RX_POLL_INTV_1G 10 787 #define RX_POLL_INTV_100M 100 788 #define RX_POLL_INTV_10M 1000 789 typedef union _nge_rx_poll { 790 uint32_t poll_val; 791 struct { 792 uint32_t rpi:16; 793 uint32_t rpen:1; 794 uint32_t resv17_31:15; 795 } poll_bits; 796 } nge_rx_poll; 797 798 /* 799 * Transmit polling count 800 */ 801 #define NGE_TX_PCNT 0x114 802 union { 803 uint32_t cnt_val; 804 struct { 805 uint32_t pcnt:32; 806 } cnt_bits; 807 } nge_tx_pcnt; 808 809 /* 810 * Receive polling count 811 */ 812 #define NGE_RX_PCNT 0x118 813 union { 814 uint32_t cnt_val; 815 struct { 816 uint32_t pcnt:32; 817 } cnt_bits; 818 } nge_rx_pcnt; 819 820 821 /* 822 * Current tx's descriptor address 823 */ 824 #define NGE_TX_CUR_DADR 0x11c 825 union { 826 uint32_t addr_val; 827 struct { 828 uint32_t resv0_2:3; 829 uint32_t addr:29; 830 } addr_bits; 831 } nge_tx_cur_addr; 832 833 /* 834 * Current rx's descriptor address 835 */ 836 #define NGE_RX_CUR_DADR 0x120 837 union { 838 uint32_t addr_val; 839 struct { 840 uint32_t resv0_2:3; 841 uint32_t addr:29; 842 } addr_bits; 843 } nge_rx_cur_addr; 844 845 /* 846 * Current tx's data buffer address 847 */ 848 #define NGE_TX_CUR_PRD0 0x124 849 union { 850 uint32_t prd0_val; 851 struct { 852 uint32_t prd0:32; 853 } prd0_bits; 854 } nge_tx_cur_prd0; 855 856 /* 857 * Current tx's data buffer status 858 */ 859 #define NGE_TX_CUR_PRD1 0x128 860 union { 861 uint32_t prd1_val; 862 struct { 863 uint32_t rebytes:16; 864 uint32_t status:16; 865 } prd1_bits; 866 } nge_tx_cur_prd1; 867 868 /* 869 * Current rx's data buffer address 870 */ 871 #define NGE_RX_CUR_PRD0 0x12c 872 union { 873 uint32_t prd0_val; 874 struct { 875 uint32_t prd0:32; 876 }prd0_bits; 877 }nge_rx_cur_prd0; 878 879 /* 880 * Current rx's data buffer status 881 */ 882 #define NGE_RX_CUR_PRD1 0x130 883 884 /* 885 * Next tx's descriptor address 886 */ 887 #define NGE_TX_NXT_DADR 0x134 888 union { 889 uint32_t dadr_val; 890 struct { 891 uint32_t addr:32; 892 }addr_bits; 893 }nge_tx_nxt_dadr; 894 895 /* 896 * Next rx's descriptor address 897 */ 898 #define NGE_RX_NXT_DADR 0x138 899 union { 900 uint32_t dadr_val; 901 struct { 902 uint32_t addr:32; 903 } addr_bits; 904 } nge_rx_nxt_dadr; 905 906 /* 907 * Transmit fifo watermark 908 */ 909 #define NGE_TX_FIFO_WM 0x13c 910 #define TX_FIFO_TBFW 0 911 #define TX_FIFO_NOB_WM_MII 1 912 #define TX_FIFO_NOB_WM_GMII 8 913 #define TX_FIFO_DATA_LWM 0x20 914 #define TX_FIFO_PRD_LWM 0x8 915 #define TX_FIFO_PRD_HWM 0x38 916 typedef union _nge_tx_fifo_wm { 917 uint32_t wm_val; 918 struct { 919 uint32_t data_lwm:9; 920 uint32_t resv8_11:3; 921 uint32_t prd_lwm:6; 922 uint32_t uprd_hwm:6; 923 uint32_t nbfb_wm:4; 924 uint32_t fb_wm:4; 925 } wm_bits; 926 } nge_tx_fifo_wm; 927 928 /* 929 * Receive fifo watermark 930 */ 931 #define NGE_RX_FIFO_WM 0x140 932 typedef union _nge_rx_fifo_wm { 933 uint32_t wm_val; 934 struct { 935 uint32_t data_hwm:9; 936 uint32_t resv9_11:3; 937 uint32_t prd_lwm:4; 938 uint32_t resv16_17:2; 939 uint32_t prd_hwm:4; 940 uint32_t resv22_31:10; 941 } wm_bits; 942 } nge_rx_fifo_wm; 943 944 /* 945 * Chip mode control 946 */ 947 #define NGE_MODE_CNTL 0x144 948 #define DESC_MCP1 0x0 949 #define DESC_OFFLOAD 0x1 950 #define DESC_HOT 0x2 951 #define DESC_RESV 0x3 952 #define MACHINE_BUSY 0x0 953 #define MACHINE_IDLE 0x1 954 typedef union _nge_mode_cntl { 955 uint32_t mode_val; 956 struct { 957 uint32_t txdm:1; 958 uint32_t rxdm:1; 959 uint32_t dma_dis:1; 960 uint32_t dma_status:1; 961 uint32_t bm_reset:1; 962 uint32_t resv5:1; 963 uint32_t vlan_strip:1; /* mcp55 chip only */ 964 uint32_t vlan_ins:1; /* mcp55 chip only */ 965 uint32_t desc_type:2; 966 uint32_t rx_sum_en:1; 967 uint32_t tx_prd_cu_en:1; 968 uint32_t w64_dis:1; 969 uint32_t tx_rcom_en:1; 970 uint32_t rx_filter_en:1; 971 uint32_t resv15:1; 972 uint32_t resv16:1; /* ck804 and mcp51 only */ 973 uint32_t resv17:1; /* ck804 and mcp51 only */ 974 uint32_t resv18:1; /* ck804 and mcp51 only */ 975 uint32_t resv19_21:3; 976 uint32_t tx_fetch_prd:1; /* mcp51/mcp55 only */ 977 uint32_t rx_fetch_prd:1; /* mcp51/mcp55 only */ 978 uint32_t resv24_29:6; 979 uint32_t rx_status:1; 980 uint32_t tx_status:1; 981 } mode_bits; 982 } nge_mode_cntl; 983 984 #define NGE_TX_DADR_HI 0x148 985 #define NGE_RX_DADR_HI 0x14c 986 987 /* 988 * Mii interrupt register 989 * Note: for mcp55, this is a 32-bit register. 990 */ 991 #define NGE_MINTR_SRC 0x180 992 typedef union _nge_mintr_src { 993 uint8_t src_val; 994 struct { 995 uint8_t mrei:1; 996 uint8_t mcc2:1; 997 uint8_t mcc1:1; 998 uint8_t mapi:1; 999 uint8_t mpdi:1; 1000 uint8_t resv5_7:3; 1001 } src_bits; 1002 } nge_mintr_src; 1003 1004 /* 1005 * Mii interrupt mask 1006 * Note: for mcp55, this is a 32-bit register. 1007 */ 1008 #define NGE_MINTR_MASK 0x184 1009 typedef union _nge_mintr_mask { 1010 uint8_t mask_val; 1011 struct { 1012 uint8_t mrei:1; 1013 uint8_t mcc2:1; 1014 uint8_t mcc1:1; 1015 uint8_t mapi:1; 1016 uint8_t mpdi:1; 1017 uint8_t resv5_7:3; 1018 } mask_bits; 1019 } nge_mintr_mask; 1020 1021 /* 1022 * Mii control and status 1023 */ 1024 #define NGE_MII_CS 0x188 1025 #define MII_POLL_INTV 0x4 1026 typedef union _nge_mii_cs { 1027 uint32_t cs_val; 1028 struct { 1029 uint32_t excap:1; 1030 uint32_t jab_dec:1; 1031 uint32_t lk_up:1; 1032 uint32_t ana_cap:1; 1033 uint32_t rfault:1; 1034 uint32_t auto_neg:1; 1035 uint32_t mfps:1; 1036 uint32_t resv7:1; 1037 uint32_t exst:1; 1038 uint32_t hdup_100m_t2:1; 1039 uint32_t fdup_100m_t2:1; 1040 uint32_t hdup_10m:1; 1041 uint32_t fdup_10m:1; 1042 uint32_t hdup_100m_x:1; 1043 uint32_t fdup_100m_x:1; 1044 uint32_t cap_100m_t4:1; 1045 uint32_t ap_intv:4; 1046 uint32_t ap_en:1; 1047 uint32_t resv21_23:3; 1048 uint32_t ap_paddr:5; 1049 uint32_t resv29_31:3; 1050 } cs_bits; 1051 } nge_mii_cs; 1052 1053 /* 1054 * Mii Clock timer register 1055 */ 1056 #define NGE_MII_TM 0x18c 1057 typedef union _nge_mii_tm { 1058 uint16_t tm_val; 1059 struct { 1060 uint16_t timer_interv:8; 1061 uint16_t timer_en:1; 1062 uint16_t resv9_14:6; 1063 uint16_t timer_status:1; 1064 } tm_bits; 1065 } nge_mii_tm; 1066 1067 /* 1068 * Mdio address 1069 */ 1070 #define NGE_MDIO_ADR 0x190 1071 typedef union _nge_mdio_adr { 1072 uint16_t adr_val; 1073 struct { 1074 uint16_t phy_reg:5; 1075 uint16_t phy_adr:5; 1076 uint16_t mdio_rw:1; 1077 uint16_t resv11_14:4; 1078 uint16_t mdio_clc:1; 1079 } adr_bits; 1080 } nge_mdio_adr; 1081 1082 /* 1083 * Mdio data 1084 */ 1085 #define NGE_MDIO_DATA 0x194 1086 1087 /* 1088 * Power Management and Control 1089 */ 1090 #define NGE_PM_CNTL 0x200 1091 typedef union _nge_pm_cntl { 1092 uint32_t cntl_val; 1093 struct { 1094 /* 1095 * mp_en: Magic Packet Enable 1096 * pm_en: Pattern Match Enable 1097 * lc_en: Link Change Enable 1098 */ 1099 uint32_t mp_en_d0:1; 1100 uint32_t pm_en_d0:1; 1101 uint32_t lc_en_d0:1; 1102 uint32_t resv3:1; 1103 uint32_t mp_en_d1:1; 1104 uint32_t pm_en_d1:1; 1105 uint32_t lc_en_d1:1; 1106 uint32_t resv7:1; 1107 uint32_t mp_en_d2:1; 1108 uint32_t pm_en_d2:1; 1109 uint32_t lc_en_d2:1; 1110 uint32_t resv11:1; 1111 uint32_t mp_en_d3:1; 1112 uint32_t pm_en_d3:1; 1113 uint32_t lc_en_d3:1; 1114 uint32_t resv15:1; 1115 uint32_t pat_match_en:5; 1116 uint32_t resv21_23:3; 1117 uint32_t pat_match_stat:5; 1118 uint32_t magic_status:1; 1119 uint32_t netman_status:1; 1120 uint32_t resv31:1; 1121 } cntl_bits; 1122 } nge_pm_cntl; 1123 1124 #define NGE_MPT_CRC0 0x204 1125 #define NGE_PMC_MK00 0x208 1126 #define NGE_PMC_MK01 0x20C 1127 #define NGE_PMC_MK02 0x210 1128 #define NGE_PMC_MK03 0x214 1129 #define NGE_MPT_CRC1 0x218 1130 #define NGE_PMC_MK10 0x21c 1131 #define NGE_PMC_MK11 0x220 1132 #define NGE_PMC_MK12 0x224 1133 #define NGE_PMC_MK13 0x228 1134 #define NGE_MPT_CRC2 0x22c 1135 #define NGE_PMC_MK20 0x230 1136 #define NGE_PMC_MK21 0x234 1137 #define NGE_PMC_MK22 0x238 1138 #define NGE_PMC_MK23 0x23c 1139 #define NGE_MPT_CRC3 0x240 1140 #define NGE_PMC_MK30 0x244 1141 #define NGE_PMC_MK31 0x248 1142 #define NGE_PMC_MK32 0x24c 1143 #define NGE_PMC_MK33 0x250 1144 #define NGE_MPT_CRC4 0x254 1145 #define NGE_PMC_MK40 0x258 1146 #define NGE_PMC_MK41 0x25c 1147 #define NGE_PMC_MK42 0x260 1148 #define NGE_PMC_MK43 0x264 1149 #define NGE_PMC_ALIAS 0x268 1150 #define NGE_PMCSR_ALIAS 0x26c 1151 1152 /* 1153 * Seeprom control 1154 */ 1155 #define NGE_EP_CNTL 0x500 1156 #define EEPROM_CLKDIV 249 1157 #define EEPROM_WAITCLK 0x7 1158 typedef union _nge_cp_cntl { 1159 uint32_t cntl_val; 1160 struct { 1161 uint32_t clkdiv:8; 1162 uint32_t rom_size:3; 1163 uint32_t resv11:1; 1164 uint32_t word_wid:1; 1165 uint32_t resv13_15:3; 1166 uint32_t wait_slots:4; 1167 uint32_t resv20_31:12; 1168 } cntl_bits; 1169 } nge_cp_cntl; 1170 1171 /* 1172 * Seeprom cmd control 1173 */ 1174 #define NGE_EP_CMD 0x504 1175 #define SEEPROM_CMD_READ 0x0 1176 #define SEEPROM_CMD_WRITE_ENABLE 0x1 1177 #define SEEPROM_CMD_ERASE 0x2 1178 #define SEEPROM_CMD_WRITE 0x3 1179 #define SEEPROM_CMD_ERALSE_ALL 0x4 1180 #define SEEPROM_CMD_WRITE_ALL 0x5 1181 #define SEEPROM_CMD_WRITE_DIS 0x6 1182 #define SEEPROM_READY 0x1 1183 typedef union _nge_ep_cmd { 1184 uint32_t cmd_val; 1185 struct { 1186 uint32_t addr:16; 1187 uint32_t cmd:3; 1188 uint32_t resv19_30:12; 1189 uint32_t sts:1; 1190 } cmd_bits; 1191 } nge_ep_cmd; 1192 1193 /* 1194 * Seeprom data register 1195 */ 1196 #define NGE_EP_DATA 0x508 1197 typedef union _nge_ep_data { 1198 uint32_t data_val; 1199 struct { 1200 uint32_t data:16; 1201 uint32_t resv16_31:16; 1202 } data_bits; 1203 } nge_ep_data; 1204 1205 /* 1206 * Power management control 2nd register (since MCP51) 1207 */ 1208 #define NGE_PM_CNTL2 0x600 1209 typedef union _nge_pm_cntl2 { 1210 uint32_t cntl_val; 1211 struct { 1212 uint32_t phy_coma_set:1; 1213 uint32_t phy_coma_status:1; 1214 uint32_t resv2_3:2; 1215 uint32_t resv4:1; 1216 uint32_t resv5_7:3; 1217 uint32_t resv8_11:4; 1218 uint32_t resv12_15:4; 1219 uint32_t pmt5_en:1; 1220 uint32_t pmt6_en:1; 1221 uint32_t pmt7_en:1; 1222 uint32_t resv19_23:5; 1223 uint32_t pmt5_status:1; 1224 uint32_t pmt6_status:1; 1225 uint32_t pmt7_status:1; 1226 uint32_t resv27_31:5; 1227 } cntl_bits; 1228 } nge_pm_cntl2; 1229 1230 1231 /* 1232 * ASF RAM 0x800-0xfff 1233 */ 1234 1235 /* 1236 * Hardware-defined Statistics Block Offsets 1237 * 1238 * These are given in the manual as addresses in NIC memory, starting 1239 * from the NIC statistics area base address of 0x2000; 1240 */ 1241 1242 #define KS_BASE 0x0280 1243 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint32_t)) 1244 1245 typedef enum { 1246 KS_ifHOutOctets = KS_ADDR(0x0280), 1247 KS_ifHOutZeroRetranCount, 1248 KS_ifHOutOneRetranCount, 1249 KS_ifHOutMoreRetranCount, 1250 KS_ifHOutColCount, 1251 KS_ifHOutFifoovCount, 1252 KS_ifHOutLOCCount, 1253 KS_ifHOutExDecCount, 1254 KS_ifHOutRetryCount, 1255 1256 KS_ifHInFrameErrCount, 1257 KS_ifHInExtraOctErrCount, 1258 KS_ifHInLColErrCount, 1259 KS_ifHInRuntCount, 1260 KS_ifHInOversizeErrCount, 1261 KS_ifHInFovErrCount, 1262 KS_ifHInFCSErrCount, 1263 KS_ifHInAlignErrCount, 1264 KS_ifHInLenErrCount, 1265 KS_ifHInUniPktsCount, 1266 KS_ifHInBroadPksCount, 1267 KS_ifHInMulPksCount, 1268 KS_STATS_SIZE = KS_ADDR(0x2d0) 1269 1270 } nge_stats_offset_t; 1271 1272 /* 1273 * Hardware-defined Statistics Block 1274 * 1275 * Another view of the statistic block, as a array and a structure ... 1276 */ 1277 1278 typedef union { 1279 uint64_t a[KS_STATS_SIZE]; 1280 struct { 1281 uint64_t OutOctets; 1282 uint64_t OutZeroRetranCount; 1283 uint64_t OutOneRetranCount; 1284 uint64_t OutMoreRetranCount; 1285 uint64_t OutColCount; 1286 uint64_t OutFifoovCount; 1287 uint64_t OutLOCCount; 1288 uint64_t OutExDecCount; 1289 uint64_t OutRetryCount; 1290 1291 uint64_t InFrameErrCount; 1292 uint64_t InExtraOctErrCount; 1293 uint64_t InLColErrCount; 1294 uint64_t InRuntCount; 1295 uint64_t InOversizeErrCount; 1296 uint64_t InFovErrCount; 1297 uint64_t InFCSErrCount; 1298 uint64_t InAlignErrCount; 1299 uint64_t InLenErrCount; 1300 uint64_t InUniPktsCount; 1301 uint64_t InBroadPksCount; 1302 uint64_t InMulPksCount; 1303 } s; 1304 } nge_hw_statistics_t; 1305 1306 /* 1307 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1308 */ 1309 1310 #define NGE_PHY_NUMBER 32 1311 #define MII_LP_ASYM_PAUSE 0x0800 1312 #define MII_LP_PAUSE 0x0400 1313 1314 #define MII_100BASE_T4 0x0200 1315 #define MII_100BASET_FD 0x0100 1316 #define MII_100BASET_HD 0x0080 1317 #define MII_10BASET_FD 0x0040 1318 #define MII_10BASET_HD 0x0020 1319 1320 #define MII_ID_MARVELL 0x5043 1321 #define MII_ID_CICADA 0x03f1 1322 #define MII_IDL_MASK 0xfc00 1323 #define MII_AN_LPNXTPG 8 1324 1325 1326 #define MII_IEEE_EXT_STATUS 15 1327 1328 /* 1329 * New bits in the MII_CONTROL register 1330 */ 1331 #define MII_CONTROL_1000MB 0x0040 1332 1333 /* 1334 * New bits in the MII_AN_ADVERT register 1335 */ 1336 #define MII_ABILITY_ASYM_PAUSE 0x0800 1337 #define MII_ABILITY_PAUSE 0x0400 1338 1339 /* 1340 * Values for the <selector> field of the MII_AN_ADVERT register 1341 */ 1342 #define MII_AN_SELECTOR_8023 0x0001 1343 1344 /* 1345 * Bits in the MII_1000BASE_T_CONTROL register 1346 * 1347 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1348 * (otherwise, roles are automatically negotiated). When this bit is set, 1349 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1350 */ 1351 #define MII_1000BASE_T_CONTROL 9 1352 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1353 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1354 #define MII_1000BT_CTL_ADV_FDX 0x0200 1355 #define MII_1000BT_CTL_ADV_HDX 0x0100 1356 1357 /* 1358 * Bits in the MII_1000BASE_T_STATUS register 1359 */ 1360 #define MII_1000BASE_T_STATUS 10 1361 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1362 #define MII_1000BT_STAT_MASTER_MODE 0x4000 1363 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1364 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1365 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1366 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1367 1368 #define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2) 1369 #define CICADA_125MHZ_CLOCK_ENABLE 0x0001 1370 1371 #define MII_CICADA_10BASET_CONTROL MII_VENDOR(6) 1372 #define MII_CICADA_DISABLE_ECHO_MODE 0x2000 1373 1374 #define MII_CICADA_EXT_CONTROL MII_VENDOR(7) 1375 #define MII_CICADA_MODE_SELECT_BITS 0xf000 1376 #define MII_CICADA_MODE_SELECT_RGMII 0x1000 1377 #define MII_CICADA_POWER_SUPPLY_BITS 0x0e00 1378 #define MII_CICADA_POWER_SUPPLY_3_3V 0x0000 1379 #define MII_CICADA_POWER_SUPPLY_2_5V 0x0200 1380 1381 #define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12) 1382 #define MII_CICADA_PIN_PRORITY_SETTING 0x0004 1383 #define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000 1384 1385 1386 #define NGE_REG_SIZE 0xfff 1387 #define NGE_MII_SIZE 0x20 1388 #define NGE_SEEROM_SIZE 0x800 1389 /* 1390 * Legacy rx's bd which does not support 1391 * any hardware offload 1392 */ 1393 typedef struct _legacy_rx_bd { 1394 uint32_t host_buf_addr; 1395 union { 1396 uint32_t cntl_val; 1397 struct { 1398 uint32_t bcnt:16; 1399 uint32_t end:1; 1400 uint32_t miss:1; 1401 uint32_t extra:1; 1402 uint32_t inten:1; 1403 uint32_t bam:1; 1404 uint32_t mam:1; 1405 uint32_t pam:1; 1406 uint32_t runt:1; 1407 uint32_t lcol:1; 1408 uint32_t max:1; 1409 uint32_t lfer:1; 1410 uint32_t crc:1; 1411 uint32_t ofol:1; 1412 uint32_t fram:1; 1413 uint32_t err:1; 1414 uint32_t own:1; 1415 } cntl_bits; 1416 } cntl_status; 1417 } legacy_rx_bd, *plegacy_rx_bd; 1418 1419 /* 1420 * Stand offload rx's bd which supports hareware checksum 1421 * for tcp/ip 1422 */ 1423 #define CK8G_NO_HSUM 0x0 1424 #define CK8G_TCP_SUM_ERR 0x1 1425 #define CK8G_UDP_SUM_ERR 0x2 1426 #define CK8G_IP_HSUM_ERR 0x3 1427 #define CK8G_IP_HSUM 0x4 1428 #define CK8G_TCP_SUM 0x5 1429 #define CK8G_UDP_SUM 0x6 1430 #define CK8G_RESV 0x7 1431 typedef struct _sum_rx_bd { 1432 uint32_t host_buf_addr; 1433 union { 1434 uint32_t cntl_val; 1435 struct { 1436 uint32_t bcnt:14; 1437 uint32_t resv14_29:16; 1438 uint32_t inten:1; 1439 uint32_t own:1; 1440 } control_bits; 1441 struct { 1442 uint32_t bcnt:14; 1443 uint32_t resv14:1; 1444 uint32_t bam:1; 1445 uint32_t mam:1; 1446 uint32_t pam:1; 1447 uint32_t runt:1; 1448 uint32_t lcol:1; 1449 uint32_t max:1; 1450 uint32_t lfer:1; 1451 uint32_t crc:1; 1452 uint32_t ofol:1; 1453 uint32_t fram:1; 1454 uint32_t extra:1; 1455 uint32_t l3_l4_sum:3; 1456 uint32_t rend:1; 1457 uint32_t err:1; 1458 uint32_t own:1; 1459 } status_bits; 1460 } cntl_status; 1461 } sum_rx_bd, *psum_rx_bd; 1462 /* 1463 * Hot offload rx's bd which support 64bit access and 1464 * full-tcp hardware offload 1465 */ 1466 typedef struct _hot_rx_bd { 1467 uint32_t host_buf_addr_hi; 1468 uint32_t host_buf_addr_lo; 1469 uint32_t sw_tag; 1470 union { 1471 uint32_t cntl_val; 1472 struct { 1473 uint32_t bcnt:14; 1474 uint32_t resv14_29:16; 1475 uint32_t inten:1; 1476 uint32_t own:1; 1477 } control_bits; 1478 1479 struct { 1480 uint32_t bcnt:14; 1481 uint32_t ctmach_rd:1; 1482 uint32_t bam:1; 1483 uint32_t mam:1; 1484 uint32_t pam:1; 1485 uint32_t runt:1; 1486 uint32_t lcol:1; 1487 uint32_t max:1; 1488 uint32_t lfer:1; 1489 uint32_t crc:1; 1490 uint32_t ofol:1; 1491 uint32_t fram:1; 1492 uint32_t extra:1; 1493 uint32_t l3_l4_sum:3; 1494 uint32_t rend:1; 1495 uint32_t err:1; 1496 uint32_t own:1; 1497 } status_bits_legacy; 1498 } cntl_status; 1499 } hot_rx_bd, *phot_rx_bd; 1500 1501 /* 1502 * Legacy tx's bd which does not support 1503 * any hardware offload 1504 */ 1505 typedef struct _legacy_tx_bd { 1506 uint32_t host_buf_addr; 1507 union { 1508 uint32_t cntl_val; 1509 struct { 1510 uint32_t bcnt:16; 1511 uint32_t end:1; 1512 uint32_t resv17_23:7; 1513 uint32_t inten:1; 1514 uint32_t resv25_30:6; 1515 uint32_t own:1; 1516 } control_bits; 1517 1518 struct { 1519 uint32_t bcnt:16; 1520 uint32_t end:1; 1521 uint32_t rtry:1; 1522 uint32_t trc:4; 1523 uint32_t inten:1; 1524 uint32_t exdef:1; 1525 uint32_t def:1; 1526 uint32_t lcar:1; 1527 uint32_t lcol:1; 1528 uint32_t uflo:1; 1529 uint32_t err:1; 1530 uint32_t own:1; 1531 } status_bits; 1532 } cntl_status; 1533 } legacy_tx_bd, *plegacy_tx_bd; 1534 1535 /* 1536 * Stand offload tx's bd which supports hareware checksum 1537 * for tcp/ip 1538 */ 1539 typedef struct _sum_tx_bd { 1540 uint32_t host_buf_addr; 1541 union { 1542 uint32_t cntl_val; 1543 struct { 1544 uint32_t bcnt:14; 1545 uint32_t resv14_25:12; 1546 uint32_t tcp_hsum:1; 1547 uint32_t ip_hsum:1; 1548 uint32_t segen:1; 1549 uint32_t end:1; 1550 uint32_t inten:1; 1551 uint32_t own:1; 1552 } control_sum_bits; 1553 1554 struct { 1555 uint32_t bcnt:14; 1556 uint32_t mss:14; 1557 uint32_t segen:1; 1558 uint32_t end:1; 1559 uint32_t inten:1; 1560 uint32_t own:1; 1561 } control_tso_bits; 1562 1563 struct { 1564 uint32_t bcnt:14; 1565 uint32_t resv14_17:4; 1566 uint32_t rtry:1; 1567 uint32_t trc:4; 1568 uint32_t inten:1; 1569 uint32_t exdef:1; 1570 uint32_t def:1; 1571 uint32_t lcar:1; 1572 uint32_t lcol:1; 1573 uint32_t uflo:1; 1574 uint32_t end:1; 1575 uint32_t err:1; 1576 uint32_t own:1; 1577 } status_bits; 1578 } control_status; 1579 } sum_tx_bd, *psum_tx_bd; 1580 1581 /* 1582 * Hot offload tx's bd which support 64bit access and 1583 * full-tcp hardware offload 1584 */ 1585 1586 typedef struct _hot_tx_bd { 1587 uint32_t host_buf_addr_hi; 1588 uint32_t host_buf_addr_lo; 1589 union { 1590 uint32_t parm_val; 1591 struct { 1592 uint32_t resv0_15:16; 1593 uint32_t resv16:1; 1594 uint32_t resv17:1; 1595 uint32_t resv18_31:14; 1596 } parm_bits; 1597 } hot_parms; 1598 1599 union { 1600 uint32_t cntl_val; 1601 struct { 1602 uint32_t bcnt:14; 1603 uint32_t resv14_25:12; 1604 uint32_t tcp_hsum:1; 1605 uint32_t ip_hsum:1; 1606 uint32_t segen:1; 1607 uint32_t end:1; 1608 uint32_t inten:1; 1609 uint32_t own:1; 1610 } control_sum_bits; 1611 1612 struct { 1613 uint32_t bcnt:14; 1614 uint32_t mss:14; 1615 uint32_t segen:1; 1616 uint32_t end:1; 1617 uint32_t inten:1; 1618 uint32_t own:1; 1619 } control_tso_bits; 1620 1621 struct { 1622 uint32_t bcnt:14; 1623 uint32_t resv14_17:4; 1624 uint32_t rtry:1; 1625 uint32_t trc:4; 1626 uint32_t inten:1; 1627 uint32_t exdef:1; 1628 uint32_t def:1; 1629 uint32_t lcar:1; 1630 uint32_t lcol:1; 1631 uint32_t uflo:1; 1632 uint32_t end:1; 1633 uint32_t err:1; 1634 uint32_t own:1; 1635 } status_bits; 1636 } control_status; 1637 } hot_tx_bd, *phot_tx_bd; 1638 1639 #ifdef __cplusplus 1640 } 1641 #endif 1642 1643 #endif /* _SYS_NGE_CHIP_H */ 1644