1 /* 2 * Solaris driver for ethernet cards based on the Macronix 98715 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MXFEIMPL_H 33 #define _MXFEIMPL_H 34 35 #pragma ident "%Z%%M% %I% %E% SMI" 36 37 /* 38 * This entire file is private to the MXFE driver. 39 */ 40 41 #ifdef _KERNEL 42 43 /* 44 * Compile time tunables. 45 */ 46 #define MXFE_TXRING 128 /* number of xmt buffers */ 47 #define MXFE_RXRING 256 /* number of rcv buffers */ 48 #define MXFE_TXRECLAIM 32 /* when to reclaim tx buffers (txavail) */ 49 #define MXFE_TXRESCHED 120 /* when to resched (txavail) */ 50 #define MXFE_LINKTIMER 5000 /* how often we check link state (msec) */ 51 #define MXFE_HEADROOM 34 /* headroom in packet (should be 2 modulo 4) */ 52 53 /* 54 * Constants, do not change. The bufsize is setup to make sure it comes 55 * in at a whole number of cache lines, even for 32-long-word aligned 56 * caches. 57 */ 58 #define MXFE_BUFSZ (1664) /* big enough for a vlan frame */ 59 #define MXFE_SETUP_LEN 192 /* size of a setup frame */ 60 61 typedef struct mxfe mxfe_t; 62 typedef struct mxfe_card mxfe_card_t; 63 typedef struct mxfe_nd mxfe_nd_t; 64 typedef struct mxfe_rxbuf mxfe_rxbuf_t; 65 typedef struct mxfe_txbuf mxfe_txbuf_t; 66 typedef struct mxfe_desc mxfe_desc_t; 67 typedef int (*mxfe_nd_pf_t)(mxfe_t *, mblk_t *, mxfe_nd_t *); 68 69 struct mxfe_card { 70 uint16_t card_venid; /* PCI vendor id */ 71 uint16_t card_devid; /* PCI device id */ 72 uint16_t card_revid; /* PCI revision id */ 73 uint16_t card_revmask; 74 char *card_cardname; /* Description of the card */ 75 unsigned card_model; /* Card specific flags */ 76 }; 77 78 struct mxfe_nd { 79 mxfe_nd_t *nd_next; 80 char *nd_name; 81 mxfe_nd_pf_t nd_get; 82 mxfe_nd_pf_t nd_set; 83 intptr_t nd_arg1; 84 intptr_t nd_arg2; 85 }; 86 87 /* 88 * Device instance structure, one per PCI card. 89 */ 90 struct mxfe { 91 dev_info_t *mxfe_dip; 92 mac_handle_t mxfe_mh; 93 mxfe_card_t *mxfe_cardp; 94 ushort_t mxfe_cachesize; 95 ushort_t mxfe_sromwidth; 96 int mxfe_flags; 97 kmutex_t mxfe_xmtlock; 98 kmutex_t mxfe_intrlock; 99 ddi_iblock_cookie_t mxfe_icookie; 100 101 /* 102 * Register access. 103 */ 104 uint32_t *mxfe_regs; 105 ddi_acc_handle_t mxfe_regshandle; 106 107 /* 108 * Receive descriptors. 109 */ 110 int mxfe_rxhead; 111 struct mxfe_desc *mxfe_rxdescp; 112 ddi_dma_handle_t mxfe_rxdesc_dmah; 113 ddi_acc_handle_t mxfe_rxdesc_acch; 114 uint32_t mxfe_rxdesc_paddr; 115 struct mxfe_rxbuf **mxfe_rxbufs; 116 117 /* 118 * Transmit descriptors. 119 */ 120 int mxfe_txreclaim; 121 int mxfe_txsend; 122 int mxfe_txavail; 123 struct mxfe_desc *mxfe_txdescp; 124 ddi_dma_handle_t mxfe_txdesc_dmah; 125 ddi_acc_handle_t mxfe_txdesc_acch; 126 uint32_t mxfe_txdesc_paddr; 127 struct mxfe_txbuf **mxfe_txbufs; 128 hrtime_t mxfe_txstall_time; 129 boolean_t mxfe_wantw; 130 131 /* 132 * Address management. 133 */ 134 uchar_t mxfe_curraddr[ETHERADDRL]; 135 boolean_t mxfe_promisc; 136 137 /* 138 * Link state. 139 */ 140 int mxfe_linkstate; 141 int mxfe_lastifspeed; 142 int mxfe_lastduplex; 143 int mxfe_lastlinkup; 144 int mxfe_linkup; 145 int mxfe_duplex; 146 int mxfe_ifspeed; 147 boolean_t mxfe_resetting; /* no link warning */ 148 149 /* 150 * NDD related support. 151 */ 152 mxfe_nd_t *mxfe_ndp; 153 154 /* 155 * Transceiver stuff. 156 */ 157 int mxfe_phyaddr; 158 int mxfe_phyid; 159 int mxfe_phyinuse; 160 int mxfe_adv_aneg; 161 int mxfe_adv_100T4; 162 int mxfe_adv_100fdx; 163 int mxfe_adv_100hdx; 164 int mxfe_adv_10fdx; 165 int mxfe_adv_10hdx; 166 int mxfe_forcephy; 167 int mxfe_bmsr; 168 int mxfe_anlpar; 169 int mxfe_aner; 170 171 /* 172 * Kstats. 173 */ 174 kstat_t *mxfe_intrstat; 175 uint64_t mxfe_ipackets; 176 uint64_t mxfe_opackets; 177 uint64_t mxfe_rbytes; 178 uint64_t mxfe_obytes; 179 uint64_t mxfe_brdcstrcv; 180 uint64_t mxfe_multircv; 181 uint64_t mxfe_brdcstxmt; 182 uint64_t mxfe_multixmt; 183 184 unsigned mxfe_norcvbuf; 185 unsigned mxfe_noxmtbuf; 186 unsigned mxfe_errrcv; 187 unsigned mxfe_errxmt; 188 unsigned mxfe_missed; 189 unsigned mxfe_underflow; 190 unsigned mxfe_overflow; 191 unsigned mxfe_align_errors; 192 unsigned mxfe_fcs_errors; 193 unsigned mxfe_carrier_errors; 194 unsigned mxfe_collisions; 195 unsigned mxfe_ex_collisions; 196 unsigned mxfe_tx_late_collisions; 197 unsigned mxfe_defer_xmts; 198 unsigned mxfe_first_collisions; 199 unsigned mxfe_multi_collisions; 200 unsigned mxfe_sqe_errors; 201 unsigned mxfe_macxmt_errors; 202 unsigned mxfe_macrcv_errors; 203 unsigned mxfe_toolong_errors; 204 unsigned mxfe_runt; 205 unsigned mxfe_jabber; 206 }; 207 208 struct mxfe_rxbuf { 209 caddr_t rxb_buf; 210 ddi_dma_handle_t rxb_dmah; 211 ddi_acc_handle_t rxb_acch; 212 uint32_t rxb_paddr; 213 }; 214 215 struct mxfe_txbuf { 216 /* bcopy version of tx */ 217 caddr_t txb_buf; 218 uint32_t txb_paddr; 219 ddi_dma_handle_t txb_dmah; 220 ddi_acc_handle_t txb_acch; 221 }; 222 223 /* 224 * Descriptor. We use rings rather than chains. 225 */ 226 struct mxfe_desc { 227 unsigned desc_status; 228 unsigned desc_control; 229 unsigned desc_buffer1; 230 unsigned desc_buffer2; 231 }; 232 233 #define PUTTXDESC(mxfep, member, val) \ 234 ddi_put32(mxfep->mxfe_txdesc_acch, &member, val) 235 236 #define PUTRXDESC(mxfep, member, val) \ 237 ddi_put32(mxfep->mxfe_rxdesc_acch, &member, val) 238 239 #define GETTXDESC(mxfep, member) \ 240 ddi_get32(mxfep->mxfe_txdesc_acch, &member) 241 242 #define GETRXDESC(mxfep, member) \ 243 ddi_get32(mxfep->mxfe_rxdesc_acch, &member) 244 245 /* 246 * Receive descriptor fields. 247 */ 248 #define RXSTAT_OWN 0x80000000U /* ownership */ 249 #define RXSTAT_RXLEN 0x3FFF0000U /* frame length, incl. crc */ 250 #define RXSTAT_RXERR 0x00008000U /* error summary */ 251 #define RXSTAT_DESCERR 0x00004000U /* descriptor error */ 252 #define RXSTAT_RXTYPE 0x00003000U /* data type */ 253 #define RXSTAT_RUNT 0x00000800U /* runt frame */ 254 #define RXSTAT_GROUP 0x00000400U /* multicast/brdcast frame */ 255 #define RXSTAT_FIRST 0x00000200U /* first descriptor */ 256 #define RXSTAT_LAST 0x00000100U /* last descriptor */ 257 #define RXSTAT_TOOLONG 0x00000080U /* frame too long */ 258 #define RXSTAT_COLLSEEN 0x00000040U /* late collision seen */ 259 #define RXSTAT_FRTYPE 0x00000020U /* frame type */ 260 #define RXSTAT_WATCHDOG 0x00000010U /* receive watchdog */ 261 #define RXSTAT_DRIBBLE 0x00000004U /* dribbling bit */ 262 #define RXSTAT_CRCERR 0x00000002U /* crc error */ 263 #define RXSTAT_OFLOW 0x00000001U /* fifo overflow */ 264 #define RXSTAT_ERRS (RXSTAT_DESCERR | RXSTAT_RUNT | \ 265 RXSTAT_COLLSEEN | RXSTAT_DRIBBLE | \ 266 RXSTAT_CRCERR | RXSTAT_OFLOW) 267 #define RXLENGTH(x) ((x & RXSTAT_RXLEN) >> 16) 268 269 #define RXCTL_ENDRING 0x02000000U /* end of ring */ 270 #define RXCTL_CHAIN 0x01000000U /* chained descriptors */ 271 #define RXCTL_BUFLEN2 0x003FF800U /* buffer 2 length */ 272 #define RXCTL_BUFLEN1 0x000007FFU /* buffer 1 length */ 273 274 /* 275 * Transmit descriptor fields. 276 */ 277 #define TXSTAT_OWN 0x80000000U /* ownership */ 278 #define TXSTAT_URCNT 0x00C00000U /* underrun count */ 279 #define TXSTAT_TXERR 0x00008000U /* error summary */ 280 #define TXSTAT_JABBER 0x00004000U /* jabber timeout */ 281 #define TXSTAT_CARRLOST 0x00000800U /* lost carrier */ 282 #define TXSTAT_NOCARR 0x00000400U /* no carrier */ 283 #define TXSTAT_LATECOL 0x00000200U /* late collision */ 284 #define TXSTAT_EXCOLL 0x00000100U /* excessive collisions */ 285 #define TXSTAT_SQE 0x00000080U /* heartbeat failure */ 286 #define TXSTAT_COLLCNT 0x00000078U /* collision count */ 287 #define TXSTAT_UFLOW 0x00000002U /* underflow */ 288 #define TXSTAT_DEFER 0x00000001U /* deferred */ 289 #define TXCOLLCNT(x) ((x & TXSTAT_COLLCNT) >> 3) 290 #define TXUFLOWCNT(x) ((x & TXSTAT_URCNT) >> 22) 291 292 #define TXCTL_INTCMPLTE 0x80000000U /* interrupt completed */ 293 #define TXCTL_LAST 0x40000000U /* last descriptor */ 294 #define TXCTL_FIRST 0x20000000U /* first descriptor */ 295 #define TXCTL_NOCRC 0x04000000U /* disable crc */ 296 #define TXCTL_SETUP 0x08000000U /* setup frame */ 297 #define TXCTL_ENDRING 0x02000000U /* end of ring */ 298 #define TXCTL_CHAIN 0x01000000U /* chained descriptors */ 299 #define TXCTL_NOPAD 0x00800000U /* disable padding */ 300 #define TXCTL_HASHPERF 0x00400000U /* hash perfect mode */ 301 #define TXCTL_BUFLEN2 0x003FF800U /* buffer length 2 */ 302 #define TXCTL_BUFLEN1 0x000007FFU /* buffer length 1 */ 303 304 /* 305 * Interface flags. 306 */ 307 #define MXFE_RUNNING 0x1 /* chip is initialized */ 308 #define MXFE_SUSPENDED 0x2 /* interface is suspended */ 309 #define MXFE_SYMBOL 0x8 /* use symbol mode */ 310 311 /* 312 * Link flags... 313 */ 314 #define MXFE_NOLINK 0x0 /* initial link state, no timer */ 315 #define MXFE_NWAYCHECK 0x2 /* checking for NWay support */ 316 #define MXFE_NWAYRENEG 0x3 /* renegotiating NWay mode */ 317 #define MXFE_GOODLINK 0x4 /* detected link is good */ 318 319 /* 320 * Card models. 321 */ 322 #define MXFE_MODEL(mxfep) ((mxfep)->mxfe_cardp->card_model) 323 #define MXFE_98715 0x1 324 #define MXFE_98715A 0x2 325 #define MXFE_98715AEC 0x3 326 #define MXFE_98715B 0x4 327 #define MXFE_98725 0x5 328 #define MXFE_98713 0x6 329 #define MXFE_98713A 0x7 330 #define MXFE_PNICII 0x8 331 332 /* 333 * Register definitions located in mxfe.h exported header file. 334 */ 335 336 /* 337 * Macros to simplify hardware access. Note that the reg/4 is used to 338 * help with pointer arithmetic. 339 */ 340 #define GETCSR(mxfep, reg) \ 341 ddi_get32(mxfep->mxfe_regshandle, mxfep->mxfe_regs + (reg/4)) 342 343 #define PUTCSR(mxfep, reg, val) \ 344 ddi_put32(mxfep->mxfe_regshandle, mxfep->mxfe_regs + (reg/4), val) 345 346 #define SETBIT(mxfep, reg, val) \ 347 PUTCSR(mxfep, reg, GETCSR(mxfep, reg) | (val)) 348 349 #define CLRBIT(mxfep, reg, val) \ 350 PUTCSR(mxfep, reg, GETCSR(mxfep, reg) & ~(val)) 351 352 #define SYNCTXDESC(mxfep, index, who) \ 353 (void) ddi_dma_sync(mxfep->mxfe_txdesc_dmah, \ 354 (index * sizeof (mxfe_desc_t)), sizeof (mxfe_desc_t), who) 355 356 #define SYNCTXBUF(txb, len, who) \ 357 (void) (ddi_dma_sync(txb->txb_dmah, 0, len, who)) 358 359 #define SYNCRXDESC(mxfep, index, who) \ 360 (void) ddi_dma_sync(mxfep->mxfe_rxdesc_dmah, \ 361 (index * sizeof (mxfe_desc_t)), sizeof (mxfe_desc_t), who) 362 363 #define SYNCRXBUF(rxb, len, who) \ 364 (void) (ddi_dma_sync(rxb->rxb_dmah, 0, len, who)) 365 366 /* 367 * Debugging flags. 368 */ 369 #define DWARN 0x0001 370 #define DINTR 0x0002 371 #define DWSRV 0x0004 372 #define DMACID 0x0008 373 #define DDLPI 0x0010 374 #define DPHY 0x0020 375 #define DPCI 0x0040 376 #define DCHATTY 0x0080 377 #define DDMA 0x0100 378 #define DLINK 0x0200 379 #define DSROM 0x0400 380 #define DRECV 0x0800 381 #define DXMIT 0x1000 382 383 #ifdef DEBUG 384 #define DBG(lvl, ...) mxfe_dprintf(mxfep, __func__, lvl, __VA_ARGS__); 385 #else 386 #define DBG(lvl, ...) 387 #endif 388 389 #endif /* _KERNEL */ 390 391 #endif /* _MXFEIMPL_H */ 392