1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #ifndef _IXGBE_SW_H 32 #define _IXGBE_SW_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac_provider.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/tcp.h> 66 #include <inet/ip.h> 67 #include <inet/mi.h> 68 #include <inet/nd.h> 69 #include <sys/bitmap.h> 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 #include "ixgbe_api.h" 75 76 #define MODULE_NAME "ixgbe" /* module name */ 77 78 #define IXGBE_FAILURE DDI_FAILURE 79 80 #define IXGBE_UNKNOWN 0x00 81 #define IXGBE_INITIALIZED 0x01 82 #define IXGBE_STARTED 0x02 83 #define IXGBE_SUSPENDED 0x04 84 85 #define MAX_NUM_UNICAST_ADDRESSES 0x10 86 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 87 #define IXGBE_INTR_NONE 0 88 #define IXGBE_INTR_MSIX 1 89 #define IXGBE_INTR_MSI 2 90 #define IXGBE_INTR_LEGACY 3 91 92 #define IXGBE_POLL_NULL -1 93 94 #define MAX_COOKIE 18 95 #define MIN_NUM_TX_DESC 2 96 97 /* 98 * MAX_xx_QUEUE_NUM and MAX_RING_VECTOR values need to be the maximum of all 99 * supported silicon types. 100 */ 101 #define MAX_TX_QUEUE_NUM 32 102 #define MAX_RX_QUEUE_NUM 64 103 #define MAX_RING_VECTOR 16 104 105 /* 106 * Maximum values for user configurable parameters 107 */ 108 #define MAX_RX_GROUP_NUM 1 109 #define MAX_TX_RING_SIZE 4096 110 #define MAX_RX_RING_SIZE 4096 111 112 #define MAX_MTU 16366 113 #define MAX_RX_LIMIT_PER_INTR 4096 114 #define MAX_INTR_THROTTLING 65535 115 116 #define MAX_RX_COPY_THRESHOLD 9216 117 #define MAX_TX_COPY_THRESHOLD 9216 118 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 119 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 120 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 121 122 /* 123 * Minimum values for user configurable parameters 124 */ 125 #define MIN_RX_GROUP_NUM 1 126 #define MIN_TX_RING_SIZE 64 127 #define MIN_RX_RING_SIZE 64 128 129 #define MIN_MTU ETHERMIN 130 #define MIN_RX_LIMIT_PER_INTR 16 131 #define MIN_INTR_THROTTLING 0 132 #define MIN_TX_COPY_THRESHOLD 0 133 #define MIN_RX_COPY_THRESHOLD 0 134 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 135 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 136 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 137 138 /* 139 * Default values for user configurable parameters 140 */ 141 #define DEFAULT_RX_GROUP_NUM 1 142 #define DEFAULT_TX_RING_SIZE 1024 143 #define DEFAULT_RX_RING_SIZE 1024 144 145 #define DEFAULT_MTU ETHERMTU 146 #define DEFAULT_RX_LIMIT_PER_INTR 256 147 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 148 #define DEFAULT_RX_COPY_THRESHOLD 128 149 #define DEFAULT_TX_COPY_THRESHOLD 512 150 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 151 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 152 #define DEFAULT_TX_RESCHED_THRESHOLD 128 153 #define DEFAULT_FCRTH 0x20000 154 #define DEFAULT_FCRTL 0x10000 155 #define DEFAULT_FCPAUSE 0xFFFF 156 157 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 158 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 159 #define DEFAULT_LSO_ENABLE B_TRUE 160 #define DEFAULT_MR_ENABLE B_TRUE 161 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 162 163 #define IXGBE_LSO_MAXLEN 65535 164 165 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 166 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 167 #define DEFAULT_LSO_ENABLE B_TRUE 168 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 169 170 #define IXGBE_LSO_MAXLEN 65535 171 172 #define TX_DRAIN_TIME 200 173 #define RX_DRAIN_TIME 200 174 175 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 176 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 177 178 /* 179 * Extra register bit masks for 82598 180 */ 181 #define IXGBE_PCS1GANA_FDC 0x20 182 #define IXGBE_PCS1GANLP_LPFD 0x20 183 #define IXGBE_PCS1GANLP_LPHD 0x40 184 185 /* 186 * Defined for IP header alignment. 187 */ 188 #define IPHDR_ALIGN_ROOM 2 189 190 /* 191 * Bit flags for attach_progress 192 */ 193 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 194 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 195 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 196 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 197 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 198 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 199 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 200 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 201 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 202 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 203 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 204 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 205 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 206 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 207 #define ATTACH_PROGRESS_LSC_TASKQ 0x4000 /* LSC taskq created */ 208 209 #define PROP_DEFAULT_MTU "default_mtu" 210 #define PROP_FLOW_CONTROL "flow_control" 211 #define PROP_TX_QUEUE_NUM "tx_queue_number" 212 #define PROP_TX_RING_SIZE "tx_ring_size" 213 #define PROP_RX_QUEUE_NUM "rx_queue_number" 214 #define PROP_RX_RING_SIZE "rx_ring_size" 215 #define PROP_RX_GROUP_NUM "rx_group_number" 216 217 #define PROP_INTR_FORCE "intr_force" 218 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 219 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 220 #define PROP_LSO_ENABLE "lso_enable" 221 #define PROP_MR_ENABLE "mr_enable" 222 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 223 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 224 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 225 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 226 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 227 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 228 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 229 #define PROP_INTR_THROTTLING "intr_throttling" 230 #define PROP_FM_CAPABLE "fm_capable" 231 232 #define IXGBE_LB_NONE 0 233 #define IXGBE_LB_EXTERNAL 1 234 #define IXGBE_LB_INTERNAL_MAC 2 235 #define IXGBE_LB_INTERNAL_PHY 3 236 #define IXGBE_LB_INTERNAL_SERDES 4 237 238 /* 239 * capability/feature flags 240 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 241 * Separately, the flag named _ENABLED is set when the feature is enabled. 242 */ 243 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 244 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 245 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 246 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 247 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 248 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 249 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 250 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 251 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 252 253 /* adapter-specific info for each supported device type */ 254 typedef struct adapter_info { 255 uint32_t max_rx_que_num; /* maximum number of rx queues */ 256 uint32_t min_rx_que_num; /* minimum number of rx queues */ 257 uint32_t def_rx_que_num; /* default number of rx queues */ 258 uint32_t max_tx_que_num; /* maximum number of tx queues */ 259 uint32_t min_tx_que_num; /* minimum number of tx queues */ 260 uint32_t def_tx_que_num; /* default number of tx queues */ 261 uint32_t max_msix_vect; /* maximum total msix vectors */ 262 uint32_t max_ring_vect; /* maximum number of ring vectors */ 263 uint32_t max_other_vect; /* maximum number of other vectors */ 264 uint32_t other_intr; /* "other" interrupt types handled */ 265 uint32_t flags; /* capability flags */ 266 } adapter_info_t; 267 268 /* bits representing all interrupt types other than tx & rx */ 269 #define IXGBE_OTHER_INTR 0x3ff00000 270 271 /* 272 * Shorthand for the NDD parameters 273 */ 274 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 275 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 276 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 277 #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 278 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 279 #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 280 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 281 282 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 283 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 284 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 285 #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 286 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 287 #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 288 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 289 290 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 291 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 292 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 293 #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 294 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 295 #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 296 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 297 298 enum ioc_reply { 299 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 300 IOC_DONE, /* OK, reply sent */ 301 IOC_ACK, /* OK, just send ACK */ 302 IOC_REPLY /* OK, just send reply */ 303 }; 304 305 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 306 0, 0, (flag))) 307 308 /* 309 * Defined for ring index operations 310 * ASSERT(index < limit) 311 * ASSERT(step < limit) 312 * ASSERT(index1 < limit) 313 * ASSERT(index2 < limit) 314 */ 315 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 316 (index) + (step) : (index) + (step) - (limit)) 317 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 318 (index) - (step) : (index) + (limit) - (step)) 319 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 320 (index2) - (index1) : (index2) + (limit) - (index1)) 321 322 #define LINK_LIST_INIT(_LH) \ 323 (_LH)->head = (_LH)->tail = NULL 324 325 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 326 327 #define LIST_POP_HEAD(_LH) \ 328 (single_link_t *)(_LH)->head; \ 329 { \ 330 if ((_LH)->head != NULL) { \ 331 (_LH)->head = (_LH)->head->link; \ 332 if ((_LH)->head == NULL) \ 333 (_LH)->tail = NULL; \ 334 } \ 335 } 336 337 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 338 339 #define LIST_PUSH_TAIL(_LH, _E) \ 340 if ((_LH)->tail != NULL) { \ 341 (_LH)->tail->link = (single_link_t *)(_E); \ 342 (_LH)->tail = (single_link_t *)(_E); \ 343 } else { \ 344 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 345 } \ 346 (_E)->link = NULL; 347 348 #define LIST_GET_NEXT(_LH, _E) \ 349 (((_LH)->tail == (single_link_t *)(_E)) ? \ 350 NULL : ((single_link_t *)(_E))->link) 351 352 353 typedef struct single_link { 354 struct single_link *link; 355 } single_link_t; 356 357 typedef struct link_list { 358 single_link_t *head; 359 single_link_t *tail; 360 } link_list_t; 361 362 /* 363 * Property lookups 364 */ 365 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 366 DDI_PROP_DONTPASS, (n)) 367 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 368 DDI_PROP_DONTPASS, (n), -1) 369 370 371 /* 372 * Named Data (ND) Parameter Management Structure 373 */ 374 typedef struct { 375 struct ixgbe *private; 376 uint32_t info; 377 uint32_t min; 378 uint32_t max; 379 uint32_t val; 380 char *name; 381 } nd_param_t; 382 383 /* 384 * NDD parameter indexes, divided into: 385 * 386 * read-only parameters describing the hardware's capabilities 387 * read-write parameters controlling the advertised capabilities 388 * read-only parameters describing the partner's capabilities 389 * read-write parameters controlling the force speed and duplex 390 * read-only parameters describing the link state 391 * read-only parameters describing the driver properties 392 * read-write parameters controlling the driver properties 393 */ 394 enum { 395 PARAM_AUTONEG_CAP, 396 PARAM_PAUSE_CAP, 397 PARAM_ASYM_PAUSE_CAP, 398 PARAM_10000FDX_CAP, 399 PARAM_1000FDX_CAP, 400 PARAM_100FDX_CAP, 401 PARAM_REM_FAULT, 402 403 PARAM_ADV_AUTONEG_CAP, 404 PARAM_ADV_PAUSE_CAP, 405 PARAM_ADV_ASYM_PAUSE_CAP, 406 PARAM_ADV_10000FDX_CAP, 407 PARAM_ADV_1000FDX_CAP, 408 PARAM_ADV_100FDX_CAP, 409 PARAM_ADV_REM_FAULT, 410 411 PARAM_LP_AUTONEG_CAP, 412 PARAM_LP_PAUSE_CAP, 413 PARAM_LP_ASYM_PAUSE_CAP, 414 PARAM_LP_10000FDX_CAP, 415 PARAM_LP_1000FDX_CAP, 416 PARAM_LP_100FDX_CAP, 417 PARAM_LP_REM_FAULT, 418 419 PARAM_LINK_STATUS, 420 PARAM_LINK_SPEED, 421 PARAM_LINK_DUPLEX, 422 423 PARAM_COUNT 424 }; 425 426 typedef union ixgbe_ether_addr { 427 struct { 428 uint32_t high; 429 uint32_t low; 430 } reg; 431 struct { 432 uint8_t set; 433 uint8_t redundant; 434 uint8_t addr[ETHERADDRL]; 435 } mac; 436 } ixgbe_ether_addr_t; 437 438 typedef enum { 439 USE_NONE, 440 USE_COPY, 441 USE_DMA 442 } tx_type_t; 443 444 typedef enum { 445 RCB_FREE, 446 RCB_SENDUP 447 } rcb_state_t; 448 449 typedef struct ixgbe_tx_context { 450 uint32_t hcksum_flags; 451 uint32_t ip_hdr_len; 452 uint32_t mac_hdr_len; 453 uint32_t l4_proto; 454 uint32_t mss; 455 uint32_t l4_hdr_len; 456 boolean_t lso_flag; 457 } ixgbe_tx_context_t; 458 459 /* 460 * Hold address/length of each DMA segment 461 */ 462 typedef struct sw_desc { 463 uint64_t address; 464 size_t length; 465 } sw_desc_t; 466 467 /* 468 * Handles and addresses of DMA buffer 469 */ 470 typedef struct dma_buffer { 471 caddr_t address; /* Virtual address */ 472 uint64_t dma_address; /* DMA (Hardware) address */ 473 ddi_acc_handle_t acc_handle; /* Data access handle */ 474 ddi_dma_handle_t dma_handle; /* DMA handle */ 475 size_t size; /* Buffer size */ 476 size_t len; /* Data length in the buffer */ 477 } dma_buffer_t; 478 479 /* 480 * Tx Control Block 481 */ 482 typedef struct tx_control_block { 483 single_link_t link; 484 uint32_t frag_num; 485 uint32_t desc_num; 486 mblk_t *mp; 487 tx_type_t tx_type; 488 ddi_dma_handle_t tx_dma_handle; 489 dma_buffer_t tx_buf; 490 sw_desc_t desc[MAX_COOKIE]; 491 } tx_control_block_t; 492 493 /* 494 * RX Control Block 495 */ 496 typedef struct rx_control_block { 497 mblk_t *mp; 498 rcb_state_t state; 499 dma_buffer_t rx_buf; 500 frtn_t free_rtn; 501 struct ixgbe_rx_ring *rx_ring; 502 } rx_control_block_t; 503 504 /* 505 * Software Data Structure for Tx Ring 506 */ 507 typedef struct ixgbe_tx_ring { 508 uint32_t index; /* Ring index */ 509 uint32_t intr_vector; /* Interrupt vector index */ 510 uint32_t vect_bit; /* vector's bit in register */ 511 512 /* 513 * Mutexes 514 */ 515 kmutex_t tx_lock; 516 kmutex_t recycle_lock; 517 kmutex_t tcb_head_lock; 518 kmutex_t tcb_tail_lock; 519 520 /* 521 * Tx descriptor ring definitions 522 */ 523 dma_buffer_t tbd_area; 524 union ixgbe_adv_tx_desc *tbd_ring; 525 uint32_t tbd_head; /* Index of next tbd to recycle */ 526 uint32_t tbd_tail; /* Index of next tbd to transmit */ 527 uint32_t tbd_free; /* Number of free tbd */ 528 529 /* 530 * Tx control block list definitions 531 */ 532 tx_control_block_t *tcb_area; 533 tx_control_block_t **work_list; 534 tx_control_block_t **free_list; 535 uint32_t tcb_head; /* Head index of free list */ 536 uint32_t tcb_tail; /* Tail index of free list */ 537 uint32_t tcb_free; /* Number of free tcb in free list */ 538 539 uint32_t *tbd_head_wb; /* Head write-back */ 540 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 541 542 /* 543 * s/w context structure for TCP/UDP checksum offload 544 * and LSO. 545 */ 546 ixgbe_tx_context_t tx_context; 547 548 /* 549 * Tx ring settings and status 550 */ 551 uint32_t ring_size; /* Tx descriptor ring size */ 552 uint32_t free_list_size; /* Tx free list size */ 553 uint32_t copy_thresh; 554 uint32_t recycle_thresh; 555 uint32_t overload_thresh; 556 uint32_t resched_thresh; 557 558 boolean_t reschedule; 559 uint32_t recycle_fail; 560 uint32_t stall_watchdog; 561 562 #ifdef IXGBE_DEBUG 563 /* 564 * Debug statistics 565 */ 566 uint32_t stat_overload; 567 uint32_t stat_fail_no_tbd; 568 uint32_t stat_fail_no_tcb; 569 uint32_t stat_fail_dma_bind; 570 uint32_t stat_reschedule; 571 uint32_t stat_lso_header_fail; 572 #endif 573 574 mac_ring_handle_t ring_handle; 575 576 /* 577 * Pointer to the ixgbe struct 578 */ 579 struct ixgbe *ixgbe; 580 } ixgbe_tx_ring_t; 581 582 /* 583 * Software Receive Ring 584 */ 585 typedef struct ixgbe_rx_ring { 586 uint32_t index; /* Ring index */ 587 uint32_t intr_vector; /* Interrupt vector index */ 588 uint32_t vect_bit; /* vector's bit in register */ 589 590 /* 591 * Mutexes 592 */ 593 kmutex_t rx_lock; /* Rx access lock */ 594 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 595 596 /* 597 * Rx descriptor ring definitions 598 */ 599 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 600 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 601 uint32_t rbd_next; /* Index of next rx desc */ 602 603 /* 604 * Rx control block list definitions 605 */ 606 rx_control_block_t *rcb_area; 607 rx_control_block_t **work_list; /* Work list of rcbs */ 608 rx_control_block_t **free_list; /* Free list of rcbs */ 609 uint32_t rcb_head; /* Index of next free rcb */ 610 uint32_t rcb_tail; /* Index to put recycled rcb */ 611 uint32_t rcb_free; /* Number of free rcbs */ 612 613 /* 614 * Rx ring settings and status 615 */ 616 uint32_t ring_size; /* Rx descriptor ring size */ 617 uint32_t free_list_size; /* Rx free list size */ 618 uint32_t limit_per_intr; /* Max packets per interrupt */ 619 uint32_t copy_thresh; 620 621 #ifdef IXGBE_DEBUG 622 /* 623 * Debug statistics 624 */ 625 uint32_t stat_frame_error; 626 uint32_t stat_cksum_error; 627 uint32_t stat_exceed_pkt; 628 #endif 629 630 mac_ring_handle_t ring_handle; 631 uint64_t ring_gen_num; 632 633 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 634 } ixgbe_rx_ring_t; 635 636 /* 637 * Software Receive Ring Group 638 */ 639 typedef struct ixgbe_rx_group { 640 uint32_t index; /* Group index */ 641 mac_group_handle_t group_handle; /* call back group handle */ 642 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 643 } ixgbe_rx_group_t; 644 645 /* 646 * structure to map ring cleanup to msi-x vector 647 */ 648 typedef struct ixgbe_ring_vector { 649 struct ixgbe *ixgbe; /* point to my adapter */ 650 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 651 int rxr_cnt; /* count rx rings */ 652 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 653 int txr_cnt; /* count tx rings */ 654 } ixgbe_ring_vector_t; 655 656 /* 657 * Software adapter state 658 */ 659 typedef struct ixgbe { 660 int instance; 661 mac_handle_t mac_hdl; 662 dev_info_t *dip; 663 struct ixgbe_hw hw; 664 struct ixgbe_osdep osdep; 665 666 adapter_info_t *capab; /* adapter hardware capabilities */ 667 ddi_taskq_t *lsc_taskq; /* link-status-change taskq */ 668 uint32_t eims; /* interrupt mask setting */ 669 670 uint32_t ixgbe_state; 671 link_state_t link_state; 672 uint32_t link_speed; 673 uint32_t link_duplex; 674 uint32_t link_down_timeout; 675 676 uint32_t reset_count; 677 uint32_t attach_progress; 678 uint32_t loopback_mode; 679 uint32_t default_mtu; 680 uint32_t max_frame_size; 681 682 /* 683 * Each msi-x vector: map vector to ring cleanup 684 */ 685 ixgbe_ring_vector_t vect_map[MAX_RING_VECTOR]; 686 687 /* 688 * Receive Rings 689 */ 690 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 691 uint32_t num_rx_rings; /* Number of rx rings in use */ 692 uint32_t rx_ring_size; /* Rx descriptor ring size */ 693 uint32_t rx_buf_size; /* Rx buffer size */ 694 695 /* 696 * Receive Groups 697 */ 698 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 699 uint32_t num_rx_groups; /* Number of rx groups in use */ 700 701 /* 702 * Transmit Rings 703 */ 704 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 705 uint32_t num_tx_rings; /* Number of tx rings in use */ 706 uint32_t tx_ring_size; /* Tx descriptor ring size */ 707 uint32_t tx_buf_size; /* Tx buffer size */ 708 709 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 710 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 711 boolean_t lso_enable; /* Large Segment Offload */ 712 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 713 uint32_t tx_copy_thresh; /* Tx copy threshold */ 714 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 715 uint32_t tx_overload_thresh; /* Tx overload threshold */ 716 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 717 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 718 uint32_t rx_copy_thresh; /* Rx copy threshold */ 719 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 720 uint32_t intr_throttling[MAX_RING_VECTOR]; 721 uint32_t intr_force; 722 int fm_capabilities; /* FMA capabilities */ 723 724 int intr_type; 725 int intr_cnt; 726 int intr_cap; 727 size_t intr_size; 728 uint_t intr_pri; 729 ddi_intr_handle_t *htable; 730 uint32_t eims_mask; 731 732 kmutex_t gen_lock; /* General lock for device access */ 733 kmutex_t watchdog_lock; 734 735 boolean_t watchdog_enable; 736 boolean_t watchdog_start; 737 timeout_id_t watchdog_tid; 738 739 boolean_t unicst_init; 740 uint32_t unicst_avail; 741 uint32_t unicst_total; 742 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 743 uint32_t mcast_count; 744 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 745 746 ulong_t sys_page_size; 747 748 /* 749 * Kstat definitions 750 */ 751 kstat_t *ixgbe_ks; 752 753 /* 754 * NDD definitions 755 */ 756 caddr_t nd_data; 757 nd_param_t nd_params[PARAM_COUNT]; 758 } ixgbe_t; 759 760 typedef struct ixgbe_stat { 761 kstat_named_t link_speed; /* Link Speed */ 762 763 kstat_named_t reset_count; /* Reset Count */ 764 765 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 766 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 767 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 768 769 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 770 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 771 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 772 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 773 kstat_named_t tx_reschedule; /* Tx Reschedule */ 774 775 kstat_named_t gprc; /* Good Packets Received Count */ 776 kstat_named_t gptc; /* Good Packets Xmitted Count */ 777 kstat_named_t gor; /* Good Octets Received Count */ 778 kstat_named_t got; /* Good Octets Xmitd Count */ 779 kstat_named_t prc64; /* Packets Received - 64b */ 780 kstat_named_t prc127; /* Packets Received - 65-127b */ 781 kstat_named_t prc255; /* Packets Received - 127-255b */ 782 kstat_named_t prc511; /* Packets Received - 256-511b */ 783 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 784 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 785 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 786 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 787 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 788 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 789 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 790 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 791 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 792 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 793 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 794 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 795 796 kstat_named_t crcerrs; /* CRC Error Count */ 797 kstat_named_t illerrc; /* Illegal Byte Error Count */ 798 kstat_named_t errbc; /* Error Byte Count */ 799 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 800 kstat_named_t mpc; /* Missed Packets Count */ 801 kstat_named_t mlfc; /* MAC Local Fault Count */ 802 kstat_named_t mrfc; /* MAC Remote Fault Count */ 803 kstat_named_t rlec; /* Receive Length Error Count */ 804 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 805 kstat_named_t lxonrxc; /* Link XON Received Count */ 806 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 807 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 808 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 809 kstat_named_t mprc; /* Multicast Pkts Received Count */ 810 kstat_named_t rnbc; /* Receive No Buffers Count */ 811 kstat_named_t ruc; /* Receive Undersize Count */ 812 kstat_named_t rfc; /* Receive Frag Count */ 813 kstat_named_t roc; /* Receive Oversize Count */ 814 kstat_named_t rjc; /* Receive Jabber Count */ 815 kstat_named_t tor; /* Total Octets Recvd Count */ 816 kstat_named_t tot; /* Total Octets Xmitted Count */ 817 kstat_named_t tpr; /* Total Packets Received */ 818 kstat_named_t tpt; /* Total Packets Xmitted */ 819 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 820 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 821 } ixgbe_stat_t; 822 823 /* 824 * Function prototypes in ixgbe_buf.c 825 */ 826 int ixgbe_alloc_dma(ixgbe_t *); 827 void ixgbe_free_dma(ixgbe_t *); 828 void ixgbe_set_fma_flags(int, int); 829 830 /* 831 * Function prototypes in ixgbe_main.c 832 */ 833 int ixgbe_start(ixgbe_t *); 834 void ixgbe_stop(ixgbe_t *); 835 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 836 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 837 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 838 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 839 840 void ixgbe_enable_watchdog_timer(ixgbe_t *); 841 void ixgbe_disable_watchdog_timer(ixgbe_t *); 842 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 843 844 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 845 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 846 void ixgbe_fm_ereport(ixgbe_t *, char *); 847 848 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 849 mac_ring_info_t *, mac_ring_handle_t); 850 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 851 mac_group_info_t *, mac_group_handle_t); 852 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 853 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 854 855 /* 856 * Function prototypes in ixgbe_gld.c 857 */ 858 int ixgbe_m_start(void *); 859 void ixgbe_m_stop(void *); 860 int ixgbe_m_promisc(void *, boolean_t); 861 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 862 int ixgbe_m_stat(void *, uint_t, uint64_t *); 863 void ixgbe_m_resources(void *); 864 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 865 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 866 867 /* 868 * Function prototypes in ixgbe_rx.c 869 */ 870 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 871 void ixgbe_rx_recycle(caddr_t arg); 872 mblk_t *ixgbe_ring_rx_poll(void *, int); 873 874 /* 875 * Function prototypes in ixgbe_tx.c 876 */ 877 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 878 void ixgbe_free_tcb(tx_control_block_t *); 879 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 880 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 881 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 882 883 /* 884 * Function prototypes in ixgbe_log.c 885 */ 886 void ixgbe_notice(void *, const char *, ...); 887 void ixgbe_log(void *, const char *, ...); 888 void ixgbe_error(void *, const char *, ...); 889 890 /* 891 * Function prototypes in ixgbe_ndd.c 892 */ 893 int ixgbe_nd_init(ixgbe_t *); 894 void ixgbe_nd_cleanup(ixgbe_t *); 895 enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 896 897 /* 898 * Function prototypes in ixgbe_stat.c 899 */ 900 int ixgbe_init_stats(ixgbe_t *); 901 902 #ifdef __cplusplus 903 } 904 #endif 905 906 #endif /* _IXGBE_SW_H */ 907