1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 32 #include "ixgbe_sw.h" 33 34 static char ident[] = "Intel 10Gb Ethernet"; 35 36 /* 37 * Local function protoypes 38 */ 39 static int ixgbe_register_mac(ixgbe_t *); 40 static int ixgbe_identify_hardware(ixgbe_t *); 41 static int ixgbe_regs_map(ixgbe_t *); 42 static void ixgbe_init_properties(ixgbe_t *); 43 static int ixgbe_init_driver_settings(ixgbe_t *); 44 static void ixgbe_init_locks(ixgbe_t *); 45 static void ixgbe_destroy_locks(ixgbe_t *); 46 static int ixgbe_init(ixgbe_t *); 47 static int ixgbe_chip_start(ixgbe_t *); 48 static void ixgbe_chip_stop(ixgbe_t *); 49 static int ixgbe_reset(ixgbe_t *); 50 static void ixgbe_tx_clean(ixgbe_t *); 51 static boolean_t ixgbe_tx_drain(ixgbe_t *); 52 static boolean_t ixgbe_rx_drain(ixgbe_t *); 53 static int ixgbe_alloc_rings(ixgbe_t *); 54 static int ixgbe_init_rings(ixgbe_t *); 55 static void ixgbe_free_rings(ixgbe_t *); 56 static void ixgbe_fini_rings(ixgbe_t *); 57 static void ixgbe_setup_rings(ixgbe_t *); 58 static void ixgbe_setup_rx(ixgbe_t *); 59 static void ixgbe_setup_tx(ixgbe_t *); 60 static void ixgbe_setup_rx_ring(ixgbe_rx_ring_t *); 61 static void ixgbe_setup_tx_ring(ixgbe_tx_ring_t *); 62 static void ixgbe_setup_rss(ixgbe_t *); 63 static void ixgbe_init_unicst(ixgbe_t *); 64 static int ixgbe_unicst_set(ixgbe_t *, const uint8_t *, int); 65 static int ixgbe_unicst_find(ixgbe_t *, const uint8_t *); 66 static void ixgbe_setup_multicst(ixgbe_t *); 67 static void ixgbe_get_hw_state(ixgbe_t *); 68 static void ixgbe_get_conf(ixgbe_t *); 69 static int ixgbe_get_prop(ixgbe_t *, char *, int, int, int); 70 static void ixgbe_driver_link_check(void *); 71 static void ixgbe_local_timer(void *); 72 static void ixgbe_arm_watchdog_timer(ixgbe_t *); 73 static void ixgbe_restart_watchdog_timer(ixgbe_t *); 74 static void ixgbe_disable_adapter_interrupts(ixgbe_t *); 75 static void ixgbe_enable_adapter_interrupts(ixgbe_t *); 76 static boolean_t is_valid_mac_addr(uint8_t *); 77 static boolean_t ixgbe_stall_check(ixgbe_t *); 78 static boolean_t ixgbe_set_loopback_mode(ixgbe_t *, uint32_t); 79 static void ixgbe_set_internal_mac_loopback(ixgbe_t *); 80 static boolean_t ixgbe_find_mac_address(ixgbe_t *); 81 static int ixgbe_alloc_intrs(ixgbe_t *); 82 static int ixgbe_alloc_intr_handles(ixgbe_t *, int); 83 static int ixgbe_add_intr_handlers(ixgbe_t *); 84 static void ixgbe_map_rxring_to_vector(ixgbe_t *, int, int); 85 static void ixgbe_map_txring_to_vector(ixgbe_t *, int, int); 86 static void ixgbe_setup_ivar(ixgbe_t *, uint16_t, uint8_t); 87 static void ixgbe_enable_ivar(ixgbe_t *, uint16_t); 88 static void ixgbe_disable_ivar(ixgbe_t *, uint16_t); 89 static int ixgbe_map_rings_to_vectors(ixgbe_t *); 90 static void ixgbe_setup_adapter_vector(ixgbe_t *); 91 static void ixgbe_rem_intr_handlers(ixgbe_t *); 92 static void ixgbe_rem_intrs(ixgbe_t *); 93 static int ixgbe_enable_intrs(ixgbe_t *); 94 static int ixgbe_disable_intrs(ixgbe_t *); 95 static uint_t ixgbe_intr_legacy(void *, void *); 96 static uint_t ixgbe_intr_msi(void *, void *); 97 static uint_t ixgbe_intr_rx_tx(void *, void *); 98 static uint_t ixgbe_intr_other(void *, void *); 99 static void ixgbe_intr_rx_work(ixgbe_rx_ring_t *); 100 static void ixgbe_intr_tx_work(ixgbe_tx_ring_t *); 101 static void ixgbe_intr_other_work(ixgbe_t *, uint32_t); 102 static void ixgbe_get_driver_control(struct ixgbe_hw *); 103 static int ixgbe_addmac(void *, const uint8_t *); 104 static int ixgbe_remmac(void *, const uint8_t *); 105 static void ixgbe_release_driver_control(struct ixgbe_hw *); 106 107 static int ixgbe_attach(dev_info_t *, ddi_attach_cmd_t); 108 static int ixgbe_detach(dev_info_t *, ddi_detach_cmd_t); 109 static int ixgbe_resume(dev_info_t *); 110 static int ixgbe_suspend(dev_info_t *); 111 static void ixgbe_unconfigure(dev_info_t *, ixgbe_t *); 112 static uint8_t *ixgbe_mc_table_itr(struct ixgbe_hw *, uint8_t **, uint32_t *); 113 114 static int ixgbe_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 115 const void *impl_data); 116 static void ixgbe_fm_init(ixgbe_t *); 117 static void ixgbe_fm_fini(ixgbe_t *); 118 119 static struct cb_ops ixgbe_cb_ops = { 120 nulldev, /* cb_open */ 121 nulldev, /* cb_close */ 122 nodev, /* cb_strategy */ 123 nodev, /* cb_print */ 124 nodev, /* cb_dump */ 125 nodev, /* cb_read */ 126 nodev, /* cb_write */ 127 nodev, /* cb_ioctl */ 128 nodev, /* cb_devmap */ 129 nodev, /* cb_mmap */ 130 nodev, /* cb_segmap */ 131 nochpoll, /* cb_chpoll */ 132 ddi_prop_op, /* cb_prop_op */ 133 NULL, /* cb_stream */ 134 D_MP | D_HOTPLUG, /* cb_flag */ 135 CB_REV, /* cb_rev */ 136 nodev, /* cb_aread */ 137 nodev /* cb_awrite */ 138 }; 139 140 static struct dev_ops ixgbe_dev_ops = { 141 DEVO_REV, /* devo_rev */ 142 0, /* devo_refcnt */ 143 NULL, /* devo_getinfo */ 144 nulldev, /* devo_identify */ 145 nulldev, /* devo_probe */ 146 ixgbe_attach, /* devo_attach */ 147 ixgbe_detach, /* devo_detach */ 148 nodev, /* devo_reset */ 149 &ixgbe_cb_ops, /* devo_cb_ops */ 150 NULL, /* devo_bus_ops */ 151 ddi_power, /* devo_power */ 152 ddi_quiesce_not_supported, /* devo_quiesce */ 153 }; 154 155 static struct modldrv ixgbe_modldrv = { 156 &mod_driverops, /* Type of module. This one is a driver */ 157 ident, /* Discription string */ 158 &ixgbe_dev_ops /* driver ops */ 159 }; 160 161 static struct modlinkage ixgbe_modlinkage = { 162 MODREV_1, &ixgbe_modldrv, NULL 163 }; 164 165 /* 166 * Access attributes for register mapping 167 */ 168 ddi_device_acc_attr_t ixgbe_regs_acc_attr = { 169 DDI_DEVICE_ATTR_V0, 170 DDI_STRUCTURE_LE_ACC, 171 DDI_STRICTORDER_ACC, 172 DDI_FLAGERR_ACC 173 }; 174 175 /* 176 * Loopback property 177 */ 178 static lb_property_t lb_normal = { 179 normal, "normal", IXGBE_LB_NONE 180 }; 181 182 static lb_property_t lb_mac = { 183 internal, "MAC", IXGBE_LB_INTERNAL_MAC 184 }; 185 186 #define IXGBE_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 187 188 static mac_callbacks_t ixgbe_m_callbacks = { 189 IXGBE_M_CALLBACK_FLAGS, 190 ixgbe_m_stat, 191 ixgbe_m_start, 192 ixgbe_m_stop, 193 ixgbe_m_promisc, 194 ixgbe_m_multicst, 195 NULL, 196 NULL, 197 ixgbe_m_ioctl, 198 ixgbe_m_getcapab 199 }; 200 201 /* 202 * Initialize capabilities of each supported adapter type 203 */ 204 static adapter_info_t ixgbe_82598eb_cap = { 205 64, /* maximum number of rx queues */ 206 1, /* minimum number of rx queues */ 207 8, /* default number of rx queues */ 208 32, /* maximum number of tx queues */ 209 1, /* minimum number of tx queues */ 210 8, /* default number of tx queues */ 211 18, /* maximum total msix vectors */ 212 16, /* maximum number of ring vectors */ 213 2, /* maximum number of other vectors */ 214 IXGBE_EICR_LSC, /* "other" interrupt types handled */ 215 (IXGBE_FLAG_DCA_CAPABLE /* capability flags */ 216 | IXGBE_FLAG_RSS_CAPABLE 217 | IXGBE_FLAG_VMDQ_CAPABLE) 218 }; 219 220 /* 221 * Module Initialization Functions. 222 */ 223 224 int 225 _init(void) 226 { 227 int status; 228 229 mac_init_ops(&ixgbe_dev_ops, MODULE_NAME); 230 231 status = mod_install(&ixgbe_modlinkage); 232 233 if (status != DDI_SUCCESS) { 234 mac_fini_ops(&ixgbe_dev_ops); 235 } 236 237 return (status); 238 } 239 240 int 241 _fini(void) 242 { 243 int status; 244 245 status = mod_remove(&ixgbe_modlinkage); 246 247 if (status == DDI_SUCCESS) { 248 mac_fini_ops(&ixgbe_dev_ops); 249 } 250 251 return (status); 252 } 253 254 int 255 _info(struct modinfo *modinfop) 256 { 257 int status; 258 259 status = mod_info(&ixgbe_modlinkage, modinfop); 260 261 return (status); 262 } 263 264 /* 265 * ixgbe_attach - Driver attach. 266 * 267 * This function is the device specific initialization entry 268 * point. This entry point is required and must be written. 269 * The DDI_ATTACH command must be provided in the attach entry 270 * point. When attach() is called with cmd set to DDI_ATTACH, 271 * all normal kernel services (such as kmem_alloc(9F)) are 272 * available for use by the driver. 273 * 274 * The attach() function will be called once for each instance 275 * of the device on the system with cmd set to DDI_ATTACH. 276 * Until attach() succeeds, the only driver entry points which 277 * may be called are open(9E) and getinfo(9E). 278 */ 279 static int 280 ixgbe_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 281 { 282 ixgbe_t *ixgbe; 283 struct ixgbe_osdep *osdep; 284 struct ixgbe_hw *hw; 285 int instance; 286 char taskqname[32]; 287 288 /* 289 * Check the command and perform corresponding operations 290 */ 291 switch (cmd) { 292 default: 293 return (DDI_FAILURE); 294 295 case DDI_RESUME: 296 return (ixgbe_resume(devinfo)); 297 298 case DDI_ATTACH: 299 break; 300 } 301 302 /* Get the device instance */ 303 instance = ddi_get_instance(devinfo); 304 305 /* Allocate memory for the instance data structure */ 306 ixgbe = kmem_zalloc(sizeof (ixgbe_t), KM_SLEEP); 307 308 ixgbe->dip = devinfo; 309 ixgbe->instance = instance; 310 311 hw = &ixgbe->hw; 312 osdep = &ixgbe->osdep; 313 hw->back = osdep; 314 osdep->ixgbe = ixgbe; 315 316 /* Attach the instance pointer to the dev_info data structure */ 317 ddi_set_driver_private(devinfo, ixgbe); 318 319 /* 320 * Initialize for fma support 321 */ 322 ixgbe->fm_capabilities = ixgbe_get_prop(ixgbe, PROP_FM_CAPABLE, 323 0, 0x0f, DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 324 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 325 ixgbe_fm_init(ixgbe); 326 ixgbe->attach_progress |= ATTACH_PROGRESS_FM_INIT; 327 328 /* 329 * Map PCI config space registers 330 */ 331 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 332 ixgbe_error(ixgbe, "Failed to map PCI configurations"); 333 goto attach_fail; 334 } 335 ixgbe->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 336 337 /* 338 * Identify the chipset family 339 */ 340 if (ixgbe_identify_hardware(ixgbe) != IXGBE_SUCCESS) { 341 ixgbe_error(ixgbe, "Failed to identify hardware"); 342 goto attach_fail; 343 } 344 345 /* 346 * Map device registers 347 */ 348 if (ixgbe_regs_map(ixgbe) != IXGBE_SUCCESS) { 349 ixgbe_error(ixgbe, "Failed to map device registers"); 350 goto attach_fail; 351 } 352 ixgbe->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 353 354 /* 355 * Initialize driver parameters 356 */ 357 ixgbe_init_properties(ixgbe); 358 ixgbe->attach_progress |= ATTACH_PROGRESS_PROPS; 359 360 /* 361 * Allocate interrupts 362 */ 363 if (ixgbe_alloc_intrs(ixgbe) != IXGBE_SUCCESS) { 364 ixgbe_error(ixgbe, "Failed to allocate interrupts"); 365 goto attach_fail; 366 } 367 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 368 369 /* 370 * Allocate rx/tx rings based on the ring numbers. 371 * The actual numbers of rx/tx rings are decided by the number of 372 * allocated interrupt vectors, so we should allocate the rings after 373 * interrupts are allocated. 374 */ 375 if (ixgbe_alloc_rings(ixgbe) != IXGBE_SUCCESS) { 376 ixgbe_error(ixgbe, "Failed to allocate rx and tx rings"); 377 goto attach_fail; 378 } 379 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 380 381 /* 382 * Map rings to interrupt vectors 383 */ 384 if (ixgbe_map_rings_to_vectors(ixgbe) != IXGBE_SUCCESS) { 385 ixgbe_error(ixgbe, "Failed to map rings to vectors"); 386 goto attach_fail; 387 } 388 389 /* 390 * Add interrupt handlers 391 */ 392 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) { 393 ixgbe_error(ixgbe, "Failed to add interrupt handlers"); 394 goto attach_fail; 395 } 396 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 397 398 /* 399 * Create a taskq for link-status-change 400 */ 401 (void) sprintf(taskqname, "ixgbe%d_taskq", instance); 402 if ((ixgbe->lsc_taskq = ddi_taskq_create(devinfo, taskqname, 403 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 404 ixgbe_error(ixgbe, "taskq_create failed"); 405 goto attach_fail; 406 } 407 ixgbe->attach_progress |= ATTACH_PROGRESS_LSC_TASKQ; 408 409 /* 410 * Initialize driver parameters 411 */ 412 if (ixgbe_init_driver_settings(ixgbe) != IXGBE_SUCCESS) { 413 ixgbe_error(ixgbe, "Failed to initialize driver settings"); 414 goto attach_fail; 415 } 416 417 /* 418 * Initialize mutexes for this device. 419 * Do this before enabling the interrupt handler and 420 * register the softint to avoid the condition where 421 * interrupt handler can try using uninitialized mutex. 422 */ 423 ixgbe_init_locks(ixgbe); 424 ixgbe->attach_progress |= ATTACH_PROGRESS_LOCKS; 425 426 /* 427 * Initialize chipset hardware 428 */ 429 if (ixgbe_init(ixgbe) != IXGBE_SUCCESS) { 430 ixgbe_error(ixgbe, "Failed to initialize adapter"); 431 goto attach_fail; 432 } 433 ixgbe->attach_progress |= ATTACH_PROGRESS_INIT; 434 435 if (ixgbe_check_acc_handle(ixgbe->osdep.cfg_handle) != DDI_FM_OK) { 436 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST); 437 goto attach_fail; 438 } 439 440 /* 441 * Initialize DMA and hardware settings for rx/tx rings 442 */ 443 if (ixgbe_init_rings(ixgbe) != IXGBE_SUCCESS) { 444 ixgbe_error(ixgbe, "Failed to initialize rings"); 445 goto attach_fail; 446 } 447 ixgbe->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 448 449 /* 450 * Initialize statistics 451 */ 452 if (ixgbe_init_stats(ixgbe) != IXGBE_SUCCESS) { 453 ixgbe_error(ixgbe, "Failed to initialize statistics"); 454 goto attach_fail; 455 } 456 ixgbe->attach_progress |= ATTACH_PROGRESS_STATS; 457 458 /* 459 * Initialize NDD parameters 460 */ 461 if (ixgbe_nd_init(ixgbe) != IXGBE_SUCCESS) { 462 ixgbe_error(ixgbe, "Failed to initialize ndd"); 463 goto attach_fail; 464 } 465 ixgbe->attach_progress |= ATTACH_PROGRESS_NDD; 466 467 /* 468 * Register the driver to the MAC 469 */ 470 if (ixgbe_register_mac(ixgbe) != IXGBE_SUCCESS) { 471 ixgbe_error(ixgbe, "Failed to register MAC"); 472 goto attach_fail; 473 } 474 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN); 475 ixgbe->attach_progress |= ATTACH_PROGRESS_MAC; 476 477 /* 478 * Now that mutex locks are initialized, and the chip is also 479 * initialized, enable interrupts. 480 */ 481 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) { 482 ixgbe_error(ixgbe, "Failed to enable DDI interrupts"); 483 goto attach_fail; 484 } 485 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 486 487 ixgbe->ixgbe_state |= IXGBE_INITIALIZED; 488 489 return (DDI_SUCCESS); 490 491 attach_fail: 492 ixgbe_unconfigure(devinfo, ixgbe); 493 return (DDI_FAILURE); 494 } 495 496 /* 497 * ixgbe_detach - Driver detach. 498 * 499 * The detach() function is the complement of the attach routine. 500 * If cmd is set to DDI_DETACH, detach() is used to remove the 501 * state associated with a given instance of a device node 502 * prior to the removal of that instance from the system. 503 * 504 * The detach() function will be called once for each instance 505 * of the device for which there has been a successful attach() 506 * once there are no longer any opens on the device. 507 * 508 * Interrupts routine are disabled, All memory allocated by this 509 * driver are freed. 510 */ 511 static int 512 ixgbe_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 513 { 514 ixgbe_t *ixgbe; 515 516 /* 517 * Check detach command 518 */ 519 switch (cmd) { 520 default: 521 return (DDI_FAILURE); 522 523 case DDI_SUSPEND: 524 return (ixgbe_suspend(devinfo)); 525 526 case DDI_DETACH: 527 break; 528 } 529 530 531 /* 532 * Get the pointer to the driver private data structure 533 */ 534 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo); 535 if (ixgbe == NULL) 536 return (DDI_FAILURE); 537 538 /* 539 * Unregister MAC. If failed, we have to fail the detach 540 */ 541 if (mac_unregister(ixgbe->mac_hdl) != 0) { 542 ixgbe_error(ixgbe, "Failed to unregister MAC"); 543 return (DDI_FAILURE); 544 } 545 ixgbe->attach_progress &= ~ATTACH_PROGRESS_MAC; 546 547 /* 548 * If the device is still running, it needs to be stopped first. 549 * This check is necessary because under some specific circumstances, 550 * the detach routine can be called without stopping the interface 551 * first. 552 */ 553 mutex_enter(&ixgbe->gen_lock); 554 if (ixgbe->ixgbe_state & IXGBE_STARTED) { 555 ixgbe->ixgbe_state &= ~IXGBE_STARTED; 556 ixgbe_stop(ixgbe); 557 mutex_exit(&ixgbe->gen_lock); 558 /* Disable and stop the watchdog timer */ 559 ixgbe_disable_watchdog_timer(ixgbe); 560 } else 561 mutex_exit(&ixgbe->gen_lock); 562 563 /* 564 * Check if there are still rx buffers held by the upper layer. 565 * If so, fail the detach. 566 */ 567 if (!ixgbe_rx_drain(ixgbe)) 568 return (DDI_FAILURE); 569 570 /* 571 * Do the remaining unconfigure routines 572 */ 573 ixgbe_unconfigure(devinfo, ixgbe); 574 575 return (DDI_SUCCESS); 576 } 577 578 static void 579 ixgbe_unconfigure(dev_info_t *devinfo, ixgbe_t *ixgbe) 580 { 581 /* 582 * Disable interrupt 583 */ 584 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 585 (void) ixgbe_disable_intrs(ixgbe); 586 } 587 588 /* 589 * Unregister MAC 590 */ 591 if (ixgbe->attach_progress & ATTACH_PROGRESS_MAC) { 592 (void) mac_unregister(ixgbe->mac_hdl); 593 } 594 595 /* 596 * Free ndd parameters 597 */ 598 if (ixgbe->attach_progress & ATTACH_PROGRESS_NDD) { 599 ixgbe_nd_cleanup(ixgbe); 600 } 601 602 /* 603 * Free statistics 604 */ 605 if (ixgbe->attach_progress & ATTACH_PROGRESS_STATS) { 606 kstat_delete((kstat_t *)ixgbe->ixgbe_ks); 607 } 608 609 /* 610 * Remove interrupt handlers 611 */ 612 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 613 ixgbe_rem_intr_handlers(ixgbe); 614 } 615 616 /* 617 * Remove taskq for link-status-change 618 */ 619 if (ixgbe->attach_progress & ATTACH_PROGRESS_LSC_TASKQ) { 620 ddi_taskq_destroy(ixgbe->lsc_taskq); 621 } 622 623 /* 624 * Remove interrupts 625 */ 626 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 627 ixgbe_rem_intrs(ixgbe); 628 } 629 630 /* 631 * Remove driver properties 632 */ 633 if (ixgbe->attach_progress & ATTACH_PROGRESS_PROPS) { 634 (void) ddi_prop_remove_all(devinfo); 635 } 636 637 /* 638 * Release the DMA resources of rx/tx rings 639 */ 640 if (ixgbe->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 641 ixgbe_fini_rings(ixgbe); 642 } 643 644 /* 645 * Stop the chipset 646 */ 647 if (ixgbe->attach_progress & ATTACH_PROGRESS_INIT) { 648 mutex_enter(&ixgbe->gen_lock); 649 ixgbe_chip_stop(ixgbe); 650 mutex_exit(&ixgbe->gen_lock); 651 } 652 653 /* 654 * Free register handle 655 */ 656 if (ixgbe->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 657 if (ixgbe->osdep.reg_handle != NULL) 658 ddi_regs_map_free(&ixgbe->osdep.reg_handle); 659 } 660 661 /* 662 * Free PCI config handle 663 */ 664 if (ixgbe->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 665 if (ixgbe->osdep.cfg_handle != NULL) 666 pci_config_teardown(&ixgbe->osdep.cfg_handle); 667 } 668 669 /* 670 * Free locks 671 */ 672 if (ixgbe->attach_progress & ATTACH_PROGRESS_LOCKS) { 673 ixgbe_destroy_locks(ixgbe); 674 } 675 676 /* 677 * Free the rx/tx rings 678 */ 679 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 680 ixgbe_free_rings(ixgbe); 681 } 682 683 /* 684 * Unregister FMA capabilities 685 */ 686 if (ixgbe->attach_progress & ATTACH_PROGRESS_FM_INIT) { 687 ixgbe_fm_fini(ixgbe); 688 } 689 690 /* 691 * Free the driver data structure 692 */ 693 kmem_free(ixgbe, sizeof (ixgbe_t)); 694 695 ddi_set_driver_private(devinfo, NULL); 696 } 697 698 /* 699 * ixgbe_register_mac - Register the driver and its function pointers with 700 * the GLD interface. 701 */ 702 static int 703 ixgbe_register_mac(ixgbe_t *ixgbe) 704 { 705 struct ixgbe_hw *hw = &ixgbe->hw; 706 mac_register_t *mac; 707 int status; 708 709 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 710 return (IXGBE_FAILURE); 711 712 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 713 mac->m_driver = ixgbe; 714 mac->m_dip = ixgbe->dip; 715 mac->m_src_addr = hw->mac.addr; 716 mac->m_callbacks = &ixgbe_m_callbacks; 717 mac->m_min_sdu = 0; 718 mac->m_max_sdu = ixgbe->default_mtu; 719 mac->m_margin = VLAN_TAGSZ; 720 mac->m_v12n = MAC_VIRT_LEVEL1; 721 722 status = mac_register(mac, &ixgbe->mac_hdl); 723 724 mac_free(mac); 725 726 return ((status == 0) ? IXGBE_SUCCESS : IXGBE_FAILURE); 727 } 728 729 /* 730 * ixgbe_identify_hardware - Identify the type of the chipset. 731 */ 732 static int 733 ixgbe_identify_hardware(ixgbe_t *ixgbe) 734 { 735 struct ixgbe_hw *hw = &ixgbe->hw; 736 struct ixgbe_osdep *osdep = &ixgbe->osdep; 737 738 /* 739 * Get the device id 740 */ 741 hw->vendor_id = 742 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 743 hw->device_id = 744 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 745 hw->revision_id = 746 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 747 hw->subsystem_device_id = 748 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 749 hw->subsystem_vendor_id = 750 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 751 752 /* 753 * Set the mac type of the adapter based on the device id 754 */ 755 if (ixgbe_set_mac_type(hw) != IXGBE_SUCCESS) { 756 return (IXGBE_FAILURE); 757 } 758 759 /* 760 * Install adapter capabilities 761 */ 762 switch (hw->mac.type) { 763 case ixgbe_mac_82598EB: 764 ixgbe_log(ixgbe, "identify oplin adapter\n"); 765 ixgbe->capab = &ixgbe_82598eb_cap; 766 767 if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) { 768 ixgbe->capab->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 769 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP1; 770 } 771 772 break; 773 default: 774 ixgbe_log(ixgbe, 775 "adapter not supported in ixgbe_identify_hardware(): %d\n", 776 hw->mac.type); 777 return (IXGBE_FAILURE); 778 } 779 780 return (IXGBE_SUCCESS); 781 } 782 783 /* 784 * ixgbe_regs_map - Map the device registers. 785 * 786 */ 787 static int 788 ixgbe_regs_map(ixgbe_t *ixgbe) 789 { 790 dev_info_t *devinfo = ixgbe->dip; 791 struct ixgbe_hw *hw = &ixgbe->hw; 792 struct ixgbe_osdep *osdep = &ixgbe->osdep; 793 off_t mem_size; 794 795 /* 796 * First get the size of device registers to be mapped. 797 */ 798 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 799 return (IXGBE_FAILURE); 800 } 801 802 /* 803 * Call ddi_regs_map_setup() to map registers 804 */ 805 if ((ddi_regs_map_setup(devinfo, 1, 806 (caddr_t *)&hw->hw_addr, 0, 807 mem_size, &ixgbe_regs_acc_attr, 808 &osdep->reg_handle)) != DDI_SUCCESS) { 809 return (IXGBE_FAILURE); 810 } 811 812 return (IXGBE_SUCCESS); 813 } 814 815 /* 816 * ixgbe_init_properties - Initialize driver properties. 817 */ 818 static void 819 ixgbe_init_properties(ixgbe_t *ixgbe) 820 { 821 /* 822 * Get conf file properties, including link settings 823 * jumbo frames, ring number, descriptor number, etc. 824 */ 825 ixgbe_get_conf(ixgbe); 826 } 827 828 /* 829 * ixgbe_init_driver_settings - Initialize driver settings. 830 * 831 * The settings include hardware function pointers, bus information, 832 * rx/tx rings settings, link state, and any other parameters that 833 * need to be setup during driver initialization. 834 */ 835 static int 836 ixgbe_init_driver_settings(ixgbe_t *ixgbe) 837 { 838 struct ixgbe_hw *hw = &ixgbe->hw; 839 dev_info_t *devinfo = ixgbe->dip; 840 ixgbe_rx_ring_t *rx_ring; 841 ixgbe_tx_ring_t *tx_ring; 842 uint32_t rx_size; 843 uint32_t tx_size; 844 int i; 845 846 /* 847 * Initialize chipset specific hardware function pointers 848 */ 849 if (ixgbe_init_shared_code(hw) != IXGBE_SUCCESS) { 850 return (IXGBE_FAILURE); 851 } 852 853 /* 854 * Get the system page size 855 */ 856 ixgbe->sys_page_size = ddi_ptob(devinfo, (ulong_t)1); 857 858 /* 859 * Set rx buffer size 860 * 861 * The IP header alignment room is counted in the calculation. 862 * The rx buffer size is in unit of 1K that is required by the 863 * chipset hardware. 864 */ 865 rx_size = ixgbe->max_frame_size + IPHDR_ALIGN_ROOM; 866 ixgbe->rx_buf_size = ((rx_size >> 10) + 867 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 868 869 /* 870 * Set tx buffer size 871 */ 872 tx_size = ixgbe->max_frame_size; 873 ixgbe->tx_buf_size = ((tx_size >> 10) + 874 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 875 876 /* 877 * Initialize rx/tx rings parameters 878 */ 879 for (i = 0; i < ixgbe->num_rx_rings; i++) { 880 rx_ring = &ixgbe->rx_rings[i]; 881 rx_ring->index = i; 882 rx_ring->ixgbe = ixgbe; 883 884 rx_ring->ring_size = ixgbe->rx_ring_size; 885 rx_ring->free_list_size = ixgbe->rx_ring_size; 886 rx_ring->copy_thresh = ixgbe->rx_copy_thresh; 887 rx_ring->limit_per_intr = ixgbe->rx_limit_per_intr; 888 } 889 890 for (i = 0; i < ixgbe->num_tx_rings; i++) { 891 tx_ring = &ixgbe->tx_rings[i]; 892 tx_ring->index = i; 893 tx_ring->ixgbe = ixgbe; 894 if (ixgbe->tx_head_wb_enable) 895 tx_ring->tx_recycle = ixgbe_tx_recycle_head_wb; 896 else 897 tx_ring->tx_recycle = ixgbe_tx_recycle_legacy; 898 899 tx_ring->ring_size = ixgbe->tx_ring_size; 900 tx_ring->free_list_size = ixgbe->tx_ring_size + 901 (ixgbe->tx_ring_size >> 1); 902 tx_ring->copy_thresh = ixgbe->tx_copy_thresh; 903 tx_ring->recycle_thresh = ixgbe->tx_recycle_thresh; 904 tx_ring->overload_thresh = ixgbe->tx_overload_thresh; 905 tx_ring->resched_thresh = ixgbe->tx_resched_thresh; 906 } 907 908 /* 909 * Initialize values of interrupt throttling rate 910 */ 911 for (i = 1; i < MAX_RING_VECTOR; i++) 912 ixgbe->intr_throttling[i] = ixgbe->intr_throttling[0]; 913 914 /* 915 * The initial link state should be "unknown" 916 */ 917 ixgbe->link_state = LINK_STATE_UNKNOWN; 918 return (IXGBE_SUCCESS); 919 } 920 921 /* 922 * ixgbe_init_locks - Initialize locks. 923 */ 924 static void 925 ixgbe_init_locks(ixgbe_t *ixgbe) 926 { 927 ixgbe_rx_ring_t *rx_ring; 928 ixgbe_tx_ring_t *tx_ring; 929 int i; 930 931 for (i = 0; i < ixgbe->num_rx_rings; i++) { 932 rx_ring = &ixgbe->rx_rings[i]; 933 mutex_init(&rx_ring->rx_lock, NULL, 934 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 935 mutex_init(&rx_ring->recycle_lock, NULL, 936 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 937 } 938 939 for (i = 0; i < ixgbe->num_tx_rings; i++) { 940 tx_ring = &ixgbe->tx_rings[i]; 941 mutex_init(&tx_ring->tx_lock, NULL, 942 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 943 mutex_init(&tx_ring->recycle_lock, NULL, 944 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 945 mutex_init(&tx_ring->tcb_head_lock, NULL, 946 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 947 mutex_init(&tx_ring->tcb_tail_lock, NULL, 948 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 949 } 950 951 mutex_init(&ixgbe->gen_lock, NULL, 952 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 953 954 mutex_init(&ixgbe->watchdog_lock, NULL, 955 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri)); 956 } 957 958 /* 959 * ixgbe_destroy_locks - Destroy locks. 960 */ 961 static void 962 ixgbe_destroy_locks(ixgbe_t *ixgbe) 963 { 964 ixgbe_rx_ring_t *rx_ring; 965 ixgbe_tx_ring_t *tx_ring; 966 int i; 967 968 for (i = 0; i < ixgbe->num_rx_rings; i++) { 969 rx_ring = &ixgbe->rx_rings[i]; 970 mutex_destroy(&rx_ring->rx_lock); 971 mutex_destroy(&rx_ring->recycle_lock); 972 } 973 974 for (i = 0; i < ixgbe->num_tx_rings; i++) { 975 tx_ring = &ixgbe->tx_rings[i]; 976 mutex_destroy(&tx_ring->tx_lock); 977 mutex_destroy(&tx_ring->recycle_lock); 978 mutex_destroy(&tx_ring->tcb_head_lock); 979 mutex_destroy(&tx_ring->tcb_tail_lock); 980 } 981 982 mutex_destroy(&ixgbe->gen_lock); 983 mutex_destroy(&ixgbe->watchdog_lock); 984 } 985 986 static int 987 ixgbe_resume(dev_info_t *devinfo) 988 { 989 ixgbe_t *ixgbe; 990 991 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo); 992 if (ixgbe == NULL) 993 return (DDI_FAILURE); 994 995 mutex_enter(&ixgbe->gen_lock); 996 997 if (ixgbe->ixgbe_state & IXGBE_STARTED) { 998 if (ixgbe_start(ixgbe) != IXGBE_SUCCESS) { 999 mutex_exit(&ixgbe->gen_lock); 1000 return (DDI_FAILURE); 1001 } 1002 1003 /* 1004 * Enable and start the watchdog timer 1005 */ 1006 ixgbe_enable_watchdog_timer(ixgbe); 1007 } 1008 1009 ixgbe->ixgbe_state &= ~IXGBE_SUSPENDED; 1010 1011 mutex_exit(&ixgbe->gen_lock); 1012 1013 return (DDI_SUCCESS); 1014 } 1015 1016 static int 1017 ixgbe_suspend(dev_info_t *devinfo) 1018 { 1019 ixgbe_t *ixgbe; 1020 1021 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo); 1022 if (ixgbe == NULL) 1023 return (DDI_FAILURE); 1024 1025 mutex_enter(&ixgbe->gen_lock); 1026 1027 ixgbe->ixgbe_state |= IXGBE_SUSPENDED; 1028 1029 ixgbe_stop(ixgbe); 1030 1031 mutex_exit(&ixgbe->gen_lock); 1032 1033 /* 1034 * Disable and stop the watchdog timer 1035 */ 1036 ixgbe_disable_watchdog_timer(ixgbe); 1037 1038 return (DDI_SUCCESS); 1039 } 1040 1041 /* 1042 * ixgbe_init - Initialize the device. 1043 */ 1044 static int 1045 ixgbe_init(ixgbe_t *ixgbe) 1046 { 1047 struct ixgbe_hw *hw = &ixgbe->hw; 1048 1049 mutex_enter(&ixgbe->gen_lock); 1050 1051 /* 1052 * Reset chipset to put the hardware in a known state 1053 * before we try to do anything with the eeprom. 1054 */ 1055 if (ixgbe_reset_hw(hw) != IXGBE_SUCCESS) { 1056 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE); 1057 goto init_fail; 1058 } 1059 1060 /* 1061 * Need to init eeprom before validating the checksum. 1062 */ 1063 if (ixgbe_init_eeprom_params(hw) < 0) { 1064 ixgbe_error(ixgbe, 1065 "Unable to intitialize the eeprom interface."); 1066 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE); 1067 goto init_fail; 1068 } 1069 1070 /* 1071 * NVM validation 1072 */ 1073 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) { 1074 /* 1075 * Some PCI-E parts fail the first check due to 1076 * the link being in sleep state. Call it again, 1077 * if it fails a second time it's a real issue. 1078 */ 1079 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) { 1080 ixgbe_error(ixgbe, 1081 "Invalid NVM checksum. Please contact " 1082 "the vendor to update the NVM."); 1083 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE); 1084 goto init_fail; 1085 } 1086 } 1087 1088 /* 1089 * Setup default flow control thresholds - enable/disable 1090 * & flow control type is controlled by ixgbe.conf 1091 */ 1092 hw->fc.high_water = DEFAULT_FCRTH; 1093 hw->fc.low_water = DEFAULT_FCRTL; 1094 hw->fc.pause_time = DEFAULT_FCPAUSE; 1095 hw->fc.send_xon = B_TRUE; 1096 1097 /* 1098 * Don't wait for auto-negotiation to complete 1099 */ 1100 hw->phy.autoneg_wait_to_complete = B_FALSE; 1101 1102 /* 1103 * Initialize link settings 1104 */ 1105 (void) ixgbe_driver_setup_link(ixgbe, B_FALSE); 1106 1107 /* 1108 * Initialize the chipset hardware 1109 */ 1110 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) { 1111 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE); 1112 goto init_fail; 1113 } 1114 1115 if (ixgbe_check_acc_handle(ixgbe->osdep.cfg_handle) != DDI_FM_OK) { 1116 goto init_fail; 1117 } 1118 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 1119 goto init_fail; 1120 } 1121 1122 mutex_exit(&ixgbe->gen_lock); 1123 return (IXGBE_SUCCESS); 1124 1125 init_fail: 1126 /* 1127 * Reset PHY 1128 */ 1129 (void) ixgbe_reset_phy(hw); 1130 1131 mutex_exit(&ixgbe->gen_lock); 1132 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST); 1133 return (IXGBE_FAILURE); 1134 } 1135 1136 /* 1137 * ixgbe_init_rings - Allocate DMA resources for all rx/tx rings and 1138 * initialize relevant hardware settings. 1139 */ 1140 static int 1141 ixgbe_init_rings(ixgbe_t *ixgbe) 1142 { 1143 int i; 1144 1145 /* 1146 * Allocate buffers for all the rx/tx rings 1147 */ 1148 if (ixgbe_alloc_dma(ixgbe) != IXGBE_SUCCESS) 1149 return (IXGBE_FAILURE); 1150 1151 /* 1152 * Setup the rx/tx rings 1153 */ 1154 mutex_enter(&ixgbe->gen_lock); 1155 1156 for (i = 0; i < ixgbe->num_rx_rings; i++) 1157 mutex_enter(&ixgbe->rx_rings[i].rx_lock); 1158 for (i = 0; i < ixgbe->num_tx_rings; i++) 1159 mutex_enter(&ixgbe->tx_rings[i].tx_lock); 1160 1161 ixgbe_setup_rings(ixgbe); 1162 1163 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--) 1164 mutex_exit(&ixgbe->tx_rings[i].tx_lock); 1165 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--) 1166 mutex_exit(&ixgbe->rx_rings[i].rx_lock); 1167 1168 mutex_exit(&ixgbe->gen_lock); 1169 1170 return (IXGBE_SUCCESS); 1171 } 1172 1173 /* 1174 * ixgbe_fini_rings - Release DMA resources of all rx/tx rings. 1175 */ 1176 static void 1177 ixgbe_fini_rings(ixgbe_t *ixgbe) 1178 { 1179 /* 1180 * Release the DMA/memory resources of rx/tx rings 1181 */ 1182 ixgbe_free_dma(ixgbe); 1183 } 1184 1185 /* 1186 * ixgbe_chip_start - Initialize and start the chipset hardware. 1187 */ 1188 static int 1189 ixgbe_chip_start(ixgbe_t *ixgbe) 1190 { 1191 struct ixgbe_hw *hw = &ixgbe->hw; 1192 int i; 1193 1194 ASSERT(mutex_owned(&ixgbe->gen_lock)); 1195 1196 /* 1197 * Get the mac address 1198 * This function should handle SPARC case correctly. 1199 */ 1200 if (!ixgbe_find_mac_address(ixgbe)) { 1201 ixgbe_error(ixgbe, "Failed to get the mac address"); 1202 return (IXGBE_FAILURE); 1203 } 1204 1205 /* 1206 * Validate the mac address 1207 */ 1208 (void) ixgbe_init_rx_addrs(hw); 1209 if (!is_valid_mac_addr(hw->mac.addr)) { 1210 ixgbe_error(ixgbe, "Invalid mac address"); 1211 return (IXGBE_FAILURE); 1212 } 1213 1214 /* 1215 * Configure/Initialize hardware 1216 */ 1217 if (ixgbe_init_hw(hw) != IXGBE_SUCCESS) { 1218 ixgbe_error(ixgbe, "Failed to initialize hardware"); 1219 return (IXGBE_FAILURE); 1220 } 1221 1222 /* 1223 * Setup adapter interrupt vectors 1224 */ 1225 ixgbe_setup_adapter_vector(ixgbe); 1226 1227 /* 1228 * Initialize unicast addresses. 1229 */ 1230 ixgbe_init_unicst(ixgbe); 1231 1232 /* 1233 * Setup and initialize the mctable structures. 1234 */ 1235 ixgbe_setup_multicst(ixgbe); 1236 1237 /* 1238 * Set interrupt throttling rate 1239 */ 1240 for (i = 0; i < ixgbe->intr_cnt; i++) 1241 IXGBE_WRITE_REG(hw, IXGBE_EITR(i), ixgbe->intr_throttling[i]); 1242 1243 /* 1244 * Save the state of the phy 1245 */ 1246 ixgbe_get_hw_state(ixgbe); 1247 1248 /* 1249 * Make sure driver has control 1250 */ 1251 ixgbe_get_driver_control(hw); 1252 1253 return (IXGBE_SUCCESS); 1254 } 1255 1256 /* 1257 * ixgbe_chip_stop - Stop the chipset hardware 1258 */ 1259 static void 1260 ixgbe_chip_stop(ixgbe_t *ixgbe) 1261 { 1262 struct ixgbe_hw *hw = &ixgbe->hw; 1263 1264 ASSERT(mutex_owned(&ixgbe->gen_lock)); 1265 1266 /* 1267 * Tell firmware driver is no longer in control 1268 */ 1269 ixgbe_release_driver_control(hw); 1270 1271 /* 1272 * Reset the chipset 1273 */ 1274 (void) ixgbe_reset_hw(hw); 1275 1276 /* 1277 * Reset PHY 1278 */ 1279 (void) ixgbe_reset_phy(hw); 1280 } 1281 1282 /* 1283 * ixgbe_reset - Reset the chipset and re-start the driver. 1284 * 1285 * It involves stopping and re-starting the chipset, 1286 * and re-configuring the rx/tx rings. 1287 */ 1288 static int 1289 ixgbe_reset(ixgbe_t *ixgbe) 1290 { 1291 int i; 1292 1293 mutex_enter(&ixgbe->gen_lock); 1294 1295 ASSERT(ixgbe->ixgbe_state & IXGBE_STARTED); 1296 ixgbe->ixgbe_state &= ~IXGBE_STARTED; 1297 1298 /* 1299 * Disable the adapter interrupts to stop any rx/tx activities 1300 * before draining pending data and resetting hardware. 1301 */ 1302 ixgbe_disable_adapter_interrupts(ixgbe); 1303 1304 /* 1305 * Drain the pending transmit packets 1306 */ 1307 (void) ixgbe_tx_drain(ixgbe); 1308 1309 for (i = 0; i < ixgbe->num_rx_rings; i++) 1310 mutex_enter(&ixgbe->rx_rings[i].rx_lock); 1311 for (i = 0; i < ixgbe->num_tx_rings; i++) 1312 mutex_enter(&ixgbe->tx_rings[i].tx_lock); 1313 1314 /* 1315 * Stop the chipset hardware 1316 */ 1317 ixgbe_chip_stop(ixgbe); 1318 1319 /* 1320 * Clean the pending tx data/resources 1321 */ 1322 ixgbe_tx_clean(ixgbe); 1323 1324 /* 1325 * Start the chipset hardware 1326 */ 1327 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) { 1328 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE); 1329 goto reset_failure; 1330 } 1331 1332 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 1333 goto reset_failure; 1334 } 1335 1336 /* 1337 * Setup the rx/tx rings 1338 */ 1339 ixgbe_setup_rings(ixgbe); 1340 1341 /* 1342 * Enable adapter interrupts 1343 * The interrupts must be enabled after the driver state is START 1344 */ 1345 ixgbe_enable_adapter_interrupts(ixgbe); 1346 1347 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--) 1348 mutex_exit(&ixgbe->tx_rings[i].tx_lock); 1349 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--) 1350 mutex_exit(&ixgbe->rx_rings[i].rx_lock); 1351 1352 ixgbe->ixgbe_state |= IXGBE_STARTED; 1353 mutex_exit(&ixgbe->gen_lock); 1354 1355 return (IXGBE_SUCCESS); 1356 1357 reset_failure: 1358 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--) 1359 mutex_exit(&ixgbe->tx_rings[i].tx_lock); 1360 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--) 1361 mutex_exit(&ixgbe->rx_rings[i].rx_lock); 1362 1363 mutex_exit(&ixgbe->gen_lock); 1364 1365 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST); 1366 1367 return (IXGBE_FAILURE); 1368 } 1369 1370 /* 1371 * ixgbe_tx_clean - Clean the pending transmit packets and DMA resources. 1372 */ 1373 static void 1374 ixgbe_tx_clean(ixgbe_t *ixgbe) 1375 { 1376 ixgbe_tx_ring_t *tx_ring; 1377 tx_control_block_t *tcb; 1378 link_list_t pending_list; 1379 uint32_t desc_num; 1380 int i, j; 1381 1382 LINK_LIST_INIT(&pending_list); 1383 1384 for (i = 0; i < ixgbe->num_tx_rings; i++) { 1385 tx_ring = &ixgbe->tx_rings[i]; 1386 1387 mutex_enter(&tx_ring->recycle_lock); 1388 1389 /* 1390 * Clean the pending tx data - the pending packets in the 1391 * work_list that have no chances to be transmitted again. 1392 * 1393 * We must ensure the chipset is stopped or the link is down 1394 * before cleaning the transmit packets. 1395 */ 1396 desc_num = 0; 1397 for (j = 0; j < tx_ring->ring_size; j++) { 1398 tcb = tx_ring->work_list[j]; 1399 if (tcb != NULL) { 1400 desc_num += tcb->desc_num; 1401 1402 tx_ring->work_list[j] = NULL; 1403 1404 ixgbe_free_tcb(tcb); 1405 1406 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1407 } 1408 } 1409 1410 if (desc_num > 0) { 1411 atomic_add_32(&tx_ring->tbd_free, desc_num); 1412 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1413 1414 /* 1415 * Reset the head and tail pointers of the tbd ring; 1416 * Reset the writeback head if it's enable. 1417 */ 1418 tx_ring->tbd_head = 0; 1419 tx_ring->tbd_tail = 0; 1420 if (ixgbe->tx_head_wb_enable) 1421 *tx_ring->tbd_head_wb = 0; 1422 1423 IXGBE_WRITE_REG(&ixgbe->hw, 1424 IXGBE_TDH(tx_ring->index), 0); 1425 IXGBE_WRITE_REG(&ixgbe->hw, 1426 IXGBE_TDT(tx_ring->index), 0); 1427 } 1428 1429 mutex_exit(&tx_ring->recycle_lock); 1430 1431 /* 1432 * Add the tx control blocks in the pending list to 1433 * the free list. 1434 */ 1435 ixgbe_put_free_list(tx_ring, &pending_list); 1436 } 1437 } 1438 1439 /* 1440 * ixgbe_tx_drain - Drain the tx rings to allow pending packets to be 1441 * transmitted. 1442 */ 1443 static boolean_t 1444 ixgbe_tx_drain(ixgbe_t *ixgbe) 1445 { 1446 ixgbe_tx_ring_t *tx_ring; 1447 boolean_t done; 1448 int i, j; 1449 1450 /* 1451 * Wait for a specific time to allow pending tx packets 1452 * to be transmitted. 1453 * 1454 * Check the counter tbd_free to see if transmission is done. 1455 * No lock protection is needed here. 1456 * 1457 * Return B_TRUE if all pending packets have been transmitted; 1458 * Otherwise return B_FALSE; 1459 */ 1460 for (i = 0; i < TX_DRAIN_TIME; i++) { 1461 1462 done = B_TRUE; 1463 for (j = 0; j < ixgbe->num_tx_rings; j++) { 1464 tx_ring = &ixgbe->tx_rings[j]; 1465 done = done && 1466 (tx_ring->tbd_free == tx_ring->ring_size); 1467 } 1468 1469 if (done) 1470 break; 1471 1472 msec_delay(1); 1473 } 1474 1475 return (done); 1476 } 1477 1478 /* 1479 * ixgbe_rx_drain - Wait for all rx buffers to be released by upper layer. 1480 */ 1481 static boolean_t 1482 ixgbe_rx_drain(ixgbe_t *ixgbe) 1483 { 1484 ixgbe_rx_ring_t *rx_ring; 1485 boolean_t done; 1486 int i, j; 1487 1488 /* 1489 * Polling the rx free list to check if those rx buffers held by 1490 * the upper layer are released. 1491 * 1492 * Check the counter rcb_free to see if all pending buffers are 1493 * released. No lock protection is needed here. 1494 * 1495 * Return B_TRUE if all pending buffers have been released; 1496 * Otherwise return B_FALSE; 1497 */ 1498 for (i = 0; i < RX_DRAIN_TIME; i++) { 1499 1500 done = B_TRUE; 1501 for (j = 0; j < ixgbe->num_rx_rings; j++) { 1502 rx_ring = &ixgbe->rx_rings[j]; 1503 done = done && 1504 (rx_ring->rcb_free == rx_ring->free_list_size); 1505 } 1506 1507 if (done) 1508 break; 1509 1510 msec_delay(1); 1511 } 1512 1513 return (done); 1514 } 1515 1516 /* 1517 * ixgbe_start - Start the driver/chipset. 1518 */ 1519 int 1520 ixgbe_start(ixgbe_t *ixgbe) 1521 { 1522 int i; 1523 1524 ASSERT(mutex_owned(&ixgbe->gen_lock)); 1525 1526 for (i = 0; i < ixgbe->num_rx_rings; i++) 1527 mutex_enter(&ixgbe->rx_rings[i].rx_lock); 1528 for (i = 0; i < ixgbe->num_tx_rings; i++) 1529 mutex_enter(&ixgbe->tx_rings[i].tx_lock); 1530 1531 /* 1532 * Start the chipset hardware 1533 */ 1534 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) { 1535 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE); 1536 goto start_failure; 1537 } 1538 1539 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 1540 goto start_failure; 1541 } 1542 1543 /* 1544 * Setup the rx/tx rings 1545 */ 1546 ixgbe_setup_rings(ixgbe); 1547 1548 /* 1549 * Enable adapter interrupts 1550 * The interrupts must be enabled after the driver state is START 1551 */ 1552 ixgbe_enable_adapter_interrupts(ixgbe); 1553 1554 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--) 1555 mutex_exit(&ixgbe->tx_rings[i].tx_lock); 1556 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--) 1557 mutex_exit(&ixgbe->rx_rings[i].rx_lock); 1558 1559 return (IXGBE_SUCCESS); 1560 1561 start_failure: 1562 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--) 1563 mutex_exit(&ixgbe->tx_rings[i].tx_lock); 1564 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--) 1565 mutex_exit(&ixgbe->rx_rings[i].rx_lock); 1566 1567 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST); 1568 1569 return (IXGBE_FAILURE); 1570 } 1571 1572 /* 1573 * ixgbe_stop - Stop the driver/chipset. 1574 */ 1575 void 1576 ixgbe_stop(ixgbe_t *ixgbe) 1577 { 1578 int i; 1579 1580 ASSERT(mutex_owned(&ixgbe->gen_lock)); 1581 1582 /* 1583 * Disable the adapter interrupts 1584 */ 1585 ixgbe_disable_adapter_interrupts(ixgbe); 1586 1587 /* 1588 * Drain the pending tx packets 1589 */ 1590 (void) ixgbe_tx_drain(ixgbe); 1591 1592 for (i = 0; i < ixgbe->num_rx_rings; i++) 1593 mutex_enter(&ixgbe->rx_rings[i].rx_lock); 1594 for (i = 0; i < ixgbe->num_tx_rings; i++) 1595 mutex_enter(&ixgbe->tx_rings[i].tx_lock); 1596 1597 /* 1598 * Stop the chipset hardware 1599 */ 1600 ixgbe_chip_stop(ixgbe); 1601 1602 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 1603 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST); 1604 } 1605 1606 /* 1607 * Clean the pending tx data/resources 1608 */ 1609 ixgbe_tx_clean(ixgbe); 1610 1611 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--) 1612 mutex_exit(&ixgbe->tx_rings[i].tx_lock); 1613 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--) 1614 mutex_exit(&ixgbe->rx_rings[i].rx_lock); 1615 } 1616 1617 /* 1618 * ixgbe_alloc_rings - Allocate memory space for rx/tx rings. 1619 */ 1620 static int 1621 ixgbe_alloc_rings(ixgbe_t *ixgbe) 1622 { 1623 /* 1624 * Allocate memory space for rx rings 1625 */ 1626 ixgbe->rx_rings = kmem_zalloc( 1627 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings, 1628 KM_NOSLEEP); 1629 1630 if (ixgbe->rx_rings == NULL) { 1631 return (IXGBE_FAILURE); 1632 } 1633 1634 /* 1635 * Allocate memory space for tx rings 1636 */ 1637 ixgbe->tx_rings = kmem_zalloc( 1638 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings, 1639 KM_NOSLEEP); 1640 1641 if (ixgbe->tx_rings == NULL) { 1642 kmem_free(ixgbe->rx_rings, 1643 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings); 1644 ixgbe->rx_rings = NULL; 1645 return (IXGBE_FAILURE); 1646 } 1647 1648 /* 1649 * Allocate memory space for rx ring groups 1650 */ 1651 ixgbe->rx_groups = kmem_zalloc( 1652 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups, 1653 KM_NOSLEEP); 1654 1655 if (ixgbe->rx_groups == NULL) { 1656 kmem_free(ixgbe->rx_rings, 1657 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings); 1658 kmem_free(ixgbe->tx_rings, 1659 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings); 1660 ixgbe->rx_rings = NULL; 1661 ixgbe->tx_rings = NULL; 1662 return (IXGBE_FAILURE); 1663 } 1664 1665 return (IXGBE_SUCCESS); 1666 } 1667 1668 /* 1669 * ixgbe_free_rings - Free the memory space of rx/tx rings. 1670 */ 1671 static void 1672 ixgbe_free_rings(ixgbe_t *ixgbe) 1673 { 1674 if (ixgbe->rx_rings != NULL) { 1675 kmem_free(ixgbe->rx_rings, 1676 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings); 1677 ixgbe->rx_rings = NULL; 1678 } 1679 1680 if (ixgbe->tx_rings != NULL) { 1681 kmem_free(ixgbe->tx_rings, 1682 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings); 1683 ixgbe->tx_rings = NULL; 1684 } 1685 1686 if (ixgbe->rx_groups != NULL) { 1687 kmem_free(ixgbe->rx_groups, 1688 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups); 1689 ixgbe->rx_groups = NULL; 1690 } 1691 } 1692 1693 /* 1694 * ixgbe_setup_rings - Setup rx/tx rings. 1695 */ 1696 static void 1697 ixgbe_setup_rings(ixgbe_t *ixgbe) 1698 { 1699 /* 1700 * Setup the rx/tx rings, including the following: 1701 * 1702 * 1. Setup the descriptor ring and the control block buffers; 1703 * 2. Initialize necessary registers for receive/transmit; 1704 * 3. Initialize software pointers/parameters for receive/transmit; 1705 */ 1706 ixgbe_setup_rx(ixgbe); 1707 1708 ixgbe_setup_tx(ixgbe); 1709 } 1710 1711 static void 1712 ixgbe_setup_rx_ring(ixgbe_rx_ring_t *rx_ring) 1713 { 1714 ixgbe_t *ixgbe = rx_ring->ixgbe; 1715 struct ixgbe_hw *hw = &ixgbe->hw; 1716 rx_control_block_t *rcb; 1717 union ixgbe_adv_rx_desc *rbd; 1718 uint32_t size; 1719 uint32_t buf_low; 1720 uint32_t buf_high; 1721 uint32_t reg_val; 1722 int i; 1723 1724 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1725 ASSERT(mutex_owned(&ixgbe->gen_lock)); 1726 1727 for (i = 0; i < ixgbe->rx_ring_size; i++) { 1728 rcb = rx_ring->work_list[i]; 1729 rbd = &rx_ring->rbd_ring[i]; 1730 1731 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1732 rbd->read.hdr_addr = NULL; 1733 } 1734 1735 /* 1736 * Initialize the length register 1737 */ 1738 size = rx_ring->ring_size * sizeof (union ixgbe_adv_rx_desc); 1739 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rx_ring->index), size); 1740 1741 /* 1742 * Initialize the base address registers 1743 */ 1744 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1745 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1746 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rx_ring->index), buf_high); 1747 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rx_ring->index), buf_low); 1748 1749 /* 1750 * Setup head & tail pointers 1751 */ 1752 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->index), rx_ring->ring_size - 1); 1753 IXGBE_WRITE_REG(hw, IXGBE_RDH(rx_ring->index), 0); 1754 1755 rx_ring->rbd_next = 0; 1756 1757 /* 1758 * Note: Considering the case that the chipset is being reset 1759 * and there are still some buffers held by the upper layer, 1760 * we should not reset the values of rcb_head, rcb_tail and 1761 * rcb_free if the state is not IXGBE_UNKNOWN. 1762 */ 1763 if (ixgbe->ixgbe_state == IXGBE_UNKNOWN) { 1764 rx_ring->rcb_head = 0; 1765 rx_ring->rcb_tail = 0; 1766 rx_ring->rcb_free = rx_ring->free_list_size; 1767 } 1768 1769 /* 1770 * Setup the Receive Descriptor Control Register (RXDCTL) 1771 * PTHRESH=32 descriptors (half the internal cache) 1772 * HTHRESH=0 descriptors (to minimize latency on fetch) 1773 * WTHRESH defaults to 1 (writeback each descriptor) 1774 */ 1775 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->index)); 1776 reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */ 1777 reg_val |= 0x0020; /* pthresh */ 1778 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->index), reg_val); 1779 1780 /* 1781 * Setup the Split and Replication Receive Control Register. 1782 * Set the rx buffer size and the advanced descriptor type. 1783 */ 1784 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) | 1785 IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 1786 1787 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rx_ring->index), reg_val); 1788 } 1789 1790 static void 1791 ixgbe_setup_rx(ixgbe_t *ixgbe) 1792 { 1793 ixgbe_rx_ring_t *rx_ring; 1794 struct ixgbe_hw *hw = &ixgbe->hw; 1795 ixgbe_rx_group_t *rx_group; 1796 uint32_t reg_val; 1797 uint32_t ring_mapping; 1798 int i; 1799 1800 /* 1801 * Set filter control in FCTRL to accept broadcast packets and do 1802 * not pass pause frames to host. Flow control settings are already 1803 * in this register, so preserve them. 1804 */ 1805 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1806 reg_val |= IXGBE_FCTRL_BAM; /* broadcast accept mode */ 1807 reg_val |= IXGBE_FCTRL_DPF; /* discard pause frames */ 1808 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_val); 1809 1810 /* 1811 * Enable the receive unit. This must be done after filter 1812 * control is set in FCTRL. 1813 */ 1814 reg_val = (IXGBE_RXCTRL_RXEN /* Enable Receive Unit */ 1815 | IXGBE_RXCTRL_DMBYPS); /* descriptor monitor bypass */ 1816 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 1817 1818 /* 1819 * ixgbe_setup_rx_ring must be called after configuring RXCTRL 1820 */ 1821 for (i = 0; i < ixgbe->num_rx_rings; i++) { 1822 rx_ring = &ixgbe->rx_rings[i]; 1823 ixgbe_setup_rx_ring(rx_ring); 1824 } 1825 1826 /* 1827 * Setup rx groups. 1828 */ 1829 for (i = 0; i < ixgbe->num_rx_groups; i++) { 1830 rx_group = &ixgbe->rx_groups[i]; 1831 rx_group->index = i; 1832 rx_group->ixgbe = ixgbe; 1833 } 1834 1835 /* 1836 * Setup the per-ring statistics mapping. 1837 */ 1838 ring_mapping = 0; 1839 for (i = 0; i < ixgbe->num_rx_rings; i++) { 1840 ring_mapping |= (i & 0xF) << (8 * (i & 0x3)); 1841 if ((i & 0x3) == 0x3) { 1842 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i >> 2), ring_mapping); 1843 ring_mapping = 0; 1844 } 1845 } 1846 if ((i & 0x3) != 0x3) 1847 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i >> 2), ring_mapping); 1848 1849 /* 1850 * The Max Frame Size in MHADD will be internally increased by four 1851 * bytes if the packet has a VLAN field, so includes MTU, ethernet 1852 * header and frame check sequence. 1853 */ 1854 reg_val = (ixgbe->default_mtu + sizeof (struct ether_header) 1855 + ETHERFCSL) << IXGBE_MHADD_MFS_SHIFT; 1856 IXGBE_WRITE_REG(hw, IXGBE_MHADD, reg_val); 1857 1858 /* 1859 * Setup Jumbo Frame enable bit 1860 */ 1861 if (ixgbe->default_mtu > ETHERMTU) { 1862 reg_val = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1863 reg_val |= IXGBE_HLREG0_JUMBOEN; 1864 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val); 1865 } 1866 1867 /* 1868 * Hardware checksum settings 1869 */ 1870 if (ixgbe->rx_hcksum_enable) { 1871 reg_val = IXGBE_RXCSUM_IPPCSE; /* IP checksum */ 1872 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, reg_val); 1873 } 1874 1875 /* 1876 * Setup RSS for multiple receive queues 1877 */ 1878 if (ixgbe->num_rx_rings > 1) 1879 ixgbe_setup_rss(ixgbe); 1880 } 1881 1882 static void 1883 ixgbe_setup_tx_ring(ixgbe_tx_ring_t *tx_ring) 1884 { 1885 ixgbe_t *ixgbe = tx_ring->ixgbe; 1886 struct ixgbe_hw *hw = &ixgbe->hw; 1887 uint32_t size; 1888 uint32_t buf_low; 1889 uint32_t buf_high; 1890 uint32_t reg_val; 1891 1892 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1893 ASSERT(mutex_owned(&ixgbe->gen_lock)); 1894 1895 /* 1896 * Initialize the length register 1897 */ 1898 size = tx_ring->ring_size * sizeof (union ixgbe_adv_tx_desc); 1899 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(tx_ring->index), size); 1900 1901 /* 1902 * Initialize the base address registers 1903 */ 1904 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1905 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1906 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(tx_ring->index), buf_low); 1907 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(tx_ring->index), buf_high); 1908 1909 /* 1910 * setup TXDCTL(tx_ring->index) 1911 */ 1912 reg_val = IXGBE_TXDCTL_ENABLE; 1913 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->index), reg_val); 1914 1915 /* 1916 * Setup head & tail pointers 1917 */ 1918 IXGBE_WRITE_REG(hw, IXGBE_TDH(tx_ring->index), 0); 1919 IXGBE_WRITE_REG(hw, IXGBE_TDT(tx_ring->index), 0); 1920 1921 /* 1922 * Setup head write-back 1923 */ 1924 if (ixgbe->tx_head_wb_enable) { 1925 /* 1926 * The memory of the head write-back is allocated using 1927 * the extra tbd beyond the tail of the tbd ring. 1928 */ 1929 tx_ring->tbd_head_wb = (uint32_t *) 1930 ((uintptr_t)tx_ring->tbd_area.address + size); 1931 *tx_ring->tbd_head_wb = 0; 1932 1933 buf_low = (uint32_t) 1934 (tx_ring->tbd_area.dma_address + size); 1935 buf_high = (uint32_t) 1936 ((tx_ring->tbd_area.dma_address + size) >> 32); 1937 1938 /* Set the head write-back enable bit */ 1939 buf_low |= IXGBE_TDWBAL_HEAD_WB_ENABLE; 1940 1941 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(tx_ring->index), buf_low); 1942 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(tx_ring->index), buf_high); 1943 1944 /* 1945 * Turn off relaxed ordering for head write back or it will 1946 * cause problems with the tx recycling 1947 */ 1948 reg_val = IXGBE_READ_REG(hw, 1949 IXGBE_DCA_TXCTRL(tx_ring->index)); 1950 reg_val &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 1951 IXGBE_WRITE_REG(hw, 1952 IXGBE_DCA_TXCTRL(tx_ring->index), reg_val); 1953 } else { 1954 tx_ring->tbd_head_wb = NULL; 1955 } 1956 1957 tx_ring->tbd_head = 0; 1958 tx_ring->tbd_tail = 0; 1959 tx_ring->tbd_free = tx_ring->ring_size; 1960 1961 /* 1962 * Note: Considering the case that the chipset is being reset, 1963 * and there are still some tcb in the pending list, 1964 * we should not reset the values of tcb_head, tcb_tail and 1965 * tcb_free if the state is not IXGBE_UNKNOWN. 1966 */ 1967 if (ixgbe->ixgbe_state == IXGBE_UNKNOWN) { 1968 tx_ring->tcb_head = 0; 1969 tx_ring->tcb_tail = 0; 1970 tx_ring->tcb_free = tx_ring->free_list_size; 1971 } 1972 1973 /* 1974 * Initialize the s/w context structure 1975 */ 1976 bzero(&tx_ring->tx_context, sizeof (ixgbe_tx_context_t)); 1977 } 1978 1979 static void 1980 ixgbe_setup_tx(ixgbe_t *ixgbe) 1981 { 1982 struct ixgbe_hw *hw = &ixgbe->hw; 1983 ixgbe_tx_ring_t *tx_ring; 1984 uint32_t reg_val; 1985 uint32_t ring_mapping; 1986 int i; 1987 1988 for (i = 0; i < ixgbe->num_tx_rings; i++) { 1989 tx_ring = &ixgbe->tx_rings[i]; 1990 ixgbe_setup_tx_ring(tx_ring); 1991 } 1992 1993 /* 1994 * Setup the per-ring statistics mapping. 1995 */ 1996 ring_mapping = 0; 1997 for (i = 0; i < ixgbe->num_tx_rings; i++) { 1998 ring_mapping |= (i & 0xF) << (8 * (i & 0x3)); 1999 if ((i & 0x3) == 0x3) { 2000 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2), ring_mapping); 2001 ring_mapping = 0; 2002 } 2003 } 2004 if ((i & 0x3) != 0x3) 2005 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2), ring_mapping); 2006 2007 /* 2008 * Enable CRC appending and TX padding (for short tx frames) 2009 */ 2010 reg_val = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2011 reg_val |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN; 2012 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val); 2013 } 2014 2015 /* 2016 * ixgbe_setup_rss - Setup receive-side scaling feature. 2017 */ 2018 static void 2019 ixgbe_setup_rss(ixgbe_t *ixgbe) 2020 { 2021 struct ixgbe_hw *hw = &ixgbe->hw; 2022 uint32_t i, mrqc, rxcsum; 2023 uint32_t random; 2024 uint32_t reta; 2025 2026 /* 2027 * Fill out redirection table 2028 */ 2029 reta = 0; 2030 for (i = 0; i < 128; i++) { 2031 reta = (reta << 8) | (i % ixgbe->num_rx_rings); 2032 if ((i & 3) == 3) 2033 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 2034 } 2035 2036 /* 2037 * Fill out hash function seeds with a random constant 2038 */ 2039 for (i = 0; i < 10; i++) { 2040 (void) random_get_pseudo_bytes((uint8_t *)&random, 2041 sizeof (uint32_t)); 2042 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random); 2043 } 2044 2045 /* 2046 * Enable RSS & perform hash on these packet types 2047 */ 2048 mrqc = IXGBE_MRQC_RSSEN | 2049 IXGBE_MRQC_RSS_FIELD_IPV4 | 2050 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 2051 IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2052 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP | 2053 IXGBE_MRQC_RSS_FIELD_IPV6_EX | 2054 IXGBE_MRQC_RSS_FIELD_IPV6 | 2055 IXGBE_MRQC_RSS_FIELD_IPV6_TCP | 2056 IXGBE_MRQC_RSS_FIELD_IPV6_UDP | 2057 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; 2058 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2059 2060 /* 2061 * Disable Packet Checksum to enable RSS for multiple receive queues. 2062 * It is an adapter hardware limitation that Packet Checksum is 2063 * mutually exclusive with RSS. 2064 */ 2065 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 2066 rxcsum |= IXGBE_RXCSUM_PCSD; 2067 rxcsum &= ~IXGBE_RXCSUM_IPPCSE; 2068 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 2069 } 2070 2071 /* 2072 * ixgbe_init_unicst - Initialize the unicast addresses. 2073 */ 2074 static void 2075 ixgbe_init_unicst(ixgbe_t *ixgbe) 2076 { 2077 struct ixgbe_hw *hw = &ixgbe->hw; 2078 uint8_t *mac_addr; 2079 int slot; 2080 /* 2081 * Here we should consider two situations: 2082 * 2083 * 1. Chipset is initialized at the first time, 2084 * Clear all the multiple unicast addresses. 2085 * 2086 * 2. Chipset is reset 2087 * Recover the multiple unicast addresses from the 2088 * software data structure to the RAR registers. 2089 */ 2090 if (!ixgbe->unicst_init) { 2091 /* 2092 * Initialize the multiple unicast addresses 2093 */ 2094 ixgbe->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2095 ixgbe->unicst_avail = ixgbe->unicst_total; 2096 for (slot = 0; slot < ixgbe->unicst_total; slot++) { 2097 mac_addr = ixgbe->unicst_addr[slot].mac.addr; 2098 bzero(mac_addr, ETHERADDRL); 2099 (void) ixgbe_set_rar(hw, slot, mac_addr, NULL, NULL); 2100 ixgbe->unicst_addr[slot].mac.set = 0; 2101 } 2102 ixgbe->unicst_init = B_TRUE; 2103 } else { 2104 /* Re-configure the RAR registers */ 2105 for (slot = 0; slot < ixgbe->unicst_total; slot++) { 2106 mac_addr = ixgbe->unicst_addr[slot].mac.addr; 2107 if (ixgbe->unicst_addr[slot].mac.set == 1) { 2108 (void) ixgbe_set_rar(hw, slot, mac_addr, 2109 NULL, IXGBE_RAH_AV); 2110 } else { 2111 bzero(mac_addr, ETHERADDRL); 2112 (void) ixgbe_set_rar(hw, slot, mac_addr, 2113 NULL, NULL); 2114 } 2115 } 2116 } 2117 } 2118 2119 /* 2120 * ixgbe_unicst_set - Set the unicast address to the specified slot. 2121 */ 2122 int 2123 ixgbe_unicst_set(ixgbe_t *ixgbe, const uint8_t *mac_addr, 2124 int slot) 2125 { 2126 struct ixgbe_hw *hw = &ixgbe->hw; 2127 2128 ASSERT(mutex_owned(&ixgbe->gen_lock)); 2129 2130 /* 2131 * Save the unicast address in the software data structure 2132 */ 2133 bcopy(mac_addr, ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL); 2134 2135 /* 2136 * Set the unicast address to the RAR register 2137 */ 2138 (void) ixgbe_set_rar(hw, slot, (uint8_t *)mac_addr, NULL, IXGBE_RAH_AV); 2139 2140 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 2141 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED); 2142 return (EIO); 2143 } 2144 2145 return (0); 2146 } 2147 2148 /* 2149 * ixgbe_unicst_find - Find the slot for the specified unicast address 2150 */ 2151 int 2152 ixgbe_unicst_find(ixgbe_t *ixgbe, const uint8_t *mac_addr) 2153 { 2154 int slot; 2155 2156 ASSERT(mutex_owned(&ixgbe->gen_lock)); 2157 2158 for (slot = 0; slot < ixgbe->unicst_total; slot++) { 2159 if (bcmp(ixgbe->unicst_addr[slot].mac.addr, 2160 mac_addr, ETHERADDRL) == 0) 2161 return (slot); 2162 } 2163 2164 return (-1); 2165 } 2166 2167 /* 2168 * ixgbe_multicst_add - Add a multicst address. 2169 */ 2170 int 2171 ixgbe_multicst_add(ixgbe_t *ixgbe, const uint8_t *multiaddr) 2172 { 2173 ASSERT(mutex_owned(&ixgbe->gen_lock)); 2174 2175 if ((multiaddr[0] & 01) == 0) { 2176 return (EINVAL); 2177 } 2178 2179 if (ixgbe->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2180 return (ENOENT); 2181 } 2182 2183 bcopy(multiaddr, 2184 &ixgbe->mcast_table[ixgbe->mcast_count], ETHERADDRL); 2185 ixgbe->mcast_count++; 2186 2187 /* 2188 * Update the multicast table in the hardware 2189 */ 2190 ixgbe_setup_multicst(ixgbe); 2191 2192 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 2193 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED); 2194 return (EIO); 2195 } 2196 2197 return (0); 2198 } 2199 2200 /* 2201 * ixgbe_multicst_remove - Remove a multicst address. 2202 */ 2203 int 2204 ixgbe_multicst_remove(ixgbe_t *ixgbe, const uint8_t *multiaddr) 2205 { 2206 int i; 2207 2208 ASSERT(mutex_owned(&ixgbe->gen_lock)); 2209 2210 for (i = 0; i < ixgbe->mcast_count; i++) { 2211 if (bcmp(multiaddr, &ixgbe->mcast_table[i], 2212 ETHERADDRL) == 0) { 2213 for (i++; i < ixgbe->mcast_count; i++) { 2214 ixgbe->mcast_table[i - 1] = 2215 ixgbe->mcast_table[i]; 2216 } 2217 ixgbe->mcast_count--; 2218 break; 2219 } 2220 } 2221 2222 /* 2223 * Update the multicast table in the hardware 2224 */ 2225 ixgbe_setup_multicst(ixgbe); 2226 2227 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 2228 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED); 2229 return (EIO); 2230 } 2231 2232 return (0); 2233 } 2234 2235 /* 2236 * ixgbe_setup_multicast - Setup multicast data structures. 2237 * 2238 * This routine initializes all of the multicast related structures 2239 * and save them in the hardware registers. 2240 */ 2241 static void 2242 ixgbe_setup_multicst(ixgbe_t *ixgbe) 2243 { 2244 uint8_t *mc_addr_list; 2245 uint32_t mc_addr_count; 2246 struct ixgbe_hw *hw = &ixgbe->hw; 2247 2248 ASSERT(mutex_owned(&ixgbe->gen_lock)); 2249 2250 ASSERT(ixgbe->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2251 2252 mc_addr_list = (uint8_t *)ixgbe->mcast_table; 2253 mc_addr_count = ixgbe->mcast_count; 2254 2255 /* 2256 * Update the multicast addresses to the MTA registers 2257 */ 2258 (void) ixgbe_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2259 ixgbe_mc_table_itr); 2260 } 2261 2262 /* 2263 * ixgbe_get_conf - Get driver configurations set in driver.conf. 2264 * 2265 * This routine gets user-configured values out of the configuration 2266 * file ixgbe.conf. 2267 * 2268 * For each configurable value, there is a minimum, a maximum, and a 2269 * default. 2270 * If user does not configure a value, use the default. 2271 * If user configures below the minimum, use the minumum. 2272 * If user configures above the maximum, use the maxumum. 2273 */ 2274 static void 2275 ixgbe_get_conf(ixgbe_t *ixgbe) 2276 { 2277 struct ixgbe_hw *hw = &ixgbe->hw; 2278 uint32_t flow_control; 2279 2280 /* 2281 * ixgbe driver supports the following user configurations: 2282 * 2283 * Jumbo frame configuration: 2284 * default_mtu 2285 * 2286 * Ethernet flow control configuration: 2287 * flow_control 2288 * 2289 * Multiple rings configurations: 2290 * tx_queue_number 2291 * tx_ring_size 2292 * rx_queue_number 2293 * rx_ring_size 2294 * 2295 * Call ixgbe_get_prop() to get the value for a specific 2296 * configuration parameter. 2297 */ 2298 2299 /* 2300 * Jumbo frame configuration - max_frame_size controls host buffer 2301 * allocation, so includes MTU, ethernet header, vlan tag and 2302 * frame check sequence. 2303 */ 2304 ixgbe->default_mtu = ixgbe_get_prop(ixgbe, PROP_DEFAULT_MTU, 2305 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2306 2307 ixgbe->max_frame_size = ixgbe->default_mtu + 2308 sizeof (struct ether_vlan_header) + ETHERFCSL; 2309 2310 /* 2311 * Ethernet flow control configuration 2312 */ 2313 flow_control = ixgbe_get_prop(ixgbe, PROP_FLOW_CONTROL, 2314 ixgbe_fc_none, 3, ixgbe_fc_none); 2315 if (flow_control == 3) 2316 flow_control = ixgbe_fc_default; 2317 2318 hw->fc.type = flow_control; 2319 2320 /* 2321 * Multiple rings configurations 2322 */ 2323 ixgbe->num_tx_rings = ixgbe_get_prop(ixgbe, PROP_TX_QUEUE_NUM, 2324 ixgbe->capab->min_tx_que_num, 2325 ixgbe->capab->max_tx_que_num, 2326 ixgbe->capab->def_tx_que_num); 2327 ixgbe->tx_ring_size = ixgbe_get_prop(ixgbe, PROP_TX_RING_SIZE, 2328 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2329 2330 ixgbe->num_rx_rings = ixgbe_get_prop(ixgbe, PROP_RX_QUEUE_NUM, 2331 ixgbe->capab->min_rx_que_num, 2332 ixgbe->capab->max_rx_que_num, 2333 ixgbe->capab->def_rx_que_num); 2334 ixgbe->rx_ring_size = ixgbe_get_prop(ixgbe, PROP_RX_RING_SIZE, 2335 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2336 2337 /* 2338 * Multiple groups configuration 2339 */ 2340 ixgbe->num_rx_groups = ixgbe_get_prop(ixgbe, PROP_RX_GROUP_NUM, 2341 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2342 2343 ixgbe->mr_enable = ixgbe_get_prop(ixgbe, PROP_MR_ENABLE, 2344 0, 1, DEFAULT_MR_ENABLE); 2345 2346 if (ixgbe->mr_enable == B_FALSE) { 2347 ixgbe->num_tx_rings = 1; 2348 ixgbe->num_rx_rings = 1; 2349 ixgbe->num_rx_groups = 1; 2350 } 2351 2352 /* 2353 * Tunable used to force an interrupt type. The only use is 2354 * for testing of the lesser interrupt types. 2355 * 0 = don't force interrupt type 2356 * 1 = force interrupt type MSI-X 2357 * 2 = force interrupt type MSI 2358 * 3 = force interrupt type Legacy 2359 */ 2360 ixgbe->intr_force = ixgbe_get_prop(ixgbe, PROP_INTR_FORCE, 2361 IXGBE_INTR_NONE, IXGBE_INTR_LEGACY, IXGBE_INTR_NONE); 2362 2363 ixgbe->tx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_TX_HCKSUM_ENABLE, 2364 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 2365 ixgbe->rx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_RX_HCKSUM_ENABLE, 2366 0, 1, DEFAULT_RX_HCKSUM_ENABLE); 2367 ixgbe->lso_enable = ixgbe_get_prop(ixgbe, PROP_LSO_ENABLE, 2368 0, 1, DEFAULT_LSO_ENABLE); 2369 ixgbe->tx_head_wb_enable = ixgbe_get_prop(ixgbe, PROP_TX_HEAD_WB_ENABLE, 2370 0, 1, DEFAULT_TX_HEAD_WB_ENABLE); 2371 2372 /* 2373 * ixgbe LSO needs the tx h/w checksum support. 2374 * LSO will be disabled if tx h/w checksum is not 2375 * enabled. 2376 */ 2377 if (ixgbe->tx_hcksum_enable == B_FALSE) { 2378 ixgbe->lso_enable = B_FALSE; 2379 } 2380 2381 ixgbe->tx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_TX_COPY_THRESHOLD, 2382 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2383 DEFAULT_TX_COPY_THRESHOLD); 2384 ixgbe->tx_recycle_thresh = ixgbe_get_prop(ixgbe, 2385 PROP_TX_RECYCLE_THRESHOLD, MIN_TX_RECYCLE_THRESHOLD, 2386 MAX_TX_RECYCLE_THRESHOLD, DEFAULT_TX_RECYCLE_THRESHOLD); 2387 ixgbe->tx_overload_thresh = ixgbe_get_prop(ixgbe, 2388 PROP_TX_OVERLOAD_THRESHOLD, MIN_TX_OVERLOAD_THRESHOLD, 2389 MAX_TX_OVERLOAD_THRESHOLD, DEFAULT_TX_OVERLOAD_THRESHOLD); 2390 ixgbe->tx_resched_thresh = ixgbe_get_prop(ixgbe, 2391 PROP_TX_RESCHED_THRESHOLD, MIN_TX_RESCHED_THRESHOLD, 2392 MAX_TX_RESCHED_THRESHOLD, DEFAULT_TX_RESCHED_THRESHOLD); 2393 2394 ixgbe->rx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_RX_COPY_THRESHOLD, 2395 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2396 DEFAULT_RX_COPY_THRESHOLD); 2397 ixgbe->rx_limit_per_intr = ixgbe_get_prop(ixgbe, PROP_RX_LIMIT_PER_INTR, 2398 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2399 DEFAULT_RX_LIMIT_PER_INTR); 2400 2401 ixgbe->intr_throttling[0] = ixgbe_get_prop(ixgbe, PROP_INTR_THROTTLING, 2402 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2403 DEFAULT_INTR_THROTTLING); 2404 } 2405 2406 /* 2407 * ixgbe_get_prop - Get a property value out of the configuration file 2408 * ixgbe.conf. 2409 * 2410 * Caller provides the name of the property, a default value, a minimum 2411 * value, and a maximum value. 2412 * 2413 * Return configured value of the property, with default, minimum and 2414 * maximum properly applied. 2415 */ 2416 static int 2417 ixgbe_get_prop(ixgbe_t *ixgbe, 2418 char *propname, /* name of the property */ 2419 int minval, /* minimum acceptable value */ 2420 int maxval, /* maximim acceptable value */ 2421 int defval) /* default value */ 2422 { 2423 int value; 2424 2425 /* 2426 * Call ddi_prop_get_int() to read the conf settings 2427 */ 2428 value = ddi_prop_get_int(DDI_DEV_T_ANY, ixgbe->dip, 2429 DDI_PROP_DONTPASS, propname, defval); 2430 if (value > maxval) 2431 value = maxval; 2432 2433 if (value < minval) 2434 value = minval; 2435 2436 return (value); 2437 } 2438 2439 /* 2440 * ixgbe_driver_setup_link - Using the link properties to setup the link. 2441 */ 2442 int 2443 ixgbe_driver_setup_link(ixgbe_t *ixgbe, boolean_t setup_hw) 2444 { 2445 struct ixgbe_mac_info *mac; 2446 struct ixgbe_phy_info *phy; 2447 boolean_t invalid; 2448 2449 mac = &ixgbe->hw.mac; 2450 phy = &ixgbe->hw.phy; 2451 invalid = B_FALSE; 2452 2453 if (ixgbe->param_adv_autoneg_cap == 1) { 2454 mac->autoneg = B_TRUE; 2455 phy->autoneg_advertised = 0; 2456 2457 /* 2458 * No half duplex support with 10Gb parts 2459 */ 2460 if (ixgbe->param_adv_10000fdx_cap == 1) 2461 phy->autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 2462 2463 if (ixgbe->param_adv_1000fdx_cap == 1) 2464 phy->autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 2465 2466 if (ixgbe->param_adv_100fdx_cap == 1) 2467 phy->autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 2468 2469 if (phy->autoneg_advertised == 0) 2470 invalid = B_TRUE; 2471 } else { 2472 ixgbe->hw.mac.autoneg = B_FALSE; 2473 } 2474 2475 if (invalid) { 2476 ixgbe_notice(ixgbe, "Invalid link settings. Setup link to " 2477 "autonegotiation with full link capabilities."); 2478 ixgbe->hw.mac.autoneg = B_TRUE; 2479 } 2480 2481 if (setup_hw) { 2482 if (ixgbe_setup_link(&ixgbe->hw) != IXGBE_SUCCESS) 2483 return (IXGBE_FAILURE); 2484 } 2485 2486 return (IXGBE_SUCCESS); 2487 } 2488 2489 /* 2490 * ixgbe_driver_link_check - Link status processing done in taskq. 2491 */ 2492 static void 2493 ixgbe_driver_link_check(void *arg) 2494 { 2495 ixgbe_t *ixgbe = (ixgbe_t *)arg; 2496 struct ixgbe_hw *hw = &ixgbe->hw; 2497 ixgbe_link_speed speed = IXGBE_LINK_SPEED_UNKNOWN; 2498 boolean_t link_up = B_FALSE; 2499 boolean_t link_changed = B_FALSE; 2500 2501 mutex_enter(&ixgbe->gen_lock); 2502 2503 /* check for link, wait the full time */ 2504 (void) ixgbe_check_link(hw, &speed, &link_up, true); 2505 if (link_up) { 2506 /* 2507 * The Link is up, check whether it was marked as down earlier 2508 */ 2509 if (ixgbe->link_state != LINK_STATE_UP) { 2510 switch (speed) { 2511 case IXGBE_LINK_SPEED_10GB_FULL: 2512 ixgbe->link_speed = SPEED_10GB; 2513 break; 2514 case IXGBE_LINK_SPEED_1GB_FULL: 2515 ixgbe->link_speed = SPEED_1GB; 2516 break; 2517 case IXGBE_LINK_SPEED_100_FULL: 2518 ixgbe->link_speed = SPEED_100; 2519 } 2520 ixgbe->link_duplex = LINK_DUPLEX_FULL; 2521 ixgbe->link_state = LINK_STATE_UP; 2522 ixgbe->link_down_timeout = 0; 2523 link_changed = B_TRUE; 2524 } 2525 } else { 2526 if (ixgbe->link_state != LINK_STATE_DOWN) { 2527 ixgbe->link_speed = 0; 2528 ixgbe->link_duplex = 0; 2529 ixgbe->link_state = LINK_STATE_DOWN; 2530 link_changed = B_TRUE; 2531 } 2532 2533 if (ixgbe->ixgbe_state & IXGBE_STARTED) { 2534 if (ixgbe->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2535 ixgbe->link_down_timeout++; 2536 } else if (ixgbe->link_down_timeout == 2537 MAX_LINK_DOWN_TIMEOUT) { 2538 ixgbe_tx_clean(ixgbe); 2539 ixgbe->link_down_timeout++; 2540 } 2541 } 2542 } 2543 2544 /* 2545 * this is only reached after a link-status-change interrupt 2546 * so always get new phy state 2547 */ 2548 ixgbe_get_hw_state(ixgbe); 2549 2550 /* re-enable the interrupt, which was automasked */ 2551 ixgbe->eims |= IXGBE_EICR_LSC; 2552 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims); 2553 2554 mutex_exit(&ixgbe->gen_lock); 2555 2556 /* outside the gen_lock */ 2557 if (link_changed) { 2558 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state); 2559 } 2560 } 2561 2562 /* 2563 * ixgbe_local_timer - Driver watchdog function. 2564 * 2565 * This function will handle the transmit stall check, link status check and 2566 * other routines. 2567 */ 2568 static void 2569 ixgbe_local_timer(void *arg) 2570 { 2571 ixgbe_t *ixgbe = (ixgbe_t *)arg; 2572 2573 if (ixgbe_stall_check(ixgbe)) { 2574 ixgbe->reset_count++; 2575 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS) 2576 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED); 2577 } 2578 2579 ixgbe_restart_watchdog_timer(ixgbe); 2580 } 2581 2582 /* 2583 * ixgbe_stall_check - Check for transmit stall. 2584 * 2585 * This function checks if the adapter is stalled (in transmit). 2586 * 2587 * It is called each time the watchdog timeout is invoked. 2588 * If the transmit descriptor reclaim continuously fails, 2589 * the watchdog value will increment by 1. If the watchdog 2590 * value exceeds the threshold, the ixgbe is assumed to 2591 * have stalled and need to be reset. 2592 */ 2593 static boolean_t 2594 ixgbe_stall_check(ixgbe_t *ixgbe) 2595 { 2596 ixgbe_tx_ring_t *tx_ring; 2597 boolean_t result; 2598 int i; 2599 2600 if (ixgbe->link_state != LINK_STATE_UP) 2601 return (B_FALSE); 2602 2603 /* 2604 * If any tx ring is stalled, we'll reset the chipset 2605 */ 2606 result = B_FALSE; 2607 for (i = 0; i < ixgbe->num_tx_rings; i++) { 2608 tx_ring = &ixgbe->tx_rings[i]; 2609 tx_ring->tx_recycle(tx_ring); 2610 2611 if (tx_ring->recycle_fail > 0) 2612 tx_ring->stall_watchdog++; 2613 else 2614 tx_ring->stall_watchdog = 0; 2615 2616 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2617 result = B_TRUE; 2618 break; 2619 } 2620 } 2621 2622 if (result) { 2623 tx_ring->stall_watchdog = 0; 2624 tx_ring->recycle_fail = 0; 2625 } 2626 2627 return (result); 2628 } 2629 2630 2631 /* 2632 * is_valid_mac_addr - Check if the mac address is valid. 2633 */ 2634 static boolean_t 2635 is_valid_mac_addr(uint8_t *mac_addr) 2636 { 2637 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2638 const uint8_t addr_test2[6] = 2639 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2640 2641 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2642 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2643 return (B_FALSE); 2644 2645 return (B_TRUE); 2646 } 2647 2648 static boolean_t 2649 ixgbe_find_mac_address(ixgbe_t *ixgbe) 2650 { 2651 #ifdef __sparc 2652 struct ixgbe_hw *hw = &ixgbe->hw; 2653 uchar_t *bytes; 2654 struct ether_addr sysaddr; 2655 uint_t nelts; 2656 int err; 2657 boolean_t found = B_FALSE; 2658 2659 /* 2660 * The "vendor's factory-set address" may already have 2661 * been extracted from the chip, but if the property 2662 * "local-mac-address" is set we use that instead. 2663 * 2664 * We check whether it looks like an array of 6 2665 * bytes (which it should, if OBP set it). If we can't 2666 * make sense of it this way, we'll ignore it. 2667 */ 2668 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip, 2669 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2670 if (err == DDI_PROP_SUCCESS) { 2671 if (nelts == ETHERADDRL) { 2672 while (nelts--) 2673 hw->mac.addr[nelts] = bytes[nelts]; 2674 found = B_TRUE; 2675 } 2676 ddi_prop_free(bytes); 2677 } 2678 2679 /* 2680 * Look up the OBP property "local-mac-address?". If the user has set 2681 * 'local-mac-address? = false', use "the system address" instead. 2682 */ 2683 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip, 0, 2684 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2685 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2686 if (localetheraddr(NULL, &sysaddr) != 0) { 2687 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2688 found = B_TRUE; 2689 } 2690 } 2691 ddi_prop_free(bytes); 2692 } 2693 2694 /* 2695 * Finally(!), if there's a valid "mac-address" property (created 2696 * if we netbooted from this interface), we must use this instead 2697 * of any of the above to ensure that the NFS/install server doesn't 2698 * get confused by the address changing as Solaris takes over! 2699 */ 2700 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip, 2701 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2702 if (err == DDI_PROP_SUCCESS) { 2703 if (nelts == ETHERADDRL) { 2704 while (nelts--) 2705 hw->mac.addr[nelts] = bytes[nelts]; 2706 found = B_TRUE; 2707 } 2708 ddi_prop_free(bytes); 2709 } 2710 2711 if (found) { 2712 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2713 return (B_TRUE); 2714 } 2715 #else 2716 _NOTE(ARGUNUSED(ixgbe)); 2717 #endif 2718 2719 return (B_TRUE); 2720 } 2721 2722 #pragma inline(ixgbe_arm_watchdog_timer) 2723 static void 2724 ixgbe_arm_watchdog_timer(ixgbe_t *ixgbe) 2725 { 2726 /* 2727 * Fire a watchdog timer 2728 */ 2729 ixgbe->watchdog_tid = 2730 timeout(ixgbe_local_timer, 2731 (void *)ixgbe, 1 * drv_usectohz(1000000)); 2732 2733 } 2734 2735 /* 2736 * ixgbe_enable_watchdog_timer - Enable and start the driver watchdog timer. 2737 */ 2738 void 2739 ixgbe_enable_watchdog_timer(ixgbe_t *ixgbe) 2740 { 2741 mutex_enter(&ixgbe->watchdog_lock); 2742 2743 if (!ixgbe->watchdog_enable) { 2744 ixgbe->watchdog_enable = B_TRUE; 2745 ixgbe->watchdog_start = B_TRUE; 2746 ixgbe_arm_watchdog_timer(ixgbe); 2747 } 2748 2749 mutex_exit(&ixgbe->watchdog_lock); 2750 } 2751 2752 /* 2753 * ixgbe_disable_watchdog_timer - Disable and stop the driver watchdog timer. 2754 */ 2755 void 2756 ixgbe_disable_watchdog_timer(ixgbe_t *ixgbe) 2757 { 2758 timeout_id_t tid; 2759 2760 mutex_enter(&ixgbe->watchdog_lock); 2761 2762 ixgbe->watchdog_enable = B_FALSE; 2763 ixgbe->watchdog_start = B_FALSE; 2764 tid = ixgbe->watchdog_tid; 2765 ixgbe->watchdog_tid = 0; 2766 2767 mutex_exit(&ixgbe->watchdog_lock); 2768 2769 if (tid != 0) 2770 (void) untimeout(tid); 2771 } 2772 2773 /* 2774 * ixgbe_start_watchdog_timer - Start the driver watchdog timer. 2775 */ 2776 void 2777 ixgbe_start_watchdog_timer(ixgbe_t *ixgbe) 2778 { 2779 mutex_enter(&ixgbe->watchdog_lock); 2780 2781 if (ixgbe->watchdog_enable) { 2782 if (!ixgbe->watchdog_start) { 2783 ixgbe->watchdog_start = B_TRUE; 2784 ixgbe_arm_watchdog_timer(ixgbe); 2785 } 2786 } 2787 2788 mutex_exit(&ixgbe->watchdog_lock); 2789 } 2790 2791 /* 2792 * ixgbe_restart_watchdog_timer - Restart the driver watchdog timer. 2793 */ 2794 static void 2795 ixgbe_restart_watchdog_timer(ixgbe_t *ixgbe) 2796 { 2797 mutex_enter(&ixgbe->watchdog_lock); 2798 2799 if (ixgbe->watchdog_start) 2800 ixgbe_arm_watchdog_timer(ixgbe); 2801 2802 mutex_exit(&ixgbe->watchdog_lock); 2803 } 2804 2805 /* 2806 * ixgbe_stop_watchdog_timer - Stop the driver watchdog timer. 2807 */ 2808 void 2809 ixgbe_stop_watchdog_timer(ixgbe_t *ixgbe) 2810 { 2811 timeout_id_t tid; 2812 2813 mutex_enter(&ixgbe->watchdog_lock); 2814 2815 ixgbe->watchdog_start = B_FALSE; 2816 tid = ixgbe->watchdog_tid; 2817 ixgbe->watchdog_tid = 0; 2818 2819 mutex_exit(&ixgbe->watchdog_lock); 2820 2821 if (tid != 0) 2822 (void) untimeout(tid); 2823 } 2824 2825 /* 2826 * ixgbe_disable_adapter_interrupts - Disable all adapter interrupts. 2827 */ 2828 static void 2829 ixgbe_disable_adapter_interrupts(ixgbe_t *ixgbe) 2830 { 2831 struct ixgbe_hw *hw = &ixgbe->hw; 2832 2833 /* 2834 * mask all interrupts off 2835 */ 2836 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xffffffff); 2837 2838 /* 2839 * for MSI-X, also disable autoclear 2840 */ 2841 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) { 2842 IXGBE_WRITE_REG(hw, IXGBE_EIAC, 0x0); 2843 } 2844 2845 IXGBE_WRITE_FLUSH(hw); 2846 } 2847 2848 /* 2849 * ixgbe_enable_adapter_interrupts - Enable all hardware interrupts. 2850 */ 2851 static void 2852 ixgbe_enable_adapter_interrupts(ixgbe_t *ixgbe) 2853 { 2854 struct ixgbe_hw *hw = &ixgbe->hw; 2855 uint32_t eiac, eiam; 2856 uint32_t gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2857 2858 /* interrupt types to enable */ 2859 ixgbe->eims = IXGBE_EIMS_ENABLE_MASK; /* shared code default */ 2860 ixgbe->eims &= ~IXGBE_EIMS_TCP_TIMER; /* minus tcp timer */ 2861 ixgbe->eims |= ixgbe->capab->other_intr; /* "other" interrupt types */ 2862 2863 /* enable automask on "other" causes that this adapter can generate */ 2864 eiam = ixgbe->capab->other_intr; 2865 2866 /* 2867 * msi-x mode 2868 */ 2869 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) { 2870 /* enable autoclear but not on bits 29:20 */ 2871 eiac = (ixgbe->eims & ~IXGBE_OTHER_INTR); 2872 2873 /* general purpose interrupt enable */ 2874 gpie |= (IXGBE_GPIE_MSIX_MODE 2875 | IXGBE_GPIE_PBA_SUPPORT 2876 | IXGBE_GPIE_OCD 2877 | IXGBE_GPIE_EIAME); 2878 /* 2879 * non-msi-x mode 2880 */ 2881 } else { 2882 2883 /* disable autoclear, leave gpie at default */ 2884 eiac = 0; 2885 2886 /* general purpose interrupt enable */ 2887 gpie |= IXGBE_GPIE_EIAME; 2888 } 2889 2890 /* write to interrupt control registers */ 2891 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims); 2892 IXGBE_WRITE_REG(hw, IXGBE_EIAC, eiac); 2893 IXGBE_WRITE_REG(hw, IXGBE_EIAM, eiam); 2894 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2895 IXGBE_WRITE_FLUSH(hw); 2896 } 2897 2898 /* 2899 * ixgbe_loopback_ioctl - Loopback support. 2900 */ 2901 enum ioc_reply 2902 ixgbe_loopback_ioctl(ixgbe_t *ixgbe, struct iocblk *iocp, mblk_t *mp) 2903 { 2904 lb_info_sz_t *lbsp; 2905 lb_property_t *lbpp; 2906 uint32_t *lbmp; 2907 uint32_t size; 2908 uint32_t value; 2909 2910 if (mp->b_cont == NULL) 2911 return (IOC_INVAL); 2912 2913 switch (iocp->ioc_cmd) { 2914 default: 2915 return (IOC_INVAL); 2916 2917 case LB_GET_INFO_SIZE: 2918 size = sizeof (lb_info_sz_t); 2919 if (iocp->ioc_count != size) 2920 return (IOC_INVAL); 2921 2922 value = sizeof (lb_normal); 2923 value += sizeof (lb_mac); 2924 2925 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 2926 *lbsp = value; 2927 break; 2928 2929 case LB_GET_INFO: 2930 value = sizeof (lb_normal); 2931 value += sizeof (lb_mac); 2932 2933 size = value; 2934 if (iocp->ioc_count != size) 2935 return (IOC_INVAL); 2936 2937 value = 0; 2938 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 2939 2940 lbpp[value++] = lb_normal; 2941 lbpp[value++] = lb_mac; 2942 break; 2943 2944 case LB_GET_MODE: 2945 size = sizeof (uint32_t); 2946 if (iocp->ioc_count != size) 2947 return (IOC_INVAL); 2948 2949 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2950 *lbmp = ixgbe->loopback_mode; 2951 break; 2952 2953 case LB_SET_MODE: 2954 size = 0; 2955 if (iocp->ioc_count != sizeof (uint32_t)) 2956 return (IOC_INVAL); 2957 2958 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2959 if (!ixgbe_set_loopback_mode(ixgbe, *lbmp)) 2960 return (IOC_INVAL); 2961 break; 2962 } 2963 2964 iocp->ioc_count = size; 2965 iocp->ioc_error = 0; 2966 2967 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) { 2968 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED); 2969 return (IOC_INVAL); 2970 } 2971 2972 return (IOC_REPLY); 2973 } 2974 2975 /* 2976 * ixgbe_set_loopback_mode - Setup loopback based on the loopback mode. 2977 */ 2978 static boolean_t 2979 ixgbe_set_loopback_mode(ixgbe_t *ixgbe, uint32_t mode) 2980 { 2981 struct ixgbe_hw *hw; 2982 2983 if (mode == ixgbe->loopback_mode) 2984 return (B_TRUE); 2985 2986 hw = &ixgbe->hw; 2987 2988 ixgbe->loopback_mode = mode; 2989 2990 if (mode == IXGBE_LB_NONE) { 2991 /* 2992 * Reset the chip 2993 */ 2994 hw->phy.autoneg_wait_to_complete = B_TRUE; 2995 (void) ixgbe_reset(ixgbe); 2996 hw->phy.autoneg_wait_to_complete = B_FALSE; 2997 return (B_TRUE); 2998 } 2999 3000 mutex_enter(&ixgbe->gen_lock); 3001 3002 switch (mode) { 3003 default: 3004 mutex_exit(&ixgbe->gen_lock); 3005 return (B_FALSE); 3006 3007 case IXGBE_LB_INTERNAL_MAC: 3008 ixgbe_set_internal_mac_loopback(ixgbe); 3009 break; 3010 } 3011 3012 mutex_exit(&ixgbe->gen_lock); 3013 3014 return (B_TRUE); 3015 } 3016 3017 /* 3018 * ixgbe_set_internal_mac_loopback - Set the internal MAC loopback mode. 3019 */ 3020 static void 3021 ixgbe_set_internal_mac_loopback(ixgbe_t *ixgbe) 3022 { 3023 struct ixgbe_hw *hw; 3024 uint32_t reg; 3025 uint8_t atlas; 3026 3027 hw = &ixgbe->hw; 3028 3029 /* 3030 * Setup MAC loopback 3031 */ 3032 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_HLREG0); 3033 reg |= IXGBE_HLREG0_LPBK; 3034 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_HLREG0, reg); 3035 3036 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC); 3037 reg &= ~IXGBE_AUTOC_LMS_MASK; 3038 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg); 3039 3040 /* 3041 * Disable Atlas Tx lanes to keep packets in loopback and not on wire 3042 */ 3043 if (hw->mac.type == ixgbe_mac_82598EB) { 3044 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK, 3045 &atlas); 3046 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 3047 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK, 3048 atlas); 3049 3050 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G, 3051 &atlas); 3052 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 3053 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G, 3054 atlas); 3055 3056 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G, 3057 &atlas); 3058 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 3059 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G, 3060 atlas); 3061 3062 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN, 3063 &atlas); 3064 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 3065 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN, 3066 atlas); 3067 } 3068 } 3069 3070 #pragma inline(ixgbe_intr_rx_work) 3071 /* 3072 * ixgbe_intr_rx_work - RX processing of ISR. 3073 */ 3074 static void 3075 ixgbe_intr_rx_work(ixgbe_rx_ring_t *rx_ring) 3076 { 3077 mblk_t *mp; 3078 3079 mutex_enter(&rx_ring->rx_lock); 3080 3081 mp = ixgbe_ring_rx(rx_ring, IXGBE_POLL_NULL); 3082 mutex_exit(&rx_ring->rx_lock); 3083 3084 if (mp != NULL) 3085 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp, 3086 rx_ring->ring_gen_num); 3087 } 3088 3089 #pragma inline(ixgbe_intr_tx_work) 3090 /* 3091 * ixgbe_intr_tx_work - TX processing of ISR. 3092 */ 3093 static void 3094 ixgbe_intr_tx_work(ixgbe_tx_ring_t *tx_ring) 3095 { 3096 /* 3097 * Recycle the tx descriptors 3098 */ 3099 tx_ring->tx_recycle(tx_ring); 3100 3101 /* 3102 * Schedule the re-transmit 3103 */ 3104 if (tx_ring->reschedule && 3105 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3106 tx_ring->reschedule = B_FALSE; 3107 mac_tx_ring_update(tx_ring->ixgbe->mac_hdl, 3108 tx_ring->ring_handle); 3109 IXGBE_DEBUG_STAT(tx_ring->stat_reschedule); 3110 } 3111 } 3112 3113 #pragma inline(ixgbe_intr_other_work) 3114 /* 3115 * ixgbe_intr_other_work - Process interrupt types other than tx/rx 3116 */ 3117 static void 3118 ixgbe_intr_other_work(ixgbe_t *ixgbe, uint32_t eicr) 3119 { 3120 /* 3121 * dispatch taskq to handle link status change 3122 */ 3123 if (eicr & IXGBE_EICR_LSC) { 3124 if ((ddi_taskq_dispatch(ixgbe->lsc_taskq, 3125 ixgbe_driver_link_check, (void *)ixgbe, DDI_NOSLEEP)) 3126 != DDI_SUCCESS) { 3127 ixgbe_log(ixgbe, "Fail to dispatch taskq"); 3128 } 3129 } 3130 3131 /* 3132 * check for fan failure on adapters with fans 3133 */ 3134 if ((ixgbe->capab->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 3135 (eicr & IXGBE_EICR_GPI_SDP1)) { 3136 3137 ixgbe_log(ixgbe, 3138 "Fan has stopped, replace the adapter\n"); 3139 3140 /* re-enable the interrupt, which was automasked */ 3141 ixgbe->eims |= IXGBE_EICR_GPI_SDP1; 3142 } 3143 } 3144 3145 /* 3146 * ixgbe_intr_legacy - Interrupt handler for legacy interrupts. 3147 */ 3148 static uint_t 3149 ixgbe_intr_legacy(void *arg1, void *arg2) 3150 { 3151 ixgbe_t *ixgbe = (ixgbe_t *)arg1; 3152 struct ixgbe_hw *hw = &ixgbe->hw; 3153 ixgbe_tx_ring_t *tx_ring; 3154 ixgbe_rx_ring_t *rx_ring; 3155 uint32_t eicr; 3156 mblk_t *mp; 3157 boolean_t tx_reschedule; 3158 uint_t result; 3159 3160 _NOTE(ARGUNUSED(arg2)); 3161 3162 mutex_enter(&ixgbe->gen_lock); 3163 3164 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) { 3165 mutex_exit(&ixgbe->gen_lock); 3166 return (DDI_INTR_UNCLAIMED); 3167 } 3168 3169 mp = NULL; 3170 tx_reschedule = B_FALSE; 3171 3172 /* 3173 * Any bit set in eicr: claim this interrupt 3174 */ 3175 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3176 if (eicr) { 3177 /* 3178 * For legacy interrupt, we have only one interrupt, 3179 * so we have only one rx ring and one tx ring enabled. 3180 */ 3181 ASSERT(ixgbe->num_rx_rings == 1); 3182 ASSERT(ixgbe->num_tx_rings == 1); 3183 3184 /* 3185 * For legacy interrupt, rx rings[0] will use RTxQ[0]. 3186 */ 3187 if (eicr & 0x1) { 3188 /* 3189 * Clean the rx descriptors 3190 */ 3191 rx_ring = &ixgbe->rx_rings[0]; 3192 mp = ixgbe_ring_rx(rx_ring, IXGBE_POLL_NULL); 3193 } 3194 3195 /* 3196 * For legacy interrupt, tx rings[0] will use RTxQ[1]. 3197 */ 3198 if (eicr & 0x2) { 3199 /* 3200 * Recycle the tx descriptors 3201 */ 3202 tx_ring = &ixgbe->tx_rings[0]; 3203 tx_ring->tx_recycle(tx_ring); 3204 3205 /* 3206 * Schedule the re-transmit 3207 */ 3208 tx_reschedule = (tx_ring->reschedule && 3209 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3210 } 3211 3212 /* any interrupt type other than tx/rx */ 3213 if (eicr & ixgbe->capab->other_intr) { 3214 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR); 3215 ixgbe_intr_other_work(ixgbe, eicr); 3216 } 3217 3218 mutex_exit(&ixgbe->gen_lock); 3219 3220 result = DDI_INTR_CLAIMED; 3221 } else { 3222 mutex_exit(&ixgbe->gen_lock); 3223 3224 /* 3225 * No interrupt cause bits set: don't claim this interrupt. 3226 */ 3227 result = DDI_INTR_UNCLAIMED; 3228 } 3229 3230 /* re-enable the interrupts which were automasked */ 3231 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims); 3232 3233 /* 3234 * Do the following work outside of the gen_lock 3235 */ 3236 if (mp != NULL) 3237 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp, 3238 rx_ring->ring_gen_num); 3239 3240 if (tx_reschedule) { 3241 tx_ring->reschedule = B_FALSE; 3242 mac_tx_ring_update(ixgbe->mac_hdl, tx_ring->ring_handle); 3243 IXGBE_DEBUG_STAT(tx_ring->stat_reschedule); 3244 } 3245 3246 return (result); 3247 } 3248 3249 /* 3250 * ixgbe_intr_msi - Interrupt handler for MSI. 3251 */ 3252 static uint_t 3253 ixgbe_intr_msi(void *arg1, void *arg2) 3254 { 3255 ixgbe_t *ixgbe = (ixgbe_t *)arg1; 3256 struct ixgbe_hw *hw = &ixgbe->hw; 3257 uint32_t eicr; 3258 3259 _NOTE(ARGUNUSED(arg2)); 3260 3261 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3262 3263 /* 3264 * For MSI interrupt, we have only one vector, 3265 * so we have only one rx ring and one tx ring enabled. 3266 */ 3267 ASSERT(ixgbe->num_rx_rings == 1); 3268 ASSERT(ixgbe->num_tx_rings == 1); 3269 3270 /* 3271 * For MSI interrupt, rx rings[0] will use RTxQ[0]. 3272 */ 3273 if (eicr & 0x1) { 3274 ixgbe_intr_rx_work(&ixgbe->rx_rings[0]); 3275 } 3276 3277 /* 3278 * For MSI interrupt, tx rings[0] will use RTxQ[1]. 3279 */ 3280 if (eicr & 0x2) { 3281 ixgbe_intr_tx_work(&ixgbe->tx_rings[0]); 3282 } 3283 3284 /* any interrupt type other than tx/rx */ 3285 if (eicr & ixgbe->capab->other_intr) { 3286 mutex_enter(&ixgbe->gen_lock); 3287 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR); 3288 ixgbe_intr_other_work(ixgbe, eicr); 3289 mutex_exit(&ixgbe->gen_lock); 3290 } 3291 3292 /* re-enable the interrupts which were automasked */ 3293 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims); 3294 3295 return (DDI_INTR_CLAIMED); 3296 } 3297 3298 /* 3299 * ixgbe_intr_rx_tx - Interrupt handler for rx and tx. 3300 */ 3301 static uint_t 3302 ixgbe_intr_rx_tx(void *arg1, void *arg2) 3303 { 3304 ixgbe_ring_vector_t *vect = (ixgbe_ring_vector_t *)arg1; 3305 ixgbe_t *ixgbe = vect->ixgbe; 3306 int r_idx = 0; 3307 3308 _NOTE(ARGUNUSED(arg2)); 3309 3310 /* 3311 * Clean each rx ring that has its bit set in the map 3312 */ 3313 r_idx = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1)); 3314 while (r_idx >= 0) { 3315 ixgbe_intr_rx_work(&ixgbe->rx_rings[r_idx]); 3316 r_idx = bt_getlowbit(vect->rx_map, (r_idx + 1), 3317 (ixgbe->num_rx_rings - 1)); 3318 } 3319 3320 /* 3321 * Clean each tx ring that has its bit set in the map 3322 */ 3323 r_idx = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1)); 3324 while (r_idx >= 0) { 3325 ixgbe_intr_tx_work(&ixgbe->tx_rings[r_idx]); 3326 r_idx = bt_getlowbit(vect->tx_map, (r_idx + 1), 3327 (ixgbe->num_tx_rings - 1)); 3328 } 3329 3330 return (DDI_INTR_CLAIMED); 3331 } 3332 3333 /* 3334 * ixgbe_intr_other - Interrupt handler for other. 3335 * 3336 * Only look for other work if the right bits are set in the 3337 * Interrupt Cause Register. 3338 */ 3339 static uint_t 3340 ixgbe_intr_other(void *arg1, void *arg2) 3341 { 3342 ixgbe_t *ixgbe = (ixgbe_t *)arg1; 3343 struct ixgbe_hw *hw = &ixgbe->hw; 3344 uint32_t eicr; 3345 3346 _NOTE(ARGUNUSED(arg2)); 3347 3348 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3349 3350 /* 3351 * Need check cause bits and only other causes will 3352 * be processed 3353 */ 3354 /* any interrupt type other than tx/rx */ 3355 if (eicr & ixgbe->capab->other_intr) { 3356 mutex_enter(&ixgbe->gen_lock); 3357 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR); 3358 ixgbe_intr_other_work(ixgbe, eicr); 3359 mutex_exit(&ixgbe->gen_lock); 3360 } 3361 3362 /* re-enable the interrupts which were automasked */ 3363 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims); 3364 3365 return (DDI_INTR_CLAIMED); 3366 } 3367 3368 /* 3369 * ixgbe_alloc_intrs - Allocate interrupts for the driver. 3370 * 3371 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3372 * if not successful, try Legacy. 3373 * ixgbe->intr_force can be used to force sequence to start with 3374 * any of the 3 types. 3375 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3376 */ 3377 static int 3378 ixgbe_alloc_intrs(ixgbe_t *ixgbe) 3379 { 3380 dev_info_t *devinfo; 3381 int intr_types; 3382 int rc; 3383 3384 devinfo = ixgbe->dip; 3385 3386 /* 3387 * Get supported interrupt types 3388 */ 3389 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3390 3391 if (rc != DDI_SUCCESS) { 3392 ixgbe_log(ixgbe, 3393 "Get supported interrupt types failed: %d", rc); 3394 return (IXGBE_FAILURE); 3395 } 3396 IXGBE_DEBUGLOG_1(ixgbe, "Supported interrupt types: %x", intr_types); 3397 3398 ixgbe->intr_type = 0; 3399 3400 /* 3401 * Install MSI-X interrupts 3402 */ 3403 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3404 (ixgbe->intr_force <= IXGBE_INTR_MSIX)) { 3405 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSIX); 3406 if (rc == IXGBE_SUCCESS) 3407 return (IXGBE_SUCCESS); 3408 3409 ixgbe_log(ixgbe, 3410 "Allocate MSI-X failed, trying MSI interrupts..."); 3411 } 3412 3413 /* 3414 * MSI-X not used, force rings and groups to 1 3415 */ 3416 ixgbe->num_rx_rings = 1; 3417 ixgbe->num_rx_groups = 1; 3418 ixgbe->num_tx_rings = 1; 3419 ixgbe_log(ixgbe, 3420 "MSI-X not used, force rings and groups number to 1"); 3421 3422 /* 3423 * Install MSI interrupts 3424 */ 3425 if ((intr_types & DDI_INTR_TYPE_MSI) && 3426 (ixgbe->intr_force <= IXGBE_INTR_MSI)) { 3427 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSI); 3428 if (rc == IXGBE_SUCCESS) 3429 return (IXGBE_SUCCESS); 3430 3431 ixgbe_log(ixgbe, 3432 "Allocate MSI failed, trying Legacy interrupts..."); 3433 } 3434 3435 /* 3436 * Install legacy interrupts 3437 */ 3438 if (intr_types & DDI_INTR_TYPE_FIXED) { 3439 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_FIXED); 3440 if (rc == IXGBE_SUCCESS) 3441 return (IXGBE_SUCCESS); 3442 3443 ixgbe_log(ixgbe, 3444 "Allocate Legacy interrupts failed"); 3445 } 3446 3447 /* 3448 * If none of the 3 types succeeded, return failure 3449 */ 3450 return (IXGBE_FAILURE); 3451 } 3452 3453 /* 3454 * ixgbe_alloc_intr_handles - Allocate interrupt handles. 3455 * 3456 * For legacy and MSI, only 1 handle is needed. For MSI-X, 3457 * if fewer than 2 handles are available, return failure. 3458 * Upon success, this maps the vectors to rx and tx rings for 3459 * interrupts. 3460 */ 3461 static int 3462 ixgbe_alloc_intr_handles(ixgbe_t *ixgbe, int intr_type) 3463 { 3464 dev_info_t *devinfo; 3465 int request, count, avail, actual; 3466 int minimum; 3467 int rc; 3468 3469 devinfo = ixgbe->dip; 3470 3471 switch (intr_type) { 3472 case DDI_INTR_TYPE_FIXED: 3473 request = 1; /* Request 1 legacy interrupt handle */ 3474 minimum = 1; 3475 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: legacy"); 3476 break; 3477 3478 case DDI_INTR_TYPE_MSI: 3479 request = 1; /* Request 1 MSI interrupt handle */ 3480 minimum = 1; 3481 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI"); 3482 break; 3483 3484 case DDI_INTR_TYPE_MSIX: 3485 /* 3486 * Best number of vectors for the adapter is 3487 * # rx rings + # tx rings + 1 for other. 3488 */ 3489 request = ixgbe->num_rx_rings + ixgbe->num_tx_rings + 1; 3490 if (request > (ixgbe->capab->max_ring_vect + 1)) 3491 request = ixgbe->capab->max_ring_vect + 1; 3492 minimum = 2; 3493 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI-X"); 3494 break; 3495 3496 default: 3497 ixgbe_log(ixgbe, 3498 "invalid call to ixgbe_alloc_intr_handles(): %d\n", 3499 intr_type); 3500 return (IXGBE_FAILURE); 3501 } 3502 IXGBE_DEBUGLOG_2(ixgbe, "interrupt handles requested: %d minimum: %d", 3503 request, minimum); 3504 3505 /* 3506 * Get number of supported interrupts 3507 */ 3508 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3509 if ((rc != DDI_SUCCESS) || (count < minimum)) { 3510 ixgbe_log(ixgbe, 3511 "Get interrupt number failed. Return: %d, count: %d", 3512 rc, count); 3513 return (IXGBE_FAILURE); 3514 } 3515 IXGBE_DEBUGLOG_1(ixgbe, "interrupts supported: %d", count); 3516 3517 /* 3518 * Get number of available interrupts 3519 */ 3520 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3521 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 3522 ixgbe_log(ixgbe, 3523 "Get interrupt available number failed. " 3524 "Return: %d, available: %d", rc, avail); 3525 return (IXGBE_FAILURE); 3526 } 3527 IXGBE_DEBUGLOG_1(ixgbe, "interrupts available: %d", avail); 3528 3529 if (avail < request) { 3530 ixgbe_log(ixgbe, "Request %d handles, %d available", 3531 request, avail); 3532 request = avail; 3533 } 3534 3535 actual = 0; 3536 ixgbe->intr_cnt = 0; 3537 3538 /* 3539 * Allocate an array of interrupt handles 3540 */ 3541 ixgbe->intr_size = request * sizeof (ddi_intr_handle_t); 3542 ixgbe->htable = kmem_alloc(ixgbe->intr_size, KM_SLEEP); 3543 3544 rc = ddi_intr_alloc(devinfo, ixgbe->htable, intr_type, 0, 3545 request, &actual, DDI_INTR_ALLOC_NORMAL); 3546 if (rc != DDI_SUCCESS) { 3547 ixgbe_log(ixgbe, "Allocate interrupts failed. " 3548 "return: %d, request: %d, actual: %d", 3549 rc, request, actual); 3550 goto alloc_handle_fail; 3551 } 3552 IXGBE_DEBUGLOG_1(ixgbe, "interrupts actually allocated: %d", actual); 3553 3554 ixgbe->intr_cnt = actual; 3555 3556 /* 3557 * Now we know the actual number of vectors. Here we map the vector 3558 * to other, rx rings and tx ring. 3559 */ 3560 if (actual < minimum) { 3561 ixgbe_log(ixgbe, "Insufficient interrupt handles available: %d", 3562 actual); 3563 goto alloc_handle_fail; 3564 } 3565 3566 /* 3567 * Get priority for first vector, assume remaining are all the same 3568 */ 3569 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri); 3570 if (rc != DDI_SUCCESS) { 3571 ixgbe_log(ixgbe, 3572 "Get interrupt priority failed: %d", rc); 3573 goto alloc_handle_fail; 3574 } 3575 3576 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap); 3577 if (rc != DDI_SUCCESS) { 3578 ixgbe_log(ixgbe, 3579 "Get interrupt cap failed: %d", rc); 3580 goto alloc_handle_fail; 3581 } 3582 3583 ixgbe->intr_type = intr_type; 3584 3585 return (IXGBE_SUCCESS); 3586 3587 alloc_handle_fail: 3588 ixgbe_rem_intrs(ixgbe); 3589 3590 return (IXGBE_FAILURE); 3591 } 3592 3593 /* 3594 * ixgbe_add_intr_handlers - Add interrupt handlers based on the interrupt type. 3595 * 3596 * Before adding the interrupt handlers, the interrupt vectors have 3597 * been allocated, and the rx/tx rings have also been allocated. 3598 */ 3599 static int 3600 ixgbe_add_intr_handlers(ixgbe_t *ixgbe) 3601 { 3602 int vector = 0; 3603 int rc; 3604 3605 switch (ixgbe->intr_type) { 3606 case DDI_INTR_TYPE_MSIX: 3607 /* 3608 * Add interrupt handler for rx and tx rings: vector[0 - 3609 * (ixgbe->intr_cnt -1)]. 3610 */ 3611 for (vector = 0; vector < (ixgbe->intr_cnt -1); vector++) { 3612 /* 3613 * install pointer to vect_map[vector] 3614 */ 3615 rc = ddi_intr_add_handler(ixgbe->htable[vector], 3616 (ddi_intr_handler_t *)ixgbe_intr_rx_tx, 3617 (void *)&ixgbe->vect_map[vector], NULL); 3618 3619 if (rc != DDI_SUCCESS) { 3620 ixgbe_log(ixgbe, 3621 "Add rx interrupt handler failed. " 3622 "return: %d, vector: %d", rc, vector); 3623 for (vector--; vector >= 0; vector--) { 3624 (void) ddi_intr_remove_handler( 3625 ixgbe->htable[vector]); 3626 } 3627 return (IXGBE_FAILURE); 3628 } 3629 } 3630 3631 /* 3632 * Add interrupt handler for other: vector[ixgbe->intr_cnt -1] 3633 */ 3634 rc = ddi_intr_add_handler(ixgbe->htable[vector], 3635 (ddi_intr_handler_t *)ixgbe_intr_other, 3636 (void *)ixgbe, NULL); 3637 if (rc != DDI_SUCCESS) { 3638 ixgbe_log(ixgbe, 3639 "Add other interrupt handler failed: %d", rc); 3640 return (IXGBE_FAILURE); 3641 } 3642 3643 break; 3644 3645 case DDI_INTR_TYPE_MSI: 3646 /* 3647 * Add interrupt handlers for the only vector 3648 */ 3649 rc = ddi_intr_add_handler(ixgbe->htable[vector], 3650 (ddi_intr_handler_t *)ixgbe_intr_msi, 3651 (void *)ixgbe, NULL); 3652 3653 if (rc != DDI_SUCCESS) { 3654 ixgbe_log(ixgbe, 3655 "Add MSI interrupt handler failed: %d", rc); 3656 return (IXGBE_FAILURE); 3657 } 3658 3659 break; 3660 3661 case DDI_INTR_TYPE_FIXED: 3662 /* 3663 * Add interrupt handlers for the only vector 3664 */ 3665 rc = ddi_intr_add_handler(ixgbe->htable[vector], 3666 (ddi_intr_handler_t *)ixgbe_intr_legacy, 3667 (void *)ixgbe, NULL); 3668 3669 if (rc != DDI_SUCCESS) { 3670 ixgbe_log(ixgbe, 3671 "Add legacy interrupt handler failed: %d", rc); 3672 return (IXGBE_FAILURE); 3673 } 3674 3675 break; 3676 3677 default: 3678 return (IXGBE_FAILURE); 3679 } 3680 3681 ASSERT(vector == (ixgbe->intr_cnt -1)); 3682 3683 return (IXGBE_SUCCESS); 3684 } 3685 3686 #pragma inline(ixgbe_map_rxring_to_vector) 3687 /* 3688 * ixgbe_map_rxring_to_vector - Map given rx ring to given interrupt vector. 3689 */ 3690 static void 3691 ixgbe_map_rxring_to_vector(ixgbe_t *ixgbe, int r_idx, int v_idx) 3692 { 3693 ixgbe->vect_map[v_idx].ixgbe = ixgbe; 3694 3695 /* 3696 * Set bit in map 3697 */ 3698 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx); 3699 3700 /* 3701 * Count bits set 3702 */ 3703 ixgbe->vect_map[v_idx].rxr_cnt++; 3704 3705 /* 3706 * Remember bit position 3707 */ 3708 ixgbe->rx_rings[r_idx].intr_vector = v_idx; 3709 ixgbe->rx_rings[r_idx].vect_bit = 1 << v_idx; 3710 } 3711 3712 #pragma inline(ixgbe_map_txring_to_vector) 3713 /* 3714 * ixgbe_map_txring_to_vector - Map given tx ring to given interrupt vector. 3715 */ 3716 static void 3717 ixgbe_map_txring_to_vector(ixgbe_t *ixgbe, int t_idx, int v_idx) 3718 { 3719 ixgbe->vect_map[v_idx].ixgbe = ixgbe; 3720 3721 /* 3722 * Set bit in map 3723 */ 3724 BT_SET(ixgbe->vect_map[v_idx].tx_map, t_idx); 3725 3726 /* 3727 * Count bits set 3728 */ 3729 ixgbe->vect_map[v_idx].txr_cnt++; 3730 3731 /* 3732 * Remember bit position 3733 */ 3734 ixgbe->tx_rings[t_idx].intr_vector = v_idx; 3735 ixgbe->tx_rings[t_idx].vect_bit = 1 << v_idx; 3736 } 3737 3738 /* 3739 * ixgbe_setup_ivar - Set the given entry in the given interrupt vector 3740 * allocation register (IVAR). 3741 */ 3742 static void 3743 ixgbe_setup_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, uint8_t msix_vector) 3744 { 3745 struct ixgbe_hw *hw = &ixgbe->hw; 3746 u32 ivar, index; 3747 3748 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 3749 index = (intr_alloc_entry >> 2) & 0x1F; 3750 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 3751 ivar &= ~(0xFF << (8 * (intr_alloc_entry & 0x3))); 3752 ivar |= (msix_vector << (8 * (intr_alloc_entry & 0x3))); 3753 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 3754 } 3755 3756 /* 3757 * ixgbe_enable_ivar - Enable the given entry by setting the VAL bit of 3758 * given interrupt vector allocation register (IVAR). 3759 */ 3760 static void 3761 ixgbe_enable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry) 3762 { 3763 struct ixgbe_hw *hw = &ixgbe->hw; 3764 u32 ivar, index; 3765 3766 index = (intr_alloc_entry >> 2) & 0x1F; 3767 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 3768 ivar |= (IXGBE_IVAR_ALLOC_VAL << (8 * (intr_alloc_entry & 0x3))); 3769 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 3770 } 3771 3772 /* 3773 * ixgbe_enable_ivar - Disble the given entry by clearing the VAL bit of 3774 * given interrupt vector allocation register (IVAR). 3775 */ 3776 static void 3777 ixgbe_disable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry) 3778 { 3779 struct ixgbe_hw *hw = &ixgbe->hw; 3780 u32 ivar, index; 3781 3782 index = (intr_alloc_entry >> 2) & 0x1F; 3783 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 3784 ivar &= ~(IXGBE_IVAR_ALLOC_VAL << (8 * (intr_alloc_entry & 0x3))); 3785 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 3786 } 3787 3788 /* 3789 * ixgbe_map_rings_to_vectors - Map descriptor rings to interrupt vectors. 3790 * 3791 * For MSI-X, here will map rx and tx ring to vector[0 - (vectors -1)]. 3792 * The last vector will be used for other interrupt. 3793 */ 3794 static int 3795 ixgbe_map_rings_to_vectors(ixgbe_t *ixgbe) 3796 { 3797 int i, vector = 0; 3798 3799 /* initialize vector map */ 3800 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map)); 3801 3802 /* 3803 * non-MSI-X case is very simple: rx rings[0] on RTxQ[0], 3804 * tx rings[0] on RTxQ[1]. 3805 */ 3806 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) { 3807 ixgbe_map_rxring_to_vector(ixgbe, 0, 0); 3808 ixgbe_map_txring_to_vector(ixgbe, 0, 1); 3809 return (IXGBE_SUCCESS); 3810 } 3811 3812 /* 3813 * Ring/vector mapping for MSI-X 3814 */ 3815 3816 /* 3817 * Map vectors to rx rings 3818 */ 3819 for (i = 0; i < ixgbe->num_rx_rings; i++) { 3820 ixgbe_map_rxring_to_vector(ixgbe, i, vector); 3821 vector = (vector +1) % (ixgbe->intr_cnt -1); 3822 } 3823 3824 /* 3825 * Map vectors to tx rings 3826 */ 3827 for (i = 0; i < ixgbe->num_tx_rings; i++) { 3828 ixgbe_map_txring_to_vector(ixgbe, i, vector); 3829 vector = (vector +1) % (ixgbe->intr_cnt -1); 3830 } 3831 3832 return (IXGBE_SUCCESS); 3833 } 3834 3835 /* 3836 * ixgbe_setup_adapter_vector - Setup the adapter interrupt vector(s). 3837 * 3838 * This relies on ring/vector mapping already set up in the 3839 * vect_map[] structures 3840 */ 3841 static void 3842 ixgbe_setup_adapter_vector(ixgbe_t *ixgbe) 3843 { 3844 struct ixgbe_hw *hw = &ixgbe->hw; 3845 ixgbe_ring_vector_t *vect; /* vector bitmap */ 3846 int r_idx; /* ring index */ 3847 int v_idx; /* vector index */ 3848 3849 /* 3850 * Clear any previous entries 3851 */ 3852 for (v_idx = 0; v_idx < IXGBE_IVAR_REG_NUM; v_idx++) 3853 IXGBE_WRITE_REG(hw, IXGBE_IVAR(v_idx), 0); 3854 3855 /* 3856 * For non MSI-X interrupt, rx rings[0] will use RTxQ[0], and 3857 * tx rings[0] will use RTxQ[1]. 3858 */ 3859 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) { 3860 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_RX_QUEUE(0), 0); 3861 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_TX_QUEUE(0), 1); 3862 return; 3863 } 3864 3865 /* 3866 * For MSI-X interrupt, "Other" is always on last vector. 3867 */ 3868 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_OTHER_CAUSES_INDEX, 3869 (ixgbe->intr_cnt - 1)); 3870 3871 /* 3872 * For each interrupt vector, populate the IVAR table 3873 */ 3874 for (v_idx = 0; v_idx < ixgbe->intr_cnt; v_idx++) { 3875 vect = &ixgbe->vect_map[v_idx]; 3876 3877 /* 3878 * For each rx ring bit set 3879 */ 3880 r_idx = bt_getlowbit(vect->rx_map, 0, 3881 (ixgbe->num_rx_rings - 1)); 3882 3883 while (r_idx >= 0) { 3884 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_RX_QUEUE(r_idx), 3885 v_idx); 3886 r_idx = bt_getlowbit(vect->rx_map, (r_idx + 1), 3887 (ixgbe->num_rx_rings - 1)); 3888 } 3889 3890 /* 3891 * For each tx ring bit set 3892 */ 3893 r_idx = bt_getlowbit(vect->tx_map, 0, 3894 (ixgbe->num_tx_rings - 1)); 3895 3896 while (r_idx >= 0) { 3897 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_TX_QUEUE(r_idx), 3898 v_idx); 3899 r_idx = bt_getlowbit(vect->tx_map, (r_idx + 1), 3900 (ixgbe->num_tx_rings - 1)); 3901 } 3902 } 3903 } 3904 3905 /* 3906 * ixgbe_rem_intr_handlers - Remove the interrupt handlers. 3907 */ 3908 static void 3909 ixgbe_rem_intr_handlers(ixgbe_t *ixgbe) 3910 { 3911 int i; 3912 int rc; 3913 3914 for (i = 0; i < ixgbe->intr_cnt; i++) { 3915 rc = ddi_intr_remove_handler(ixgbe->htable[i]); 3916 if (rc != DDI_SUCCESS) { 3917 IXGBE_DEBUGLOG_1(ixgbe, 3918 "Remove intr handler failed: %d", rc); 3919 } 3920 } 3921 } 3922 3923 /* 3924 * ixgbe_rem_intrs - Remove the allocated interrupts. 3925 */ 3926 static void 3927 ixgbe_rem_intrs(ixgbe_t *ixgbe) 3928 { 3929 int i; 3930 int rc; 3931 3932 for (i = 0; i < ixgbe->intr_cnt; i++) { 3933 rc = ddi_intr_free(ixgbe->htable[i]); 3934 if (rc != DDI_SUCCESS) { 3935 IXGBE_DEBUGLOG_1(ixgbe, 3936 "Free intr failed: %d", rc); 3937 } 3938 } 3939 3940 kmem_free(ixgbe->htable, ixgbe->intr_size); 3941 ixgbe->htable = NULL; 3942 } 3943 3944 /* 3945 * ixgbe_enable_intrs - Enable all the ddi interrupts. 3946 */ 3947 static int 3948 ixgbe_enable_intrs(ixgbe_t *ixgbe) 3949 { 3950 int i; 3951 int rc; 3952 3953 /* 3954 * Enable interrupts 3955 */ 3956 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) { 3957 /* 3958 * Call ddi_intr_block_enable() for MSI 3959 */ 3960 rc = ddi_intr_block_enable(ixgbe->htable, ixgbe->intr_cnt); 3961 if (rc != DDI_SUCCESS) { 3962 ixgbe_log(ixgbe, 3963 "Enable block intr failed: %d", rc); 3964 return (IXGBE_FAILURE); 3965 } 3966 } else { 3967 /* 3968 * Call ddi_intr_enable() for Legacy/MSI non block enable 3969 */ 3970 for (i = 0; i < ixgbe->intr_cnt; i++) { 3971 rc = ddi_intr_enable(ixgbe->htable[i]); 3972 if (rc != DDI_SUCCESS) { 3973 ixgbe_log(ixgbe, 3974 "Enable intr failed: %d", rc); 3975 return (IXGBE_FAILURE); 3976 } 3977 } 3978 } 3979 3980 return (IXGBE_SUCCESS); 3981 } 3982 3983 /* 3984 * ixgbe_disable_intrs - Disable all the interrupts. 3985 */ 3986 static int 3987 ixgbe_disable_intrs(ixgbe_t *ixgbe) 3988 { 3989 int i; 3990 int rc; 3991 3992 /* 3993 * Disable all interrupts 3994 */ 3995 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) { 3996 rc = ddi_intr_block_disable(ixgbe->htable, ixgbe->intr_cnt); 3997 if (rc != DDI_SUCCESS) { 3998 ixgbe_log(ixgbe, 3999 "Disable block intr failed: %d", rc); 4000 return (IXGBE_FAILURE); 4001 } 4002 } else { 4003 for (i = 0; i < ixgbe->intr_cnt; i++) { 4004 rc = ddi_intr_disable(ixgbe->htable[i]); 4005 if (rc != DDI_SUCCESS) { 4006 ixgbe_log(ixgbe, 4007 "Disable intr failed: %d", rc); 4008 return (IXGBE_FAILURE); 4009 } 4010 } 4011 } 4012 4013 return (IXGBE_SUCCESS); 4014 } 4015 4016 /* 4017 * ixgbe_get_hw_state - Get and save parameters related to adapter hardware. 4018 */ 4019 static void 4020 ixgbe_get_hw_state(ixgbe_t *ixgbe) 4021 { 4022 struct ixgbe_hw *hw = &ixgbe->hw; 4023 ixgbe_link_speed speed = IXGBE_LINK_SPEED_UNKNOWN; 4024 boolean_t link_up = B_FALSE; 4025 uint32_t pcs1g_anlp = 0; 4026 uint32_t pcs1g_ana = 0; 4027 4028 ASSERT(mutex_owned(&ixgbe->gen_lock)); 4029 ixgbe->param_lp_1000fdx_cap = 0; 4030 ixgbe->param_lp_100fdx_cap = 0; 4031 4032 /* check for link, don't wait */ 4033 (void) ixgbe_check_link(hw, &speed, &link_up, false); 4034 if (link_up) { 4035 pcs1g_anlp = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 4036 pcs1g_ana = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 4037 4038 ixgbe->param_lp_1000fdx_cap = 4039 (pcs1g_anlp & IXGBE_PCS1GANLP_LPFD) ? 1 : 0; 4040 ixgbe->param_lp_100fdx_cap = 4041 (pcs1g_anlp & IXGBE_PCS1GANLP_LPFD) ? 1 : 0; 4042 } 4043 4044 ixgbe->param_1000fdx_cap = (pcs1g_ana & IXGBE_PCS1GANA_FDC) ? 1 : 0; 4045 ixgbe->param_100fdx_cap = (pcs1g_ana & IXGBE_PCS1GANA_FDC) ? 1 : 0; 4046 } 4047 4048 /* 4049 * ixgbe_get_driver_control - Notify that driver is in control of device. 4050 */ 4051 static void 4052 ixgbe_get_driver_control(struct ixgbe_hw *hw) 4053 { 4054 uint32_t ctrl_ext; 4055 4056 /* 4057 * Notify firmware that driver is in control of device 4058 */ 4059 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4060 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 4061 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4062 } 4063 4064 /* 4065 * ixgbe_release_driver_control - Notify that driver is no longer in control 4066 * of device. 4067 */ 4068 static void 4069 ixgbe_release_driver_control(struct ixgbe_hw *hw) 4070 { 4071 uint32_t ctrl_ext; 4072 4073 /* 4074 * Notify firmware that driver is no longer in control of device 4075 */ 4076 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4077 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 4078 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4079 } 4080 4081 /* 4082 * ixgbe_atomic_reserve - Atomic decrease operation. 4083 */ 4084 int 4085 ixgbe_atomic_reserve(uint32_t *count_p, uint32_t n) 4086 { 4087 uint32_t oldval; 4088 uint32_t newval; 4089 4090 /* 4091 * ATOMICALLY 4092 */ 4093 do { 4094 oldval = *count_p; 4095 if (oldval < n) 4096 return (-1); 4097 newval = oldval - n; 4098 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4099 4100 return (newval); 4101 } 4102 4103 /* 4104 * ixgbe_mc_table_itr - Traverse the entries in the multicast table. 4105 */ 4106 static uint8_t * 4107 ixgbe_mc_table_itr(struct ixgbe_hw *hw, uint8_t **upd_ptr, uint32_t *vmdq) 4108 { 4109 uint8_t *addr = *upd_ptr; 4110 uint8_t *new_ptr; 4111 4112 _NOTE(ARGUNUSED(hw)); 4113 _NOTE(ARGUNUSED(vmdq)); 4114 4115 new_ptr = addr + IXGBE_ETH_LENGTH_OF_ADDRESS; 4116 *upd_ptr = new_ptr; 4117 return (addr); 4118 } 4119 4120 /* 4121 * FMA support 4122 */ 4123 int 4124 ixgbe_check_acc_handle(ddi_acc_handle_t handle) 4125 { 4126 ddi_fm_error_t de; 4127 4128 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4129 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4130 return (de.fme_status); 4131 } 4132 4133 int 4134 ixgbe_check_dma_handle(ddi_dma_handle_t handle) 4135 { 4136 ddi_fm_error_t de; 4137 4138 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4139 return (de.fme_status); 4140 } 4141 4142 /* 4143 * ixgbe_fm_error_cb - The IO fault service error handling callback function. 4144 */ 4145 static int 4146 ixgbe_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4147 { 4148 _NOTE(ARGUNUSED(impl_data)); 4149 /* 4150 * as the driver can always deal with an error in any dma or 4151 * access handle, we can just return the fme_status value. 4152 */ 4153 pci_ereport_post(dip, err, NULL); 4154 return (err->fme_status); 4155 } 4156 4157 static void 4158 ixgbe_fm_init(ixgbe_t *ixgbe) 4159 { 4160 ddi_iblock_cookie_t iblk; 4161 int fma_acc_flag, fma_dma_flag; 4162 4163 /* 4164 * Only register with IO Fault Services if we have some capability 4165 */ 4166 if (ixgbe->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4167 ixgbe_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4168 fma_acc_flag = 1; 4169 } else { 4170 ixgbe_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4171 fma_acc_flag = 0; 4172 } 4173 4174 if (ixgbe->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4175 fma_dma_flag = 1; 4176 } else { 4177 fma_dma_flag = 0; 4178 } 4179 4180 ixgbe_set_fma_flags(fma_acc_flag, fma_dma_flag); 4181 4182 if (ixgbe->fm_capabilities) { 4183 4184 /* 4185 * Register capabilities with IO Fault Services 4186 */ 4187 ddi_fm_init(ixgbe->dip, &ixgbe->fm_capabilities, &iblk); 4188 4189 /* 4190 * Initialize pci ereport capabilities if ereport capable 4191 */ 4192 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) || 4193 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities)) 4194 pci_ereport_setup(ixgbe->dip); 4195 4196 /* 4197 * Register error callback if error callback capable 4198 */ 4199 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities)) 4200 ddi_fm_handler_register(ixgbe->dip, 4201 ixgbe_fm_error_cb, (void*) ixgbe); 4202 } 4203 } 4204 4205 static void 4206 ixgbe_fm_fini(ixgbe_t *ixgbe) 4207 { 4208 /* 4209 * Only unregister FMA capabilities if they are registered 4210 */ 4211 if (ixgbe->fm_capabilities) { 4212 4213 /* 4214 * Release any resources allocated by pci_ereport_setup() 4215 */ 4216 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) || 4217 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities)) 4218 pci_ereport_teardown(ixgbe->dip); 4219 4220 /* 4221 * Un-register error callback if error callback capable 4222 */ 4223 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities)) 4224 ddi_fm_handler_unregister(ixgbe->dip); 4225 4226 /* 4227 * Unregister from IO Fault Service 4228 */ 4229 ddi_fm_fini(ixgbe->dip); 4230 } 4231 } 4232 4233 void 4234 ixgbe_fm_ereport(ixgbe_t *ixgbe, char *detail) 4235 { 4236 uint64_t ena; 4237 char buf[FM_MAX_CLASS]; 4238 4239 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4240 ena = fm_ena_generate(0, FM_ENA_FMT1); 4241 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities)) { 4242 ddi_fm_ereport_post(ixgbe->dip, buf, ena, DDI_NOSLEEP, 4243 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4244 } 4245 } 4246 4247 static int 4248 ixgbe_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 4249 { 4250 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)rh; 4251 4252 mutex_enter(&rx_ring->rx_lock); 4253 rx_ring->ring_gen_num = mr_gen_num; 4254 mutex_exit(&rx_ring->rx_lock); 4255 return (0); 4256 } 4257 4258 /* 4259 * Callback funtion for MAC layer to register all rings. 4260 */ 4261 /* ARGSUSED */ 4262 void 4263 ixgbe_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index, 4264 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 4265 { 4266 ixgbe_t *ixgbe = (ixgbe_t *)arg; 4267 mac_intr_t *mintr = &infop->mri_intr; 4268 4269 switch (rtype) { 4270 case MAC_RING_TYPE_RX: { 4271 ASSERT(rg_index == 0); 4272 ASSERT(ring_index < ixgbe->num_rx_rings); 4273 4274 ixgbe_rx_ring_t *rx_ring = &ixgbe->rx_rings[ring_index]; 4275 rx_ring->ring_handle = rh; 4276 4277 infop->mri_driver = (mac_ring_driver_t)rx_ring; 4278 infop->mri_start = ixgbe_ring_start; 4279 infop->mri_stop = NULL; 4280 infop->mri_poll = ixgbe_ring_rx_poll; 4281 4282 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 4283 mintr->mi_enable = ixgbe_rx_ring_intr_enable; 4284 mintr->mi_disable = ixgbe_rx_ring_intr_disable; 4285 4286 break; 4287 } 4288 case MAC_RING_TYPE_TX: { 4289 ASSERT(rg_index == -1); 4290 ASSERT(ring_index < ixgbe->num_tx_rings); 4291 4292 ixgbe_tx_ring_t *tx_ring = &ixgbe->tx_rings[ring_index]; 4293 tx_ring->ring_handle = rh; 4294 4295 infop->mri_driver = (mac_ring_driver_t)tx_ring; 4296 infop->mri_start = NULL; 4297 infop->mri_stop = NULL; 4298 infop->mri_tx = ixgbe_ring_tx; 4299 4300 break; 4301 } 4302 default: 4303 break; 4304 } 4305 } 4306 4307 /* 4308 * Callback funtion for MAC layer to register all groups. 4309 */ 4310 void 4311 ixgbe_fill_group(void *arg, mac_ring_type_t rtype, const int index, 4312 mac_group_info_t *infop, mac_group_handle_t gh) 4313 { 4314 ixgbe_t *ixgbe = (ixgbe_t *)arg; 4315 4316 switch (rtype) { 4317 case MAC_RING_TYPE_RX: { 4318 ixgbe_rx_group_t *rx_group; 4319 4320 rx_group = &ixgbe->rx_groups[index]; 4321 rx_group->group_handle = gh; 4322 4323 infop->mgi_driver = (mac_group_driver_t)rx_group; 4324 infop->mgi_start = NULL; 4325 infop->mgi_stop = NULL; 4326 infop->mgi_addmac = ixgbe_addmac; 4327 infop->mgi_remmac = ixgbe_remmac; 4328 infop->mgi_count = (ixgbe->num_rx_rings / ixgbe->num_rx_groups); 4329 4330 break; 4331 } 4332 case MAC_RING_TYPE_TX: 4333 break; 4334 default: 4335 break; 4336 } 4337 } 4338 4339 /* 4340 * Enable interrupt on the specificed rx ring. 4341 */ 4342 int 4343 ixgbe_rx_ring_intr_enable(mac_intr_handle_t intrh) 4344 { 4345 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)intrh; 4346 ixgbe_t *ixgbe = rx_ring->ixgbe; 4347 int r_idx = rx_ring->index; 4348 int v_idx = rx_ring->intr_vector; 4349 4350 mutex_enter(&ixgbe->gen_lock); 4351 ASSERT(BT_TEST(ixgbe->vect_map[v_idx].rx_map, r_idx) == 0); 4352 4353 /* 4354 * To enable interrupt by setting the VAL bit of given interrupt 4355 * vector allocation register (IVAR). 4356 */ 4357 ixgbe_enable_ivar(ixgbe, IXGBE_IVAR_RX_QUEUE(r_idx)); 4358 4359 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx); 4360 mutex_exit(&ixgbe->gen_lock); 4361 4362 return (0); 4363 } 4364 4365 /* 4366 * Disable interrupt on the specificed rx ring. 4367 */ 4368 int 4369 ixgbe_rx_ring_intr_disable(mac_intr_handle_t intrh) 4370 { 4371 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)intrh; 4372 ixgbe_t *ixgbe = rx_ring->ixgbe; 4373 int r_idx = rx_ring->index; 4374 int v_idx = rx_ring->intr_vector; 4375 4376 mutex_enter(&ixgbe->gen_lock); 4377 4378 ASSERT(BT_TEST(ixgbe->vect_map[v_idx].rx_map, r_idx) == 1); 4379 4380 /* 4381 * To disable interrupt by clearing the VAL bit of given interrupt 4382 * vector allocation register (IVAR). 4383 */ 4384 ixgbe_disable_ivar(ixgbe, IXGBE_IVAR_RX_QUEUE(r_idx)); 4385 4386 BT_CLEAR(ixgbe->vect_map[v_idx].rx_map, r_idx); 4387 4388 mutex_exit(&ixgbe->gen_lock); 4389 4390 return (0); 4391 } 4392 4393 /* 4394 * Add a mac address. 4395 */ 4396 static int 4397 ixgbe_addmac(void *arg, const uint8_t *mac_addr) 4398 { 4399 ixgbe_rx_group_t *rx_group = (ixgbe_rx_group_t *)arg; 4400 ixgbe_t *ixgbe = rx_group->ixgbe; 4401 int slot; 4402 int err; 4403 4404 mutex_enter(&ixgbe->gen_lock); 4405 4406 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) { 4407 mutex_exit(&ixgbe->gen_lock); 4408 return (ECANCELED); 4409 } 4410 4411 if (ixgbe->unicst_avail == 0) { 4412 /* no slots available */ 4413 mutex_exit(&ixgbe->gen_lock); 4414 return (ENOSPC); 4415 } 4416 4417 for (slot = 0; slot < ixgbe->unicst_total; slot++) { 4418 if (ixgbe->unicst_addr[slot].mac.set == 0) 4419 break; 4420 } 4421 4422 ASSERT((slot >= 0) && (slot < ixgbe->unicst_total)); 4423 4424 if ((err = ixgbe_unicst_set(ixgbe, mac_addr, slot)) == 0) { 4425 ixgbe->unicst_addr[slot].mac.set = 1; 4426 ixgbe->unicst_avail--; 4427 } 4428 4429 mutex_exit(&ixgbe->gen_lock); 4430 4431 return (err); 4432 } 4433 4434 /* 4435 * Remove a mac address. 4436 */ 4437 static int 4438 ixgbe_remmac(void *arg, const uint8_t *mac_addr) 4439 { 4440 ixgbe_rx_group_t *rx_group = (ixgbe_rx_group_t *)arg; 4441 ixgbe_t *ixgbe = rx_group->ixgbe; 4442 int slot; 4443 int err; 4444 4445 mutex_enter(&ixgbe->gen_lock); 4446 4447 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) { 4448 mutex_exit(&ixgbe->gen_lock); 4449 return (ECANCELED); 4450 } 4451 4452 slot = ixgbe_unicst_find(ixgbe, mac_addr); 4453 if (slot == -1) { 4454 mutex_exit(&ixgbe->gen_lock); 4455 return (EINVAL); 4456 } 4457 4458 if (ixgbe->unicst_addr[slot].mac.set == 0) { 4459 mutex_exit(&ixgbe->gen_lock); 4460 return (EINVAL); 4461 } 4462 4463 bzero(ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL); 4464 if ((err = ixgbe_unicst_set(ixgbe, 4465 ixgbe->unicst_addr[slot].mac.addr, slot)) == 0) { 4466 ixgbe->unicst_addr[slot].mac.set = 0; 4467 ixgbe->unicst_avail++; 4468 } 4469 4470 mutex_exit(&ixgbe->gen_lock); 4471 4472 return (err); 4473 } 4474