1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWK_VAR_H 30 #define _IWK_VAR_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define IWK_DMA_SYNC(area, flag) \ 37 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38 (area).alength, (flag)) 39 40 #define IWK_CHK_FAST_RECOVER(sc) \ 41 (sc->sc_ic.ic_state == IEEE80211_S_RUN && \ 42 sc->sc_ic.ic_opmode == IEEE80211_M_STA) 43 44 typedef struct iwk_dma_area { 45 ddi_acc_handle_t acc_hdl; /* handle for memory */ 46 caddr_t mem_va; /* CPU VA of memory */ 47 uint32_t nslots; /* number of slots */ 48 uint32_t size; /* size per slot */ 49 size_t alength; /* allocated size */ 50 /* >= product of above */ 51 ddi_dma_handle_t dma_hdl; /* DMA handle */ 52 offset_t offset; /* relative to handle */ 53 ddi_dma_cookie_t cookie; /* associated cookie */ 54 uint32_t ncookies; 55 uint32_t token; /* arbitrary identifier */ 56 } iwk_dma_t; 57 58 typedef struct iwk_tx_data { 59 iwk_dma_t dma_data; 60 iwk_tx_desc_t *desc; 61 uint32_t paddr_desc; 62 iwk_cmd_t *cmd; 63 uint32_t paddr_cmd; 64 } iwk_tx_data_t; 65 66 typedef struct iwk_tx_ring { 67 iwk_dma_t dma_desc; 68 iwk_dma_t dma_cmd; 69 iwk_tx_data_t *data; 70 int qid; 71 int count; 72 int window; 73 int queued; 74 int cur; 75 } iwk_tx_ring_t; 76 77 typedef struct iwk_rx_data { 78 iwk_dma_t dma_data; 79 } iwk_rx_data_t; 80 81 typedef struct iwk_rx_ring { 82 iwk_dma_t dma_desc; 83 uint32_t *desc; 84 iwk_rx_data_t data[RX_QUEUE_SIZE]; 85 int cur; 86 } iwk_rx_ring_t; 87 88 typedef struct iwk_amrr { 89 ieee80211_node_t in; /* must be the first */ 90 int txcnt; 91 int retrycnt; 92 int success; 93 int success_threshold; 94 int recovery; 95 } iwk_amrr_t; 96 97 typedef struct iwk_ibss_node { 98 iwk_add_sta_t node; 99 int8_t used; 100 } iwk_ibss_node_t; 101 102 typedef struct iwk_ibss_beacon { 103 /* for update beacon frame dynamically */ 104 struct ieee80211_beacon_offsets iwk_boff; 105 uint32_t beacon_cmd_len; 106 iwk_tx_beacon_cmd_t beacon_cmd; 107 uint8_t syncbeacon; 108 /* beacon frame allocated from net80211 module */ 109 mblk_t *mp; 110 } iwk_ibss_beacon_t; 111 112 typedef struct iwk_ibss { 113 iwk_ibss_node_t ibss_node_tb[IWK_STATION_COUNT]; 114 uint32_t node_number; 115 kmutex_t node_tb_lock; 116 iwk_ibss_beacon_t ibss_beacon; 117 } iwk_ibss_t; 118 119 typedef struct iwk_softc { 120 struct ieee80211com sc_ic; 121 dev_info_t *sc_dip; 122 int (*sc_newstate)(struct ieee80211com *, 123 enum ieee80211_state, int); 124 void (*sc_recv_mgmt)(ieee80211com_t *, mblk_t *, 125 ieee80211_node_t *, int, int, uint32_t); 126 enum ieee80211_state sc_ostate; 127 kmutex_t sc_glock; 128 kmutex_t sc_mt_lock; 129 kmutex_t sc_tx_lock; 130 kcondvar_t sc_mt_cv; 131 kcondvar_t sc_tx_cv; 132 kcondvar_t sc_cmd_cv; 133 kcondvar_t sc_fw_cv; 134 135 kthread_t *sc_mf_thread; 136 uint32_t sc_mf_thread_switch; 137 138 uint32_t sc_flags; 139 uint32_t sc_dmabuf_sz; 140 uint16_t sc_clsz; 141 uint8_t sc_rev; 142 uint8_t sc_resv; 143 uint16_t sc_assoc_id; 144 uint16_t sc_reserved0; 145 146 /* shared area */ 147 iwk_dma_t sc_dma_sh; 148 iwk_shared_t *sc_shared; 149 /* keep warm area */ 150 iwk_dma_t sc_dma_kw; 151 /* tx scheduler base address */ 152 uint32_t sc_scd_base_addr; 153 154 iwk_tx_ring_t sc_txq[IWK_NUM_QUEUES]; 155 iwk_rx_ring_t sc_rxq; 156 157 /* firmware dma */ 158 iwk_firmware_hdr_t *sc_hdr; 159 char *sc_boot; 160 iwk_dma_t sc_dma_fw_text; 161 iwk_dma_t sc_dma_fw_init_text; 162 iwk_dma_t sc_dma_fw_data; 163 iwk_dma_t sc_dma_fw_data_bak; 164 iwk_dma_t sc_dma_fw_init_data; 165 166 ddi_acc_handle_t sc_cfg_handle; 167 caddr_t sc_cfg_base; 168 ddi_acc_handle_t sc_handle; 169 caddr_t sc_base; 170 ddi_intr_handle_t *sc_intr_htable; 171 uint_t sc_intr_pri; 172 173 iwk_rxon_cmd_t sc_config; 174 iwk_rxon_cmd_t sc_config_save; 175 struct iwk_eep sc_eep_map; /* eeprom map */ 176 uint32_t sc_scd_base; 177 178 struct iwk_alive_resp sc_card_alive_run; 179 struct iwk_init_alive_resp sc_card_alive_init; 180 181 int32_t sc_tempera; 182 int32_t sc_last_tempera; 183 int32_t sc_user_txpower; 184 struct iwk_notif_statistics sc_statistics; 185 struct iwk_rx_gain_diff sc_rxgain_diff; 186 struct iwk_rx_sensitivity sc_rx_sens; 187 188 uint32_t sc_tx_timer; 189 uint32_t sc_scan_pending; 190 uint8_t *sc_fw_bin; 191 192 ddi_softint_handle_t sc_soft_hdl; 193 uint32_t sc_rx_softint_pending; 194 uint32_t sc_need_reschedule; 195 196 clock_t sc_clk; 197 198 /* kstats */ 199 uint32_t sc_tx_nobuf; 200 uint32_t sc_rx_nobuf; 201 uint32_t sc_tx_err; 202 uint32_t sc_rx_err; 203 uint32_t sc_tx_retries; 204 iwk_ibss_t sc_ibss; 205 } iwk_sc_t; 206 207 #define IWK_F_ATTACHED (1 << 0) 208 #define IWK_F_CMD_DONE (1 << 1) 209 #define IWK_F_FW_INIT (1 << 2) 210 #define IWK_F_HW_ERR_RECOVER (1 << 3) 211 #define IWK_F_RATE_AUTO_CTL (1 << 4) 212 #define IWK_F_RUNNING (1 << 5) 213 #define IWK_F_SCANNING (1 << 6) 214 #define IWK_F_SUSPEND (1 << 7) 215 #define IWK_F_RADIO_OFF (1 << 8) 216 #define IWK_F_STATISTICS (1 << 9) 217 #define IWK_F_QUIESCED (1 << 10) 218 #define IWK_F_LAZY_RESUME (1 << 11) 219 220 #define IWK_SUCCESS 0 221 #define IWK_FAIL EIO 222 223 #ifdef __cplusplus 224 } 225 #endif 226 227 #endif /* _IWK_VAR_H */ 228