1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #include "igb_osdep.h" 30 #include "igb_api.h" 31 32 33 void 34 e1000_pci_set_mwi(struct e1000_hw *hw) 35 { 36 uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 37 38 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 39 } 40 41 void 42 e1000_pci_clear_mwi(struct e1000_hw *hw) 43 { 44 uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 45 46 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 47 } 48 49 void 50 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 51 { 52 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); 53 } 54 55 void 56 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 57 { 58 *value = 59 pci_config_get16(OS_DEP(hw)->cfg_handle, reg); 60 } 61 62 /* 63 * Return the 16-bit value from pci-e config space at offset reg into the pci-e 64 * capability block. 65 */ 66 int32_t 67 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 68 { 69 uint32_t pcie_cap = PCI_EX_CONF_CAP; /* default */ 70 71 switch (hw->mac.type) { 72 case e1000_82575: 73 pcie_cap = 0xa0; 74 break; 75 case e1000_82576: 76 pcie_cap = 0xa0; 77 break; 78 } 79 80 *value = pci_config_get16(OS_DEP(hw)->cfg_handle, (pcie_cap + reg)); 81 82 return (0); 83 } 84 85 /* 86 * e1000_rar_set_vmdq - Clear the RAR registers 87 */ 88 void 89 e1000_rar_clear(struct e1000_hw *hw, uint32_t index) 90 { 91 92 uint32_t rar_high; 93 94 /* Make the hardware the Address invalid by setting the clear bit */ 95 rar_high = ~E1000_RAH_AV; 96 97 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 98 E1000_WRITE_FLUSH(hw); 99 } 100 101 /* 102 * e1000_rar_set_vmdq - Set the RAR registers for VMDq 103 */ 104 void 105 e1000_rar_set_vmdq(struct e1000_hw *hw, const uint8_t *addr, uint32_t index, 106 uint32_t vmdq_mode, uint8_t qsel) 107 { 108 uint32_t rar_low, rar_high; 109 110 /* 111 * NIC expects these in little endian so reverse the byte order 112 * from network order (big endian) to little endian. 113 */ 114 115 rar_low = ((uint32_t)addr[0] | ((uint32_t)addr[1] << 8) | 116 ((uint32_t)addr[2] << 16) | ((uint32_t)addr[3] << 24)); 117 118 rar_high = ((uint32_t)addr[4] | ((uint32_t)addr[5] << 8)); 119 120 /* Indicate to hardware the Address is Valid. */ 121 rar_high |= E1000_RAH_AV; 122 123 /* Set que selector based on vmdq mode */ 124 switch (vmdq_mode) { 125 default: 126 case E1000_VMDQ_OFF: 127 break; 128 case E1000_VMDQ_MAC: 129 rar_high |= (qsel << 18); 130 break; 131 case E1000_VMDQ_MAC_RSS: 132 rar_high |= 1 << (18 + qsel); 133 break; 134 135 } 136 137 /* write to receive address registers */ 138 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 139 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 140 E1000_WRITE_FLUSH(hw); 141 } 142