1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #include "igb_sw.h" 30 31 static char ident[] = "Intel 1Gb Ethernet"; 32 static char igb_version[] = "igb 1.1.5"; 33 34 /* 35 * Local function protoypes 36 */ 37 static int igb_register_mac(igb_t *); 38 static int igb_identify_hardware(igb_t *); 39 static int igb_regs_map(igb_t *); 40 static void igb_init_properties(igb_t *); 41 static int igb_init_driver_settings(igb_t *); 42 static void igb_init_locks(igb_t *); 43 static void igb_destroy_locks(igb_t *); 44 static int igb_init_mac_address(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_init_adapter(igb_t *); 47 static void igb_stop_adapter(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static void igb_free_rings(igb_t *); 54 static void igb_setup_rings(igb_t *); 55 static void igb_setup_rx(igb_t *); 56 static void igb_setup_tx(igb_t *); 57 static void igb_setup_rx_ring(igb_rx_ring_t *); 58 static void igb_setup_tx_ring(igb_tx_ring_t *); 59 static void igb_setup_rss(igb_t *); 60 static void igb_setup_mac_rss_classify(igb_t *); 61 static void igb_setup_mac_classify(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts_82575(igb_t *); 76 static void igb_enable_adapter_interrupts_82576(igb_t *); 77 static boolean_t is_valid_mac_addr(uint8_t *); 78 static boolean_t igb_stall_check(igb_t *); 79 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 80 static void igb_set_external_loopback(igb_t *); 81 static void igb_set_internal_mac_loopback(igb_t *); 82 static void igb_set_internal_phy_loopback(igb_t *); 83 static void igb_set_internal_serdes_loopback(igb_t *); 84 static boolean_t igb_find_mac_address(igb_t *); 85 static int igb_alloc_intrs(igb_t *); 86 static int igb_alloc_intr_handles(igb_t *, int); 87 static int igb_add_intr_handlers(igb_t *); 88 static void igb_rem_intr_handlers(igb_t *); 89 static void igb_rem_intrs(igb_t *); 90 static int igb_enable_intrs(igb_t *); 91 static int igb_disable_intrs(igb_t *); 92 static void igb_setup_msix_82575(igb_t *); 93 static void igb_setup_msix_82576(igb_t *); 94 static uint_t igb_intr_legacy(void *, void *); 95 static uint_t igb_intr_msi(void *, void *); 96 static uint_t igb_intr_rx(void *, void *); 97 static uint_t igb_intr_tx(void *, void *); 98 static uint_t igb_intr_tx_other(void *, void *); 99 static void igb_intr_rx_work(igb_rx_ring_t *); 100 static void igb_intr_tx_work(igb_tx_ring_t *); 101 static void igb_intr_link_work(igb_t *); 102 static void igb_get_driver_control(struct e1000_hw *); 103 static void igb_release_driver_control(struct e1000_hw *); 104 105 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 106 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 107 static int igb_resume(dev_info_t *); 108 static int igb_suspend(dev_info_t *); 109 static int igb_quiesce(dev_info_t *); 110 static void igb_unconfigure(dev_info_t *, igb_t *); 111 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 112 const void *); 113 static void igb_fm_init(igb_t *); 114 static void igb_fm_fini(igb_t *); 115 116 117 static struct cb_ops igb_cb_ops = { 118 nulldev, /* cb_open */ 119 nulldev, /* cb_close */ 120 nodev, /* cb_strategy */ 121 nodev, /* cb_print */ 122 nodev, /* cb_dump */ 123 nodev, /* cb_read */ 124 nodev, /* cb_write */ 125 nodev, /* cb_ioctl */ 126 nodev, /* cb_devmap */ 127 nodev, /* cb_mmap */ 128 nodev, /* cb_segmap */ 129 nochpoll, /* cb_chpoll */ 130 ddi_prop_op, /* cb_prop_op */ 131 NULL, /* cb_stream */ 132 D_MP | D_HOTPLUG, /* cb_flag */ 133 CB_REV, /* cb_rev */ 134 nodev, /* cb_aread */ 135 nodev /* cb_awrite */ 136 }; 137 138 static struct dev_ops igb_dev_ops = { 139 DEVO_REV, /* devo_rev */ 140 0, /* devo_refcnt */ 141 NULL, /* devo_getinfo */ 142 nulldev, /* devo_identify */ 143 nulldev, /* devo_probe */ 144 igb_attach, /* devo_attach */ 145 igb_detach, /* devo_detach */ 146 nodev, /* devo_reset */ 147 &igb_cb_ops, /* devo_cb_ops */ 148 NULL, /* devo_bus_ops */ 149 ddi_power, /* devo_power */ 150 igb_quiesce, /* devo_quiesce */ 151 }; 152 153 static struct modldrv igb_modldrv = { 154 &mod_driverops, /* Type of module. This one is a driver */ 155 ident, /* Discription string */ 156 &igb_dev_ops, /* driver ops */ 157 }; 158 159 static struct modlinkage igb_modlinkage = { 160 MODREV_1, &igb_modldrv, NULL 161 }; 162 163 /* Access attributes for register mapping */ 164 ddi_device_acc_attr_t igb_regs_acc_attr = { 165 DDI_DEVICE_ATTR_V0, 166 DDI_STRUCTURE_LE_ACC, 167 DDI_STRICTORDER_ACC, 168 DDI_FLAGERR_ACC 169 }; 170 171 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 172 173 static mac_callbacks_t igb_m_callbacks = { 174 IGB_M_CALLBACK_FLAGS, 175 igb_m_stat, 176 igb_m_start, 177 igb_m_stop, 178 igb_m_promisc, 179 igb_m_multicst, 180 NULL, 181 NULL, 182 igb_m_ioctl, 183 igb_m_getcapab 184 }; 185 186 /* 187 * Initialize capabilities of each supported adapter type 188 */ 189 static adapter_info_t igb_82575_cap = { 190 /* limits */ 191 4, /* maximum number of rx queues */ 192 1, /* minimum number of rx queues */ 193 4, /* default number of rx queues */ 194 4, /* maximum number of tx queues */ 195 1, /* minimum number of tx queues */ 196 4, /* default number of tx queues */ 197 65535, /* maximum interrupt throttle rate */ 198 0, /* minimum interrupt throttle rate */ 199 200, /* default interrupt throttle rate */ 200 201 /* function pointers */ 202 igb_enable_adapter_interrupts_82575, 203 igb_setup_msix_82575, 204 205 /* capabilities */ 206 (IGB_FLAG_HAS_DCA | /* capability flags */ 207 IGB_FLAG_VMDQ_POOL), 208 209 0xffc00000 /* mask for RXDCTL register */ 210 }; 211 212 static adapter_info_t igb_82576_cap = { 213 /* limits */ 214 16, /* maximum number of rx queues */ 215 1, /* minimum number of rx queues */ 216 4, /* default number of rx queues */ 217 16, /* maximum number of tx queues */ 218 1, /* minimum number of tx queues */ 219 4, /* default number of tx queues */ 220 65535, /* maximum interrupt throttle rate */ 221 0, /* minimum interrupt throttle rate */ 222 200, /* default interrupt throttle rate */ 223 224 /* function pointers */ 225 igb_enable_adapter_interrupts_82576, 226 igb_setup_msix_82576, 227 228 /* capabilities */ 229 (IGB_FLAG_HAS_DCA | /* capability flags */ 230 IGB_FLAG_VMDQ_POOL | 231 IGB_FLAG_NEED_CTX_IDX), 232 233 0xffe00000 /* mask for RXDCTL register */ 234 }; 235 236 /* 237 * Module Initialization Functions 238 */ 239 240 int 241 _init(void) 242 { 243 int status; 244 245 mac_init_ops(&igb_dev_ops, MODULE_NAME); 246 247 status = mod_install(&igb_modlinkage); 248 249 if (status != DDI_SUCCESS) { 250 mac_fini_ops(&igb_dev_ops); 251 } 252 253 return (status); 254 } 255 256 int 257 _fini(void) 258 { 259 int status; 260 261 status = mod_remove(&igb_modlinkage); 262 263 if (status == DDI_SUCCESS) { 264 mac_fini_ops(&igb_dev_ops); 265 } 266 267 return (status); 268 269 } 270 271 int 272 _info(struct modinfo *modinfop) 273 { 274 int status; 275 276 status = mod_info(&igb_modlinkage, modinfop); 277 278 return (status); 279 } 280 281 /* 282 * igb_attach - driver attach 283 * 284 * This function is the device specific initialization entry 285 * point. This entry point is required and must be written. 286 * The DDI_ATTACH command must be provided in the attach entry 287 * point. When attach() is called with cmd set to DDI_ATTACH, 288 * all normal kernel services (such as kmem_alloc(9F)) are 289 * available for use by the driver. 290 * 291 * The attach() function will be called once for each instance 292 * of the device on the system with cmd set to DDI_ATTACH. 293 * Until attach() succeeds, the only driver entry points which 294 * may be called are open(9E) and getinfo(9E). 295 */ 296 static int 297 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 298 { 299 igb_t *igb; 300 struct igb_osdep *osdep; 301 struct e1000_hw *hw; 302 int instance; 303 304 /* 305 * Check the command and perform corresponding operations 306 */ 307 switch (cmd) { 308 default: 309 return (DDI_FAILURE); 310 311 case DDI_RESUME: 312 return (igb_resume(devinfo)); 313 314 case DDI_ATTACH: 315 break; 316 } 317 318 /* Get the device instance */ 319 instance = ddi_get_instance(devinfo); 320 321 /* Allocate memory for the instance data structure */ 322 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 323 324 igb->dip = devinfo; 325 igb->instance = instance; 326 327 hw = &igb->hw; 328 osdep = &igb->osdep; 329 hw->back = osdep; 330 osdep->igb = igb; 331 332 /* Attach the instance pointer to the dev_info data structure */ 333 ddi_set_driver_private(devinfo, igb); 334 335 336 /* Initialize for fma support */ 337 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 338 0, 0x0f, 339 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 340 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 341 igb_fm_init(igb); 342 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 343 344 /* 345 * Map PCI config space registers 346 */ 347 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 348 igb_error(igb, "Failed to map PCI configurations"); 349 goto attach_fail; 350 } 351 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 352 353 /* 354 * Identify the chipset family 355 */ 356 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 357 igb_error(igb, "Failed to identify hardware"); 358 goto attach_fail; 359 } 360 361 /* 362 * Map device registers 363 */ 364 if (igb_regs_map(igb) != IGB_SUCCESS) { 365 igb_error(igb, "Failed to map device registers"); 366 goto attach_fail; 367 } 368 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 369 370 /* 371 * Initialize driver parameters 372 */ 373 igb_init_properties(igb); 374 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 375 376 /* 377 * Allocate interrupts 378 */ 379 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 380 igb_error(igb, "Failed to allocate interrupts"); 381 goto attach_fail; 382 } 383 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 384 385 /* 386 * Allocate rx/tx rings based on the ring numbers. 387 * The actual numbers of rx/tx rings are decided by the number of 388 * allocated interrupt vectors, so we should allocate the rings after 389 * interrupts are allocated. 390 */ 391 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 392 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 393 goto attach_fail; 394 } 395 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 396 397 /* 398 * Add interrupt handlers 399 */ 400 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 401 igb_error(igb, "Failed to add interrupt handlers"); 402 goto attach_fail; 403 } 404 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 405 406 /* 407 * Initialize driver parameters 408 */ 409 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 410 igb_error(igb, "Failed to initialize driver settings"); 411 goto attach_fail; 412 } 413 414 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 415 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 416 goto attach_fail; 417 } 418 419 /* 420 * Initialize mutexes for this device. 421 * Do this before enabling the interrupt handler and 422 * register the softint to avoid the condition where 423 * interrupt handler can try using uninitialized mutex 424 */ 425 igb_init_locks(igb); 426 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 427 428 /* 429 * Allocate DMA resources 430 */ 431 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 432 igb_error(igb, "Failed to allocate DMA resources"); 433 goto attach_fail; 434 } 435 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_DMA; 436 437 /* 438 * Initialize the adapter and setup the rx/tx rings 439 */ 440 if (igb_init(igb) != IGB_SUCCESS) { 441 igb_error(igb, "Failed to initialize adapter"); 442 goto attach_fail; 443 } 444 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 445 446 /* 447 * Initialize statistics 448 */ 449 if (igb_init_stats(igb) != IGB_SUCCESS) { 450 igb_error(igb, "Failed to initialize statistics"); 451 goto attach_fail; 452 } 453 igb->attach_progress |= ATTACH_PROGRESS_STATS; 454 455 /* 456 * Initialize NDD parameters 457 */ 458 if (igb_nd_init(igb) != IGB_SUCCESS) { 459 igb_error(igb, "Failed to initialize ndd"); 460 goto attach_fail; 461 } 462 igb->attach_progress |= ATTACH_PROGRESS_NDD; 463 464 /* 465 * Register the driver to the MAC 466 */ 467 if (igb_register_mac(igb) != IGB_SUCCESS) { 468 igb_error(igb, "Failed to register MAC"); 469 goto attach_fail; 470 } 471 igb->attach_progress |= ATTACH_PROGRESS_MAC; 472 473 /* 474 * Now that mutex locks are initialized, and the chip is also 475 * initialized, enable interrupts. 476 */ 477 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 478 igb_error(igb, "Failed to enable DDI interrupts"); 479 goto attach_fail; 480 } 481 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 482 483 igb_log(igb, "%s", igb_version); 484 igb->igb_state |= IGB_INITIALIZED; 485 486 return (DDI_SUCCESS); 487 488 attach_fail: 489 igb_unconfigure(devinfo, igb); 490 return (DDI_FAILURE); 491 } 492 493 /* 494 * igb_detach - driver detach 495 * 496 * The detach() function is the complement of the attach routine. 497 * If cmd is set to DDI_DETACH, detach() is used to remove the 498 * state associated with a given instance of a device node 499 * prior to the removal of that instance from the system. 500 * 501 * The detach() function will be called once for each instance 502 * of the device for which there has been a successful attach() 503 * once there are no longer any opens on the device. 504 * 505 * Interrupts routine are disabled, All memory allocated by this 506 * driver are freed. 507 */ 508 static int 509 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 510 { 511 igb_t *igb; 512 513 /* 514 * Check detach command 515 */ 516 switch (cmd) { 517 default: 518 return (DDI_FAILURE); 519 520 case DDI_SUSPEND: 521 return (igb_suspend(devinfo)); 522 523 case DDI_DETACH: 524 break; 525 } 526 527 528 /* 529 * Get the pointer to the driver private data structure 530 */ 531 igb = (igb_t *)ddi_get_driver_private(devinfo); 532 if (igb == NULL) 533 return (DDI_FAILURE); 534 535 /* 536 * Unregister MAC. If failed, we have to fail the detach 537 */ 538 if (mac_unregister(igb->mac_hdl) != 0) { 539 igb_error(igb, "Failed to unregister MAC"); 540 return (DDI_FAILURE); 541 } 542 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 543 544 /* 545 * If the device is still running, it needs to be stopped first. 546 * This check is necessary because under some specific circumstances, 547 * the detach routine can be called without stopping the interface 548 * first. 549 */ 550 mutex_enter(&igb->gen_lock); 551 if (igb->igb_state & IGB_STARTED) { 552 igb->igb_state &= ~IGB_STARTED; 553 igb_stop(igb); 554 mutex_exit(&igb->gen_lock); 555 /* Disable and stop the watchdog timer */ 556 igb_disable_watchdog_timer(igb); 557 } else 558 mutex_exit(&igb->gen_lock); 559 560 /* 561 * Check if there are still rx buffers held by the upper layer. 562 * If so, fail the detach. 563 */ 564 if (!igb_rx_drain(igb)) 565 return (DDI_FAILURE); 566 567 /* 568 * Do the remaining unconfigure routines 569 */ 570 igb_unconfigure(devinfo, igb); 571 572 return (DDI_SUCCESS); 573 } 574 575 /* 576 * quiesce(9E) entry point. 577 * 578 * This function is called when the system is single-threaded at high 579 * PIL with preemption disabled. Therefore, this function must not be 580 * blocked. 581 * 582 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 583 * DDI_FAILURE indicates an error condition and should almost never happen. 584 */ 585 static int 586 igb_quiesce(dev_info_t *devinfo) 587 { 588 igb_t *igb; 589 struct e1000_hw *hw; 590 591 igb = (igb_t *)ddi_get_driver_private(devinfo); 592 593 if (igb == NULL) 594 return (DDI_FAILURE); 595 596 hw = &igb->hw; 597 598 /* 599 * Disable the adapter interrupts 600 */ 601 igb_disable_adapter_interrupts(igb); 602 603 /* Tell firmware driver is no longer in control */ 604 igb_release_driver_control(hw); 605 606 /* 607 * Reset the chipset 608 */ 609 (void) e1000_reset_hw(hw); 610 611 /* 612 * Reset PHY if possible 613 */ 614 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 615 (void) e1000_phy_hw_reset(hw); 616 617 return (DDI_SUCCESS); 618 } 619 620 /* 621 * igb_unconfigure - release all resources held by this instance 622 */ 623 static void 624 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 625 { 626 /* 627 * Disable interrupt 628 */ 629 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 630 (void) igb_disable_intrs(igb); 631 } 632 633 /* 634 * Unregister MAC 635 */ 636 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 637 (void) mac_unregister(igb->mac_hdl); 638 } 639 640 /* 641 * Free ndd parameters 642 */ 643 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 644 igb_nd_cleanup(igb); 645 } 646 647 /* 648 * Free statistics 649 */ 650 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 651 kstat_delete((kstat_t *)igb->igb_ks); 652 } 653 654 /* 655 * Remove interrupt handlers 656 */ 657 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 658 igb_rem_intr_handlers(igb); 659 } 660 661 /* 662 * Remove interrupts 663 */ 664 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 665 igb_rem_intrs(igb); 666 } 667 668 /* 669 * Remove driver properties 670 */ 671 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 672 (void) ddi_prop_remove_all(devinfo); 673 } 674 675 /* 676 * Release the DMA resources of rx/tx rings 677 */ 678 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_DMA) { 679 igb_free_dma(igb); 680 } 681 682 /* 683 * Stop the adapter 684 */ 685 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 686 mutex_enter(&igb->gen_lock); 687 igb_stop_adapter(igb); 688 mutex_exit(&igb->gen_lock); 689 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 690 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 691 } 692 693 /* 694 * Free register handle 695 */ 696 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 697 if (igb->osdep.reg_handle != NULL) 698 ddi_regs_map_free(&igb->osdep.reg_handle); 699 } 700 701 /* 702 * Free PCI config handle 703 */ 704 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 705 if (igb->osdep.cfg_handle != NULL) 706 pci_config_teardown(&igb->osdep.cfg_handle); 707 } 708 709 /* 710 * Free locks 711 */ 712 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 713 igb_destroy_locks(igb); 714 } 715 716 /* 717 * Free the rx/tx rings 718 */ 719 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 720 igb_free_rings(igb); 721 } 722 723 /* 724 * Remove FMA 725 */ 726 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 727 igb_fm_fini(igb); 728 } 729 730 /* 731 * Free the driver data structure 732 */ 733 kmem_free(igb, sizeof (igb_t)); 734 735 ddi_set_driver_private(devinfo, NULL); 736 } 737 738 /* 739 * igb_register_mac - Register the driver and its function pointers with 740 * the GLD interface 741 */ 742 static int 743 igb_register_mac(igb_t *igb) 744 { 745 struct e1000_hw *hw = &igb->hw; 746 mac_register_t *mac; 747 int status; 748 749 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 750 return (IGB_FAILURE); 751 752 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 753 mac->m_driver = igb; 754 mac->m_dip = igb->dip; 755 mac->m_src_addr = hw->mac.addr; 756 mac->m_callbacks = &igb_m_callbacks; 757 mac->m_min_sdu = 0; 758 mac->m_max_sdu = igb->max_frame_size - 759 sizeof (struct ether_vlan_header) - ETHERFCSL; 760 mac->m_margin = VLAN_TAGSZ; 761 mac->m_v12n = MAC_VIRT_LEVEL1; 762 763 status = mac_register(mac, &igb->mac_hdl); 764 765 mac_free(mac); 766 767 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 768 } 769 770 /* 771 * igb_identify_hardware - Identify the type of the chipset 772 */ 773 static int 774 igb_identify_hardware(igb_t *igb) 775 { 776 struct e1000_hw *hw = &igb->hw; 777 struct igb_osdep *osdep = &igb->osdep; 778 779 /* 780 * Get the device id 781 */ 782 hw->vendor_id = 783 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 784 hw->device_id = 785 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 786 hw->revision_id = 787 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 788 hw->subsystem_device_id = 789 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 790 hw->subsystem_vendor_id = 791 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 792 793 /* 794 * Set the mac type of the adapter based on the device id 795 */ 796 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 797 return (IGB_FAILURE); 798 } 799 800 /* 801 * Install adapter capabilities based on mac type 802 */ 803 switch (hw->mac.type) { 804 case e1000_82575: 805 igb->capab = &igb_82575_cap; 806 break; 807 case e1000_82576: 808 igb->capab = &igb_82576_cap; 809 break; 810 default: 811 return (IGB_FAILURE); 812 } 813 814 return (IGB_SUCCESS); 815 } 816 817 /* 818 * igb_regs_map - Map the device registers 819 */ 820 static int 821 igb_regs_map(igb_t *igb) 822 { 823 dev_info_t *devinfo = igb->dip; 824 struct e1000_hw *hw = &igb->hw; 825 struct igb_osdep *osdep = &igb->osdep; 826 off_t mem_size; 827 828 /* 829 * First get the size of device registers to be mapped. 830 */ 831 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 832 DDI_SUCCESS) { 833 return (IGB_FAILURE); 834 } 835 836 /* 837 * Call ddi_regs_map_setup() to map registers 838 */ 839 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 840 (caddr_t *)&hw->hw_addr, 0, 841 mem_size, &igb_regs_acc_attr, 842 &osdep->reg_handle)) != DDI_SUCCESS) { 843 return (IGB_FAILURE); 844 } 845 846 return (IGB_SUCCESS); 847 } 848 849 /* 850 * igb_init_properties - Initialize driver properties 851 */ 852 static void 853 igb_init_properties(igb_t *igb) 854 { 855 /* 856 * Get conf file properties, including link settings 857 * jumbo frames, ring number, descriptor number, etc. 858 */ 859 igb_get_conf(igb); 860 } 861 862 /* 863 * igb_init_driver_settings - Initialize driver settings 864 * 865 * The settings include hardware function pointers, bus information, 866 * rx/tx rings settings, link state, and any other parameters that 867 * need to be setup during driver initialization. 868 */ 869 static int 870 igb_init_driver_settings(igb_t *igb) 871 { 872 struct e1000_hw *hw = &igb->hw; 873 igb_rx_ring_t *rx_ring; 874 igb_tx_ring_t *tx_ring; 875 uint32_t rx_size; 876 uint32_t tx_size; 877 int i; 878 879 /* 880 * Initialize chipset specific hardware function pointers 881 */ 882 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 883 return (IGB_FAILURE); 884 } 885 886 /* 887 * Get bus information 888 */ 889 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 890 return (IGB_FAILURE); 891 } 892 893 /* 894 * Set rx buffer size 895 * The IP header alignment room is counted in the calculation. 896 * The rx buffer size is in unit of 1K that is required by the 897 * chipset hardware. 898 */ 899 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 900 igb->rx_buf_size = ((rx_size >> 10) + 901 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 902 903 /* 904 * Set tx buffer size 905 */ 906 tx_size = igb->max_frame_size; 907 igb->tx_buf_size = ((tx_size >> 10) + 908 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 909 910 /* 911 * Initialize rx/tx rings parameters 912 */ 913 for (i = 0; i < igb->num_rx_rings; i++) { 914 rx_ring = &igb->rx_rings[i]; 915 rx_ring->index = i; 916 rx_ring->igb = igb; 917 918 rx_ring->ring_size = igb->rx_ring_size; 919 rx_ring->free_list_size = igb->rx_ring_size; 920 rx_ring->copy_thresh = igb->rx_copy_thresh; 921 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 922 } 923 924 for (i = 0; i < igb->num_tx_rings; i++) { 925 tx_ring = &igb->tx_rings[i]; 926 tx_ring->index = i; 927 tx_ring->igb = igb; 928 if (igb->tx_head_wb_enable) 929 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 930 else 931 tx_ring->tx_recycle = igb_tx_recycle_legacy; 932 933 tx_ring->ring_size = igb->tx_ring_size; 934 tx_ring->free_list_size = igb->tx_ring_size + 935 (igb->tx_ring_size >> 1); 936 tx_ring->copy_thresh = igb->tx_copy_thresh; 937 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 938 tx_ring->overload_thresh = igb->tx_overload_thresh; 939 tx_ring->resched_thresh = igb->tx_resched_thresh; 940 } 941 942 /* 943 * Initialize values of interrupt throttling rates 944 */ 945 for (i = 1; i < MAX_NUM_EITR; i++) 946 igb->intr_throttling[i] = igb->intr_throttling[0]; 947 948 /* 949 * The initial link state should be "unknown" 950 */ 951 igb->link_state = LINK_STATE_UNKNOWN; 952 953 return (IGB_SUCCESS); 954 } 955 956 /* 957 * igb_init_locks - Initialize locks 958 */ 959 static void 960 igb_init_locks(igb_t *igb) 961 { 962 igb_rx_ring_t *rx_ring; 963 igb_tx_ring_t *tx_ring; 964 int i; 965 966 for (i = 0; i < igb->num_rx_rings; i++) { 967 rx_ring = &igb->rx_rings[i]; 968 mutex_init(&rx_ring->rx_lock, NULL, 969 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 970 mutex_init(&rx_ring->recycle_lock, NULL, 971 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 972 } 973 974 for (i = 0; i < igb->num_tx_rings; i++) { 975 tx_ring = &igb->tx_rings[i]; 976 mutex_init(&tx_ring->tx_lock, NULL, 977 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 978 mutex_init(&tx_ring->recycle_lock, NULL, 979 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 980 mutex_init(&tx_ring->tcb_head_lock, NULL, 981 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 982 mutex_init(&tx_ring->tcb_tail_lock, NULL, 983 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 984 } 985 986 mutex_init(&igb->gen_lock, NULL, 987 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 988 989 mutex_init(&igb->watchdog_lock, NULL, 990 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 991 } 992 993 /* 994 * igb_destroy_locks - Destroy locks 995 */ 996 static void 997 igb_destroy_locks(igb_t *igb) 998 { 999 igb_rx_ring_t *rx_ring; 1000 igb_tx_ring_t *tx_ring; 1001 int i; 1002 1003 for (i = 0; i < igb->num_rx_rings; i++) { 1004 rx_ring = &igb->rx_rings[i]; 1005 mutex_destroy(&rx_ring->rx_lock); 1006 mutex_destroy(&rx_ring->recycle_lock); 1007 } 1008 1009 for (i = 0; i < igb->num_tx_rings; i++) { 1010 tx_ring = &igb->tx_rings[i]; 1011 mutex_destroy(&tx_ring->tx_lock); 1012 mutex_destroy(&tx_ring->recycle_lock); 1013 mutex_destroy(&tx_ring->tcb_head_lock); 1014 mutex_destroy(&tx_ring->tcb_tail_lock); 1015 } 1016 1017 mutex_destroy(&igb->gen_lock); 1018 mutex_destroy(&igb->watchdog_lock); 1019 } 1020 1021 static int 1022 igb_resume(dev_info_t *devinfo) 1023 { 1024 igb_t *igb; 1025 1026 igb = (igb_t *)ddi_get_driver_private(devinfo); 1027 if (igb == NULL) 1028 return (DDI_FAILURE); 1029 1030 mutex_enter(&igb->gen_lock); 1031 1032 if (igb->igb_state & IGB_STARTED) { 1033 if (igb_start(igb) != IGB_SUCCESS) { 1034 mutex_exit(&igb->gen_lock); 1035 return (DDI_FAILURE); 1036 } 1037 1038 /* 1039 * Enable and start the watchdog timer 1040 */ 1041 igb_enable_watchdog_timer(igb); 1042 } 1043 1044 igb->igb_state &= ~IGB_SUSPENDED; 1045 1046 mutex_exit(&igb->gen_lock); 1047 1048 return (DDI_SUCCESS); 1049 } 1050 1051 static int 1052 igb_suspend(dev_info_t *devinfo) 1053 { 1054 igb_t *igb; 1055 1056 igb = (igb_t *)ddi_get_driver_private(devinfo); 1057 if (igb == NULL) 1058 return (DDI_FAILURE); 1059 1060 mutex_enter(&igb->gen_lock); 1061 1062 igb->igb_state |= IGB_SUSPENDED; 1063 1064 if (!(igb->igb_state & IGB_STARTED)) { 1065 mutex_exit(&igb->gen_lock); 1066 return (DDI_SUCCESS); 1067 } 1068 1069 igb_stop(igb); 1070 1071 mutex_exit(&igb->gen_lock); 1072 1073 /* 1074 * Disable and stop the watchdog timer 1075 */ 1076 igb_disable_watchdog_timer(igb); 1077 1078 return (DDI_SUCCESS); 1079 } 1080 1081 static int 1082 igb_init(igb_t *igb) 1083 { 1084 int i; 1085 1086 mutex_enter(&igb->gen_lock); 1087 1088 /* 1089 * Initilize the adapter 1090 */ 1091 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1092 mutex_exit(&igb->gen_lock); 1093 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1094 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1095 return (IGB_FAILURE); 1096 } 1097 1098 /* 1099 * Setup the rx/tx rings 1100 */ 1101 for (i = 0; i < igb->num_rx_rings; i++) 1102 mutex_enter(&igb->rx_rings[i].rx_lock); 1103 for (i = 0; i < igb->num_tx_rings; i++) 1104 mutex_enter(&igb->tx_rings[i].tx_lock); 1105 1106 igb_setup_rings(igb); 1107 1108 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1109 mutex_exit(&igb->tx_rings[i].tx_lock); 1110 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1111 mutex_exit(&igb->rx_rings[i].rx_lock); 1112 1113 mutex_exit(&igb->gen_lock); 1114 1115 return (IGB_SUCCESS); 1116 } 1117 1118 /* 1119 * igb_init_mac_address - Initialize the default MAC address 1120 * 1121 * On success, the MAC address is entered in the igb->hw.mac.addr 1122 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1123 * address register. 1124 * 1125 * Important side effects: 1126 * 1. adapter is reset - this is required to put it in a known state. 1127 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1128 * MAC address and all default settings are stored, so a valid checksum 1129 * is required. 1130 */ 1131 static int 1132 igb_init_mac_address(igb_t *igb) 1133 { 1134 struct e1000_hw *hw = &igb->hw; 1135 1136 ASSERT(mutex_owned(&igb->gen_lock)); 1137 1138 /* 1139 * Reset chipset to put the hardware in a known state 1140 * before we try to get MAC address from NVM. 1141 */ 1142 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1143 igb_error(igb, "Adapter reset failed."); 1144 goto init_mac_fail; 1145 } 1146 1147 /* 1148 * NVM validation 1149 */ 1150 if (e1000_validate_nvm_checksum(hw) < 0) { 1151 /* 1152 * Some PCI-E parts fail the first check due to 1153 * the link being in sleep state. Call it again, 1154 * if it fails a second time its a real issue. 1155 */ 1156 if (e1000_validate_nvm_checksum(hw) < 0) { 1157 igb_error(igb, 1158 "Invalid NVM checksum. Please contact " 1159 "the vendor to update the NVM."); 1160 goto init_mac_fail; 1161 } 1162 } 1163 1164 /* 1165 * Get the mac address 1166 * This function should handle SPARC case correctly. 1167 */ 1168 if (!igb_find_mac_address(igb)) { 1169 igb_error(igb, "Failed to get the mac address"); 1170 goto init_mac_fail; 1171 } 1172 1173 /* Validate mac address */ 1174 if (!is_valid_mac_addr(hw->mac.addr)) { 1175 igb_error(igb, "Invalid mac address"); 1176 goto init_mac_fail; 1177 } 1178 1179 return (IGB_SUCCESS); 1180 1181 init_mac_fail: 1182 return (IGB_FAILURE); 1183 } 1184 1185 /* 1186 * igb_init_adapter - Initialize the adapter 1187 */ 1188 static int 1189 igb_init_adapter(igb_t *igb) 1190 { 1191 struct e1000_hw *hw = &igb->hw; 1192 uint32_t pba; 1193 uint32_t high_water; 1194 int i; 1195 1196 ASSERT(mutex_owned(&igb->gen_lock)); 1197 1198 /* 1199 * In order to obtain the default MAC address, this will reset the 1200 * adapter and validate the NVM that the address and many other 1201 * default settings come from. 1202 */ 1203 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1204 igb_error(igb, "Failed to initialize MAC address"); 1205 goto init_adapter_fail; 1206 } 1207 1208 /* 1209 * Setup flow control 1210 * 1211 * These parameters set thresholds for the adapter's generation(Tx) 1212 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1213 * settings. Flow control is enabled or disabled in the configuration 1214 * file. 1215 * High-water mark is set down from the top of the rx fifo (not 1216 * sensitive to max_frame_size) and low-water is set just below 1217 * high-water mark. 1218 * The high water mark must be low enough to fit one full frame above 1219 * it in the rx FIFO. Should be the lower of: 1220 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1221 * frame. 1222 */ 1223 /* 1224 * The default setting of PBA is correct for 82575 and other supported 1225 * adapters do not have the E1000_PBA register, so PBA value is only 1226 * used for calculation here and is never written to the adapter. 1227 */ 1228 if (hw->mac.type == e1000_82575) { 1229 pba = E1000_PBA_34K; 1230 } else { 1231 pba = E1000_PBA_64K; 1232 } 1233 1234 high_water = min(((pba << 10) * 9 / 10), 1235 ((pba << 10) - igb->max_frame_size)); 1236 1237 if (hw->mac.type == e1000_82575) { 1238 /* 8-byte granularity */ 1239 hw->fc.high_water = high_water & 0xFFF8; 1240 hw->fc.low_water = hw->fc.high_water - 8; 1241 } else { 1242 /* 16-byte granularity */ 1243 hw->fc.high_water = high_water & 0xFFF0; 1244 hw->fc.low_water = hw->fc.high_water - 16; 1245 } 1246 1247 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1248 hw->fc.send_xon = B_TRUE; 1249 1250 e1000_validate_mdi_setting(hw); 1251 1252 /* 1253 * Reset the chipset hardware the second time to put PBA settings 1254 * into effect. 1255 */ 1256 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1257 igb_error(igb, "Second reset failed"); 1258 goto init_adapter_fail; 1259 } 1260 1261 /* 1262 * Don't wait for auto-negotiation to complete 1263 */ 1264 hw->phy.autoneg_wait_to_complete = B_FALSE; 1265 1266 /* 1267 * Copper options 1268 */ 1269 if (hw->phy.media_type == e1000_media_type_copper) { 1270 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1271 hw->phy.disable_polarity_correction = B_FALSE; 1272 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1273 } 1274 1275 /* 1276 * Initialize link settings 1277 */ 1278 (void) igb_setup_link(igb, B_FALSE); 1279 1280 /* 1281 * Configure/Initialize hardware 1282 */ 1283 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1284 igb_error(igb, "Failed to initialize hardware"); 1285 goto init_adapter_fail; 1286 } 1287 1288 /* 1289 * Disable wakeup control by default 1290 */ 1291 E1000_WRITE_REG(hw, E1000_WUC, 0); 1292 1293 /* 1294 * Record phy info in hw struct 1295 */ 1296 (void) e1000_get_phy_info(hw); 1297 1298 /* 1299 * Make sure driver has control 1300 */ 1301 igb_get_driver_control(hw); 1302 1303 /* 1304 * Restore LED settings to the default from EEPROM 1305 * to meet the standard for Sun platforms. 1306 */ 1307 (void) e1000_cleanup_led(hw); 1308 1309 /* 1310 * Setup MSI-X interrupts 1311 */ 1312 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1313 igb->capab->setup_msix(igb); 1314 1315 /* 1316 * Initialize unicast addresses. 1317 */ 1318 igb_init_unicst(igb); 1319 1320 /* 1321 * Setup and initialize the mctable structures. 1322 */ 1323 igb_setup_multicst(igb); 1324 1325 /* 1326 * Set interrupt throttling rate 1327 */ 1328 for (i = 0; i < igb->intr_cnt; i++) 1329 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1330 1331 /* 1332 * Save the state of the phy 1333 */ 1334 igb_get_phy_state(igb); 1335 1336 return (IGB_SUCCESS); 1337 1338 init_adapter_fail: 1339 /* 1340 * Reset PHY if possible 1341 */ 1342 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1343 (void) e1000_phy_hw_reset(hw); 1344 1345 return (IGB_FAILURE); 1346 } 1347 1348 /* 1349 * igb_stop_adapter - Stop the adapter 1350 */ 1351 static void 1352 igb_stop_adapter(igb_t *igb) 1353 { 1354 struct e1000_hw *hw = &igb->hw; 1355 1356 ASSERT(mutex_owned(&igb->gen_lock)); 1357 1358 /* Tell firmware driver is no longer in control */ 1359 igb_release_driver_control(hw); 1360 1361 /* 1362 * Reset the chipset 1363 */ 1364 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1365 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1366 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1367 } 1368 1369 /* 1370 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1371 */ 1372 } 1373 1374 /* 1375 * igb_reset - Reset the chipset and restart the driver. 1376 * 1377 * It involves stopping and re-starting the chipset, 1378 * and re-configuring the rx/tx rings. 1379 */ 1380 static int 1381 igb_reset(igb_t *igb) 1382 { 1383 int i; 1384 1385 mutex_enter(&igb->gen_lock); 1386 1387 ASSERT(igb->igb_state & IGB_STARTED); 1388 1389 /* 1390 * Disable the adapter interrupts to stop any rx/tx activities 1391 * before draining pending data and resetting hardware. 1392 */ 1393 igb_disable_adapter_interrupts(igb); 1394 1395 /* 1396 * Drain the pending transmit packets 1397 */ 1398 (void) igb_tx_drain(igb); 1399 1400 for (i = 0; i < igb->num_rx_rings; i++) 1401 mutex_enter(&igb->rx_rings[i].rx_lock); 1402 for (i = 0; i < igb->num_tx_rings; i++) 1403 mutex_enter(&igb->tx_rings[i].tx_lock); 1404 1405 /* 1406 * Stop the adapter 1407 */ 1408 igb_stop_adapter(igb); 1409 1410 /* 1411 * Clean the pending tx data/resources 1412 */ 1413 igb_tx_clean(igb); 1414 1415 /* 1416 * Start the adapter 1417 */ 1418 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1419 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1420 goto reset_failure; 1421 } 1422 1423 /* 1424 * Setup the rx/tx rings 1425 */ 1426 igb_setup_rings(igb); 1427 1428 /* 1429 * Enable adapter interrupts 1430 * The interrupts must be enabled after the driver state is START 1431 */ 1432 igb->capab->enable_intr(igb); 1433 1434 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1435 goto reset_failure; 1436 1437 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1438 goto reset_failure; 1439 1440 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1441 mutex_exit(&igb->tx_rings[i].tx_lock); 1442 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1443 mutex_exit(&igb->rx_rings[i].rx_lock); 1444 1445 mutex_exit(&igb->gen_lock); 1446 1447 return (IGB_SUCCESS); 1448 1449 reset_failure: 1450 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1451 mutex_exit(&igb->tx_rings[i].tx_lock); 1452 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1453 mutex_exit(&igb->rx_rings[i].rx_lock); 1454 1455 mutex_exit(&igb->gen_lock); 1456 1457 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1458 1459 return (IGB_FAILURE); 1460 } 1461 1462 /* 1463 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1464 */ 1465 static void 1466 igb_tx_clean(igb_t *igb) 1467 { 1468 igb_tx_ring_t *tx_ring; 1469 tx_control_block_t *tcb; 1470 link_list_t pending_list; 1471 uint32_t desc_num; 1472 int i, j; 1473 1474 LINK_LIST_INIT(&pending_list); 1475 1476 for (i = 0; i < igb->num_tx_rings; i++) { 1477 tx_ring = &igb->tx_rings[i]; 1478 1479 mutex_enter(&tx_ring->recycle_lock); 1480 1481 /* 1482 * Clean the pending tx data - the pending packets in the 1483 * work_list that have no chances to be transmitted again. 1484 * 1485 * We must ensure the chipset is stopped or the link is down 1486 * before cleaning the transmit packets. 1487 */ 1488 desc_num = 0; 1489 for (j = 0; j < tx_ring->ring_size; j++) { 1490 tcb = tx_ring->work_list[j]; 1491 if (tcb != NULL) { 1492 desc_num += tcb->desc_num; 1493 1494 tx_ring->work_list[j] = NULL; 1495 1496 igb_free_tcb(tcb); 1497 1498 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1499 } 1500 } 1501 1502 if (desc_num > 0) { 1503 atomic_add_32(&tx_ring->tbd_free, desc_num); 1504 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1505 1506 /* 1507 * Reset the head and tail pointers of the tbd ring; 1508 * Reset the head write-back if it is enabled. 1509 */ 1510 tx_ring->tbd_head = 0; 1511 tx_ring->tbd_tail = 0; 1512 if (igb->tx_head_wb_enable) 1513 *tx_ring->tbd_head_wb = 0; 1514 1515 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1516 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1517 } 1518 1519 mutex_exit(&tx_ring->recycle_lock); 1520 1521 /* 1522 * Add the tx control blocks in the pending list to 1523 * the free list. 1524 */ 1525 igb_put_free_list(tx_ring, &pending_list); 1526 } 1527 } 1528 1529 /* 1530 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1531 */ 1532 static boolean_t 1533 igb_tx_drain(igb_t *igb) 1534 { 1535 igb_tx_ring_t *tx_ring; 1536 boolean_t done; 1537 int i, j; 1538 1539 /* 1540 * Wait for a specific time to allow pending tx packets 1541 * to be transmitted. 1542 * 1543 * Check the counter tbd_free to see if transmission is done. 1544 * No lock protection is needed here. 1545 * 1546 * Return B_TRUE if all pending packets have been transmitted; 1547 * Otherwise return B_FALSE; 1548 */ 1549 for (i = 0; i < TX_DRAIN_TIME; i++) { 1550 1551 done = B_TRUE; 1552 for (j = 0; j < igb->num_tx_rings; j++) { 1553 tx_ring = &igb->tx_rings[j]; 1554 done = done && 1555 (tx_ring->tbd_free == tx_ring->ring_size); 1556 } 1557 1558 if (done) 1559 break; 1560 1561 msec_delay(1); 1562 } 1563 1564 return (done); 1565 } 1566 1567 /* 1568 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1569 */ 1570 static boolean_t 1571 igb_rx_drain(igb_t *igb) 1572 { 1573 igb_rx_ring_t *rx_ring; 1574 boolean_t done; 1575 int i, j; 1576 1577 /* 1578 * Polling the rx free list to check if those rx buffers held by 1579 * the upper layer are released. 1580 * 1581 * Check the counter rcb_free to see if all pending buffers are 1582 * released. No lock protection is needed here. 1583 * 1584 * Return B_TRUE if all pending buffers have been released; 1585 * Otherwise return B_FALSE; 1586 */ 1587 for (i = 0; i < RX_DRAIN_TIME; i++) { 1588 1589 done = B_TRUE; 1590 for (j = 0; j < igb->num_rx_rings; j++) { 1591 rx_ring = &igb->rx_rings[j]; 1592 done = done && 1593 (rx_ring->rcb_free == rx_ring->free_list_size); 1594 } 1595 1596 if (done) 1597 break; 1598 1599 msec_delay(1); 1600 } 1601 1602 return (done); 1603 } 1604 1605 /* 1606 * igb_start - Start the driver/chipset 1607 */ 1608 int 1609 igb_start(igb_t *igb) 1610 { 1611 int i; 1612 1613 ASSERT(mutex_owned(&igb->gen_lock)); 1614 1615 for (i = 0; i < igb->num_rx_rings; i++) 1616 mutex_enter(&igb->rx_rings[i].rx_lock); 1617 for (i = 0; i < igb->num_tx_rings; i++) 1618 mutex_enter(&igb->tx_rings[i].tx_lock); 1619 1620 /* 1621 * Start the adapter 1622 */ 1623 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1624 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1625 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1626 goto start_failure; 1627 } 1628 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1629 1630 /* 1631 * Setup the rx/tx rings 1632 */ 1633 igb_setup_rings(igb); 1634 } 1635 1636 /* 1637 * Enable adapter interrupts 1638 * The interrupts must be enabled after the driver state is START 1639 */ 1640 igb->capab->enable_intr(igb); 1641 1642 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1643 goto start_failure; 1644 1645 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1646 goto start_failure; 1647 1648 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1649 mutex_exit(&igb->tx_rings[i].tx_lock); 1650 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1651 mutex_exit(&igb->rx_rings[i].rx_lock); 1652 1653 return (IGB_SUCCESS); 1654 1655 start_failure: 1656 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1657 mutex_exit(&igb->tx_rings[i].tx_lock); 1658 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1659 mutex_exit(&igb->rx_rings[i].rx_lock); 1660 1661 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1662 1663 return (IGB_FAILURE); 1664 } 1665 1666 /* 1667 * igb_stop - Stop the driver/chipset 1668 */ 1669 void 1670 igb_stop(igb_t *igb) 1671 { 1672 int i; 1673 1674 ASSERT(mutex_owned(&igb->gen_lock)); 1675 1676 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1677 1678 /* 1679 * Disable the adapter interrupts 1680 */ 1681 igb_disable_adapter_interrupts(igb); 1682 1683 /* 1684 * Drain the pending tx packets 1685 */ 1686 (void) igb_tx_drain(igb); 1687 1688 for (i = 0; i < igb->num_rx_rings; i++) 1689 mutex_enter(&igb->rx_rings[i].rx_lock); 1690 for (i = 0; i < igb->num_tx_rings; i++) 1691 mutex_enter(&igb->tx_rings[i].tx_lock); 1692 1693 /* 1694 * Stop the adapter 1695 */ 1696 igb_stop_adapter(igb); 1697 1698 /* 1699 * Clean the pending tx data/resources 1700 */ 1701 igb_tx_clean(igb); 1702 1703 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1704 mutex_exit(&igb->tx_rings[i].tx_lock); 1705 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1706 mutex_exit(&igb->rx_rings[i].rx_lock); 1707 1708 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1709 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1710 } 1711 1712 /* 1713 * igb_alloc_rings - Allocate memory space for rx/tx rings 1714 */ 1715 static int 1716 igb_alloc_rings(igb_t *igb) 1717 { 1718 /* 1719 * Allocate memory space for rx rings 1720 */ 1721 igb->rx_rings = kmem_zalloc( 1722 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1723 KM_NOSLEEP); 1724 1725 if (igb->rx_rings == NULL) { 1726 return (IGB_FAILURE); 1727 } 1728 1729 /* 1730 * Allocate memory space for tx rings 1731 */ 1732 igb->tx_rings = kmem_zalloc( 1733 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1734 KM_NOSLEEP); 1735 1736 if (igb->tx_rings == NULL) { 1737 kmem_free(igb->rx_rings, 1738 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1739 igb->rx_rings = NULL; 1740 return (IGB_FAILURE); 1741 } 1742 1743 /* 1744 * Allocate memory space for rx ring groups 1745 */ 1746 igb->rx_groups = kmem_zalloc( 1747 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1748 KM_NOSLEEP); 1749 1750 if (igb->rx_groups == NULL) { 1751 kmem_free(igb->rx_rings, 1752 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1753 kmem_free(igb->tx_rings, 1754 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1755 igb->rx_rings = NULL; 1756 igb->tx_rings = NULL; 1757 return (IGB_FAILURE); 1758 } 1759 1760 return (IGB_SUCCESS); 1761 } 1762 1763 /* 1764 * igb_free_rings - Free the memory space of rx/tx rings. 1765 */ 1766 static void 1767 igb_free_rings(igb_t *igb) 1768 { 1769 if (igb->rx_rings != NULL) { 1770 kmem_free(igb->rx_rings, 1771 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1772 igb->rx_rings = NULL; 1773 } 1774 1775 if (igb->tx_rings != NULL) { 1776 kmem_free(igb->tx_rings, 1777 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1778 igb->tx_rings = NULL; 1779 } 1780 1781 if (igb->rx_groups != NULL) { 1782 kmem_free(igb->rx_groups, 1783 sizeof (igb_rx_group_t) * igb->num_rx_groups); 1784 igb->rx_groups = NULL; 1785 } 1786 } 1787 1788 /* 1789 * igb_setup_rings - Setup rx/tx rings 1790 */ 1791 static void 1792 igb_setup_rings(igb_t *igb) 1793 { 1794 /* 1795 * Setup the rx/tx rings, including the following: 1796 * 1797 * 1. Setup the descriptor ring and the control block buffers; 1798 * 2. Initialize necessary registers for receive/transmit; 1799 * 3. Initialize software pointers/parameters for receive/transmit; 1800 */ 1801 igb_setup_rx(igb); 1802 1803 igb_setup_tx(igb); 1804 1805 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1806 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1807 } 1808 1809 static void 1810 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1811 { 1812 igb_t *igb = rx_ring->igb; 1813 struct e1000_hw *hw = &igb->hw; 1814 rx_control_block_t *rcb; 1815 union e1000_adv_rx_desc *rbd; 1816 uint32_t size; 1817 uint32_t buf_low; 1818 uint32_t buf_high; 1819 uint32_t rxdctl; 1820 int i; 1821 1822 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1823 ASSERT(mutex_owned(&igb->gen_lock)); 1824 1825 /* 1826 * Initialize descriptor ring with buffer addresses 1827 */ 1828 for (i = 0; i < igb->rx_ring_size; i++) { 1829 rcb = rx_ring->work_list[i]; 1830 rbd = &rx_ring->rbd_ring[i]; 1831 1832 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1833 rbd->read.hdr_addr = NULL; 1834 } 1835 1836 /* 1837 * Initialize the base address registers 1838 */ 1839 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1840 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1841 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1842 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1843 1844 /* 1845 * Initialize the length register 1846 */ 1847 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1848 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1849 1850 /* 1851 * Initialize buffer size & descriptor type 1852 */ 1853 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 1854 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1855 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 1856 1857 /* 1858 * Setup the Receive Descriptor Control Register (RXDCTL) 1859 */ 1860 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1861 rxdctl &= igb->capab->rxdctl_mask; 1862 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 1863 rxdctl |= 16; /* pthresh */ 1864 rxdctl |= 8 << 8; /* hthresh */ 1865 rxdctl |= 1 << 16; /* wthresh */ 1866 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 1867 1868 rx_ring->rbd_next = 0; 1869 1870 /* 1871 * Note: Considering the case that the chipset is being reset 1872 * and there are still some buffers held by the upper layer, 1873 * we should not reset the values of rcb_head, rcb_tail and 1874 * rcb_free; 1875 */ 1876 if (igb->igb_state == IGB_UNKNOWN) { 1877 rx_ring->rcb_head = 0; 1878 rx_ring->rcb_tail = 0; 1879 rx_ring->rcb_free = rx_ring->free_list_size; 1880 } 1881 } 1882 1883 static void 1884 igb_setup_rx(igb_t *igb) 1885 { 1886 igb_rx_ring_t *rx_ring; 1887 igb_rx_group_t *rx_group; 1888 struct e1000_hw *hw = &igb->hw; 1889 uint32_t rctl, rxcsum; 1890 uint32_t ring_per_group; 1891 int i; 1892 1893 /* 1894 * Setup the Receive Control Register (RCTL), and enable the 1895 * receiver. The initial configuration is to: enable the receiver, 1896 * accept broadcasts, discard bad packets, accept long packets, 1897 * disable VLAN filter checking, and set receive buffer size to 1898 * 2k. For 82575, also set the receive descriptor minimum 1899 * threshold size to 1/2 the ring. 1900 */ 1901 rctl = E1000_READ_REG(hw, E1000_RCTL); 1902 1903 /* 1904 * Clear the field used for wakeup control. This driver doesn't do 1905 * wakeup but leave this here for completeness. 1906 */ 1907 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 1908 1909 switch (hw->mac.type) { 1910 case e1000_82575: 1911 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1912 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1913 E1000_RCTL_LPE | /* Large Packet Enable */ 1914 /* Multicast filter offset */ 1915 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1916 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 1917 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1918 break; 1919 1920 case e1000_82576: 1921 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1922 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1923 E1000_RCTL_LPE | /* Large Packet Enable */ 1924 /* Multicast filter offset */ 1925 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1926 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1927 break; 1928 1929 default: 1930 igb_log(igb, "unsupported MAC type: %d", hw->mac.type); 1931 return; /* should never come here; this will cause rx failure */ 1932 } 1933 1934 for (i = 0; i < igb->num_rx_groups; i++) { 1935 rx_group = &igb->rx_groups[i]; 1936 rx_group->index = i; 1937 rx_group->igb = igb; 1938 } 1939 1940 /* 1941 * Set up all rx descriptor rings - must be called before receive unit 1942 * enabled. 1943 */ 1944 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 1945 for (i = 0; i < igb->num_rx_rings; i++) { 1946 rx_ring = &igb->rx_rings[i]; 1947 igb_setup_rx_ring(rx_ring); 1948 1949 /* 1950 * Map a ring to a group by assigning a group index 1951 */ 1952 rx_ring->group_index = i / ring_per_group; 1953 } 1954 1955 /* 1956 * Setup the Rx Long Packet Max Length register 1957 */ 1958 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1959 1960 /* 1961 * Hardware checksum settings 1962 */ 1963 if (igb->rx_hcksum_enable) { 1964 rxcsum = 1965 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1966 E1000_RXCSUM_IPOFL; /* IP checksum */ 1967 1968 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1969 } 1970 1971 /* 1972 * Setup classify and RSS for multiple receive queues 1973 */ 1974 switch (igb->vmdq_mode) { 1975 case E1000_VMDQ_OFF: 1976 /* 1977 * One ring group, only RSS is needed when more than 1978 * one ring enabled. 1979 */ 1980 if (igb->num_rx_rings > 1) 1981 igb_setup_rss(igb); 1982 break; 1983 case E1000_VMDQ_MAC: 1984 /* 1985 * Multiple groups, each group has one ring, 1986 * only the MAC classification is needed. 1987 */ 1988 igb_setup_mac_classify(igb); 1989 break; 1990 case E1000_VMDQ_MAC_RSS: 1991 /* 1992 * Multiple groups and multiple rings, both 1993 * MAC classification and RSS are needed. 1994 */ 1995 igb_setup_mac_rss_classify(igb); 1996 break; 1997 } 1998 1999 /* 2000 * Enable the receive unit - must be done after all 2001 * the rx setup above. 2002 */ 2003 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2004 2005 /* 2006 * Initialize all adapter ring head & tail pointers - must 2007 * be done after receive unit is enabled 2008 */ 2009 for (i = 0; i < igb->num_rx_rings; i++) { 2010 rx_ring = &igb->rx_rings[i]; 2011 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2012 E1000_WRITE_REG(hw, E1000_RDT(i), rx_ring->ring_size - 1); 2013 } 2014 2015 /* 2016 * 82575 with manageability enabled needs a special flush to make 2017 * sure the fifos start clean. 2018 */ 2019 if ((hw->mac.type == e1000_82575) && 2020 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2021 e1000_rx_fifo_flush_82575(hw); 2022 } 2023 } 2024 2025 static void 2026 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2027 { 2028 igb_t *igb = tx_ring->igb; 2029 struct e1000_hw *hw = &igb->hw; 2030 uint32_t size; 2031 uint32_t buf_low; 2032 uint32_t buf_high; 2033 uint32_t reg_val; 2034 2035 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2036 ASSERT(mutex_owned(&igb->gen_lock)); 2037 2038 2039 /* 2040 * Initialize the length register 2041 */ 2042 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2043 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2044 2045 /* 2046 * Initialize the base address registers 2047 */ 2048 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2049 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2050 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2051 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2052 2053 /* 2054 * Setup head & tail pointers 2055 */ 2056 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2057 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2058 2059 /* 2060 * Setup head write-back 2061 */ 2062 if (igb->tx_head_wb_enable) { 2063 /* 2064 * The memory of the head write-back is allocated using 2065 * the extra tbd beyond the tail of the tbd ring. 2066 */ 2067 tx_ring->tbd_head_wb = (uint32_t *) 2068 ((uintptr_t)tx_ring->tbd_area.address + size); 2069 *tx_ring->tbd_head_wb = 0; 2070 2071 buf_low = (uint32_t) 2072 (tx_ring->tbd_area.dma_address + size); 2073 buf_high = (uint32_t) 2074 ((tx_ring->tbd_area.dma_address + size) >> 32); 2075 2076 /* Set the head write-back enable bit */ 2077 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2078 2079 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2080 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2081 2082 /* 2083 * Turn off relaxed ordering for head write back or it will 2084 * cause problems with the tx recycling 2085 */ 2086 reg_val = E1000_READ_REG(hw, 2087 E1000_DCA_TXCTRL(tx_ring->index)); 2088 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2089 E1000_WRITE_REG(hw, 2090 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2091 } else { 2092 tx_ring->tbd_head_wb = NULL; 2093 } 2094 2095 tx_ring->tbd_head = 0; 2096 tx_ring->tbd_tail = 0; 2097 tx_ring->tbd_free = tx_ring->ring_size; 2098 2099 /* 2100 * Note: for the case that the chipset is being reset, we should not 2101 * reset the values of tcb_head, tcb_tail. And considering there might 2102 * still be some packets kept in the pending_list, we should not assert 2103 * (tcb_free == free_list_size) here. 2104 */ 2105 if (igb->igb_state == IGB_UNKNOWN) { 2106 tx_ring->tcb_head = 0; 2107 tx_ring->tcb_tail = 0; 2108 tx_ring->tcb_free = tx_ring->free_list_size; 2109 } 2110 2111 /* 2112 * Initialize hardware checksum offload settings 2113 */ 2114 tx_ring->hcksum_context.hcksum_flags = 0; 2115 tx_ring->hcksum_context.ip_hdr_len = 0; 2116 tx_ring->hcksum_context.mac_hdr_len = 0; 2117 tx_ring->hcksum_context.l4_proto = 0; 2118 2119 /* 2120 * Enable TXDCTL per queue 2121 */ 2122 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2123 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2124 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2125 } 2126 2127 static void 2128 igb_setup_tx(igb_t *igb) 2129 { 2130 igb_tx_ring_t *tx_ring; 2131 struct e1000_hw *hw = &igb->hw; 2132 uint32_t reg_val; 2133 int i; 2134 2135 for (i = 0; i < igb->num_tx_rings; i++) { 2136 tx_ring = &igb->tx_rings[i]; 2137 igb_setup_tx_ring(tx_ring); 2138 } 2139 2140 /* 2141 * Setup the Transmit Control Register (TCTL) 2142 */ 2143 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2144 reg_val &= ~E1000_TCTL_CT; 2145 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2146 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2147 2148 /* Enable transmits */ 2149 reg_val |= E1000_TCTL_EN; 2150 2151 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2152 } 2153 2154 /* 2155 * igb_setup_rss - Setup receive-side scaling feature 2156 */ 2157 static void 2158 igb_setup_rss(igb_t *igb) 2159 { 2160 struct e1000_hw *hw = &igb->hw; 2161 uint32_t i, mrqc, rxcsum; 2162 int shift = 0; 2163 uint32_t random; 2164 union e1000_reta { 2165 uint32_t dword; 2166 uint8_t bytes[4]; 2167 } reta; 2168 2169 /* Setup the Redirection Table */ 2170 if (hw->mac.type == e1000_82576) { 2171 shift = 0; 2172 } else if (hw->mac.type == e1000_82575) { 2173 shift = 6; 2174 } 2175 for (i = 0; i < (32 * 4); i++) { 2176 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2177 if ((i & 3) == 3) { 2178 E1000_WRITE_REG(hw, 2179 (E1000_RETA(0) + (i & ~3)), reta.dword); 2180 } 2181 } 2182 2183 /* Fill out hash function seeds */ 2184 for (i = 0; i < 10; i++) { 2185 (void) random_get_pseudo_bytes((uint8_t *)&random, 2186 sizeof (uint32_t)); 2187 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2188 } 2189 2190 /* Setup the Multiple Receive Queue Control register */ 2191 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2192 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2193 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2194 E1000_MRQC_RSS_FIELD_IPV6 | 2195 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2196 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2197 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2198 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2199 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2200 2201 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2202 2203 /* 2204 * Disable Packet Checksum to enable RSS for multiple receive queues. 2205 * 2206 * The Packet Checksum is not ethernet CRC. It is another kind of 2207 * checksum offloading provided by the 82575 chipset besides the IP 2208 * header checksum offloading and the TCP/UDP checksum offloading. 2209 * The Packet Checksum is by default computed over the entire packet 2210 * from the first byte of the DA through the last byte of the CRC, 2211 * including the Ethernet and IP headers. 2212 * 2213 * It is a hardware limitation that Packet Checksum is mutually 2214 * exclusive with RSS. 2215 */ 2216 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2217 rxcsum |= E1000_RXCSUM_PCSD; 2218 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2219 } 2220 2221 /* 2222 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2223 */ 2224 static void 2225 igb_setup_mac_rss_classify(igb_t *igb) 2226 { 2227 struct e1000_hw *hw = &igb->hw; 2228 uint32_t i, mrqc, vmdctl, rxcsum; 2229 uint32_t ring_per_group; 2230 int shift_group0, shift_group1; 2231 uint32_t random; 2232 union e1000_reta { 2233 uint32_t dword; 2234 uint8_t bytes[4]; 2235 } reta; 2236 2237 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2238 2239 /* Setup the Redirection Table, it is shared between two groups */ 2240 shift_group0 = 2; 2241 shift_group1 = 6; 2242 for (i = 0; i < (32 * 4); i++) { 2243 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2244 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2245 if ((i & 3) == 3) { 2246 E1000_WRITE_REG(hw, 2247 (E1000_RETA(0) + (i & ~3)), reta.dword); 2248 } 2249 } 2250 2251 /* Fill out hash function seeds */ 2252 for (i = 0; i < 10; i++) { 2253 (void) random_get_pseudo_bytes((uint8_t *)&random, 2254 sizeof (uint32_t)); 2255 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2256 } 2257 2258 /* 2259 * Setup the Multiple Receive Queue Control register, 2260 * enable VMDq based on packet destination MAC address and RSS. 2261 */ 2262 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2263 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2264 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2265 E1000_MRQC_RSS_FIELD_IPV6 | 2266 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2267 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2268 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2269 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2270 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2271 2272 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2273 2274 2275 /* Define the default group and default queues */ 2276 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2277 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2278 2279 /* 2280 * Disable Packet Checksum to enable RSS for multiple receive queues. 2281 * 2282 * The Packet Checksum is not ethernet CRC. It is another kind of 2283 * checksum offloading provided by the 82575 chipset besides the IP 2284 * header checksum offloading and the TCP/UDP checksum offloading. 2285 * The Packet Checksum is by default computed over the entire packet 2286 * from the first byte of the DA through the last byte of the CRC, 2287 * including the Ethernet and IP headers. 2288 * 2289 * It is a hardware limitation that Packet Checksum is mutually 2290 * exclusive with RSS. 2291 */ 2292 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2293 rxcsum |= E1000_RXCSUM_PCSD; 2294 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2295 } 2296 2297 /* 2298 * igb_setup_mac_classify - Setup MAC classification feature 2299 */ 2300 static void 2301 igb_setup_mac_classify(igb_t *igb) 2302 { 2303 struct e1000_hw *hw = &igb->hw; 2304 uint32_t mrqc, rxcsum; 2305 2306 /* 2307 * Setup the Multiple Receive Queue Control register, 2308 * enable VMDq based on packet destination MAC address. 2309 */ 2310 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2311 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2312 2313 /* 2314 * Disable Packet Checksum to enable RSS for multiple receive queues. 2315 * 2316 * The Packet Checksum is not ethernet CRC. It is another kind of 2317 * checksum offloading provided by the 82575 chipset besides the IP 2318 * header checksum offloading and the TCP/UDP checksum offloading. 2319 * The Packet Checksum is by default computed over the entire packet 2320 * from the first byte of the DA through the last byte of the CRC, 2321 * including the Ethernet and IP headers. 2322 * 2323 * It is a hardware limitation that Packet Checksum is mutually 2324 * exclusive with RSS. 2325 */ 2326 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2327 rxcsum |= E1000_RXCSUM_PCSD; 2328 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2329 2330 } 2331 2332 /* 2333 * igb_init_unicst - Initialize the unicast addresses 2334 */ 2335 static void 2336 igb_init_unicst(igb_t *igb) 2337 { 2338 struct e1000_hw *hw = &igb->hw; 2339 int slot; 2340 2341 /* 2342 * Here we should consider two situations: 2343 * 2344 * 1. Chipset is initialized the first time 2345 * Initialize the multiple unicast addresses, and 2346 * save the default MAC address. 2347 * 2348 * 2. Chipset is reset 2349 * Recover the multiple unicast addresses from the 2350 * software data structure to the RAR registers. 2351 */ 2352 2353 /* 2354 * Clear the default MAC address in the RAR0 rgister, 2355 * which is loaded from EEPROM when system boot or chipreset, 2356 * this will cause the conficts with add_mac/rem_mac entry 2357 * points when VMDq is enabled. For this reason, the RAR0 2358 * must be cleared for both cases mentioned above. 2359 */ 2360 e1000_rar_clear(hw, 0); 2361 2362 if (!igb->unicst_init) { 2363 2364 /* Initialize the multiple unicast addresses */ 2365 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2366 igb->unicst_avail = igb->unicst_total; 2367 2368 for (slot = 0; slot < igb->unicst_total; slot++) 2369 igb->unicst_addr[slot].mac.set = 0; 2370 2371 igb->unicst_init = B_TRUE; 2372 } else { 2373 /* Re-configure the RAR registers */ 2374 for (slot = 0; slot < igb->unicst_total; slot++) { 2375 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2376 slot, igb->vmdq_mode, 2377 igb->unicst_addr[slot].mac.group_index); 2378 } 2379 } 2380 2381 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2382 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2383 } 2384 2385 /* 2386 * igb_unicst_find - Find the slot for the specified unicast address 2387 */ 2388 int 2389 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2390 { 2391 int slot; 2392 2393 ASSERT(mutex_owned(&igb->gen_lock)); 2394 2395 for (slot = 0; slot < igb->unicst_total; slot++) { 2396 if (bcmp(igb->unicst_addr[slot].mac.addr, 2397 mac_addr, ETHERADDRL) == 0) 2398 return (slot); 2399 } 2400 2401 return (-1); 2402 } 2403 2404 /* 2405 * igb_unicst_set - Set the unicast address to the specified slot 2406 */ 2407 int 2408 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2409 int slot) 2410 { 2411 struct e1000_hw *hw = &igb->hw; 2412 2413 ASSERT(mutex_owned(&igb->gen_lock)); 2414 2415 /* 2416 * Save the unicast address in the software data structure 2417 */ 2418 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2419 2420 /* 2421 * Set the unicast address to the RAR register 2422 */ 2423 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2424 2425 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2426 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2427 return (EIO); 2428 } 2429 2430 return (0); 2431 } 2432 2433 /* 2434 * igb_multicst_add - Add a multicst address 2435 */ 2436 int 2437 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2438 { 2439 ASSERT(mutex_owned(&igb->gen_lock)); 2440 2441 if ((multiaddr[0] & 01) == 0) { 2442 return (EINVAL); 2443 } 2444 2445 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2446 return (ENOENT); 2447 } 2448 2449 bcopy(multiaddr, 2450 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2451 igb->mcast_count++; 2452 2453 /* 2454 * Update the multicast table in the hardware 2455 */ 2456 igb_setup_multicst(igb); 2457 2458 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2459 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2460 return (EIO); 2461 } 2462 2463 return (0); 2464 } 2465 2466 /* 2467 * igb_multicst_remove - Remove a multicst address 2468 */ 2469 int 2470 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2471 { 2472 int i; 2473 2474 ASSERT(mutex_owned(&igb->gen_lock)); 2475 2476 for (i = 0; i < igb->mcast_count; i++) { 2477 if (bcmp(multiaddr, &igb->mcast_table[i], 2478 ETHERADDRL) == 0) { 2479 for (i++; i < igb->mcast_count; i++) { 2480 igb->mcast_table[i - 1] = 2481 igb->mcast_table[i]; 2482 } 2483 igb->mcast_count--; 2484 break; 2485 } 2486 } 2487 2488 /* 2489 * Update the multicast table in the hardware 2490 */ 2491 igb_setup_multicst(igb); 2492 2493 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2494 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2495 return (EIO); 2496 } 2497 2498 return (0); 2499 } 2500 2501 /* 2502 * igb_setup_multicast - setup multicast data structures 2503 * 2504 * This routine initializes all of the multicast related structures 2505 * and save them in the hardware registers. 2506 */ 2507 static void 2508 igb_setup_multicst(igb_t *igb) 2509 { 2510 uint8_t *mc_addr_list; 2511 uint32_t mc_addr_count; 2512 struct e1000_hw *hw = &igb->hw; 2513 2514 ASSERT(mutex_owned(&igb->gen_lock)); 2515 2516 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2517 2518 mc_addr_list = (uint8_t *)igb->mcast_table; 2519 mc_addr_count = igb->mcast_count; 2520 2521 /* 2522 * Update the multicase addresses to the MTA registers 2523 */ 2524 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2525 igb->unicst_total, hw->mac.rar_entry_count); 2526 } 2527 2528 /* 2529 * igb_get_conf - Get driver configurations set in driver.conf 2530 * 2531 * This routine gets user-configured values out of the configuration 2532 * file igb.conf. 2533 * 2534 * For each configurable value, there is a minimum, a maximum, and a 2535 * default. 2536 * If user does not configure a value, use the default. 2537 * If user configures below the minimum, use the minumum. 2538 * If user configures above the maximum, use the maxumum. 2539 */ 2540 static void 2541 igb_get_conf(igb_t *igb) 2542 { 2543 struct e1000_hw *hw = &igb->hw; 2544 uint32_t default_mtu; 2545 uint32_t flow_control; 2546 uint32_t ring_per_group; 2547 int i; 2548 2549 /* 2550 * igb driver supports the following user configurations: 2551 * 2552 * Link configurations: 2553 * adv_autoneg_cap 2554 * adv_1000fdx_cap 2555 * adv_100fdx_cap 2556 * adv_100hdx_cap 2557 * adv_10fdx_cap 2558 * adv_10hdx_cap 2559 * Note: 1000hdx is not supported. 2560 * 2561 * Jumbo frame configuration: 2562 * default_mtu 2563 * 2564 * Ethernet flow control configuration: 2565 * flow_control 2566 * 2567 * Multiple rings configurations: 2568 * tx_queue_number 2569 * tx_ring_size 2570 * rx_queue_number 2571 * rx_ring_size 2572 * 2573 * Call igb_get_prop() to get the value for a specific 2574 * configuration parameter. 2575 */ 2576 2577 /* 2578 * Link configurations 2579 */ 2580 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2581 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2582 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2583 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2584 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2585 PROP_ADV_100FDX_CAP, 0, 1, 1); 2586 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2587 PROP_ADV_100HDX_CAP, 0, 1, 1); 2588 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2589 PROP_ADV_10FDX_CAP, 0, 1, 1); 2590 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2591 PROP_ADV_10HDX_CAP, 0, 1, 1); 2592 2593 /* 2594 * Jumbo frame configurations 2595 */ 2596 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2597 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2598 2599 igb->max_frame_size = default_mtu + 2600 sizeof (struct ether_vlan_header) + ETHERFCSL; 2601 2602 /* 2603 * Ethernet flow control configuration 2604 */ 2605 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2606 e1000_fc_none, 4, e1000_fc_full); 2607 if (flow_control == 4) 2608 flow_control = e1000_fc_default; 2609 2610 hw->fc.requested_mode = flow_control; 2611 2612 /* 2613 * Multiple rings configurations 2614 */ 2615 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2616 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2617 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2618 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2619 2620 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 1); 2621 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2622 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2623 /* 2624 * Currently we do not support VMDq for 82576. 2625 * If it is e1000_82576, set num_rx_groups to 1. 2626 */ 2627 if (hw->mac.type == e1000_82576) 2628 igb->num_rx_groups = 1; 2629 2630 if (igb->mr_enable) { 2631 igb->num_tx_rings = igb->capab->def_tx_que_num; 2632 igb->num_rx_rings = igb->capab->def_rx_que_num; 2633 } else { 2634 igb->num_tx_rings = 1; 2635 igb->num_rx_rings = 1; 2636 2637 if (igb->num_rx_groups > 1) { 2638 igb_error(igb, 2639 "Invalid rx groups number. Please enable multiple " 2640 "rings first"); 2641 igb->num_rx_groups = 1; 2642 } 2643 } 2644 2645 /* 2646 * Check the divisibility between rx rings and rx groups. 2647 */ 2648 for (i = igb->num_rx_groups; i > 0; i--) { 2649 if ((igb->num_rx_rings % i) == 0) 2650 break; 2651 } 2652 if (i != igb->num_rx_groups) { 2653 igb_error(igb, 2654 "Invalid rx groups number. Downgrade the rx group " 2655 "number to %d.", i); 2656 igb->num_rx_groups = i; 2657 } 2658 2659 /* 2660 * Get the ring number per group. 2661 */ 2662 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2663 2664 if (igb->num_rx_groups == 1) { 2665 /* 2666 * One rx ring group, the rx ring number is num_rx_rings. 2667 */ 2668 igb->vmdq_mode = E1000_VMDQ_OFF; 2669 } else if (ring_per_group == 1) { 2670 /* 2671 * Multiple rx groups, each group has one rx ring. 2672 */ 2673 igb->vmdq_mode = E1000_VMDQ_MAC; 2674 } else { 2675 /* 2676 * Multiple groups and multiple rings. 2677 */ 2678 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2679 } 2680 2681 /* 2682 * Tunable used to force an interrupt type. The only use is 2683 * for testing of the lesser interrupt types. 2684 * 0 = don't force interrupt type 2685 * 1 = force interrupt type MSIX 2686 * 2 = force interrupt type MSI 2687 * 3 = force interrupt type Legacy 2688 */ 2689 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2690 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2691 2692 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2693 0, 1, 1); 2694 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2695 0, 1, 1); 2696 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2697 0, 1, 0); 2698 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2699 0, 1, 1); 2700 2701 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2702 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2703 DEFAULT_TX_COPY_THRESHOLD); 2704 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2705 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2706 DEFAULT_TX_RECYCLE_THRESHOLD); 2707 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2708 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2709 DEFAULT_TX_OVERLOAD_THRESHOLD); 2710 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2711 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2712 DEFAULT_TX_RESCHED_THRESHOLD); 2713 2714 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2715 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2716 DEFAULT_RX_COPY_THRESHOLD); 2717 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2718 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2719 DEFAULT_RX_LIMIT_PER_INTR); 2720 2721 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2722 igb->capab->min_intr_throttle, 2723 igb->capab->max_intr_throttle, 2724 igb->capab->def_intr_throttle); 2725 } 2726 2727 /* 2728 * igb_get_prop - Get a property value out of the configuration file igb.conf 2729 * 2730 * Caller provides the name of the property, a default value, a minimum 2731 * value, and a maximum value. 2732 * 2733 * Return configured value of the property, with default, minimum and 2734 * maximum properly applied. 2735 */ 2736 static int 2737 igb_get_prop(igb_t *igb, 2738 char *propname, /* name of the property */ 2739 int minval, /* minimum acceptable value */ 2740 int maxval, /* maximim acceptable value */ 2741 int defval) /* default value */ 2742 { 2743 int value; 2744 2745 /* 2746 * Call ddi_prop_get_int() to read the conf settings 2747 */ 2748 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2749 DDI_PROP_DONTPASS, propname, defval); 2750 2751 if (value > maxval) 2752 value = maxval; 2753 2754 if (value < minval) 2755 value = minval; 2756 2757 return (value); 2758 } 2759 2760 /* 2761 * igb_setup_link - Using the link properties to setup the link 2762 */ 2763 int 2764 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2765 { 2766 struct e1000_mac_info *mac; 2767 struct e1000_phy_info *phy; 2768 boolean_t invalid; 2769 2770 mac = &igb->hw.mac; 2771 phy = &igb->hw.phy; 2772 invalid = B_FALSE; 2773 2774 if (igb->param_adv_autoneg_cap == 1) { 2775 mac->autoneg = B_TRUE; 2776 phy->autoneg_advertised = 0; 2777 2778 /* 2779 * 1000hdx is not supported for autonegotiation 2780 */ 2781 if (igb->param_adv_1000fdx_cap == 1) 2782 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2783 2784 if (igb->param_adv_100fdx_cap == 1) 2785 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2786 2787 if (igb->param_adv_100hdx_cap == 1) 2788 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2789 2790 if (igb->param_adv_10fdx_cap == 1) 2791 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2792 2793 if (igb->param_adv_10hdx_cap == 1) 2794 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2795 2796 if (phy->autoneg_advertised == 0) 2797 invalid = B_TRUE; 2798 } else { 2799 mac->autoneg = B_FALSE; 2800 2801 /* 2802 * 1000fdx and 1000hdx are not supported for forced link 2803 */ 2804 if (igb->param_adv_100fdx_cap == 1) 2805 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2806 else if (igb->param_adv_100hdx_cap == 1) 2807 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2808 else if (igb->param_adv_10fdx_cap == 1) 2809 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2810 else if (igb->param_adv_10hdx_cap == 1) 2811 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2812 else 2813 invalid = B_TRUE; 2814 } 2815 2816 if (invalid) { 2817 igb_notice(igb, "Invalid link settings. Setup link to " 2818 "autonegotiation with full link capabilities."); 2819 mac->autoneg = B_TRUE; 2820 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2821 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2822 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2823 } 2824 2825 if (setup_hw) { 2826 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2827 return (IGB_FAILURE); 2828 } 2829 2830 return (IGB_SUCCESS); 2831 } 2832 2833 2834 /* 2835 * igb_is_link_up - Check if the link is up 2836 */ 2837 static boolean_t 2838 igb_is_link_up(igb_t *igb) 2839 { 2840 struct e1000_hw *hw = &igb->hw; 2841 boolean_t link_up = B_FALSE; 2842 2843 ASSERT(mutex_owned(&igb->gen_lock)); 2844 2845 /* 2846 * get_link_status is set in the interrupt handler on link-status-change 2847 * or rx sequence error interrupt. get_link_status will stay 2848 * false until the e1000_check_for_link establishes link only 2849 * for copper adapters. 2850 */ 2851 switch (hw->phy.media_type) { 2852 case e1000_media_type_copper: 2853 if (hw->mac.get_link_status) { 2854 (void) e1000_check_for_link(hw); 2855 link_up = !hw->mac.get_link_status; 2856 } else { 2857 link_up = B_TRUE; 2858 } 2859 break; 2860 case e1000_media_type_fiber: 2861 (void) e1000_check_for_link(hw); 2862 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2863 break; 2864 case e1000_media_type_internal_serdes: 2865 (void) e1000_check_for_link(hw); 2866 link_up = hw->mac.serdes_has_link; 2867 break; 2868 } 2869 2870 return (link_up); 2871 } 2872 2873 /* 2874 * igb_link_check - Link status processing 2875 */ 2876 static boolean_t 2877 igb_link_check(igb_t *igb) 2878 { 2879 struct e1000_hw *hw = &igb->hw; 2880 uint16_t speed = 0, duplex = 0; 2881 boolean_t link_changed = B_FALSE; 2882 2883 ASSERT(mutex_owned(&igb->gen_lock)); 2884 2885 if (igb_is_link_up(igb)) { 2886 /* 2887 * The Link is up, check whether it was marked as down earlier 2888 */ 2889 if (igb->link_state != LINK_STATE_UP) { 2890 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2891 igb->link_speed = speed; 2892 igb->link_duplex = duplex; 2893 igb->link_state = LINK_STATE_UP; 2894 igb->link_down_timeout = 0; 2895 link_changed = B_TRUE; 2896 } 2897 } else { 2898 if (igb->link_state != LINK_STATE_DOWN) { 2899 igb->link_speed = 0; 2900 igb->link_duplex = 0; 2901 igb->link_state = LINK_STATE_DOWN; 2902 link_changed = B_TRUE; 2903 } 2904 2905 if (igb->igb_state & IGB_STARTED) { 2906 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2907 igb->link_down_timeout++; 2908 } else if (igb->link_down_timeout == 2909 MAX_LINK_DOWN_TIMEOUT) { 2910 igb_tx_clean(igb); 2911 igb->link_down_timeout++; 2912 } 2913 } 2914 } 2915 2916 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2917 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2918 2919 return (link_changed); 2920 } 2921 2922 /* 2923 * igb_local_timer - driver watchdog function 2924 * 2925 * This function will handle the transmit stall check, link status check and 2926 * other routines. 2927 */ 2928 static void 2929 igb_local_timer(void *arg) 2930 { 2931 igb_t *igb = (igb_t *)arg; 2932 boolean_t link_changed = B_FALSE; 2933 2934 if (igb_stall_check(igb)) { 2935 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 2936 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 2937 igb->reset_count++; 2938 if (igb_reset(igb) == IGB_SUCCESS) 2939 ddi_fm_service_impact(igb->dip, 2940 DDI_SERVICE_RESTORED); 2941 } 2942 2943 mutex_enter(&igb->gen_lock); 2944 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 2945 link_changed = igb_link_check(igb); 2946 mutex_exit(&igb->gen_lock); 2947 2948 if (link_changed) 2949 mac_link_update(igb->mac_hdl, igb->link_state); 2950 2951 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2952 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2953 2954 igb_restart_watchdog_timer(igb); 2955 } 2956 2957 /* 2958 * igb_stall_check - check for transmit stall 2959 * 2960 * This function checks if the adapter is stalled (in transmit). 2961 * 2962 * It is called each time the watchdog timeout is invoked. 2963 * If the transmit descriptor reclaim continuously fails, 2964 * the watchdog value will increment by 1. If the watchdog 2965 * value exceeds the threshold, the igb is assumed to 2966 * have stalled and need to be reset. 2967 */ 2968 static boolean_t 2969 igb_stall_check(igb_t *igb) 2970 { 2971 igb_tx_ring_t *tx_ring; 2972 boolean_t result; 2973 int i; 2974 2975 if (igb->link_state != LINK_STATE_UP) 2976 return (B_FALSE); 2977 2978 /* 2979 * If any tx ring is stalled, we'll reset the chipset 2980 */ 2981 result = B_FALSE; 2982 for (i = 0; i < igb->num_tx_rings; i++) { 2983 tx_ring = &igb->tx_rings[i]; 2984 2985 if (tx_ring->recycle_fail > 0) 2986 tx_ring->stall_watchdog++; 2987 else 2988 tx_ring->stall_watchdog = 0; 2989 2990 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2991 result = B_TRUE; 2992 break; 2993 } 2994 } 2995 2996 if (result) { 2997 tx_ring->stall_watchdog = 0; 2998 tx_ring->recycle_fail = 0; 2999 } 3000 3001 return (result); 3002 } 3003 3004 3005 /* 3006 * is_valid_mac_addr - Check if the mac address is valid 3007 */ 3008 static boolean_t 3009 is_valid_mac_addr(uint8_t *mac_addr) 3010 { 3011 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3012 const uint8_t addr_test2[6] = 3013 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3014 3015 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3016 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3017 return (B_FALSE); 3018 3019 return (B_TRUE); 3020 } 3021 3022 static boolean_t 3023 igb_find_mac_address(igb_t *igb) 3024 { 3025 struct e1000_hw *hw = &igb->hw; 3026 #ifdef __sparc 3027 uchar_t *bytes; 3028 struct ether_addr sysaddr; 3029 uint_t nelts; 3030 int err; 3031 boolean_t found = B_FALSE; 3032 3033 /* 3034 * The "vendor's factory-set address" may already have 3035 * been extracted from the chip, but if the property 3036 * "local-mac-address" is set we use that instead. 3037 * 3038 * We check whether it looks like an array of 6 3039 * bytes (which it should, if OBP set it). If we can't 3040 * make sense of it this way, we'll ignore it. 3041 */ 3042 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3043 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3044 if (err == DDI_PROP_SUCCESS) { 3045 if (nelts == ETHERADDRL) { 3046 while (nelts--) 3047 hw->mac.addr[nelts] = bytes[nelts]; 3048 found = B_TRUE; 3049 } 3050 ddi_prop_free(bytes); 3051 } 3052 3053 /* 3054 * Look up the OBP property "local-mac-address?". If the user has set 3055 * 'local-mac-address? = false', use "the system address" instead. 3056 */ 3057 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3058 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3059 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3060 if (localetheraddr(NULL, &sysaddr) != 0) { 3061 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3062 found = B_TRUE; 3063 } 3064 } 3065 ddi_prop_free(bytes); 3066 } 3067 3068 /* 3069 * Finally(!), if there's a valid "mac-address" property (created 3070 * if we netbooted from this interface), we must use this instead 3071 * of any of the above to ensure that the NFS/install server doesn't 3072 * get confused by the address changing as Solaris takes over! 3073 */ 3074 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3075 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3076 if (err == DDI_PROP_SUCCESS) { 3077 if (nelts == ETHERADDRL) { 3078 while (nelts--) 3079 hw->mac.addr[nelts] = bytes[nelts]; 3080 found = B_TRUE; 3081 } 3082 ddi_prop_free(bytes); 3083 } 3084 3085 if (found) { 3086 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3087 return (B_TRUE); 3088 } 3089 #endif 3090 3091 /* 3092 * Read the device MAC address from the EEPROM 3093 */ 3094 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3095 return (B_FALSE); 3096 3097 return (B_TRUE); 3098 } 3099 3100 #pragma inline(igb_arm_watchdog_timer) 3101 3102 static void 3103 igb_arm_watchdog_timer(igb_t *igb) 3104 { 3105 /* 3106 * Fire a watchdog timer 3107 */ 3108 igb->watchdog_tid = 3109 timeout(igb_local_timer, 3110 (void *)igb, 1 * drv_usectohz(1000000)); 3111 3112 } 3113 3114 /* 3115 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3116 */ 3117 void 3118 igb_enable_watchdog_timer(igb_t *igb) 3119 { 3120 mutex_enter(&igb->watchdog_lock); 3121 3122 if (!igb->watchdog_enable) { 3123 igb->watchdog_enable = B_TRUE; 3124 igb->watchdog_start = B_TRUE; 3125 igb_arm_watchdog_timer(igb); 3126 } 3127 3128 mutex_exit(&igb->watchdog_lock); 3129 3130 } 3131 3132 /* 3133 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3134 */ 3135 void 3136 igb_disable_watchdog_timer(igb_t *igb) 3137 { 3138 timeout_id_t tid; 3139 3140 mutex_enter(&igb->watchdog_lock); 3141 3142 igb->watchdog_enable = B_FALSE; 3143 igb->watchdog_start = B_FALSE; 3144 tid = igb->watchdog_tid; 3145 igb->watchdog_tid = 0; 3146 3147 mutex_exit(&igb->watchdog_lock); 3148 3149 if (tid != 0) 3150 (void) untimeout(tid); 3151 3152 } 3153 3154 /* 3155 * igb_start_watchdog_timer - Start the driver watchdog timer 3156 */ 3157 static void 3158 igb_start_watchdog_timer(igb_t *igb) 3159 { 3160 mutex_enter(&igb->watchdog_lock); 3161 3162 if (igb->watchdog_enable) { 3163 if (!igb->watchdog_start) { 3164 igb->watchdog_start = B_TRUE; 3165 igb_arm_watchdog_timer(igb); 3166 } 3167 } 3168 3169 mutex_exit(&igb->watchdog_lock); 3170 } 3171 3172 /* 3173 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3174 */ 3175 static void 3176 igb_restart_watchdog_timer(igb_t *igb) 3177 { 3178 mutex_enter(&igb->watchdog_lock); 3179 3180 if (igb->watchdog_start) 3181 igb_arm_watchdog_timer(igb); 3182 3183 mutex_exit(&igb->watchdog_lock); 3184 } 3185 3186 /* 3187 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3188 */ 3189 static void 3190 igb_stop_watchdog_timer(igb_t *igb) 3191 { 3192 timeout_id_t tid; 3193 3194 mutex_enter(&igb->watchdog_lock); 3195 3196 igb->watchdog_start = B_FALSE; 3197 tid = igb->watchdog_tid; 3198 igb->watchdog_tid = 0; 3199 3200 mutex_exit(&igb->watchdog_lock); 3201 3202 if (tid != 0) 3203 (void) untimeout(tid); 3204 } 3205 3206 /* 3207 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3208 */ 3209 static void 3210 igb_disable_adapter_interrupts(igb_t *igb) 3211 { 3212 struct e1000_hw *hw = &igb->hw; 3213 3214 /* 3215 * Set the IMC register to mask all the interrupts, 3216 * including the tx interrupts. 3217 */ 3218 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3219 E1000_WRITE_REG(hw, E1000_IAM, 0); 3220 3221 /* 3222 * Additional disabling for MSI-X 3223 */ 3224 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3225 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3226 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3227 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3228 } 3229 3230 E1000_WRITE_FLUSH(hw); 3231 } 3232 3233 /* 3234 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3235 */ 3236 static void 3237 igb_enable_adapter_interrupts_82576(igb_t *igb) 3238 { 3239 struct e1000_hw *hw = &igb->hw; 3240 3241 /* Clear any pending interrupts */ 3242 (void) E1000_READ_REG(hw, E1000_ICR); 3243 3244 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3245 3246 /* Interrupt enabling for MSI-X */ 3247 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3248 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3249 igb->ims_mask = E1000_IMS_LSC; 3250 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3251 } else { 3252 /* Interrupt enabling for MSI and legacy */ 3253 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3254 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3255 E1000_WRITE_REG(hw, E1000_IMS, 3256 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3257 } 3258 3259 /* Disable auto-mask for ICR interrupt bits */ 3260 E1000_WRITE_REG(hw, E1000_IAM, 0); 3261 3262 E1000_WRITE_FLUSH(hw); 3263 } 3264 3265 /* 3266 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3267 */ 3268 static void 3269 igb_enable_adapter_interrupts_82575(igb_t *igb) 3270 { 3271 struct e1000_hw *hw = &igb->hw; 3272 uint32_t reg; 3273 3274 /* Clear any pending interrupts */ 3275 (void) E1000_READ_REG(hw, E1000_ICR); 3276 3277 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3278 /* Interrupt enabling for MSI-X */ 3279 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3280 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3281 igb->ims_mask = E1000_IMS_LSC; 3282 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3283 3284 /* Enable MSI-X PBA support */ 3285 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3286 reg |= E1000_CTRL_EXT_PBA_CLR; 3287 3288 /* Non-selective interrupt clear-on-read */ 3289 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3290 3291 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3292 } else { 3293 /* Interrupt enabling for MSI and legacy */ 3294 igb->ims_mask = IMS_ENABLE_MASK; 3295 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3296 } 3297 3298 E1000_WRITE_FLUSH(hw); 3299 } 3300 3301 /* 3302 * Loopback Support 3303 */ 3304 static lb_property_t lb_normal = 3305 { normal, "normal", IGB_LB_NONE }; 3306 static lb_property_t lb_external = 3307 { external, "External", IGB_LB_EXTERNAL }; 3308 static lb_property_t lb_mac = 3309 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 3310 static lb_property_t lb_phy = 3311 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3312 static lb_property_t lb_serdes = 3313 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3314 3315 enum ioc_reply 3316 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3317 { 3318 lb_info_sz_t *lbsp; 3319 lb_property_t *lbpp; 3320 struct e1000_hw *hw; 3321 uint32_t *lbmp; 3322 uint32_t size; 3323 uint32_t value; 3324 3325 hw = &igb->hw; 3326 3327 if (mp->b_cont == NULL) 3328 return (IOC_INVAL); 3329 3330 switch (iocp->ioc_cmd) { 3331 default: 3332 return (IOC_INVAL); 3333 3334 case LB_GET_INFO_SIZE: 3335 size = sizeof (lb_info_sz_t); 3336 if (iocp->ioc_count != size) 3337 return (IOC_INVAL); 3338 3339 value = sizeof (lb_normal); 3340 value += sizeof (lb_mac); 3341 if (hw->phy.media_type == e1000_media_type_copper) 3342 value += sizeof (lb_phy); 3343 else 3344 value += sizeof (lb_serdes); 3345 value += sizeof (lb_external); 3346 3347 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3348 *lbsp = value; 3349 break; 3350 3351 case LB_GET_INFO: 3352 value = sizeof (lb_normal); 3353 value += sizeof (lb_mac); 3354 if (hw->phy.media_type == e1000_media_type_copper) 3355 value += sizeof (lb_phy); 3356 else 3357 value += sizeof (lb_serdes); 3358 value += sizeof (lb_external); 3359 3360 size = value; 3361 if (iocp->ioc_count != size) 3362 return (IOC_INVAL); 3363 3364 value = 0; 3365 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3366 3367 lbpp[value++] = lb_normal; 3368 lbpp[value++] = lb_mac; 3369 if (hw->phy.media_type == e1000_media_type_copper) 3370 lbpp[value++] = lb_phy; 3371 else 3372 lbpp[value++] = lb_serdes; 3373 lbpp[value++] = lb_external; 3374 break; 3375 3376 case LB_GET_MODE: 3377 size = sizeof (uint32_t); 3378 if (iocp->ioc_count != size) 3379 return (IOC_INVAL); 3380 3381 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3382 *lbmp = igb->loopback_mode; 3383 break; 3384 3385 case LB_SET_MODE: 3386 size = 0; 3387 if (iocp->ioc_count != sizeof (uint32_t)) 3388 return (IOC_INVAL); 3389 3390 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3391 if (!igb_set_loopback_mode(igb, *lbmp)) 3392 return (IOC_INVAL); 3393 break; 3394 } 3395 3396 iocp->ioc_count = size; 3397 iocp->ioc_error = 0; 3398 3399 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3400 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3401 return (IOC_INVAL); 3402 } 3403 3404 return (IOC_REPLY); 3405 } 3406 3407 /* 3408 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3409 */ 3410 static boolean_t 3411 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3412 { 3413 struct e1000_hw *hw; 3414 3415 if (mode == igb->loopback_mode) 3416 return (B_TRUE); 3417 3418 hw = &igb->hw; 3419 3420 igb->loopback_mode = mode; 3421 3422 if (mode == IGB_LB_NONE) { 3423 /* Reset the chip */ 3424 hw->phy.autoneg_wait_to_complete = B_TRUE; 3425 (void) igb_reset(igb); 3426 hw->phy.autoneg_wait_to_complete = B_FALSE; 3427 return (B_TRUE); 3428 } 3429 3430 mutex_enter(&igb->gen_lock); 3431 3432 switch (mode) { 3433 default: 3434 mutex_exit(&igb->gen_lock); 3435 return (B_FALSE); 3436 3437 case IGB_LB_EXTERNAL: 3438 igb_set_external_loopback(igb); 3439 break; 3440 3441 case IGB_LB_INTERNAL_MAC: 3442 igb_set_internal_mac_loopback(igb); 3443 break; 3444 3445 case IGB_LB_INTERNAL_PHY: 3446 igb_set_internal_phy_loopback(igb); 3447 break; 3448 3449 case IGB_LB_INTERNAL_SERDES: 3450 igb_set_internal_serdes_loopback(igb); 3451 break; 3452 } 3453 3454 mutex_exit(&igb->gen_lock); 3455 3456 return (B_TRUE); 3457 } 3458 3459 /* 3460 * igb_set_external_loopback - Set the external loopback mode 3461 */ 3462 static void 3463 igb_set_external_loopback(igb_t *igb) 3464 { 3465 struct e1000_hw *hw; 3466 3467 hw = &igb->hw; 3468 3469 /* Set phy to known state */ 3470 (void) e1000_phy_hw_reset(hw); 3471 3472 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3473 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3474 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3475 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3476 } 3477 3478 /* 3479 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3480 */ 3481 static void 3482 igb_set_internal_mac_loopback(igb_t *igb) 3483 { 3484 struct e1000_hw *hw; 3485 uint32_t ctrl; 3486 uint32_t rctl; 3487 uint32_t ctrl_ext; 3488 uint16_t phy_ctrl; 3489 uint16_t phy_status; 3490 3491 hw = &igb->hw; 3492 3493 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3494 phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 3495 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3496 3497 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3498 3499 /* Set link mode to PHY (00b) in the Extended Control register */ 3500 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3501 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3502 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3503 3504 /* Set the Device Control register */ 3505 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3506 if (!(phy_status & MII_SR_LINK_STATUS)) 3507 ctrl |= E1000_CTRL_ILOS; /* Set ILOS when the link is down */ 3508 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3509 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3510 E1000_CTRL_FRCSPD | /* Force speed */ 3511 E1000_CTRL_FRCDPX | /* Force duplex */ 3512 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3513 E1000_CTRL_FD); /* Force full duplex */ 3514 3515 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3516 3517 /* Set the Receive Control register */ 3518 rctl = E1000_READ_REG(hw, E1000_RCTL); 3519 rctl &= ~E1000_RCTL_LBM_TCVR; 3520 rctl |= E1000_RCTL_LBM_MAC; 3521 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3522 } 3523 3524 /* 3525 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3526 */ 3527 static void 3528 igb_set_internal_phy_loopback(igb_t *igb) 3529 { 3530 struct e1000_hw *hw; 3531 uint32_t ctrl_ext; 3532 uint16_t phy_ctrl; 3533 uint16_t phy_pconf; 3534 3535 hw = &igb->hw; 3536 3537 /* Set link mode to PHY (00b) in the Extended Control register */ 3538 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3539 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3540 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3541 3542 /* 3543 * Set PHY control register (0x4140): 3544 * Set full duplex mode 3545 * Set loopback bit 3546 * Clear auto-neg enable bit 3547 * Set PHY speed 3548 */ 3549 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3550 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3551 3552 /* Set the link disable bit in the Port Configuration register */ 3553 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3554 phy_pconf |= (uint16_t)1 << 14; 3555 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3556 } 3557 3558 /* 3559 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3560 */ 3561 static void 3562 igb_set_internal_serdes_loopback(igb_t *igb) 3563 { 3564 struct e1000_hw *hw; 3565 uint32_t ctrl_ext; 3566 uint32_t ctrl; 3567 uint32_t pcs_lctl; 3568 uint32_t connsw; 3569 3570 hw = &igb->hw; 3571 3572 /* Set link mode to SerDes (11b) in the Extended Control register */ 3573 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3574 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3575 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3576 3577 /* Configure the SerDes to loopback */ 3578 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3579 3580 /* Set Device Control register */ 3581 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3582 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3583 E1000_CTRL_SLU); /* Force link up */ 3584 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3585 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3586 E1000_CTRL_LRST); /* Clear link reset */ 3587 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3588 3589 /* Set PCS Link Control register */ 3590 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3591 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3592 E1000_PCS_LCTL_FSD | 3593 E1000_PCS_LCTL_FDV_FULL | 3594 E1000_PCS_LCTL_FLV_LINK_UP); 3595 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3596 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3597 3598 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3599 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3600 connsw &= ~E1000_CONNSW_ENRGSRC; 3601 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3602 } 3603 3604 #pragma inline(igb_intr_rx_work) 3605 /* 3606 * igb_intr_rx_work - rx processing of ISR 3607 */ 3608 static void 3609 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3610 { 3611 mblk_t *mp; 3612 3613 mutex_enter(&rx_ring->rx_lock); 3614 mp = igb_rx(rx_ring, IGB_NO_POLL); 3615 mutex_exit(&rx_ring->rx_lock); 3616 3617 if (mp != NULL) 3618 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 3619 rx_ring->ring_gen_num); 3620 } 3621 3622 #pragma inline(igb_intr_tx_work) 3623 /* 3624 * igb_intr_tx_work - tx processing of ISR 3625 */ 3626 static void 3627 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3628 { 3629 /* Recycle the tx descriptors */ 3630 tx_ring->tx_recycle(tx_ring); 3631 3632 /* Schedule the re-transmit */ 3633 if (tx_ring->reschedule && 3634 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3635 tx_ring->reschedule = B_FALSE; 3636 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 3637 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3638 } 3639 } 3640 3641 #pragma inline(igb_intr_link_work) 3642 /* 3643 * igb_intr_link_work - link-status-change processing of ISR 3644 */ 3645 static void 3646 igb_intr_link_work(igb_t *igb) 3647 { 3648 boolean_t link_changed; 3649 3650 igb_stop_watchdog_timer(igb); 3651 3652 mutex_enter(&igb->gen_lock); 3653 3654 /* 3655 * Because we got a link-status-change interrupt, force 3656 * e1000_check_for_link() to look at phy 3657 */ 3658 igb->hw.mac.get_link_status = B_TRUE; 3659 3660 /* igb_link_check takes care of link status change */ 3661 link_changed = igb_link_check(igb); 3662 3663 /* Get new phy state */ 3664 igb_get_phy_state(igb); 3665 3666 mutex_exit(&igb->gen_lock); 3667 3668 if (link_changed) 3669 mac_link_update(igb->mac_hdl, igb->link_state); 3670 3671 igb_start_watchdog_timer(igb); 3672 } 3673 3674 /* 3675 * igb_intr_legacy - Interrupt handler for legacy interrupts 3676 */ 3677 static uint_t 3678 igb_intr_legacy(void *arg1, void *arg2) 3679 { 3680 igb_t *igb = (igb_t *)arg1; 3681 igb_tx_ring_t *tx_ring; 3682 uint32_t icr; 3683 mblk_t *mp; 3684 boolean_t tx_reschedule; 3685 boolean_t link_changed; 3686 uint_t result; 3687 3688 _NOTE(ARGUNUSED(arg2)); 3689 3690 mutex_enter(&igb->gen_lock); 3691 3692 if (igb->igb_state & IGB_SUSPENDED) { 3693 mutex_exit(&igb->gen_lock); 3694 return (DDI_INTR_UNCLAIMED); 3695 } 3696 3697 mp = NULL; 3698 tx_reschedule = B_FALSE; 3699 link_changed = B_FALSE; 3700 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3701 3702 if (icr & E1000_ICR_INT_ASSERTED) { 3703 /* 3704 * E1000_ICR_INT_ASSERTED bit was set: 3705 * Read(Clear) the ICR, claim this interrupt, 3706 * look for work to do. 3707 */ 3708 ASSERT(igb->num_rx_rings == 1); 3709 ASSERT(igb->num_tx_rings == 1); 3710 3711 /* Make sure all interrupt causes cleared */ 3712 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3713 3714 if (icr & E1000_ICR_RXT0) { 3715 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 3716 } 3717 3718 if (icr & E1000_ICR_TXDW) { 3719 tx_ring = &igb->tx_rings[0]; 3720 3721 /* Recycle the tx descriptors */ 3722 tx_ring->tx_recycle(tx_ring); 3723 3724 /* Schedule the re-transmit */ 3725 tx_reschedule = (tx_ring->reschedule && 3726 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3727 } 3728 3729 if (icr & E1000_ICR_LSC) { 3730 /* 3731 * Because we got a link-status-change interrupt, force 3732 * e1000_check_for_link() to look at phy 3733 */ 3734 igb->hw.mac.get_link_status = B_TRUE; 3735 3736 /* igb_link_check takes care of link status change */ 3737 link_changed = igb_link_check(igb); 3738 3739 /* Get new phy state */ 3740 igb_get_phy_state(igb); 3741 } 3742 3743 result = DDI_INTR_CLAIMED; 3744 } else { 3745 /* 3746 * E1000_ICR_INT_ASSERTED bit was not set: 3747 * Don't claim this interrupt. 3748 */ 3749 result = DDI_INTR_UNCLAIMED; 3750 } 3751 3752 mutex_exit(&igb->gen_lock); 3753 3754 /* 3755 * Do the following work outside of the gen_lock 3756 */ 3757 if (mp != NULL) 3758 mac_rx(igb->mac_hdl, NULL, mp); 3759 3760 if (tx_reschedule) { 3761 tx_ring->reschedule = B_FALSE; 3762 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 3763 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3764 } 3765 3766 if (link_changed) 3767 mac_link_update(igb->mac_hdl, igb->link_state); 3768 3769 return (result); 3770 } 3771 3772 /* 3773 * igb_intr_msi - Interrupt handler for MSI 3774 */ 3775 static uint_t 3776 igb_intr_msi(void *arg1, void *arg2) 3777 { 3778 igb_t *igb = (igb_t *)arg1; 3779 uint32_t icr; 3780 3781 _NOTE(ARGUNUSED(arg2)); 3782 3783 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3784 3785 /* Make sure all interrupt causes cleared */ 3786 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3787 3788 /* 3789 * For MSI interrupt, we have only one vector, 3790 * so we have only one rx ring and one tx ring enabled. 3791 */ 3792 ASSERT(igb->num_rx_rings == 1); 3793 ASSERT(igb->num_tx_rings == 1); 3794 3795 if (icr & E1000_ICR_RXT0) { 3796 igb_intr_rx_work(&igb->rx_rings[0]); 3797 } 3798 3799 if (icr & E1000_ICR_TXDW) { 3800 igb_intr_tx_work(&igb->tx_rings[0]); 3801 } 3802 3803 if (icr & E1000_ICR_LSC) { 3804 igb_intr_link_work(igb); 3805 } 3806 3807 return (DDI_INTR_CLAIMED); 3808 } 3809 3810 /* 3811 * igb_intr_rx - Interrupt handler for rx 3812 */ 3813 static uint_t 3814 igb_intr_rx(void *arg1, void *arg2) 3815 { 3816 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3817 3818 _NOTE(ARGUNUSED(arg2)); 3819 3820 /* 3821 * Only used via MSI-X vector so don't check cause bits 3822 * and only clean the given ring. 3823 */ 3824 igb_intr_rx_work(rx_ring); 3825 3826 return (DDI_INTR_CLAIMED); 3827 } 3828 3829 /* 3830 * igb_intr_tx - Interrupt handler for tx 3831 */ 3832 static uint_t 3833 igb_intr_tx(void *arg1, void *arg2) 3834 { 3835 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 3836 3837 _NOTE(ARGUNUSED(arg2)); 3838 3839 /* 3840 * Only used via MSI-X vector so don't check cause bits 3841 * and only clean the given ring. 3842 */ 3843 igb_intr_tx_work(tx_ring); 3844 3845 return (DDI_INTR_CLAIMED); 3846 } 3847 3848 /* 3849 * igb_intr_tx_other - Interrupt handler for both tx and other 3850 * 3851 */ 3852 static uint_t 3853 igb_intr_tx_other(void *arg1, void *arg2) 3854 { 3855 igb_t *igb = (igb_t *)arg1; 3856 uint32_t icr; 3857 3858 _NOTE(ARGUNUSED(arg2)); 3859 3860 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3861 3862 /* 3863 * Look for tx reclaiming work first. Remember, in the 3864 * case of only interrupt sharing, only one tx ring is 3865 * used 3866 */ 3867 igb_intr_tx_work(&igb->tx_rings[0]); 3868 3869 /* 3870 * Check for "other" causes. 3871 */ 3872 if (icr & E1000_ICR_LSC) { 3873 igb_intr_link_work(igb); 3874 } 3875 3876 /* 3877 * The DOUTSYNC bit indicates a tx packet dropped because 3878 * DMA engine gets "out of sync". There isn't a real fix 3879 * for this. The Intel recommendation is to count the number 3880 * of occurrences so user can detect when it is happening. 3881 * The issue is non-fatal and there's no recovery action 3882 * available. 3883 */ 3884 if (icr & E1000_ICR_DOUTSYNC) { 3885 IGB_STAT(igb->dout_sync); 3886 } 3887 3888 return (DDI_INTR_CLAIMED); 3889 } 3890 3891 /* 3892 * igb_alloc_intrs - Allocate interrupts for the driver 3893 * 3894 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3895 * if not successful, try Legacy. 3896 * igb->intr_force can be used to force sequence to start with 3897 * any of the 3 types. 3898 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3899 */ 3900 static int 3901 igb_alloc_intrs(igb_t *igb) 3902 { 3903 dev_info_t *devinfo; 3904 int intr_types; 3905 int rc; 3906 3907 devinfo = igb->dip; 3908 3909 /* Get supported interrupt types */ 3910 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3911 3912 if (rc != DDI_SUCCESS) { 3913 igb_log(igb, 3914 "Get supported interrupt types failed: %d", rc); 3915 return (IGB_FAILURE); 3916 } 3917 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3918 3919 igb->intr_type = 0; 3920 3921 /* Install MSI-X interrupts */ 3922 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3923 (igb->intr_force <= IGB_INTR_MSIX)) { 3924 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 3925 3926 if (rc == IGB_SUCCESS) 3927 return (IGB_SUCCESS); 3928 3929 igb_log(igb, 3930 "Allocate MSI-X failed, trying MSI interrupts..."); 3931 } 3932 3933 /* MSI-X not used, force rings to 1 */ 3934 igb->num_rx_rings = 1; 3935 igb->num_tx_rings = 1; 3936 igb_log(igb, 3937 "MSI-X not used, force rx and tx queue number to 1"); 3938 3939 /* Install MSI interrupts */ 3940 if ((intr_types & DDI_INTR_TYPE_MSI) && 3941 (igb->intr_force <= IGB_INTR_MSI)) { 3942 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 3943 3944 if (rc == IGB_SUCCESS) 3945 return (IGB_SUCCESS); 3946 3947 igb_log(igb, 3948 "Allocate MSI failed, trying Legacy interrupts..."); 3949 } 3950 3951 /* Install legacy interrupts */ 3952 if (intr_types & DDI_INTR_TYPE_FIXED) { 3953 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 3954 3955 if (rc == IGB_SUCCESS) 3956 return (IGB_SUCCESS); 3957 3958 igb_log(igb, 3959 "Allocate Legacy interrupts failed"); 3960 } 3961 3962 /* If none of the 3 types succeeded, return failure */ 3963 return (IGB_FAILURE); 3964 } 3965 3966 /* 3967 * igb_alloc_intr_handles - Allocate interrupt handles. 3968 * 3969 * For legacy and MSI, only 1 handle is needed. For MSI-X, 3970 * if fewer than 2 handles are available, return failure. 3971 * Upon success, this sets the number of Rx rings to a number that 3972 * matches the handles available for Rx interrupts. 3973 */ 3974 static int 3975 igb_alloc_intr_handles(igb_t *igb, int intr_type) 3976 { 3977 dev_info_t *devinfo; 3978 int orig, request, count, avail, actual; 3979 int diff, minimum; 3980 int rc; 3981 3982 devinfo = igb->dip; 3983 3984 switch (intr_type) { 3985 case DDI_INTR_TYPE_FIXED: 3986 request = 1; /* Request 1 legacy interrupt handle */ 3987 minimum = 1; 3988 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 3989 break; 3990 3991 case DDI_INTR_TYPE_MSI: 3992 request = 1; /* Request 1 MSI interrupt handle */ 3993 minimum = 1; 3994 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 3995 break; 3996 3997 case DDI_INTR_TYPE_MSIX: 3998 /* 3999 * Number of vectors for the adapter is 4000 * # rx rings + # tx rings 4001 * One of tx vectors is for tx & other 4002 */ 4003 request = igb->num_rx_rings + igb->num_tx_rings; 4004 orig = request; 4005 minimum = 2; 4006 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4007 break; 4008 4009 default: 4010 igb_log(igb, 4011 "invalid call to igb_alloc_intr_handles(): %d\n", 4012 intr_type); 4013 return (IGB_FAILURE); 4014 } 4015 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4016 request, minimum); 4017 4018 /* 4019 * Get number of supported interrupts 4020 */ 4021 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4022 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4023 igb_log(igb, 4024 "Get supported interrupt number failed. " 4025 "Return: %d, count: %d", rc, count); 4026 return (IGB_FAILURE); 4027 } 4028 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4029 4030 /* 4031 * Get number of available interrupts 4032 */ 4033 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4034 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4035 igb_log(igb, 4036 "Get available interrupt number failed. " 4037 "Return: %d, available: %d", rc, avail); 4038 return (IGB_FAILURE); 4039 } 4040 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4041 4042 if (avail < request) { 4043 igb_log(igb, "Request %d handles, %d available", 4044 request, avail); 4045 request = avail; 4046 } 4047 4048 actual = 0; 4049 igb->intr_cnt = 0; 4050 4051 /* 4052 * Allocate an array of interrupt handles 4053 */ 4054 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4055 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4056 4057 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4058 request, &actual, DDI_INTR_ALLOC_NORMAL); 4059 if (rc != DDI_SUCCESS) { 4060 igb_log(igb, "Allocate interrupts failed. " 4061 "return: %d, request: %d, actual: %d", 4062 rc, request, actual); 4063 goto alloc_handle_fail; 4064 } 4065 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4066 4067 igb->intr_cnt = actual; 4068 4069 if (actual < minimum) { 4070 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4071 actual); 4072 goto alloc_handle_fail; 4073 } 4074 4075 /* 4076 * For MSI-X, actual might force us to reduce number of tx & rx rings 4077 */ 4078 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4079 diff = orig - actual; 4080 if (diff < igb->num_tx_rings) { 4081 igb_log(igb, 4082 "MSI-X vectors force Tx queue number to %d", 4083 igb->num_tx_rings - diff); 4084 igb->num_tx_rings -= diff; 4085 } else { 4086 igb_log(igb, 4087 "MSI-X vectors force Tx queue number to 1"); 4088 igb->num_tx_rings = 1; 4089 4090 igb_log(igb, 4091 "MSI-X vectors force Rx queue number to %d", 4092 actual - 1); 4093 igb->num_rx_rings = actual - 1; 4094 } 4095 } 4096 4097 /* 4098 * Get priority for first vector, assume remaining are all the same 4099 */ 4100 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4101 if (rc != DDI_SUCCESS) { 4102 igb_log(igb, 4103 "Get interrupt priority failed: %d", rc); 4104 goto alloc_handle_fail; 4105 } 4106 4107 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4108 if (rc != DDI_SUCCESS) { 4109 igb_log(igb, 4110 "Get interrupt cap failed: %d", rc); 4111 goto alloc_handle_fail; 4112 } 4113 4114 igb->intr_type = intr_type; 4115 4116 return (IGB_SUCCESS); 4117 4118 alloc_handle_fail: 4119 igb_rem_intrs(igb); 4120 4121 return (IGB_FAILURE); 4122 } 4123 4124 /* 4125 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4126 * 4127 * Before adding the interrupt handlers, the interrupt vectors have 4128 * been allocated, and the rx/tx rings have also been allocated. 4129 */ 4130 static int 4131 igb_add_intr_handlers(igb_t *igb) 4132 { 4133 igb_rx_ring_t *rx_ring; 4134 igb_tx_ring_t *tx_ring; 4135 int vector; 4136 int rc; 4137 int i; 4138 4139 vector = 0; 4140 4141 switch (igb->intr_type) { 4142 case DDI_INTR_TYPE_MSIX: 4143 /* Add interrupt handler for tx + other */ 4144 tx_ring = &igb->tx_rings[0]; 4145 rc = ddi_intr_add_handler(igb->htable[vector], 4146 (ddi_intr_handler_t *)igb_intr_tx_other, 4147 (void *)igb, NULL); 4148 4149 if (rc != DDI_SUCCESS) { 4150 igb_log(igb, 4151 "Add tx/other interrupt handler failed: %d", rc); 4152 return (IGB_FAILURE); 4153 } 4154 tx_ring->intr_vector = vector; 4155 vector++; 4156 4157 /* Add interrupt handler for each rx ring */ 4158 for (i = 0; i < igb->num_rx_rings; i++) { 4159 rx_ring = &igb->rx_rings[i]; 4160 4161 rc = ddi_intr_add_handler(igb->htable[vector], 4162 (ddi_intr_handler_t *)igb_intr_rx, 4163 (void *)rx_ring, NULL); 4164 4165 if (rc != DDI_SUCCESS) { 4166 igb_log(igb, 4167 "Add rx interrupt handler failed. " 4168 "return: %d, rx ring: %d", rc, i); 4169 for (vector--; vector >= 0; vector--) { 4170 (void) ddi_intr_remove_handler( 4171 igb->htable[vector]); 4172 } 4173 return (IGB_FAILURE); 4174 } 4175 4176 rx_ring->intr_vector = vector; 4177 4178 vector++; 4179 } 4180 4181 /* Add interrupt handler for each tx ring from 2nd ring */ 4182 for (i = 1; i < igb->num_tx_rings; i++) { 4183 tx_ring = &igb->tx_rings[i]; 4184 4185 rc = ddi_intr_add_handler(igb->htable[vector], 4186 (ddi_intr_handler_t *)igb_intr_tx, 4187 (void *)tx_ring, NULL); 4188 4189 if (rc != DDI_SUCCESS) { 4190 igb_log(igb, 4191 "Add tx interrupt handler failed. " 4192 "return: %d, tx ring: %d", rc, i); 4193 for (vector--; vector >= 0; vector--) { 4194 (void) ddi_intr_remove_handler( 4195 igb->htable[vector]); 4196 } 4197 return (IGB_FAILURE); 4198 } 4199 4200 tx_ring->intr_vector = vector; 4201 4202 vector++; 4203 } 4204 4205 break; 4206 4207 case DDI_INTR_TYPE_MSI: 4208 /* Add interrupt handlers for the only vector */ 4209 rc = ddi_intr_add_handler(igb->htable[vector], 4210 (ddi_intr_handler_t *)igb_intr_msi, 4211 (void *)igb, NULL); 4212 4213 if (rc != DDI_SUCCESS) { 4214 igb_log(igb, 4215 "Add MSI interrupt handler failed: %d", rc); 4216 return (IGB_FAILURE); 4217 } 4218 4219 rx_ring = &igb->rx_rings[0]; 4220 rx_ring->intr_vector = vector; 4221 4222 vector++; 4223 break; 4224 4225 case DDI_INTR_TYPE_FIXED: 4226 /* Add interrupt handlers for the only vector */ 4227 rc = ddi_intr_add_handler(igb->htable[vector], 4228 (ddi_intr_handler_t *)igb_intr_legacy, 4229 (void *)igb, NULL); 4230 4231 if (rc != DDI_SUCCESS) { 4232 igb_log(igb, 4233 "Add legacy interrupt handler failed: %d", rc); 4234 return (IGB_FAILURE); 4235 } 4236 4237 rx_ring = &igb->rx_rings[0]; 4238 rx_ring->intr_vector = vector; 4239 4240 vector++; 4241 break; 4242 4243 default: 4244 return (IGB_FAILURE); 4245 } 4246 4247 ASSERT(vector == igb->intr_cnt); 4248 4249 return (IGB_SUCCESS); 4250 } 4251 4252 /* 4253 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4254 * 4255 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4256 */ 4257 static void 4258 igb_setup_msix_82575(igb_t *igb) 4259 { 4260 uint32_t eims = 0; 4261 int i, vector; 4262 struct e1000_hw *hw = &igb->hw; 4263 4264 /* 4265 * Set vector for tx ring 0 and other causes. 4266 * NOTE assumption that it is vector 0. 4267 */ 4268 vector = 0; 4269 4270 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4271 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4272 vector++; 4273 4274 for (i = 0; i < igb->num_rx_rings; i++) { 4275 /* 4276 * Set vector for each rx ring 4277 */ 4278 eims = (E1000_EICR_RX_QUEUE0 << i); 4279 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4280 4281 /* 4282 * Accumulate bits to enable in 4283 * igb_enable_adapter_interrupts_82575() 4284 */ 4285 igb->eims_mask |= eims; 4286 4287 vector++; 4288 } 4289 4290 for (i = 1; i < igb->num_tx_rings; i++) { 4291 /* 4292 * Set vector for each tx ring from 2nd tx ring 4293 */ 4294 eims = (E1000_EICR_TX_QUEUE0 << i); 4295 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4296 4297 /* 4298 * Accumulate bits to enable in 4299 * igb_enable_adapter_interrupts_82575() 4300 */ 4301 igb->eims_mask |= eims; 4302 4303 vector++; 4304 } 4305 4306 ASSERT(vector == igb->intr_cnt); 4307 4308 /* 4309 * Disable IAM for ICR interrupt bits 4310 */ 4311 E1000_WRITE_REG(hw, E1000_IAM, 0); 4312 E1000_WRITE_FLUSH(hw); 4313 } 4314 4315 /* 4316 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4317 * 4318 * 82576 uses a table based method for assigning vectors. Each queue has a 4319 * single entry in the table to which we write a vector number along with a 4320 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4321 * take a different position in the 4-byte register depending on whether 4322 * they are numbered above or below 8. 4323 */ 4324 static void 4325 igb_setup_msix_82576(igb_t *igb) 4326 { 4327 struct e1000_hw *hw = &igb->hw; 4328 uint32_t ivar, index, vector; 4329 int i; 4330 4331 /* must enable msi-x capability before IVAR settings */ 4332 E1000_WRITE_REG(hw, E1000_GPIE, 4333 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4334 4335 /* 4336 * Set vector for tx ring 0 and other causes. 4337 * NOTE assumption that it is vector 0. 4338 * This is also interdependent with installation of interrupt service 4339 * routines in igb_add_intr_handlers(). 4340 */ 4341 4342 /* assign "other" causes to vector 0 */ 4343 vector = 0; 4344 ivar = ((vector | E1000_IVAR_VALID) << 8); 4345 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4346 4347 /* assign tx ring 0 to vector 0 */ 4348 ivar = ((vector | E1000_IVAR_VALID) << 8); 4349 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4350 4351 /* prepare to enable tx & other interrupt causes */ 4352 igb->eims_mask = (1 << vector); 4353 4354 vector ++; 4355 for (i = 0; i < igb->num_rx_rings; i++) { 4356 /* 4357 * Set vector for each rx ring 4358 */ 4359 index = (i & 0x7); 4360 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4361 4362 if (i < 8) { 4363 /* vector goes into low byte of register */ 4364 ivar = ivar & 0xFFFFFF00; 4365 ivar |= (vector | E1000_IVAR_VALID); 4366 } else { 4367 /* vector goes into third byte of register */ 4368 ivar = ivar & 0xFF00FFFF; 4369 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4370 } 4371 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4372 4373 /* Accumulate interrupt-cause bits to enable */ 4374 igb->eims_mask |= (1 << vector); 4375 4376 vector ++; 4377 } 4378 4379 for (i = 1; i < igb->num_tx_rings; i++) { 4380 /* 4381 * Set vector for each tx ring from 2nd tx ring. 4382 * Note assumption that tx vectors numericall follow rx vectors. 4383 */ 4384 index = (i & 0x7); 4385 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4386 4387 if (i < 8) { 4388 /* vector goes into second byte of register */ 4389 ivar = ivar & 0xFFFF00FF; 4390 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4391 } else { 4392 /* vector goes into fourth byte of register */ 4393 ivar = ivar & 0x00FFFFFF; 4394 ivar |= (vector | E1000_IVAR_VALID) << 24; 4395 } 4396 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4397 4398 /* Accumulate interrupt-cause bits to enable */ 4399 igb->eims_mask |= (1 << vector); 4400 4401 vector ++; 4402 } 4403 4404 ASSERT(vector == igb->intr_cnt); 4405 } 4406 4407 /* 4408 * igb_rem_intr_handlers - remove the interrupt handlers 4409 */ 4410 static void 4411 igb_rem_intr_handlers(igb_t *igb) 4412 { 4413 int i; 4414 int rc; 4415 4416 for (i = 0; i < igb->intr_cnt; i++) { 4417 rc = ddi_intr_remove_handler(igb->htable[i]); 4418 if (rc != DDI_SUCCESS) { 4419 IGB_DEBUGLOG_1(igb, 4420 "Remove intr handler failed: %d", rc); 4421 } 4422 } 4423 } 4424 4425 /* 4426 * igb_rem_intrs - remove the allocated interrupts 4427 */ 4428 static void 4429 igb_rem_intrs(igb_t *igb) 4430 { 4431 int i; 4432 int rc; 4433 4434 for (i = 0; i < igb->intr_cnt; i++) { 4435 rc = ddi_intr_free(igb->htable[i]); 4436 if (rc != DDI_SUCCESS) { 4437 IGB_DEBUGLOG_1(igb, 4438 "Free intr failed: %d", rc); 4439 } 4440 } 4441 4442 kmem_free(igb->htable, igb->intr_size); 4443 igb->htable = NULL; 4444 } 4445 4446 /* 4447 * igb_enable_intrs - enable all the ddi interrupts 4448 */ 4449 static int 4450 igb_enable_intrs(igb_t *igb) 4451 { 4452 int i; 4453 int rc; 4454 4455 /* Enable interrupts */ 4456 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4457 /* Call ddi_intr_block_enable() for MSI */ 4458 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4459 if (rc != DDI_SUCCESS) { 4460 igb_log(igb, 4461 "Enable block intr failed: %d", rc); 4462 return (IGB_FAILURE); 4463 } 4464 } else { 4465 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4466 for (i = 0; i < igb->intr_cnt; i++) { 4467 rc = ddi_intr_enable(igb->htable[i]); 4468 if (rc != DDI_SUCCESS) { 4469 igb_log(igb, 4470 "Enable intr failed: %d", rc); 4471 return (IGB_FAILURE); 4472 } 4473 } 4474 } 4475 4476 return (IGB_SUCCESS); 4477 } 4478 4479 /* 4480 * igb_disable_intrs - disable all the ddi interrupts 4481 */ 4482 static int 4483 igb_disable_intrs(igb_t *igb) 4484 { 4485 int i; 4486 int rc; 4487 4488 /* Disable all interrupts */ 4489 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4490 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 4491 if (rc != DDI_SUCCESS) { 4492 igb_log(igb, 4493 "Disable block intr failed: %d", rc); 4494 return (IGB_FAILURE); 4495 } 4496 } else { 4497 for (i = 0; i < igb->intr_cnt; i++) { 4498 rc = ddi_intr_disable(igb->htable[i]); 4499 if (rc != DDI_SUCCESS) { 4500 igb_log(igb, 4501 "Disable intr failed: %d", rc); 4502 return (IGB_FAILURE); 4503 } 4504 } 4505 } 4506 4507 return (IGB_SUCCESS); 4508 } 4509 4510 /* 4511 * igb_get_phy_state - Get and save the parameters read from PHY registers 4512 */ 4513 static void 4514 igb_get_phy_state(igb_t *igb) 4515 { 4516 struct e1000_hw *hw = &igb->hw; 4517 uint16_t phy_ctrl; 4518 uint16_t phy_status; 4519 uint16_t phy_an_adv; 4520 uint16_t phy_an_exp; 4521 uint16_t phy_ext_status; 4522 uint16_t phy_1000t_ctrl; 4523 uint16_t phy_1000t_status; 4524 uint16_t phy_lp_able; 4525 4526 ASSERT(mutex_owned(&igb->gen_lock)); 4527 4528 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4529 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 4530 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4531 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4532 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4533 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4534 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 4535 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4536 4537 igb->param_autoneg_cap = 4538 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4539 igb->param_pause_cap = 4540 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4541 igb->param_asym_pause_cap = 4542 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4543 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4544 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4545 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4546 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4547 igb->param_100t4_cap = 4548 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4549 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4550 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4551 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4552 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4553 igb->param_10fdx_cap = 4554 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4555 igb->param_10hdx_cap = 4556 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4557 igb->param_rem_fault = 4558 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4559 4560 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4561 igb->param_adv_pause_cap = 4562 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4563 igb->param_adv_asym_pause_cap = 4564 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4565 igb->param_adv_1000hdx_cap = 4566 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4567 igb->param_adv_100t4_cap = 4568 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4569 igb->param_adv_rem_fault = 4570 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4571 if (igb->param_adv_autoneg_cap == 1) { 4572 igb->param_adv_1000fdx_cap = 4573 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 4574 igb->param_adv_100fdx_cap = 4575 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 4576 igb->param_adv_100hdx_cap = 4577 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 4578 igb->param_adv_10fdx_cap = 4579 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 4580 igb->param_adv_10hdx_cap = 4581 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 4582 } 4583 4584 igb->param_lp_autoneg_cap = 4585 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 4586 igb->param_lp_pause_cap = 4587 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 4588 igb->param_lp_asym_pause_cap = 4589 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 4590 igb->param_lp_1000fdx_cap = 4591 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 4592 igb->param_lp_1000hdx_cap = 4593 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 4594 igb->param_lp_100t4_cap = 4595 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 4596 igb->param_lp_100fdx_cap = 4597 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 4598 igb->param_lp_100hdx_cap = 4599 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 4600 igb->param_lp_10fdx_cap = 4601 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 4602 igb->param_lp_10hdx_cap = 4603 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 4604 igb->param_lp_rem_fault = 4605 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 4606 } 4607 4608 /* 4609 * igb_get_driver_control 4610 */ 4611 static void 4612 igb_get_driver_control(struct e1000_hw *hw) 4613 { 4614 uint32_t ctrl_ext; 4615 4616 /* Notify firmware that driver is in control of device */ 4617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4618 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 4619 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4620 } 4621 4622 /* 4623 * igb_release_driver_control 4624 */ 4625 static void 4626 igb_release_driver_control(struct e1000_hw *hw) 4627 { 4628 uint32_t ctrl_ext; 4629 4630 /* Notify firmware that driver is no longer in control of device */ 4631 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4632 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 4633 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4634 } 4635 4636 /* 4637 * igb_atomic_reserve - Atomic decrease operation 4638 */ 4639 int 4640 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4641 { 4642 uint32_t oldval; 4643 uint32_t newval; 4644 4645 /* ATOMICALLY */ 4646 do { 4647 oldval = *count_p; 4648 if (oldval < n) 4649 return (-1); 4650 newval = oldval - n; 4651 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4652 4653 return (newval); 4654 } 4655 4656 /* 4657 * FMA support 4658 */ 4659 4660 int 4661 igb_check_acc_handle(ddi_acc_handle_t handle) 4662 { 4663 ddi_fm_error_t de; 4664 4665 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4666 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4667 return (de.fme_status); 4668 } 4669 4670 int 4671 igb_check_dma_handle(ddi_dma_handle_t handle) 4672 { 4673 ddi_fm_error_t de; 4674 4675 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4676 return (de.fme_status); 4677 } 4678 4679 /* 4680 * The IO fault service error handling callback function 4681 */ 4682 /*ARGSUSED*/ 4683 static int 4684 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4685 { 4686 /* 4687 * as the driver can always deal with an error in any dma or 4688 * access handle, we can just return the fme_status value. 4689 */ 4690 pci_ereport_post(dip, err, NULL); 4691 return (err->fme_status); 4692 } 4693 4694 static void 4695 igb_fm_init(igb_t *igb) 4696 { 4697 ddi_iblock_cookie_t iblk; 4698 int fma_acc_flag, fma_dma_flag; 4699 4700 /* Only register with IO Fault Services if we have some capability */ 4701 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4702 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4703 fma_acc_flag = 1; 4704 } else { 4705 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4706 fma_acc_flag = 0; 4707 } 4708 4709 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4710 fma_dma_flag = 1; 4711 } else { 4712 fma_dma_flag = 0; 4713 } 4714 4715 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4716 4717 if (igb->fm_capabilities) { 4718 4719 /* Register capabilities with IO Fault Services */ 4720 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4721 4722 /* 4723 * Initialize pci ereport capabilities if ereport capable 4724 */ 4725 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4726 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4727 pci_ereport_setup(igb->dip); 4728 4729 /* 4730 * Register error callback if error callback capable 4731 */ 4732 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4733 ddi_fm_handler_register(igb->dip, 4734 igb_fm_error_cb, (void*) igb); 4735 } 4736 } 4737 4738 static void 4739 igb_fm_fini(igb_t *igb) 4740 { 4741 /* Only unregister FMA capabilities if we registered some */ 4742 if (igb->fm_capabilities) { 4743 4744 /* 4745 * Release any resources allocated by pci_ereport_setup() 4746 */ 4747 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4748 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4749 pci_ereport_teardown(igb->dip); 4750 4751 /* 4752 * Un-register error callback if error callback capable 4753 */ 4754 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4755 ddi_fm_handler_unregister(igb->dip); 4756 4757 /* Unregister from IO Fault Services */ 4758 ddi_fm_fini(igb->dip); 4759 } 4760 } 4761 4762 void 4763 igb_fm_ereport(igb_t *igb, char *detail) 4764 { 4765 uint64_t ena; 4766 char buf[FM_MAX_CLASS]; 4767 4768 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4769 ena = fm_ena_generate(0, FM_ENA_FMT1); 4770 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4771 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4772 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4773 } 4774 } 4775