1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 32 #include "igb_sw.h" 33 34 static char ident[] = "Intel 1Gb Ethernet"; 35 36 /* 37 * Local function protoypes 38 */ 39 static int igb_register_mac(igb_t *); 40 static int igb_identify_hardware(igb_t *); 41 static int igb_regs_map(igb_t *); 42 static void igb_init_properties(igb_t *); 43 static int igb_init_driver_settings(igb_t *); 44 static void igb_init_locks(igb_t *); 45 static void igb_destroy_locks(igb_t *); 46 static int igb_init(igb_t *); 47 static int igb_chip_start(igb_t *); 48 static void igb_chip_stop(igb_t *); 49 static int igb_reset(igb_t *); 50 static void igb_tx_clean(igb_t *); 51 static boolean_t igb_tx_drain(igb_t *); 52 static boolean_t igb_rx_drain(igb_t *); 53 static int igb_alloc_rings(igb_t *); 54 static int igb_init_rings(igb_t *); 55 static void igb_free_rings(igb_t *); 56 static void igb_fini_rings(igb_t *); 57 static void igb_setup_rings(igb_t *); 58 static void igb_setup_rx(igb_t *); 59 static void igb_setup_tx(igb_t *); 60 static void igb_setup_rx_ring(igb_rx_ring_t *); 61 static void igb_setup_tx_ring(igb_tx_ring_t *); 62 static void igb_setup_rss(igb_t *); 63 static void igb_setup_mac_rss_classify(igb_t *); 64 static void igb_setup_mac_classify(igb_t *); 65 static void igb_init_unicst(igb_t *); 66 static void igb_setup_multicst(igb_t *); 67 static void igb_get_phy_state(igb_t *); 68 static void igb_get_conf(igb_t *); 69 static int igb_get_prop(igb_t *, char *, int, int, int); 70 static boolean_t igb_is_link_up(igb_t *); 71 static boolean_t igb_link_check(igb_t *); 72 static void igb_local_timer(void *); 73 static void igb_arm_watchdog_timer(igb_t *); 74 static void igb_start_watchdog_timer(igb_t *); 75 static void igb_restart_watchdog_timer(igb_t *); 76 static void igb_stop_watchdog_timer(igb_t *); 77 static void igb_disable_adapter_interrupts(igb_t *); 78 static void igb_enable_adapter_interrupts(igb_t *); 79 static boolean_t is_valid_mac_addr(uint8_t *); 80 static boolean_t igb_stall_check(igb_t *); 81 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 82 static void igb_set_external_loopback(igb_t *); 83 static void igb_set_internal_mac_loopback(igb_t *); 84 static void igb_set_internal_phy_loopback(igb_t *); 85 static void igb_set_internal_serdes_loopback(igb_t *); 86 static boolean_t igb_find_mac_address(igb_t *); 87 static int igb_alloc_intrs(igb_t *); 88 static int igb_alloc_intr_handles(igb_t *, int); 89 static int igb_add_intr_handlers(igb_t *); 90 static void igb_rem_intr_handlers(igb_t *); 91 static void igb_rem_intrs(igb_t *); 92 static int igb_enable_intrs(igb_t *); 93 static int igb_disable_intrs(igb_t *); 94 static void igb_setup_adapter_msix(igb_t *); 95 static uint_t igb_intr_legacy(void *, void *); 96 static uint_t igb_intr_msi(void *, void *); 97 static uint_t igb_intr_rx(void *, void *); 98 static uint_t igb_intr_tx(void *, void *); 99 static uint_t igb_intr_tx_other(void *, void *); 100 static void igb_intr_rx_work(igb_rx_ring_t *); 101 static void igb_intr_tx_work(igb_tx_ring_t *); 102 static void igb_intr_link_work(igb_t *); 103 static void igb_get_driver_control(struct e1000_hw *); 104 static void igb_release_driver_control(struct e1000_hw *); 105 106 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 107 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 108 static int igb_resume(dev_info_t *); 109 static int igb_suspend(dev_info_t *); 110 static int igb_quiesce(dev_info_t *); 111 static void igb_unconfigure(dev_info_t *, igb_t *); 112 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 113 const void *); 114 static void igb_fm_init(igb_t *); 115 static void igb_fm_fini(igb_t *); 116 117 118 static struct cb_ops igb_cb_ops = { 119 nulldev, /* cb_open */ 120 nulldev, /* cb_close */ 121 nodev, /* cb_strategy */ 122 nodev, /* cb_print */ 123 nodev, /* cb_dump */ 124 nodev, /* cb_read */ 125 nodev, /* cb_write */ 126 nodev, /* cb_ioctl */ 127 nodev, /* cb_devmap */ 128 nodev, /* cb_mmap */ 129 nodev, /* cb_segmap */ 130 nochpoll, /* cb_chpoll */ 131 ddi_prop_op, /* cb_prop_op */ 132 NULL, /* cb_stream */ 133 D_MP | D_HOTPLUG, /* cb_flag */ 134 CB_REV, /* cb_rev */ 135 nodev, /* cb_aread */ 136 nodev /* cb_awrite */ 137 }; 138 139 static struct dev_ops igb_dev_ops = { 140 DEVO_REV, /* devo_rev */ 141 0, /* devo_refcnt */ 142 NULL, /* devo_getinfo */ 143 nulldev, /* devo_identify */ 144 nulldev, /* devo_probe */ 145 igb_attach, /* devo_attach */ 146 igb_detach, /* devo_detach */ 147 nodev, /* devo_reset */ 148 &igb_cb_ops, /* devo_cb_ops */ 149 NULL, /* devo_bus_ops */ 150 ddi_power, /* devo_power */ 151 igb_quiesce, /* devo_quiesce */ 152 }; 153 154 static struct modldrv igb_modldrv = { 155 &mod_driverops, /* Type of module. This one is a driver */ 156 ident, /* Discription string */ 157 &igb_dev_ops, /* driver ops */ 158 }; 159 160 static struct modlinkage igb_modlinkage = { 161 MODREV_1, &igb_modldrv, NULL 162 }; 163 164 /* Access attributes for register mapping */ 165 ddi_device_acc_attr_t igb_regs_acc_attr = { 166 DDI_DEVICE_ATTR_V0, 167 DDI_STRUCTURE_LE_ACC, 168 DDI_STRICTORDER_ACC, 169 DDI_FLAGERR_ACC 170 }; 171 172 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 173 174 static mac_callbacks_t igb_m_callbacks = { 175 IGB_M_CALLBACK_FLAGS, 176 igb_m_stat, 177 igb_m_start, 178 igb_m_stop, 179 igb_m_promisc, 180 igb_m_multicst, 181 NULL, 182 NULL, 183 igb_m_ioctl, 184 igb_m_getcapab 185 }; 186 187 /* 188 * Module Initialization Functions 189 */ 190 191 int 192 _init(void) 193 { 194 int status; 195 196 mac_init_ops(&igb_dev_ops, MODULE_NAME); 197 198 status = mod_install(&igb_modlinkage); 199 200 if (status != DDI_SUCCESS) { 201 mac_fini_ops(&igb_dev_ops); 202 } 203 204 return (status); 205 } 206 207 int 208 _fini(void) 209 { 210 int status; 211 212 status = mod_remove(&igb_modlinkage); 213 214 if (status == DDI_SUCCESS) { 215 mac_fini_ops(&igb_dev_ops); 216 } 217 218 return (status); 219 220 } 221 222 int 223 _info(struct modinfo *modinfop) 224 { 225 int status; 226 227 status = mod_info(&igb_modlinkage, modinfop); 228 229 return (status); 230 } 231 232 /* 233 * igb_attach - driver attach 234 * 235 * This function is the device specific initialization entry 236 * point. This entry point is required and must be written. 237 * The DDI_ATTACH command must be provided in the attach entry 238 * point. When attach() is called with cmd set to DDI_ATTACH, 239 * all normal kernel services (such as kmem_alloc(9F)) are 240 * available for use by the driver. 241 * 242 * The attach() function will be called once for each instance 243 * of the device on the system with cmd set to DDI_ATTACH. 244 * Until attach() succeeds, the only driver entry points which 245 * may be called are open(9E) and getinfo(9E). 246 */ 247 static int 248 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 249 { 250 igb_t *igb; 251 struct igb_osdep *osdep; 252 struct e1000_hw *hw; 253 int instance; 254 255 /* 256 * Check the command and perform corresponding operations 257 */ 258 switch (cmd) { 259 default: 260 return (DDI_FAILURE); 261 262 case DDI_RESUME: 263 return (igb_resume(devinfo)); 264 265 case DDI_ATTACH: 266 break; 267 } 268 269 /* Get the device instance */ 270 instance = ddi_get_instance(devinfo); 271 272 /* Allocate memory for the instance data structure */ 273 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 274 275 igb->dip = devinfo; 276 igb->instance = instance; 277 278 hw = &igb->hw; 279 osdep = &igb->osdep; 280 hw->back = osdep; 281 osdep->igb = igb; 282 283 /* Attach the instance pointer to the dev_info data structure */ 284 ddi_set_driver_private(devinfo, igb); 285 286 287 /* Initialize for fma support */ 288 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 289 0, 0x0f, 290 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 291 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 292 igb_fm_init(igb); 293 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 294 295 /* 296 * Map PCI config space registers 297 */ 298 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 299 igb_error(igb, "Failed to map PCI configurations"); 300 goto attach_fail; 301 } 302 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 303 304 /* 305 * Identify the chipset family 306 */ 307 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 308 igb_error(igb, "Failed to identify hardware"); 309 goto attach_fail; 310 } 311 312 /* 313 * Map device registers 314 */ 315 if (igb_regs_map(igb) != IGB_SUCCESS) { 316 igb_error(igb, "Failed to map device registers"); 317 goto attach_fail; 318 } 319 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 320 321 /* 322 * Initialize driver parameters 323 */ 324 igb_init_properties(igb); 325 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 326 327 /* 328 * Allocate interrupts 329 */ 330 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 331 igb_error(igb, "Failed to allocate interrupts"); 332 goto attach_fail; 333 } 334 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 335 336 /* 337 * Allocate rx/tx rings based on the ring numbers. 338 * The actual numbers of rx/tx rings are decided by the number of 339 * allocated interrupt vectors, so we should allocate the rings after 340 * interrupts are allocated. 341 */ 342 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 343 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 344 goto attach_fail; 345 } 346 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 347 348 /* 349 * Add interrupt handlers 350 */ 351 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 352 igb_error(igb, "Failed to add interrupt handlers"); 353 goto attach_fail; 354 } 355 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 356 357 /* 358 * Initialize driver parameters 359 */ 360 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 361 igb_error(igb, "Failed to initialize driver settings"); 362 goto attach_fail; 363 } 364 365 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 366 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 367 goto attach_fail; 368 } 369 370 /* 371 * Initialize mutexes for this device. 372 * Do this before enabling the interrupt handler and 373 * register the softint to avoid the condition where 374 * interrupt handler can try using uninitialized mutex 375 */ 376 igb_init_locks(igb); 377 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 378 379 /* 380 * Initialize chipset hardware 381 */ 382 mutex_enter(&igb->gen_lock); 383 if (igb_init(igb) != IGB_SUCCESS) { 384 mutex_exit(&igb->gen_lock); 385 igb_error(igb, "Failed to initialize adapter"); 386 goto attach_fail; 387 } 388 mutex_exit(&igb->gen_lock); 389 igb->attach_progress |= ATTACH_PROGRESS_INIT; 390 391 /* 392 * Initialize DMA and hardware settings for rx/tx rings 393 */ 394 if (igb_init_rings(igb) != IGB_SUCCESS) { 395 igb_error(igb, "Failed to initialize rings"); 396 goto attach_fail; 397 } 398 igb->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 399 400 /* 401 * Initialize statistics 402 */ 403 if (igb_init_stats(igb) != IGB_SUCCESS) { 404 igb_error(igb, "Failed to initialize statistics"); 405 goto attach_fail; 406 } 407 igb->attach_progress |= ATTACH_PROGRESS_STATS; 408 409 /* 410 * Initialize NDD parameters 411 */ 412 if (igb_nd_init(igb) != IGB_SUCCESS) { 413 igb_error(igb, "Failed to initialize ndd"); 414 goto attach_fail; 415 } 416 igb->attach_progress |= ATTACH_PROGRESS_NDD; 417 418 /* 419 * Register the driver to the MAC 420 */ 421 if (igb_register_mac(igb) != IGB_SUCCESS) { 422 igb_error(igb, "Failed to register MAC"); 423 goto attach_fail; 424 } 425 igb->attach_progress |= ATTACH_PROGRESS_MAC; 426 427 /* 428 * Now that mutex locks are initialized, and the chip is also 429 * initialized, enable interrupts. 430 */ 431 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 432 igb_error(igb, "Failed to enable DDI interrupts"); 433 goto attach_fail; 434 } 435 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 436 437 igb->igb_state |= IGB_INITIALIZED; 438 439 return (DDI_SUCCESS); 440 441 attach_fail: 442 igb_unconfigure(devinfo, igb); 443 return (DDI_FAILURE); 444 } 445 446 /* 447 * igb_detach - driver detach 448 * 449 * The detach() function is the complement of the attach routine. 450 * If cmd is set to DDI_DETACH, detach() is used to remove the 451 * state associated with a given instance of a device node 452 * prior to the removal of that instance from the system. 453 * 454 * The detach() function will be called once for each instance 455 * of the device for which there has been a successful attach() 456 * once there are no longer any opens on the device. 457 * 458 * Interrupts routine are disabled, All memory allocated by this 459 * driver are freed. 460 */ 461 static int 462 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 463 { 464 igb_t *igb; 465 466 /* 467 * Check detach command 468 */ 469 switch (cmd) { 470 default: 471 return (DDI_FAILURE); 472 473 case DDI_SUSPEND: 474 return (igb_suspend(devinfo)); 475 476 case DDI_DETACH: 477 break; 478 } 479 480 481 /* 482 * Get the pointer to the driver private data structure 483 */ 484 igb = (igb_t *)ddi_get_driver_private(devinfo); 485 if (igb == NULL) 486 return (DDI_FAILURE); 487 488 /* 489 * Unregister MAC. If failed, we have to fail the detach 490 */ 491 if (mac_unregister(igb->mac_hdl) != 0) { 492 igb_error(igb, "Failed to unregister MAC"); 493 return (DDI_FAILURE); 494 } 495 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 496 497 /* 498 * If the device is still running, it needs to be stopped first. 499 * This check is necessary because under some specific circumstances, 500 * the detach routine can be called without stopping the interface 501 * first. 502 */ 503 mutex_enter(&igb->gen_lock); 504 if (igb->igb_state & IGB_STARTED) { 505 igb->igb_state &= ~IGB_STARTED; 506 igb_stop(igb); 507 mutex_exit(&igb->gen_lock); 508 /* Disable and stop the watchdog timer */ 509 igb_disable_watchdog_timer(igb); 510 } else 511 mutex_exit(&igb->gen_lock); 512 513 /* 514 * Check if there are still rx buffers held by the upper layer. 515 * If so, fail the detach. 516 */ 517 if (!igb_rx_drain(igb)) 518 return (DDI_FAILURE); 519 520 /* 521 * Do the remaining unconfigure routines 522 */ 523 igb_unconfigure(devinfo, igb); 524 525 return (DDI_SUCCESS); 526 } 527 528 /* 529 * quiesce(9E) entry point. 530 * 531 * This function is called when the system is single-threaded at high 532 * PIL with preemption disabled. Therefore, this function must not be 533 * blocked. 534 * 535 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 536 * DDI_FAILURE indicates an error condition and should almost never happen. 537 */ 538 static int 539 igb_quiesce(dev_info_t *devinfo) 540 { 541 igb_t *igb; 542 struct e1000_hw *hw; 543 544 igb = (igb_t *)ddi_get_driver_private(devinfo); 545 546 if (igb == NULL) 547 return (DDI_FAILURE); 548 549 hw = &igb->hw; 550 551 /* 552 * Disable the adapter interrupts 553 */ 554 igb_disable_adapter_interrupts(igb); 555 556 /* Tell firmware driver is no longer in control */ 557 igb_release_driver_control(hw); 558 559 /* 560 * Reset the chipset 561 */ 562 (void) e1000_reset_hw(hw); 563 564 /* 565 * Reset PHY if possible 566 */ 567 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 568 (void) e1000_phy_hw_reset(hw); 569 570 return (DDI_SUCCESS); 571 } 572 573 574 static void 575 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 576 { 577 /* 578 * Disable interrupt 579 */ 580 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 581 (void) igb_disable_intrs(igb); 582 } 583 584 /* 585 * Unregister MAC 586 */ 587 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 588 (void) mac_unregister(igb->mac_hdl); 589 } 590 591 /* 592 * Free ndd parameters 593 */ 594 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 595 igb_nd_cleanup(igb); 596 } 597 598 /* 599 * Free statistics 600 */ 601 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 602 kstat_delete((kstat_t *)igb->igb_ks); 603 } 604 605 /* 606 * Remove interrupt handlers 607 */ 608 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 609 igb_rem_intr_handlers(igb); 610 } 611 612 /* 613 * Remove interrupts 614 */ 615 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 616 igb_rem_intrs(igb); 617 } 618 619 /* 620 * Remove driver properties 621 */ 622 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 623 (void) ddi_prop_remove_all(devinfo); 624 } 625 626 /* 627 * Release the DMA resources of rx/tx rings 628 */ 629 if (igb->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 630 igb_fini_rings(igb); 631 } 632 633 /* 634 * Stop the chipset 635 */ 636 if (igb->attach_progress & ATTACH_PROGRESS_INIT) { 637 mutex_enter(&igb->gen_lock); 638 igb_chip_stop(igb); 639 mutex_exit(&igb->gen_lock); 640 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 641 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 642 } 643 644 /* 645 * Free register handle 646 */ 647 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 648 if (igb->osdep.reg_handle != NULL) 649 ddi_regs_map_free(&igb->osdep.reg_handle); 650 } 651 652 /* 653 * Free PCI config handle 654 */ 655 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 656 if (igb->osdep.cfg_handle != NULL) 657 pci_config_teardown(&igb->osdep.cfg_handle); 658 } 659 660 /* 661 * Free locks 662 */ 663 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 664 igb_destroy_locks(igb); 665 } 666 667 /* 668 * Free the rx/tx rings 669 */ 670 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 671 igb_free_rings(igb); 672 } 673 674 /* 675 * Remove FMA 676 */ 677 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 678 igb_fm_fini(igb); 679 } 680 681 /* 682 * Free device specific structure 683 */ 684 e1000_remove_device(&igb->hw); 685 686 /* 687 * Free the driver data structure 688 */ 689 kmem_free(igb, sizeof (igb_t)); 690 691 ddi_set_driver_private(devinfo, NULL); 692 } 693 694 /* 695 * igb_register_mac - Register the driver and its function pointers with 696 * the GLD interface 697 */ 698 static int 699 igb_register_mac(igb_t *igb) 700 { 701 struct e1000_hw *hw = &igb->hw; 702 mac_register_t *mac; 703 int status; 704 705 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 706 return (IGB_FAILURE); 707 708 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 709 mac->m_driver = igb; 710 mac->m_dip = igb->dip; 711 mac->m_src_addr = hw->mac.addr; 712 mac->m_callbacks = &igb_m_callbacks; 713 mac->m_min_sdu = 0; 714 mac->m_max_sdu = igb->max_frame_size - 715 sizeof (struct ether_vlan_header) - ETHERFCSL; 716 mac->m_margin = VLAN_TAGSZ; 717 mac->m_v12n = MAC_VIRT_LEVEL1; 718 719 status = mac_register(mac, &igb->mac_hdl); 720 721 mac_free(mac); 722 723 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 724 } 725 726 /* 727 * igb_identify_hardware - Identify the type of the chipset 728 */ 729 static int 730 igb_identify_hardware(igb_t *igb) 731 { 732 struct e1000_hw *hw = &igb->hw; 733 struct igb_osdep *osdep = &igb->osdep; 734 735 /* 736 * Get the device id 737 */ 738 hw->vendor_id = 739 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 740 hw->device_id = 741 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 742 hw->revision_id = 743 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 744 hw->subsystem_device_id = 745 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 746 hw->subsystem_vendor_id = 747 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 748 749 /* 750 * Set the mac type of the adapter based on the device id 751 */ 752 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 753 return (IGB_FAILURE); 754 } 755 756 return (IGB_SUCCESS); 757 } 758 759 /* 760 * igb_regs_map - Map the device registers 761 */ 762 static int 763 igb_regs_map(igb_t *igb) 764 { 765 dev_info_t *devinfo = igb->dip; 766 struct e1000_hw *hw = &igb->hw; 767 struct igb_osdep *osdep = &igb->osdep; 768 off_t mem_size; 769 770 /* 771 * First get the size of device registers to be mapped. 772 */ 773 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 774 return (IGB_FAILURE); 775 } 776 777 /* 778 * Call ddi_regs_map_setup() to map registers 779 */ 780 if ((ddi_regs_map_setup(devinfo, 1, 781 (caddr_t *)&hw->hw_addr, 0, 782 mem_size, &igb_regs_acc_attr, 783 &osdep->reg_handle)) != DDI_SUCCESS) { 784 return (IGB_FAILURE); 785 } 786 787 return (IGB_SUCCESS); 788 } 789 790 /* 791 * igb_init_properties - Initialize driver properties 792 */ 793 static void 794 igb_init_properties(igb_t *igb) 795 { 796 /* 797 * Get conf file properties, including link settings 798 * jumbo frames, ring number, descriptor number, etc. 799 */ 800 igb_get_conf(igb); 801 } 802 803 /* 804 * igb_init_driver_settings - Initialize driver settings 805 * 806 * The settings include hardware function pointers, bus information, 807 * rx/tx rings settings, link state, and any other parameters that 808 * need to be setup during driver initialization. 809 */ 810 static int 811 igb_init_driver_settings(igb_t *igb) 812 { 813 struct e1000_hw *hw = &igb->hw; 814 igb_rx_ring_t *rx_ring; 815 igb_tx_ring_t *tx_ring; 816 uint32_t rx_size; 817 uint32_t tx_size; 818 int i; 819 820 /* 821 * Initialize chipset specific hardware function pointers 822 */ 823 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 824 return (IGB_FAILURE); 825 } 826 827 /* 828 * Get bus information 829 */ 830 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 831 return (IGB_FAILURE); 832 } 833 834 /* 835 * Set rx buffer size 836 * The IP header alignment room is counted in the calculation. 837 * The rx buffer size is in unit of 1K that is required by the 838 * chipset hardware. 839 */ 840 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 841 igb->rx_buf_size = ((rx_size >> 10) + 842 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 843 844 /* 845 * Set tx buffer size 846 */ 847 tx_size = igb->max_frame_size; 848 igb->tx_buf_size = ((tx_size >> 10) + 849 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 850 851 /* 852 * Initialize rx/tx rings parameters 853 */ 854 for (i = 0; i < igb->num_rx_rings; i++) { 855 rx_ring = &igb->rx_rings[i]; 856 rx_ring->index = i; 857 rx_ring->igb = igb; 858 859 rx_ring->ring_size = igb->rx_ring_size; 860 rx_ring->free_list_size = igb->rx_ring_size; 861 rx_ring->copy_thresh = igb->rx_copy_thresh; 862 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 863 } 864 865 for (i = 0; i < igb->num_tx_rings; i++) { 866 tx_ring = &igb->tx_rings[i]; 867 tx_ring->index = i; 868 tx_ring->igb = igb; 869 if (igb->tx_head_wb_enable) 870 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 871 else 872 tx_ring->tx_recycle = igb_tx_recycle_legacy; 873 874 tx_ring->ring_size = igb->tx_ring_size; 875 tx_ring->free_list_size = igb->tx_ring_size + 876 (igb->tx_ring_size >> 1); 877 tx_ring->copy_thresh = igb->tx_copy_thresh; 878 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 879 tx_ring->overload_thresh = igb->tx_overload_thresh; 880 tx_ring->resched_thresh = igb->tx_resched_thresh; 881 } 882 883 /* 884 * Initialize values of interrupt throttling rate 885 */ 886 for (i = 1; i < MAX_NUM_EITR; i++) 887 igb->intr_throttling[i] = igb->intr_throttling[0]; 888 889 /* 890 * The initial link state should be "unknown" 891 */ 892 igb->link_state = LINK_STATE_UNKNOWN; 893 894 return (IGB_SUCCESS); 895 } 896 897 /* 898 * igb_init_locks - Initialize locks 899 */ 900 static void 901 igb_init_locks(igb_t *igb) 902 { 903 igb_rx_ring_t *rx_ring; 904 igb_tx_ring_t *tx_ring; 905 int i; 906 907 for (i = 0; i < igb->num_rx_rings; i++) { 908 rx_ring = &igb->rx_rings[i]; 909 mutex_init(&rx_ring->rx_lock, NULL, 910 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 911 mutex_init(&rx_ring->recycle_lock, NULL, 912 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 913 } 914 915 for (i = 0; i < igb->num_tx_rings; i++) { 916 tx_ring = &igb->tx_rings[i]; 917 mutex_init(&tx_ring->tx_lock, NULL, 918 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 919 mutex_init(&tx_ring->recycle_lock, NULL, 920 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 921 mutex_init(&tx_ring->tcb_head_lock, NULL, 922 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 923 mutex_init(&tx_ring->tcb_tail_lock, NULL, 924 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 925 } 926 927 mutex_init(&igb->gen_lock, NULL, 928 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 929 930 mutex_init(&igb->watchdog_lock, NULL, 931 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 932 } 933 934 /* 935 * igb_destroy_locks - Destroy locks 936 */ 937 static void 938 igb_destroy_locks(igb_t *igb) 939 { 940 igb_rx_ring_t *rx_ring; 941 igb_tx_ring_t *tx_ring; 942 int i; 943 944 for (i = 0; i < igb->num_rx_rings; i++) { 945 rx_ring = &igb->rx_rings[i]; 946 mutex_destroy(&rx_ring->rx_lock); 947 mutex_destroy(&rx_ring->recycle_lock); 948 } 949 950 for (i = 0; i < igb->num_tx_rings; i++) { 951 tx_ring = &igb->tx_rings[i]; 952 mutex_destroy(&tx_ring->tx_lock); 953 mutex_destroy(&tx_ring->recycle_lock); 954 mutex_destroy(&tx_ring->tcb_head_lock); 955 mutex_destroy(&tx_ring->tcb_tail_lock); 956 } 957 958 mutex_destroy(&igb->gen_lock); 959 mutex_destroy(&igb->watchdog_lock); 960 } 961 962 static int 963 igb_resume(dev_info_t *devinfo) 964 { 965 igb_t *igb; 966 967 igb = (igb_t *)ddi_get_driver_private(devinfo); 968 if (igb == NULL) 969 return (DDI_FAILURE); 970 971 mutex_enter(&igb->gen_lock); 972 973 if (igb->igb_state & IGB_STARTED) { 974 if (igb_start(igb) != IGB_SUCCESS) { 975 mutex_exit(&igb->gen_lock); 976 return (DDI_FAILURE); 977 } 978 979 /* 980 * Enable and start the watchdog timer 981 */ 982 igb_enable_watchdog_timer(igb); 983 } 984 985 igb->igb_state &= ~IGB_SUSPENDED; 986 987 mutex_exit(&igb->gen_lock); 988 989 return (DDI_SUCCESS); 990 } 991 992 static int 993 igb_suspend(dev_info_t *devinfo) 994 { 995 igb_t *igb; 996 997 igb = (igb_t *)ddi_get_driver_private(devinfo); 998 if (igb == NULL) 999 return (DDI_FAILURE); 1000 1001 mutex_enter(&igb->gen_lock); 1002 1003 igb->igb_state |= IGB_SUSPENDED; 1004 1005 igb_stop(igb); 1006 1007 mutex_exit(&igb->gen_lock); 1008 1009 /* 1010 * Disable and stop the watchdog timer 1011 */ 1012 igb_disable_watchdog_timer(igb); 1013 1014 return (DDI_SUCCESS); 1015 } 1016 1017 /* 1018 * igb_init - Initialize the device 1019 */ 1020 static int 1021 igb_init(igb_t *igb) 1022 { 1023 struct e1000_hw *hw = &igb->hw; 1024 uint32_t pba; 1025 uint32_t high_water; 1026 1027 ASSERT(mutex_owned(&igb->gen_lock)); 1028 1029 /* 1030 * Reset chipset to put the hardware in a known state 1031 * before we try to do anything with the eeprom 1032 */ 1033 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1034 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1035 goto init_fail; 1036 } 1037 1038 /* 1039 * NVM validation 1040 */ 1041 if (e1000_validate_nvm_checksum(hw) < 0) { 1042 /* 1043 * Some PCI-E parts fail the first check due to 1044 * the link being in sleep state. Call it again, 1045 * if it fails a second time its a real issue. 1046 */ 1047 if (e1000_validate_nvm_checksum(hw) < 0) { 1048 igb_error(igb, 1049 "Invalid NVM checksum. Please contact " 1050 "the vendor to update the NVM."); 1051 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1052 goto init_fail; 1053 } 1054 } 1055 1056 /* 1057 * Set the FIFO size 1058 */ 1059 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1060 E1000_WRITE_REG(hw, E1000_PBA, pba); 1061 1062 /* 1063 * Setup flow control 1064 * 1065 * These parameters set thresholds for the adapter's generation(Tx) 1066 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1067 * settings. Flow control is enabled or disabled in the configuration 1068 * file. 1069 * High-water mark is set down from the top of the rx fifo (not 1070 * sensitive to max_frame_size) and low-water is set just below 1071 * high-water mark. 1072 * The high water mark must be low enough to fit one full frame above 1073 * it in the rx FIFO. Should be the lower of: 1074 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1075 * frame. 1076 */ 1077 high_water = min(((pba << 10) * 9 / 10), 1078 ((pba << 10) - igb->max_frame_size)); 1079 1080 hw->fc.high_water = high_water & 0xFFF8; 1081 hw->fc.low_water = hw->fc.high_water - 8; 1082 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1083 hw->fc.send_xon = B_TRUE; 1084 1085 /* 1086 * Reset the chipset hardware the second time to validate 1087 * the PBA setting. 1088 */ 1089 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1090 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1091 goto init_fail; 1092 } 1093 1094 /* 1095 * Don't wait for auto-negotiation to complete 1096 */ 1097 hw->phy.autoneg_wait_to_complete = B_FALSE; 1098 1099 /* 1100 * Copper options 1101 */ 1102 if (hw->phy.media_type == e1000_media_type_copper) { 1103 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1104 hw->phy.disable_polarity_correction = B_FALSE; 1105 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1106 } 1107 1108 /* 1109 * Initialize link settings 1110 */ 1111 (void) igb_setup_link(igb, B_FALSE); 1112 1113 /* 1114 * Initialize the chipset hardware 1115 */ 1116 if (igb_chip_start(igb) != IGB_SUCCESS) { 1117 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1118 goto init_fail; 1119 } 1120 1121 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 1122 goto init_fail; 1123 } 1124 1125 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 1126 goto init_fail; 1127 } 1128 1129 return (IGB_SUCCESS); 1130 1131 init_fail: 1132 /* 1133 * Reset PHY if possible 1134 */ 1135 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1136 (void) e1000_phy_hw_reset(hw); 1137 1138 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1139 1140 return (IGB_FAILURE); 1141 } 1142 1143 /* 1144 * igb_init_rings - Allocate DMA resources for all rx/tx rings and 1145 * initialize relevant hardware settings. 1146 */ 1147 static int 1148 igb_init_rings(igb_t *igb) 1149 { 1150 int i; 1151 1152 /* 1153 * Allocate buffers for all the rx/tx rings 1154 */ 1155 if (igb_alloc_dma(igb) != IGB_SUCCESS) 1156 return (IGB_FAILURE); 1157 1158 /* 1159 * Setup the rx/tx rings 1160 */ 1161 mutex_enter(&igb->gen_lock); 1162 1163 for (i = 0; i < igb->num_rx_rings; i++) 1164 mutex_enter(&igb->rx_rings[i].rx_lock); 1165 for (i = 0; i < igb->num_tx_rings; i++) 1166 mutex_enter(&igb->tx_rings[i].tx_lock); 1167 1168 igb_setup_rings(igb); 1169 1170 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1171 mutex_exit(&igb->tx_rings[i].tx_lock); 1172 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1173 mutex_exit(&igb->rx_rings[i].rx_lock); 1174 1175 mutex_exit(&igb->gen_lock); 1176 1177 return (IGB_SUCCESS); 1178 } 1179 1180 /* 1181 * igb_fini_rings - Release DMA resources of all rx/tx rings 1182 */ 1183 static void 1184 igb_fini_rings(igb_t *igb) 1185 { 1186 /* 1187 * Release the DMA/memory resources of rx/tx rings 1188 */ 1189 igb_free_dma(igb); 1190 } 1191 1192 /* 1193 * igb_chip_start - Initialize and start the chipset hardware 1194 */ 1195 static int 1196 igb_chip_start(igb_t *igb) 1197 { 1198 struct e1000_hw *hw = &igb->hw; 1199 int i; 1200 1201 ASSERT(mutex_owned(&igb->gen_lock)); 1202 1203 /* 1204 * Get the mac address 1205 * This function should handle SPARC case correctly. 1206 */ 1207 if (!igb_find_mac_address(igb)) { 1208 igb_error(igb, "Failed to get the mac address"); 1209 return (IGB_FAILURE); 1210 } 1211 1212 /* Validate mac address */ 1213 if (!is_valid_mac_addr(hw->mac.addr)) { 1214 igb_error(igb, "Invalid mac address"); 1215 return (IGB_FAILURE); 1216 } 1217 1218 /* Disable wakeup control by default */ 1219 E1000_WRITE_REG(hw, E1000_WUC, 0); 1220 1221 /* 1222 * Configure/Initialize hardware 1223 */ 1224 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1225 igb_error(igb, "Failed to initialize hardware"); 1226 return (IGB_FAILURE); 1227 } 1228 1229 /* 1230 * Make sure driver has control 1231 */ 1232 igb_get_driver_control(hw); 1233 1234 /* 1235 * Setup MSI-X interrupts 1236 */ 1237 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1238 igb_setup_adapter_msix(igb); 1239 1240 /* 1241 * Initialize unicast addresses. 1242 */ 1243 igb_init_unicst(igb); 1244 1245 /* 1246 * Setup and initialize the mctable structures. 1247 */ 1248 igb_setup_multicst(igb); 1249 1250 /* 1251 * Set interrupt throttling rate 1252 */ 1253 for (i = 0; i < igb->intr_cnt; i++) 1254 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1255 1256 /* Enable PCI-E master */ 1257 if (hw->bus.type == e1000_bus_type_pci_express) { 1258 e1000_enable_pciex_master(hw); 1259 } 1260 1261 /* 1262 * Save the state of the phy 1263 */ 1264 igb_get_phy_state(igb); 1265 1266 return (IGB_SUCCESS); 1267 } 1268 1269 /* 1270 * igb_chip_stop - Stop the chipset hardware 1271 */ 1272 static void 1273 igb_chip_stop(igb_t *igb) 1274 { 1275 struct e1000_hw *hw = &igb->hw; 1276 1277 ASSERT(mutex_owned(&igb->gen_lock)); 1278 1279 /* Tell firmware driver is no longer in control */ 1280 igb_release_driver_control(hw); 1281 1282 /* 1283 * Reset the chipset 1284 */ 1285 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1286 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1287 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1288 } 1289 1290 /* 1291 * Reset PHY if possible 1292 */ 1293 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1294 (void) e1000_phy_hw_reset(hw); 1295 } 1296 1297 /* 1298 * igb_reset - Reset the chipset and restart the driver. 1299 * 1300 * It involves stopping and re-starting the chipset, 1301 * and re-configuring the rx/tx rings. 1302 */ 1303 static int 1304 igb_reset(igb_t *igb) 1305 { 1306 int i; 1307 1308 mutex_enter(&igb->gen_lock); 1309 1310 ASSERT(igb->igb_state & IGB_STARTED); 1311 1312 /* 1313 * Disable the adapter interrupts to stop any rx/tx activities 1314 * before draining pending data and resetting hardware. 1315 */ 1316 igb_disable_adapter_interrupts(igb); 1317 1318 /* 1319 * Drain the pending transmit packets 1320 */ 1321 (void) igb_tx_drain(igb); 1322 1323 for (i = 0; i < igb->num_rx_rings; i++) 1324 mutex_enter(&igb->rx_rings[i].rx_lock); 1325 for (i = 0; i < igb->num_tx_rings; i++) 1326 mutex_enter(&igb->tx_rings[i].tx_lock); 1327 1328 /* 1329 * Stop the chipset hardware 1330 */ 1331 igb_chip_stop(igb); 1332 1333 /* 1334 * Clean the pending tx data/resources 1335 */ 1336 igb_tx_clean(igb); 1337 1338 /* 1339 * Start the chipset hardware 1340 */ 1341 if (igb_chip_start(igb) != IGB_SUCCESS) { 1342 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1343 goto reset_failure; 1344 } 1345 1346 /* 1347 * Setup the rx/tx rings 1348 */ 1349 igb_setup_rings(igb); 1350 1351 /* 1352 * Enable adapter interrupts 1353 * The interrupts must be enabled after the driver state is START 1354 */ 1355 igb_enable_adapter_interrupts(igb); 1356 1357 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1358 goto reset_failure; 1359 1360 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1361 goto reset_failure; 1362 1363 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1364 mutex_exit(&igb->tx_rings[i].tx_lock); 1365 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1366 mutex_exit(&igb->rx_rings[i].rx_lock); 1367 1368 mutex_exit(&igb->gen_lock); 1369 1370 return (IGB_SUCCESS); 1371 1372 reset_failure: 1373 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1374 mutex_exit(&igb->tx_rings[i].tx_lock); 1375 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1376 mutex_exit(&igb->rx_rings[i].rx_lock); 1377 1378 mutex_exit(&igb->gen_lock); 1379 1380 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1381 1382 return (IGB_FAILURE); 1383 } 1384 1385 /* 1386 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1387 */ 1388 static void 1389 igb_tx_clean(igb_t *igb) 1390 { 1391 igb_tx_ring_t *tx_ring; 1392 tx_control_block_t *tcb; 1393 link_list_t pending_list; 1394 uint32_t desc_num; 1395 int i, j; 1396 1397 LINK_LIST_INIT(&pending_list); 1398 1399 for (i = 0; i < igb->num_tx_rings; i++) { 1400 tx_ring = &igb->tx_rings[i]; 1401 1402 mutex_enter(&tx_ring->recycle_lock); 1403 1404 /* 1405 * Clean the pending tx data - the pending packets in the 1406 * work_list that have no chances to be transmitted again. 1407 * 1408 * We must ensure the chipset is stopped or the link is down 1409 * before cleaning the transmit packets. 1410 */ 1411 desc_num = 0; 1412 for (j = 0; j < tx_ring->ring_size; j++) { 1413 tcb = tx_ring->work_list[j]; 1414 if (tcb != NULL) { 1415 desc_num += tcb->desc_num; 1416 1417 tx_ring->work_list[j] = NULL; 1418 1419 igb_free_tcb(tcb); 1420 1421 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1422 } 1423 } 1424 1425 if (desc_num > 0) { 1426 atomic_add_32(&tx_ring->tbd_free, desc_num); 1427 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1428 1429 /* 1430 * Reset the head and tail pointers of the tbd ring; 1431 * Reset the head write-back if it is enabled. 1432 */ 1433 tx_ring->tbd_head = 0; 1434 tx_ring->tbd_tail = 0; 1435 if (igb->tx_head_wb_enable) 1436 *tx_ring->tbd_head_wb = 0; 1437 1438 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1439 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1440 } 1441 1442 mutex_exit(&tx_ring->recycle_lock); 1443 1444 /* 1445 * Add the tx control blocks in the pending list to 1446 * the free list. 1447 */ 1448 igb_put_free_list(tx_ring, &pending_list); 1449 } 1450 } 1451 1452 /* 1453 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1454 */ 1455 static boolean_t 1456 igb_tx_drain(igb_t *igb) 1457 { 1458 igb_tx_ring_t *tx_ring; 1459 boolean_t done; 1460 int i, j; 1461 1462 /* 1463 * Wait for a specific time to allow pending tx packets 1464 * to be transmitted. 1465 * 1466 * Check the counter tbd_free to see if transmission is done. 1467 * No lock protection is needed here. 1468 * 1469 * Return B_TRUE if all pending packets have been transmitted; 1470 * Otherwise return B_FALSE; 1471 */ 1472 for (i = 0; i < TX_DRAIN_TIME; i++) { 1473 1474 done = B_TRUE; 1475 for (j = 0; j < igb->num_tx_rings; j++) { 1476 tx_ring = &igb->tx_rings[j]; 1477 done = done && 1478 (tx_ring->tbd_free == tx_ring->ring_size); 1479 } 1480 1481 if (done) 1482 break; 1483 1484 msec_delay(1); 1485 } 1486 1487 return (done); 1488 } 1489 1490 /* 1491 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1492 */ 1493 static boolean_t 1494 igb_rx_drain(igb_t *igb) 1495 { 1496 igb_rx_ring_t *rx_ring; 1497 boolean_t done; 1498 int i, j; 1499 1500 /* 1501 * Polling the rx free list to check if those rx buffers held by 1502 * the upper layer are released. 1503 * 1504 * Check the counter rcb_free to see if all pending buffers are 1505 * released. No lock protection is needed here. 1506 * 1507 * Return B_TRUE if all pending buffers have been released; 1508 * Otherwise return B_FALSE; 1509 */ 1510 for (i = 0; i < RX_DRAIN_TIME; i++) { 1511 1512 done = B_TRUE; 1513 for (j = 0; j < igb->num_rx_rings; j++) { 1514 rx_ring = &igb->rx_rings[j]; 1515 done = done && 1516 (rx_ring->rcb_free == rx_ring->free_list_size); 1517 } 1518 1519 if (done) 1520 break; 1521 1522 msec_delay(1); 1523 } 1524 1525 return (done); 1526 } 1527 1528 /* 1529 * igb_start - Start the driver/chipset 1530 */ 1531 int 1532 igb_start(igb_t *igb) 1533 { 1534 int i; 1535 1536 ASSERT(mutex_owned(&igb->gen_lock)); 1537 1538 for (i = 0; i < igb->num_rx_rings; i++) 1539 mutex_enter(&igb->rx_rings[i].rx_lock); 1540 for (i = 0; i < igb->num_tx_rings; i++) 1541 mutex_enter(&igb->tx_rings[i].tx_lock); 1542 1543 /* 1544 * Start the chipset hardware 1545 */ 1546 if (!(igb->attach_progress & ATTACH_PROGRESS_INIT)) { 1547 if (igb_init(igb) != IGB_SUCCESS) { 1548 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1549 goto start_failure; 1550 } 1551 igb->attach_progress |= ATTACH_PROGRESS_INIT; 1552 } 1553 1554 /* 1555 * Setup the rx/tx rings 1556 */ 1557 igb_setup_rings(igb); 1558 1559 /* 1560 * Enable adapter interrupts 1561 * The interrupts must be enabled after the driver state is START 1562 */ 1563 igb_enable_adapter_interrupts(igb); 1564 1565 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1566 goto start_failure; 1567 1568 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1569 goto start_failure; 1570 1571 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1572 mutex_exit(&igb->tx_rings[i].tx_lock); 1573 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1574 mutex_exit(&igb->rx_rings[i].rx_lock); 1575 1576 return (IGB_SUCCESS); 1577 1578 start_failure: 1579 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1580 mutex_exit(&igb->tx_rings[i].tx_lock); 1581 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1582 mutex_exit(&igb->rx_rings[i].rx_lock); 1583 1584 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1585 1586 return (IGB_FAILURE); 1587 } 1588 1589 /* 1590 * igb_stop - Stop the driver/chipset 1591 */ 1592 void 1593 igb_stop(igb_t *igb) 1594 { 1595 int i; 1596 1597 ASSERT(mutex_owned(&igb->gen_lock)); 1598 1599 igb->attach_progress &= ~ ATTACH_PROGRESS_INIT; 1600 1601 /* 1602 * Disable the adapter interrupts 1603 */ 1604 igb_disable_adapter_interrupts(igb); 1605 1606 /* 1607 * Drain the pending tx packets 1608 */ 1609 (void) igb_tx_drain(igb); 1610 1611 for (i = 0; i < igb->num_rx_rings; i++) 1612 mutex_enter(&igb->rx_rings[i].rx_lock); 1613 for (i = 0; i < igb->num_tx_rings; i++) 1614 mutex_enter(&igb->tx_rings[i].tx_lock); 1615 1616 /* 1617 * Stop the chipset hardware 1618 */ 1619 igb_chip_stop(igb); 1620 1621 /* 1622 * Clean the pending tx data/resources 1623 */ 1624 igb_tx_clean(igb); 1625 1626 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1627 mutex_exit(&igb->tx_rings[i].tx_lock); 1628 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1629 mutex_exit(&igb->rx_rings[i].rx_lock); 1630 1631 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1632 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1633 } 1634 1635 /* 1636 * igb_alloc_rings - Allocate memory space for rx/tx rings 1637 */ 1638 static int 1639 igb_alloc_rings(igb_t *igb) 1640 { 1641 /* 1642 * Allocate memory space for rx rings 1643 */ 1644 igb->rx_rings = kmem_zalloc( 1645 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1646 KM_NOSLEEP); 1647 1648 if (igb->rx_rings == NULL) { 1649 return (IGB_FAILURE); 1650 } 1651 1652 /* 1653 * Allocate memory space for tx rings 1654 */ 1655 igb->tx_rings = kmem_zalloc( 1656 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1657 KM_NOSLEEP); 1658 1659 if (igb->tx_rings == NULL) { 1660 kmem_free(igb->rx_rings, 1661 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1662 igb->rx_rings = NULL; 1663 return (IGB_FAILURE); 1664 } 1665 1666 /* 1667 * Allocate memory space for rx ring groups 1668 */ 1669 igb->rx_groups = kmem_zalloc( 1670 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1671 KM_NOSLEEP); 1672 1673 if (igb->rx_groups == NULL) { 1674 kmem_free(igb->rx_rings, 1675 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1676 kmem_free(igb->tx_rings, 1677 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1678 igb->rx_rings = NULL; 1679 igb->tx_rings = NULL; 1680 return (IGB_FAILURE); 1681 } 1682 1683 return (IGB_SUCCESS); 1684 } 1685 1686 /* 1687 * igb_free_rings - Free the memory space of rx/tx rings. 1688 */ 1689 static void 1690 igb_free_rings(igb_t *igb) 1691 { 1692 if (igb->rx_rings != NULL) { 1693 kmem_free(igb->rx_rings, 1694 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1695 igb->rx_rings = NULL; 1696 } 1697 1698 if (igb->tx_rings != NULL) { 1699 kmem_free(igb->tx_rings, 1700 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1701 igb->tx_rings = NULL; 1702 } 1703 1704 if (igb->rx_groups != NULL) { 1705 kmem_free(igb->rx_groups, 1706 sizeof (igb_rx_group_t) * igb->num_rx_groups); 1707 igb->rx_groups = NULL; 1708 } 1709 } 1710 1711 /* 1712 * igb_setup_rings - Setup rx/tx rings 1713 */ 1714 static void 1715 igb_setup_rings(igb_t *igb) 1716 { 1717 /* 1718 * Setup the rx/tx rings, including the following: 1719 * 1720 * 1. Setup the descriptor ring and the control block buffers; 1721 * 2. Initialize necessary registers for receive/transmit; 1722 * 3. Initialize software pointers/parameters for receive/transmit; 1723 */ 1724 igb_setup_rx(igb); 1725 1726 igb_setup_tx(igb); 1727 1728 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1729 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1730 } 1731 1732 static void 1733 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1734 { 1735 igb_t *igb = rx_ring->igb; 1736 struct e1000_hw *hw = &igb->hw; 1737 rx_control_block_t *rcb; 1738 union e1000_adv_rx_desc *rbd; 1739 uint32_t size; 1740 uint32_t buf_low; 1741 uint32_t buf_high; 1742 uint32_t reg_val; 1743 int i; 1744 1745 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1746 ASSERT(mutex_owned(&igb->gen_lock)); 1747 1748 for (i = 0; i < igb->rx_ring_size; i++) { 1749 rcb = rx_ring->work_list[i]; 1750 rbd = &rx_ring->rbd_ring[i]; 1751 1752 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1753 rbd->read.hdr_addr = NULL; 1754 } 1755 1756 /* 1757 * Initialize the length register 1758 */ 1759 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1760 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1761 1762 /* 1763 * Initialize the base address registers 1764 */ 1765 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1766 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1767 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1768 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1769 1770 /* 1771 * Setup head & tail pointers 1772 */ 1773 E1000_WRITE_REG(hw, E1000_RDT(rx_ring->index), rx_ring->ring_size - 1); 1774 E1000_WRITE_REG(hw, E1000_RDH(rx_ring->index), 0); 1775 1776 rx_ring->rbd_next = 0; 1777 1778 /* 1779 * Note: Considering the case that the chipset is being reset 1780 * and there are still some buffers held by the upper layer, 1781 * we should not reset the values of rcb_head, rcb_tail and 1782 * rcb_free; 1783 */ 1784 if (igb->igb_state == IGB_UNKNOWN) { 1785 rx_ring->rcb_head = 0; 1786 rx_ring->rcb_tail = 0; 1787 rx_ring->rcb_free = rx_ring->free_list_size; 1788 } 1789 1790 /* 1791 * Setup the Receive Descriptor Control Register (RXDCTL) 1792 */ 1793 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1794 reg_val |= E1000_RXDCTL_QUEUE_ENABLE; 1795 reg_val &= 0xFFF00000; 1796 reg_val |= 16; /* pthresh */ 1797 reg_val |= 8 << 8; /* hthresh */ 1798 reg_val |= 1 << 16; /* wthresh */ 1799 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), reg_val); 1800 1801 /* 1802 * Setup the Split and Replication Receive Control Register. 1803 * Set the rx buffer size and the advanced descriptor type. 1804 */ 1805 reg_val = (igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1806 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 1807 1808 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), reg_val); 1809 } 1810 1811 static void 1812 igb_setup_rx(igb_t *igb) 1813 { 1814 igb_rx_ring_t *rx_ring; 1815 igb_rx_group_t *rx_group; 1816 struct e1000_hw *hw = &igb->hw; 1817 uint32_t reg_val; 1818 uint32_t ring_per_group; 1819 int i; 1820 1821 /* 1822 * Setup the Receive Control Register (RCTL), and ENABLE the 1823 * receiver. The initial configuration is to: Enable the receiver, 1824 * accept broadcasts, discard bad packets (and long packets), 1825 * disable VLAN filter checking, set the receive descriptor 1826 * minimum threshold size to 1/2, and the receive buffer size to 1827 * 2k. 1828 */ 1829 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 1830 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1831 E1000_RCTL_LPE | /* Large Packet Enable bit */ 1832 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1833 E1000_RCTL_RDMTS_HALF | 1834 E1000_RCTL_SECRC | /* Strip Ethernet CRC */ 1835 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 1836 1837 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 1838 1839 for (i = 0; i < igb->num_rx_groups; i++) { 1840 rx_group = &igb->rx_groups[i]; 1841 rx_group->index = i; 1842 rx_group->igb = igb; 1843 } 1844 1845 /* 1846 * igb_setup_rx_ring must be called after configuring RCTL 1847 */ 1848 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 1849 for (i = 0; i < igb->num_rx_rings; i++) { 1850 rx_ring = &igb->rx_rings[i]; 1851 igb_setup_rx_ring(rx_ring); 1852 1853 /* 1854 * Map a ring to a group by assigning a group index 1855 */ 1856 rx_ring->group_index = i / ring_per_group; 1857 } 1858 1859 /* 1860 * Setup the Rx Long Packet Max Length register 1861 */ 1862 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1863 1864 /* 1865 * Hardware checksum settings 1866 */ 1867 if (igb->rx_hcksum_enable) { 1868 reg_val = 1869 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1870 E1000_RXCSUM_IPOFL; /* IP checksum */ 1871 1872 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 1873 } 1874 1875 /* 1876 * Setup classify and RSS for multiple receive queues 1877 */ 1878 switch (igb->vmdq_mode) { 1879 case E1000_VMDQ_OFF: 1880 /* 1881 * One ring group, only RSS is needed when more than 1882 * one ring enabled. 1883 */ 1884 if (igb->num_rx_rings > 1) 1885 igb_setup_rss(igb); 1886 break; 1887 case E1000_VMDQ_MAC: 1888 /* 1889 * Multiple groups, each group has one ring, 1890 * only the MAC classification is needed. 1891 */ 1892 igb_setup_mac_classify(igb); 1893 break; 1894 case E1000_VMDQ_MAC_RSS: 1895 /* 1896 * Multiple groups and multiple rings, both 1897 * MAC classification and RSS are needed. 1898 */ 1899 igb_setup_mac_rss_classify(igb); 1900 break; 1901 } 1902 } 1903 1904 static void 1905 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 1906 { 1907 igb_t *igb = tx_ring->igb; 1908 struct e1000_hw *hw = &igb->hw; 1909 uint32_t size; 1910 uint32_t buf_low; 1911 uint32_t buf_high; 1912 uint32_t reg_val; 1913 1914 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1915 ASSERT(mutex_owned(&igb->gen_lock)); 1916 1917 1918 /* 1919 * Initialize the length register 1920 */ 1921 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 1922 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 1923 1924 /* 1925 * Initialize the base address registers 1926 */ 1927 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1928 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1929 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 1930 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 1931 1932 /* 1933 * Setup head & tail pointers 1934 */ 1935 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 1936 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 1937 1938 /* 1939 * Setup head write-back 1940 */ 1941 if (igb->tx_head_wb_enable) { 1942 /* 1943 * The memory of the head write-back is allocated using 1944 * the extra tbd beyond the tail of the tbd ring. 1945 */ 1946 tx_ring->tbd_head_wb = (uint32_t *) 1947 ((uintptr_t)tx_ring->tbd_area.address + size); 1948 *tx_ring->tbd_head_wb = 0; 1949 1950 buf_low = (uint32_t) 1951 (tx_ring->tbd_area.dma_address + size); 1952 buf_high = (uint32_t) 1953 ((tx_ring->tbd_area.dma_address + size) >> 32); 1954 1955 /* Set the head write-back enable bit */ 1956 buf_low |= E1000_TX_HEAD_WB_ENABLE; 1957 1958 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 1959 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 1960 1961 /* 1962 * Turn off relaxed ordering for head write back or it will 1963 * cause problems with the tx recycling 1964 */ 1965 reg_val = E1000_READ_REG(hw, 1966 E1000_DCA_TXCTRL(tx_ring->index)); 1967 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 1968 E1000_WRITE_REG(hw, 1969 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 1970 } else { 1971 tx_ring->tbd_head_wb = NULL; 1972 } 1973 1974 tx_ring->tbd_head = 0; 1975 tx_ring->tbd_tail = 0; 1976 tx_ring->tbd_free = tx_ring->ring_size; 1977 1978 /* 1979 * Note: Considering the case that the chipset is being reset, 1980 * and there are still some buffers held by the upper layer, 1981 * we should not reset the values of tcb_head, tcb_tail. 1982 */ 1983 if (igb->igb_state == IGB_UNKNOWN) { 1984 tx_ring->tcb_head = 0; 1985 tx_ring->tcb_tail = 0; 1986 tx_ring->tcb_free = tx_ring->free_list_size; 1987 } else { 1988 ASSERT(tx_ring->tcb_free == tx_ring->free_list_size); 1989 } 1990 1991 /* 1992 * Enable specific tx ring, it is required by multiple tx 1993 * ring support. 1994 */ 1995 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 1996 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 1997 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 1998 1999 /* 2000 * Initialize hardware checksum offload settings 2001 */ 2002 tx_ring->hcksum_context.hcksum_flags = 0; 2003 tx_ring->hcksum_context.ip_hdr_len = 0; 2004 tx_ring->hcksum_context.mac_hdr_len = 0; 2005 tx_ring->hcksum_context.l4_proto = 0; 2006 } 2007 2008 static void 2009 igb_setup_tx(igb_t *igb) 2010 { 2011 igb_tx_ring_t *tx_ring; 2012 struct e1000_hw *hw = &igb->hw; 2013 uint32_t reg_val; 2014 int i; 2015 2016 for (i = 0; i < igb->num_tx_rings; i++) { 2017 tx_ring = &igb->tx_rings[i]; 2018 igb_setup_tx_ring(tx_ring); 2019 } 2020 2021 /* 2022 * Setup the Transmit Control Register (TCTL) 2023 */ 2024 reg_val = E1000_TCTL_PSP | E1000_TCTL_EN | 2025 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 2026 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 2027 E1000_TCTL_RTLC; 2028 2029 /* Enable the MULR bit */ 2030 if (hw->bus.type == e1000_bus_type_pci_express) 2031 reg_val |= E1000_TCTL_MULR; 2032 2033 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2034 2035 /* 2036 * Set the default values for the Tx Inter Packet Gap timer 2037 */ 2038 if (hw->phy.media_type == e1000_media_type_fiber) 2039 reg_val = DEFAULT_82543_TIPG_IPGT_FIBER; 2040 else 2041 reg_val = DEFAULT_82543_TIPG_IPGT_COPPER; 2042 reg_val |= 2043 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2044 reg_val |= 2045 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2046 2047 E1000_WRITE_REG(hw, E1000_TIPG, reg_val); 2048 } 2049 2050 /* 2051 * igb_setup_rss - Setup receive-side scaling feature 2052 */ 2053 static void 2054 igb_setup_rss(igb_t *igb) 2055 { 2056 struct e1000_hw *hw = &igb->hw; 2057 uint32_t i, mrqc, rxcsum; 2058 int shift; 2059 uint32_t random; 2060 union e1000_reta { 2061 uint32_t dword; 2062 uint8_t bytes[4]; 2063 } reta; 2064 2065 /* Setup the Redirection Table */ 2066 shift = 6; 2067 for (i = 0; i < (32 * 4); i++) { 2068 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2069 if ((i & 3) == 3) { 2070 E1000_WRITE_REG(hw, 2071 (E1000_RETA(0) + (i & ~3)), reta.dword); 2072 } 2073 } 2074 2075 /* Fill out hash function seeds */ 2076 for (i = 0; i < 10; i++) { 2077 (void) random_get_pseudo_bytes((uint8_t *)&random, 2078 sizeof (uint32_t)); 2079 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2080 } 2081 2082 /* Setup the Multiple Receive Queue Control register */ 2083 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2084 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2085 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2086 E1000_MRQC_RSS_FIELD_IPV6 | 2087 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2088 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2089 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2090 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2091 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2092 2093 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2094 2095 /* 2096 * Disable Packet Checksum to enable RSS for multiple receive queues. 2097 * 2098 * The Packet Checksum is not ethernet CRC. It is another kind of 2099 * checksum offloading provided by the 82575 chipset besides the IP 2100 * header checksum offloading and the TCP/UDP checksum offloading. 2101 * The Packet Checksum is by default computed over the entire packet 2102 * from the first byte of the DA through the last byte of the CRC, 2103 * including the Ethernet and IP headers. 2104 * 2105 * It is a hardware limitation that Packet Checksum is mutually 2106 * exclusive with RSS. 2107 */ 2108 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2109 rxcsum |= E1000_RXCSUM_PCSD; 2110 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2111 } 2112 2113 /* 2114 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2115 */ 2116 static void 2117 igb_setup_mac_rss_classify(igb_t *igb) 2118 { 2119 struct e1000_hw *hw = &igb->hw; 2120 uint32_t i, mrqc, vmdctl, rxcsum; 2121 uint32_t ring_per_group; 2122 int shift_group0, shift_group1; 2123 uint32_t random; 2124 union e1000_reta { 2125 uint32_t dword; 2126 uint8_t bytes[4]; 2127 } reta; 2128 2129 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2130 2131 /* Setup the Redirection Table, it is shared between two groups */ 2132 shift_group0 = 2; 2133 shift_group1 = 6; 2134 for (i = 0; i < (32 * 4); i++) { 2135 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2136 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2137 if ((i & 3) == 3) { 2138 E1000_WRITE_REG(hw, 2139 (E1000_RETA(0) + (i & ~3)), reta.dword); 2140 } 2141 } 2142 2143 /* Fill out hash function seeds */ 2144 for (i = 0; i < 10; i++) { 2145 (void) random_get_pseudo_bytes((uint8_t *)&random, 2146 sizeof (uint32_t)); 2147 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2148 } 2149 2150 /* 2151 * Setup the Multiple Receive Queue Control register, 2152 * enable VMDq based on packet destination MAC address and RSS. 2153 */ 2154 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2155 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2156 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2157 E1000_MRQC_RSS_FIELD_IPV6 | 2158 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2159 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2160 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2161 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2162 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2163 2164 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2165 2166 2167 /* Define the default group and default queues */ 2168 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2169 E1000_WRITE_REG(hw, E1000_VMD_CTL, vmdctl); 2170 2171 /* 2172 * Disable Packet Checksum to enable RSS for multiple receive queues. 2173 * 2174 * The Packet Checksum is not ethernet CRC. It is another kind of 2175 * checksum offloading provided by the 82575 chipset besides the IP 2176 * header checksum offloading and the TCP/UDP checksum offloading. 2177 * The Packet Checksum is by default computed over the entire packet 2178 * from the first byte of the DA through the last byte of the CRC, 2179 * including the Ethernet and IP headers. 2180 * 2181 * It is a hardware limitation that Packet Checksum is mutually 2182 * exclusive with RSS. 2183 */ 2184 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2185 rxcsum |= E1000_RXCSUM_PCSD; 2186 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2187 } 2188 2189 /* 2190 * igb_setup_mac_classify - Setup MAC classification feature 2191 */ 2192 static void 2193 igb_setup_mac_classify(igb_t *igb) 2194 { 2195 struct e1000_hw *hw = &igb->hw; 2196 uint32_t mrqc, rxcsum; 2197 2198 /* 2199 * Setup the Multiple Receive Queue Control register, 2200 * enable VMDq based on packet destination MAC address. 2201 */ 2202 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2203 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2204 2205 /* 2206 * Disable Packet Checksum to enable RSS for multiple receive queues. 2207 * 2208 * The Packet Checksum is not ethernet CRC. It is another kind of 2209 * checksum offloading provided by the 82575 chipset besides the IP 2210 * header checksum offloading and the TCP/UDP checksum offloading. 2211 * The Packet Checksum is by default computed over the entire packet 2212 * from the first byte of the DA through the last byte of the CRC, 2213 * including the Ethernet and IP headers. 2214 * 2215 * It is a hardware limitation that Packet Checksum is mutually 2216 * exclusive with RSS. 2217 */ 2218 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2219 rxcsum |= E1000_RXCSUM_PCSD; 2220 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2221 2222 } 2223 2224 /* 2225 * igb_init_unicst - Initialize the unicast addresses 2226 */ 2227 static void 2228 igb_init_unicst(igb_t *igb) 2229 { 2230 struct e1000_hw *hw = &igb->hw; 2231 int slot; 2232 2233 /* 2234 * Here we should consider two situations: 2235 * 2236 * 1. Chipset is initialized the first time 2237 * Initialize the multiple unicast addresses, and 2238 * save the default MAC address. 2239 * 2240 * 2. Chipset is reset 2241 * Recover the multiple unicast addresses from the 2242 * software data structure to the RAR registers. 2243 */ 2244 2245 /* 2246 * Clear the default MAC address in the RAR0 rgister, 2247 * which is loaded from EEPROM when system boot or chipreset, 2248 * this will cause the conficts with add_mac/rem_mac entry 2249 * points when VMDq is enabled. For this reason, the RAR0 2250 * must be cleared for both cases mentioned above. 2251 */ 2252 e1000_rar_clear(hw, 0); 2253 2254 if (!igb->unicst_init) { 2255 2256 /* Initialize the multiple unicast addresses */ 2257 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2258 igb->unicst_avail = igb->unicst_total; 2259 2260 for (slot = 0; slot < igb->unicst_total; slot++) 2261 igb->unicst_addr[slot].mac.set = 0; 2262 2263 igb->unicst_init = B_TRUE; 2264 } else { 2265 /* Re-configure the RAR registers */ 2266 for (slot = 0; slot < igb->unicst_total; slot++) { 2267 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2268 slot, igb->vmdq_mode, 2269 igb->unicst_addr[slot].mac.group_index); 2270 } 2271 } 2272 2273 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2274 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2275 } 2276 2277 /* 2278 * igb_unicst_find - Find the slot for the specified unicast address 2279 */ 2280 int 2281 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2282 { 2283 int slot; 2284 2285 ASSERT(mutex_owned(&igb->gen_lock)); 2286 2287 for (slot = 0; slot < igb->unicst_total; slot++) { 2288 if (bcmp(igb->unicst_addr[slot].mac.addr, 2289 mac_addr, ETHERADDRL) == 0) 2290 return (slot); 2291 } 2292 2293 return (-1); 2294 } 2295 2296 /* 2297 * igb_unicst_set - Set the unicast address to the specified slot 2298 */ 2299 int 2300 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2301 int slot) 2302 { 2303 struct e1000_hw *hw = &igb->hw; 2304 2305 ASSERT(mutex_owned(&igb->gen_lock)); 2306 2307 /* 2308 * Save the unicast address in the software data structure 2309 */ 2310 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2311 2312 /* 2313 * Set the unicast address to the RAR register 2314 */ 2315 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2316 2317 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2318 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2319 return (EIO); 2320 } 2321 2322 return (0); 2323 } 2324 2325 /* 2326 * igb_multicst_add - Add a multicst address 2327 */ 2328 int 2329 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2330 { 2331 ASSERT(mutex_owned(&igb->gen_lock)); 2332 2333 if ((multiaddr[0] & 01) == 0) { 2334 return (EINVAL); 2335 } 2336 2337 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2338 return (ENOENT); 2339 } 2340 2341 bcopy(multiaddr, 2342 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2343 igb->mcast_count++; 2344 2345 /* 2346 * Update the multicast table in the hardware 2347 */ 2348 igb_setup_multicst(igb); 2349 2350 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2351 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2352 return (EIO); 2353 } 2354 2355 return (0); 2356 } 2357 2358 /* 2359 * igb_multicst_remove - Remove a multicst address 2360 */ 2361 int 2362 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2363 { 2364 int i; 2365 2366 ASSERT(mutex_owned(&igb->gen_lock)); 2367 2368 for (i = 0; i < igb->mcast_count; i++) { 2369 if (bcmp(multiaddr, &igb->mcast_table[i], 2370 ETHERADDRL) == 0) { 2371 for (i++; i < igb->mcast_count; i++) { 2372 igb->mcast_table[i - 1] = 2373 igb->mcast_table[i]; 2374 } 2375 igb->mcast_count--; 2376 break; 2377 } 2378 } 2379 2380 /* 2381 * Update the multicast table in the hardware 2382 */ 2383 igb_setup_multicst(igb); 2384 2385 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2386 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2387 return (EIO); 2388 } 2389 2390 return (0); 2391 } 2392 2393 /* 2394 * igb_setup_multicast - setup multicast data structures 2395 * 2396 * This routine initializes all of the multicast related structures 2397 * and save them in the hardware registers. 2398 */ 2399 static void 2400 igb_setup_multicst(igb_t *igb) 2401 { 2402 uint8_t *mc_addr_list; 2403 uint32_t mc_addr_count; 2404 struct e1000_hw *hw = &igb->hw; 2405 2406 ASSERT(mutex_owned(&igb->gen_lock)); 2407 2408 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2409 2410 mc_addr_list = (uint8_t *)igb->mcast_table; 2411 mc_addr_count = igb->mcast_count; 2412 2413 /* 2414 * Update the multicase addresses to the MTA registers 2415 */ 2416 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2417 igb->unicst_total, hw->mac.rar_entry_count); 2418 } 2419 2420 /* 2421 * igb_get_conf - Get driver configurations set in driver.conf 2422 * 2423 * This routine gets user-configured values out of the configuration 2424 * file igb.conf. 2425 * 2426 * For each configurable value, there is a minimum, a maximum, and a 2427 * default. 2428 * If user does not configure a value, use the default. 2429 * If user configures below the minimum, use the minumum. 2430 * If user configures above the maximum, use the maxumum. 2431 */ 2432 static void 2433 igb_get_conf(igb_t *igb) 2434 { 2435 struct e1000_hw *hw = &igb->hw; 2436 uint32_t default_mtu; 2437 uint32_t flow_control; 2438 uint32_t ring_per_group; 2439 int i; 2440 2441 /* 2442 * igb driver supports the following user configurations: 2443 * 2444 * Link configurations: 2445 * adv_autoneg_cap 2446 * adv_1000fdx_cap 2447 * adv_100fdx_cap 2448 * adv_100hdx_cap 2449 * adv_10fdx_cap 2450 * adv_10hdx_cap 2451 * Note: 1000hdx is not supported. 2452 * 2453 * Jumbo frame configuration: 2454 * default_mtu 2455 * 2456 * Ethernet flow control configuration: 2457 * flow_control 2458 * 2459 * Multiple rings configurations: 2460 * tx_queue_number 2461 * tx_ring_size 2462 * rx_queue_number 2463 * rx_ring_size 2464 * 2465 * Call igb_get_prop() to get the value for a specific 2466 * configuration parameter. 2467 */ 2468 2469 /* 2470 * Link configurations 2471 */ 2472 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2473 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2474 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2475 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2476 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2477 PROP_ADV_100FDX_CAP, 0, 1, 1); 2478 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2479 PROP_ADV_100HDX_CAP, 0, 1, 1); 2480 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2481 PROP_ADV_10FDX_CAP, 0, 1, 1); 2482 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2483 PROP_ADV_10HDX_CAP, 0, 1, 1); 2484 2485 /* 2486 * Jumbo frame configurations 2487 */ 2488 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2489 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2490 2491 igb->max_frame_size = default_mtu + 2492 sizeof (struct ether_vlan_header) + ETHERFCSL; 2493 2494 /* 2495 * Ethernet flow control configuration 2496 */ 2497 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2498 e1000_fc_none, 4, e1000_fc_full); 2499 if (flow_control == 4) 2500 flow_control = e1000_fc_default; 2501 2502 hw->fc.type = flow_control; 2503 2504 /* 2505 * Multiple rings configurations 2506 */ 2507 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2508 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2509 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2510 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2511 2512 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 1); 2513 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2514 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2515 2516 if (igb->mr_enable) { 2517 igb->num_tx_rings = DEFAULT_TX_QUEUE_NUM; 2518 igb->num_rx_rings = DEFAULT_RX_QUEUE_NUM; 2519 } else { 2520 igb->num_tx_rings = 1; 2521 igb->num_rx_rings = 1; 2522 2523 if (igb->num_rx_groups > 1) { 2524 igb_error(igb, 2525 "Invalid rx groups number. Please enable multiple " 2526 "rings first"); 2527 igb->num_rx_groups = 1; 2528 } 2529 } 2530 2531 /* 2532 * Check the divisibility between rx rings and rx groups. 2533 */ 2534 for (i = igb->num_rx_groups; i > 0; i--) { 2535 if ((igb->num_rx_rings % i) == 0) 2536 break; 2537 } 2538 if (i != igb->num_rx_groups) { 2539 igb_error(igb, 2540 "Invalid rx groups number. Downgrade the rx group " 2541 "number to %d.", i); 2542 igb->num_rx_groups = i; 2543 } 2544 2545 /* 2546 * Get the ring number per group. 2547 */ 2548 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2549 2550 if (igb->num_rx_groups == 1) { 2551 /* 2552 * One rx ring group, the rx ring number is num_rx_rings. 2553 */ 2554 igb->vmdq_mode = E1000_VMDQ_OFF; 2555 } else if (ring_per_group == 1) { 2556 /* 2557 * Multiple rx groups, each group has one rx ring. 2558 */ 2559 igb->vmdq_mode = E1000_VMDQ_MAC; 2560 } else { 2561 /* 2562 * Multiple groups and multiple rings. 2563 */ 2564 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2565 } 2566 2567 /* 2568 * Tunable used to force an interrupt type. The only use is 2569 * for testing of the lesser interrupt types. 2570 * 0 = don't force interrupt type 2571 * 1 = force interrupt type MSIX 2572 * 2 = force interrupt type MSI 2573 * 3 = force interrupt type Legacy 2574 */ 2575 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2576 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2577 2578 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2579 0, 1, 1); 2580 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2581 0, 1, 1); 2582 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2583 0, 1, 0); 2584 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2585 0, 1, 1); 2586 2587 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2588 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2589 DEFAULT_TX_COPY_THRESHOLD); 2590 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2591 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2592 DEFAULT_TX_RECYCLE_THRESHOLD); 2593 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2594 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2595 DEFAULT_TX_OVERLOAD_THRESHOLD); 2596 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2597 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2598 DEFAULT_TX_RESCHED_THRESHOLD); 2599 2600 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2601 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2602 DEFAULT_RX_COPY_THRESHOLD); 2603 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2604 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2605 DEFAULT_RX_LIMIT_PER_INTR); 2606 2607 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2608 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2609 DEFAULT_INTR_THROTTLING); 2610 } 2611 2612 /* 2613 * igb_get_prop - Get a property value out of the configuration file igb.conf 2614 * 2615 * Caller provides the name of the property, a default value, a minimum 2616 * value, and a maximum value. 2617 * 2618 * Return configured value of the property, with default, minimum and 2619 * maximum properly applied. 2620 */ 2621 static int 2622 igb_get_prop(igb_t *igb, 2623 char *propname, /* name of the property */ 2624 int minval, /* minimum acceptable value */ 2625 int maxval, /* maximim acceptable value */ 2626 int defval) /* default value */ 2627 { 2628 int value; 2629 2630 /* 2631 * Call ddi_prop_get_int() to read the conf settings 2632 */ 2633 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2634 DDI_PROP_DONTPASS, propname, defval); 2635 2636 if (value > maxval) 2637 value = maxval; 2638 2639 if (value < minval) 2640 value = minval; 2641 2642 return (value); 2643 } 2644 2645 /* 2646 * igb_setup_link - Using the link properties to setup the link 2647 */ 2648 int 2649 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2650 { 2651 struct e1000_mac_info *mac; 2652 struct e1000_phy_info *phy; 2653 boolean_t invalid; 2654 2655 mac = &igb->hw.mac; 2656 phy = &igb->hw.phy; 2657 invalid = B_FALSE; 2658 2659 if (igb->param_adv_autoneg_cap == 1) { 2660 mac->autoneg = B_TRUE; 2661 phy->autoneg_advertised = 0; 2662 2663 /* 2664 * 1000hdx is not supported for autonegotiation 2665 */ 2666 if (igb->param_adv_1000fdx_cap == 1) 2667 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2668 2669 if (igb->param_adv_100fdx_cap == 1) 2670 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2671 2672 if (igb->param_adv_100hdx_cap == 1) 2673 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2674 2675 if (igb->param_adv_10fdx_cap == 1) 2676 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2677 2678 if (igb->param_adv_10hdx_cap == 1) 2679 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2680 2681 if (phy->autoneg_advertised == 0) 2682 invalid = B_TRUE; 2683 } else { 2684 mac->autoneg = B_FALSE; 2685 2686 /* 2687 * 1000fdx and 1000hdx are not supported for forced link 2688 */ 2689 if (igb->param_adv_100fdx_cap == 1) 2690 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2691 else if (igb->param_adv_100hdx_cap == 1) 2692 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2693 else if (igb->param_adv_10fdx_cap == 1) 2694 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2695 else if (igb->param_adv_10hdx_cap == 1) 2696 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2697 else 2698 invalid = B_TRUE; 2699 } 2700 2701 if (invalid) { 2702 igb_notice(igb, "Invalid link settings. Setup link to " 2703 "autonegotiation with full link capabilities."); 2704 mac->autoneg = B_TRUE; 2705 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2706 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2707 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2708 } 2709 2710 if (setup_hw) { 2711 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2712 return (IGB_FAILURE); 2713 } 2714 2715 return (IGB_SUCCESS); 2716 } 2717 2718 2719 /* 2720 * igb_is_link_up - Check if the link is up 2721 */ 2722 static boolean_t 2723 igb_is_link_up(igb_t *igb) 2724 { 2725 struct e1000_hw *hw = &igb->hw; 2726 boolean_t link_up; 2727 2728 ASSERT(mutex_owned(&igb->gen_lock)); 2729 2730 (void) e1000_check_for_link(hw); 2731 2732 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 2733 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 2734 (hw->mac.serdes_has_link))) { 2735 link_up = B_TRUE; 2736 } else { 2737 link_up = B_FALSE; 2738 } 2739 2740 return (link_up); 2741 } 2742 2743 /* 2744 * igb_link_check - Link status processing 2745 */ 2746 static boolean_t 2747 igb_link_check(igb_t *igb) 2748 { 2749 struct e1000_hw *hw = &igb->hw; 2750 uint16_t speed = 0, duplex = 0; 2751 boolean_t link_changed = B_FALSE; 2752 2753 ASSERT(mutex_owned(&igb->gen_lock)); 2754 2755 if (igb_is_link_up(igb)) { 2756 /* 2757 * The Link is up, check whether it was marked as down earlier 2758 */ 2759 if (igb->link_state != LINK_STATE_UP) { 2760 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2761 igb->link_speed = speed; 2762 igb->link_duplex = duplex; 2763 igb->link_state = LINK_STATE_UP; 2764 igb->link_down_timeout = 0; 2765 link_changed = B_TRUE; 2766 } 2767 } else { 2768 if (igb->link_state != LINK_STATE_DOWN) { 2769 igb->link_speed = 0; 2770 igb->link_duplex = 0; 2771 igb->link_state = LINK_STATE_DOWN; 2772 link_changed = B_TRUE; 2773 } 2774 2775 if (igb->igb_state & IGB_STARTED) { 2776 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2777 igb->link_down_timeout++; 2778 } else if (igb->link_down_timeout == 2779 MAX_LINK_DOWN_TIMEOUT) { 2780 igb_tx_clean(igb); 2781 igb->link_down_timeout++; 2782 } 2783 } 2784 } 2785 2786 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2787 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2788 2789 return (link_changed); 2790 } 2791 2792 /* 2793 * igb_local_timer - driver watchdog function 2794 * 2795 * This function will handle the transmit stall check, link status check and 2796 * other routines. 2797 */ 2798 static void 2799 igb_local_timer(void *arg) 2800 { 2801 igb_t *igb = (igb_t *)arg; 2802 struct e1000_hw *hw = &igb->hw; 2803 boolean_t link_changed; 2804 2805 if (igb_stall_check(igb)) { 2806 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 2807 igb->reset_count++; 2808 if (igb_reset(igb) == IGB_SUCCESS) 2809 ddi_fm_service_impact(igb->dip, 2810 DDI_SERVICE_RESTORED); 2811 } 2812 2813 mutex_enter(&igb->gen_lock); 2814 link_changed = igb_link_check(igb); 2815 mutex_exit(&igb->gen_lock); 2816 2817 if (link_changed) 2818 mac_link_update(igb->mac_hdl, igb->link_state); 2819 2820 /* 2821 * Set Timer Interrupts 2822 */ 2823 if (igb->intr_type != DDI_INTR_TYPE_MSIX) 2824 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2825 2826 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2827 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2828 2829 igb_restart_watchdog_timer(igb); 2830 } 2831 2832 /* 2833 * igb_stall_check - check for transmit stall 2834 * 2835 * This function checks if the adapter is stalled (in transmit). 2836 * 2837 * It is called each time the watchdog timeout is invoked. 2838 * If the transmit descriptor reclaim continuously fails, 2839 * the watchdog value will increment by 1. If the watchdog 2840 * value exceeds the threshold, the igb is assumed to 2841 * have stalled and need to be reset. 2842 */ 2843 static boolean_t 2844 igb_stall_check(igb_t *igb) 2845 { 2846 igb_tx_ring_t *tx_ring; 2847 boolean_t result; 2848 int i; 2849 2850 if (igb->link_state != LINK_STATE_UP) 2851 return (B_FALSE); 2852 2853 /* 2854 * If any tx ring is stalled, we'll reset the chipset 2855 */ 2856 result = B_FALSE; 2857 for (i = 0; i < igb->num_tx_rings; i++) { 2858 tx_ring = &igb->tx_rings[i]; 2859 2860 if (tx_ring->recycle_fail > 0) 2861 tx_ring->stall_watchdog++; 2862 else 2863 tx_ring->stall_watchdog = 0; 2864 2865 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2866 result = B_TRUE; 2867 break; 2868 } 2869 } 2870 2871 if (result) { 2872 tx_ring->stall_watchdog = 0; 2873 tx_ring->recycle_fail = 0; 2874 } 2875 2876 return (result); 2877 } 2878 2879 2880 /* 2881 * is_valid_mac_addr - Check if the mac address is valid 2882 */ 2883 static boolean_t 2884 is_valid_mac_addr(uint8_t *mac_addr) 2885 { 2886 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2887 const uint8_t addr_test2[6] = 2888 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2889 2890 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2891 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2892 return (B_FALSE); 2893 2894 return (B_TRUE); 2895 } 2896 2897 static boolean_t 2898 igb_find_mac_address(igb_t *igb) 2899 { 2900 struct e1000_hw *hw = &igb->hw; 2901 #ifdef __sparc 2902 uchar_t *bytes; 2903 struct ether_addr sysaddr; 2904 uint_t nelts; 2905 int err; 2906 boolean_t found = B_FALSE; 2907 2908 /* 2909 * The "vendor's factory-set address" may already have 2910 * been extracted from the chip, but if the property 2911 * "local-mac-address" is set we use that instead. 2912 * 2913 * We check whether it looks like an array of 6 2914 * bytes (which it should, if OBP set it). If we can't 2915 * make sense of it this way, we'll ignore it. 2916 */ 2917 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2918 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2919 if (err == DDI_PROP_SUCCESS) { 2920 if (nelts == ETHERADDRL) { 2921 while (nelts--) 2922 hw->mac.addr[nelts] = bytes[nelts]; 2923 found = B_TRUE; 2924 } 2925 ddi_prop_free(bytes); 2926 } 2927 2928 /* 2929 * Look up the OBP property "local-mac-address?". If the user has set 2930 * 'local-mac-address? = false', use "the system address" instead. 2931 */ 2932 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 2933 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2934 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2935 if (localetheraddr(NULL, &sysaddr) != 0) { 2936 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2937 found = B_TRUE; 2938 } 2939 } 2940 ddi_prop_free(bytes); 2941 } 2942 2943 /* 2944 * Finally(!), if there's a valid "mac-address" property (created 2945 * if we netbooted from this interface), we must use this instead 2946 * of any of the above to ensure that the NFS/install server doesn't 2947 * get confused by the address changing as Solaris takes over! 2948 */ 2949 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2950 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2951 if (err == DDI_PROP_SUCCESS) { 2952 if (nelts == ETHERADDRL) { 2953 while (nelts--) 2954 hw->mac.addr[nelts] = bytes[nelts]; 2955 found = B_TRUE; 2956 } 2957 ddi_prop_free(bytes); 2958 } 2959 2960 if (found) { 2961 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2962 return (B_TRUE); 2963 } 2964 #endif 2965 2966 /* 2967 * Read the device MAC address from the EEPROM 2968 */ 2969 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 2970 return (B_FALSE); 2971 2972 return (B_TRUE); 2973 } 2974 2975 #pragma inline(igb_arm_watchdog_timer) 2976 2977 static void 2978 igb_arm_watchdog_timer(igb_t *igb) 2979 { 2980 /* 2981 * Fire a watchdog timer 2982 */ 2983 igb->watchdog_tid = 2984 timeout(igb_local_timer, 2985 (void *)igb, 1 * drv_usectohz(1000000)); 2986 2987 } 2988 2989 /* 2990 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 2991 */ 2992 void 2993 igb_enable_watchdog_timer(igb_t *igb) 2994 { 2995 mutex_enter(&igb->watchdog_lock); 2996 2997 if (!igb->watchdog_enable) { 2998 igb->watchdog_enable = B_TRUE; 2999 igb->watchdog_start = B_TRUE; 3000 igb_arm_watchdog_timer(igb); 3001 } 3002 3003 mutex_exit(&igb->watchdog_lock); 3004 3005 } 3006 3007 /* 3008 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3009 */ 3010 void 3011 igb_disable_watchdog_timer(igb_t *igb) 3012 { 3013 timeout_id_t tid; 3014 3015 mutex_enter(&igb->watchdog_lock); 3016 3017 igb->watchdog_enable = B_FALSE; 3018 igb->watchdog_start = B_FALSE; 3019 tid = igb->watchdog_tid; 3020 igb->watchdog_tid = 0; 3021 3022 mutex_exit(&igb->watchdog_lock); 3023 3024 if (tid != 0) 3025 (void) untimeout(tid); 3026 3027 } 3028 3029 /* 3030 * igb_start_watchdog_timer - Start the driver watchdog timer 3031 */ 3032 static void 3033 igb_start_watchdog_timer(igb_t *igb) 3034 { 3035 mutex_enter(&igb->watchdog_lock); 3036 3037 if (igb->watchdog_enable) { 3038 if (!igb->watchdog_start) { 3039 igb->watchdog_start = B_TRUE; 3040 igb_arm_watchdog_timer(igb); 3041 } 3042 } 3043 3044 mutex_exit(&igb->watchdog_lock); 3045 } 3046 3047 /* 3048 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3049 */ 3050 static void 3051 igb_restart_watchdog_timer(igb_t *igb) 3052 { 3053 mutex_enter(&igb->watchdog_lock); 3054 3055 if (igb->watchdog_start) 3056 igb_arm_watchdog_timer(igb); 3057 3058 mutex_exit(&igb->watchdog_lock); 3059 } 3060 3061 /* 3062 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3063 */ 3064 static void 3065 igb_stop_watchdog_timer(igb_t *igb) 3066 { 3067 timeout_id_t tid; 3068 3069 mutex_enter(&igb->watchdog_lock); 3070 3071 igb->watchdog_start = B_FALSE; 3072 tid = igb->watchdog_tid; 3073 igb->watchdog_tid = 0; 3074 3075 mutex_exit(&igb->watchdog_lock); 3076 3077 if (tid != 0) 3078 (void) untimeout(tid); 3079 } 3080 3081 /* 3082 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3083 */ 3084 static void 3085 igb_disable_adapter_interrupts(igb_t *igb) 3086 { 3087 struct e1000_hw *hw = &igb->hw; 3088 3089 /* 3090 * Set the IMC register to mask all the interrupts, 3091 * including the tx interrupts. 3092 */ 3093 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3094 3095 /* 3096 * Additional disabling for MSI-X 3097 */ 3098 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3099 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3100 E1000_WRITE_REG(hw, E1000_EIAC, 0x0); 3101 } 3102 3103 E1000_WRITE_FLUSH(hw); 3104 } 3105 3106 /* 3107 * igb_enable_adapter_interrupts - Mask/enable all hardware interrupts 3108 */ 3109 static void 3110 igb_enable_adapter_interrupts(igb_t *igb) 3111 { 3112 struct e1000_hw *hw = &igb->hw; 3113 uint32_t reg; 3114 3115 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3116 /* Interrupt enabling for MSI-X */ 3117 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3118 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3119 igb->ims_mask = E1000_IMS_LSC; 3120 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3121 3122 /* Enable MSI-X PBA support */ 3123 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3124 reg |= E1000_CTRL_EXT_PBA_CLR; 3125 3126 /* Non-selective interrupt clear-on-read */ 3127 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3128 3129 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3130 } else { 3131 /* Interrupt enabling for MSI and legacy */ 3132 igb->ims_mask = IMS_ENABLE_MASK; 3133 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3134 } 3135 3136 E1000_WRITE_FLUSH(hw); 3137 } 3138 3139 /* 3140 * Loopback Support 3141 */ 3142 static lb_property_t lb_normal = 3143 { normal, "normal", IGB_LB_NONE }; 3144 static lb_property_t lb_external = 3145 { external, "External", IGB_LB_EXTERNAL }; 3146 static lb_property_t lb_mac = 3147 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 3148 static lb_property_t lb_phy = 3149 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3150 static lb_property_t lb_serdes = 3151 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3152 3153 enum ioc_reply 3154 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3155 { 3156 lb_info_sz_t *lbsp; 3157 lb_property_t *lbpp; 3158 struct e1000_hw *hw; 3159 uint32_t *lbmp; 3160 uint32_t size; 3161 uint32_t value; 3162 3163 hw = &igb->hw; 3164 3165 if (mp->b_cont == NULL) 3166 return (IOC_INVAL); 3167 3168 switch (iocp->ioc_cmd) { 3169 default: 3170 return (IOC_INVAL); 3171 3172 case LB_GET_INFO_SIZE: 3173 size = sizeof (lb_info_sz_t); 3174 if (iocp->ioc_count != size) 3175 return (IOC_INVAL); 3176 3177 value = sizeof (lb_normal); 3178 value += sizeof (lb_mac); 3179 if (hw->phy.media_type == e1000_media_type_copper) 3180 value += sizeof (lb_phy); 3181 else 3182 value += sizeof (lb_serdes); 3183 value += sizeof (lb_external); 3184 3185 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3186 *lbsp = value; 3187 break; 3188 3189 case LB_GET_INFO: 3190 value = sizeof (lb_normal); 3191 value += sizeof (lb_mac); 3192 if (hw->phy.media_type == e1000_media_type_copper) 3193 value += sizeof (lb_phy); 3194 else 3195 value += sizeof (lb_serdes); 3196 value += sizeof (lb_external); 3197 3198 size = value; 3199 if (iocp->ioc_count != size) 3200 return (IOC_INVAL); 3201 3202 value = 0; 3203 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3204 3205 lbpp[value++] = lb_normal; 3206 lbpp[value++] = lb_mac; 3207 if (hw->phy.media_type == e1000_media_type_copper) 3208 lbpp[value++] = lb_phy; 3209 else 3210 lbpp[value++] = lb_serdes; 3211 lbpp[value++] = lb_external; 3212 break; 3213 3214 case LB_GET_MODE: 3215 size = sizeof (uint32_t); 3216 if (iocp->ioc_count != size) 3217 return (IOC_INVAL); 3218 3219 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3220 *lbmp = igb->loopback_mode; 3221 break; 3222 3223 case LB_SET_MODE: 3224 size = 0; 3225 if (iocp->ioc_count != sizeof (uint32_t)) 3226 return (IOC_INVAL); 3227 3228 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3229 if (!igb_set_loopback_mode(igb, *lbmp)) 3230 return (IOC_INVAL); 3231 break; 3232 } 3233 3234 iocp->ioc_count = size; 3235 iocp->ioc_error = 0; 3236 3237 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3238 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3239 return (IOC_INVAL); 3240 } 3241 3242 return (IOC_REPLY); 3243 } 3244 3245 /* 3246 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3247 */ 3248 static boolean_t 3249 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3250 { 3251 struct e1000_hw *hw; 3252 3253 if (mode == igb->loopback_mode) 3254 return (B_TRUE); 3255 3256 hw = &igb->hw; 3257 3258 igb->loopback_mode = mode; 3259 3260 if (mode == IGB_LB_NONE) { 3261 /* Reset the chip */ 3262 hw->phy.autoneg_wait_to_complete = B_TRUE; 3263 (void) igb_reset(igb); 3264 hw->phy.autoneg_wait_to_complete = B_FALSE; 3265 return (B_TRUE); 3266 } 3267 3268 mutex_enter(&igb->gen_lock); 3269 3270 switch (mode) { 3271 default: 3272 mutex_exit(&igb->gen_lock); 3273 return (B_FALSE); 3274 3275 case IGB_LB_EXTERNAL: 3276 igb_set_external_loopback(igb); 3277 break; 3278 3279 case IGB_LB_INTERNAL_MAC: 3280 igb_set_internal_mac_loopback(igb); 3281 break; 3282 3283 case IGB_LB_INTERNAL_PHY: 3284 igb_set_internal_phy_loopback(igb); 3285 break; 3286 3287 case IGB_LB_INTERNAL_SERDES: 3288 igb_set_internal_serdes_loopback(igb); 3289 break; 3290 } 3291 3292 mutex_exit(&igb->gen_lock); 3293 3294 return (B_TRUE); 3295 } 3296 3297 /* 3298 * igb_set_external_loopback - Set the external loopback mode 3299 */ 3300 static void 3301 igb_set_external_loopback(igb_t *igb) 3302 { 3303 struct e1000_hw *hw; 3304 3305 hw = &igb->hw; 3306 3307 /* Set phy to known state */ 3308 (void) e1000_phy_hw_reset(hw); 3309 3310 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3311 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3312 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3313 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3314 } 3315 3316 /* 3317 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3318 */ 3319 static void 3320 igb_set_internal_mac_loopback(igb_t *igb) 3321 { 3322 struct e1000_hw *hw; 3323 uint32_t ctrl; 3324 uint32_t rctl; 3325 3326 hw = &igb->hw; 3327 3328 /* Set the Receive Control register */ 3329 rctl = E1000_READ_REG(hw, E1000_RCTL); 3330 rctl &= ~E1000_RCTL_LBM_TCVR; 3331 rctl |= E1000_RCTL_LBM_MAC; 3332 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3333 3334 /* Set the Device Control register */ 3335 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3336 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3337 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3338 E1000_CTRL_FRCSPD | /* Force speed */ 3339 E1000_CTRL_FRCDPX | /* Force duplex */ 3340 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3341 E1000_CTRL_FD); /* Force full duplex */ 3342 ctrl &= ~E1000_CTRL_ILOS; /* Clear ILOS when there's a link */ 3343 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3344 } 3345 3346 /* 3347 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3348 */ 3349 static void 3350 igb_set_internal_phy_loopback(igb_t *igb) 3351 { 3352 struct e1000_hw *hw; 3353 uint32_t ctrl_ext; 3354 uint16_t phy_ctrl; 3355 uint16_t phy_pconf; 3356 3357 hw = &igb->hw; 3358 3359 /* Set link mode to PHY (00b) in the Extended Control register */ 3360 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3361 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3362 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3363 3364 /* 3365 * Set PHY control register (0x4140): 3366 * Set full duplex mode 3367 * Set loopback bit 3368 * Clear auto-neg enable bit 3369 * Set PHY speed 3370 */ 3371 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3372 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3373 3374 /* Set the link disable bit in the Port Configuration register */ 3375 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3376 phy_pconf |= (uint16_t)1 << 14; 3377 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3378 } 3379 3380 /* 3381 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3382 */ 3383 static void 3384 igb_set_internal_serdes_loopback(igb_t *igb) 3385 { 3386 struct e1000_hw *hw; 3387 uint32_t ctrl_ext; 3388 uint32_t ctrl; 3389 uint32_t pcs_lctl; 3390 uint32_t connsw; 3391 3392 hw = &igb->hw; 3393 3394 /* Set link mode to SerDes (11b) in the Extended Control register */ 3395 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3396 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3397 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3398 3399 /* Configure the SerDes to loopback */ 3400 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3401 3402 /* Set Device Control register */ 3403 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3404 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3405 E1000_CTRL_SLU); /* Force link up */ 3406 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3407 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3408 E1000_CTRL_LRST); /* Clear link reset */ 3409 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3410 3411 /* Set PCS Link Control register */ 3412 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3413 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3414 E1000_PCS_LCTL_FSD | 3415 E1000_PCS_LCTL_FDV_FULL | 3416 E1000_PCS_LCTL_FLV_LINK_UP); 3417 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3418 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3419 3420 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3421 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3422 connsw &= ~E1000_CONNSW_ENRGSRC; 3423 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3424 } 3425 3426 #pragma inline(igb_intr_rx_work) 3427 /* 3428 * igb_intr_rx_work - rx processing of ISR 3429 */ 3430 static void 3431 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3432 { 3433 mblk_t *mp; 3434 3435 mutex_enter(&rx_ring->rx_lock); 3436 mp = igb_rx(rx_ring, IGB_NO_POLL); 3437 mutex_exit(&rx_ring->rx_lock); 3438 3439 if (mp != NULL) 3440 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 3441 rx_ring->ring_gen_num); 3442 } 3443 3444 #pragma inline(igb_intr_tx_work) 3445 /* 3446 * igb_intr_tx_work - tx processing of ISR 3447 */ 3448 static void 3449 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3450 { 3451 /* Recycle the tx descriptors */ 3452 tx_ring->tx_recycle(tx_ring); 3453 3454 /* Schedule the re-transmit */ 3455 if (tx_ring->reschedule && 3456 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3457 tx_ring->reschedule = B_FALSE; 3458 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 3459 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3460 } 3461 } 3462 3463 #pragma inline(igb_intr_link_work) 3464 /* 3465 * igb_intr_link_work - link-status-change processing of ISR 3466 */ 3467 static void 3468 igb_intr_link_work(igb_t *igb) 3469 { 3470 boolean_t link_changed; 3471 3472 igb_stop_watchdog_timer(igb); 3473 3474 mutex_enter(&igb->gen_lock); 3475 3476 /* 3477 * Because we got a link-status-change interrupt, force 3478 * e1000_check_for_link() to look at phy 3479 */ 3480 igb->hw.mac.get_link_status = B_TRUE; 3481 3482 /* igb_link_check takes care of link status change */ 3483 link_changed = igb_link_check(igb); 3484 3485 /* Get new phy state */ 3486 igb_get_phy_state(igb); 3487 3488 mutex_exit(&igb->gen_lock); 3489 3490 if (link_changed) 3491 mac_link_update(igb->mac_hdl, igb->link_state); 3492 3493 igb_start_watchdog_timer(igb); 3494 } 3495 3496 /* 3497 * igb_intr_legacy - Interrupt handler for legacy interrupts 3498 */ 3499 static uint_t 3500 igb_intr_legacy(void *arg1, void *arg2) 3501 { 3502 igb_t *igb = (igb_t *)arg1; 3503 igb_tx_ring_t *tx_ring; 3504 uint32_t icr; 3505 mblk_t *mp; 3506 boolean_t tx_reschedule; 3507 boolean_t link_changed; 3508 uint_t result; 3509 3510 _NOTE(ARGUNUSED(arg2)); 3511 3512 mutex_enter(&igb->gen_lock); 3513 3514 if (igb->igb_state & IGB_SUSPENDED) { 3515 mutex_exit(&igb->gen_lock); 3516 return (DDI_INTR_UNCLAIMED); 3517 } 3518 3519 mp = NULL; 3520 tx_reschedule = B_FALSE; 3521 link_changed = B_FALSE; 3522 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3523 3524 if (icr & E1000_ICR_INT_ASSERTED) { 3525 /* 3526 * E1000_ICR_INT_ASSERTED bit was set: 3527 * Read(Clear) the ICR, claim this interrupt, 3528 * look for work to do. 3529 */ 3530 ASSERT(igb->num_rx_rings == 1); 3531 ASSERT(igb->num_tx_rings == 1); 3532 3533 if (icr & E1000_ICR_RXT0) { 3534 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 3535 } 3536 3537 if (icr & E1000_ICR_TXDW) { 3538 tx_ring = &igb->tx_rings[0]; 3539 3540 /* Recycle the tx descriptors */ 3541 tx_ring->tx_recycle(tx_ring); 3542 3543 /* Schedule the re-transmit */ 3544 tx_reschedule = (tx_ring->reschedule && 3545 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3546 } 3547 3548 if (icr & E1000_ICR_LSC) { 3549 /* 3550 * Because we got a link-status-change interrupt, force 3551 * e1000_check_for_link() to look at phy 3552 */ 3553 igb->hw.mac.get_link_status = B_TRUE; 3554 3555 /* igb_link_check takes care of link status change */ 3556 link_changed = igb_link_check(igb); 3557 3558 /* Get new phy state */ 3559 igb_get_phy_state(igb); 3560 } 3561 3562 result = DDI_INTR_CLAIMED; 3563 } else { 3564 /* 3565 * E1000_ICR_INT_ASSERTED bit was not set: 3566 * Don't claim this interrupt. 3567 */ 3568 result = DDI_INTR_UNCLAIMED; 3569 } 3570 3571 mutex_exit(&igb->gen_lock); 3572 3573 /* 3574 * Do the following work outside of the gen_lock 3575 */ 3576 if (mp != NULL) 3577 mac_rx(igb->mac_hdl, NULL, mp); 3578 3579 if (tx_reschedule) { 3580 tx_ring->reschedule = B_FALSE; 3581 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 3582 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3583 } 3584 3585 if (link_changed) 3586 mac_link_update(igb->mac_hdl, igb->link_state); 3587 3588 return (result); 3589 } 3590 3591 /* 3592 * igb_intr_msi - Interrupt handler for MSI 3593 */ 3594 static uint_t 3595 igb_intr_msi(void *arg1, void *arg2) 3596 { 3597 igb_t *igb = (igb_t *)arg1; 3598 uint32_t icr; 3599 3600 _NOTE(ARGUNUSED(arg2)); 3601 3602 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3603 3604 /* 3605 * For MSI interrupt, we have only one vector, 3606 * so we have only one rx ring and one tx ring enabled. 3607 */ 3608 ASSERT(igb->num_rx_rings == 1); 3609 ASSERT(igb->num_tx_rings == 1); 3610 3611 if (icr & E1000_ICR_RXT0) { 3612 igb_intr_rx_work(&igb->rx_rings[0]); 3613 } 3614 3615 if (icr & E1000_ICR_TXDW) { 3616 igb_intr_tx_work(&igb->tx_rings[0]); 3617 } 3618 3619 if (icr & E1000_ICR_LSC) { 3620 igb_intr_link_work(igb); 3621 } 3622 3623 return (DDI_INTR_CLAIMED); 3624 } 3625 3626 /* 3627 * igb_intr_rx - Interrupt handler for rx 3628 */ 3629 static uint_t 3630 igb_intr_rx(void *arg1, void *arg2) 3631 { 3632 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3633 3634 _NOTE(ARGUNUSED(arg2)); 3635 3636 /* 3637 * Only used via MSI-X vector so don't check cause bits 3638 * and only clean the given ring. 3639 */ 3640 igb_intr_rx_work(rx_ring); 3641 3642 return (DDI_INTR_CLAIMED); 3643 } 3644 3645 /* 3646 * igb_intr_tx - Interrupt handler for tx 3647 */ 3648 static uint_t 3649 igb_intr_tx(void *arg1, void *arg2) 3650 { 3651 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 3652 3653 _NOTE(ARGUNUSED(arg2)); 3654 3655 /* 3656 * Only used via MSI-X vector so don't check cause bits 3657 * and only clean the given ring. 3658 */ 3659 igb_intr_tx_work(tx_ring); 3660 3661 return (DDI_INTR_CLAIMED); 3662 } 3663 3664 /* 3665 * igb_intr_tx_other - Interrupt handler for both tx and other 3666 * 3667 */ 3668 static uint_t 3669 igb_intr_tx_other(void *arg1, void *arg2) 3670 { 3671 igb_t *igb = (igb_t *)arg1; 3672 uint32_t icr; 3673 3674 _NOTE(ARGUNUSED(arg2)); 3675 3676 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3677 3678 /* 3679 * Look for tx reclaiming work first. Remember, in the 3680 * case of only interrupt sharing, only one tx ring is 3681 * used 3682 */ 3683 igb_intr_tx_work(&igb->tx_rings[0]); 3684 3685 /* 3686 * Need check cause bits and only link change will 3687 * be processed 3688 */ 3689 if (icr & E1000_ICR_LSC) { 3690 igb_intr_link_work(igb); 3691 } 3692 3693 return (DDI_INTR_CLAIMED); 3694 } 3695 3696 /* 3697 * igb_alloc_intrs - Allocate interrupts for the driver 3698 * 3699 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3700 * if not successful, try Legacy. 3701 * igb->intr_force can be used to force sequence to start with 3702 * any of the 3 types. 3703 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3704 */ 3705 static int 3706 igb_alloc_intrs(igb_t *igb) 3707 { 3708 dev_info_t *devinfo; 3709 int intr_types; 3710 int rc; 3711 3712 devinfo = igb->dip; 3713 3714 /* Get supported interrupt types */ 3715 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3716 3717 if (rc != DDI_SUCCESS) { 3718 igb_log(igb, 3719 "Get supported interrupt types failed: %d", rc); 3720 return (IGB_FAILURE); 3721 } 3722 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3723 3724 igb->intr_type = 0; 3725 3726 /* Install MSI-X interrupts */ 3727 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3728 (igb->intr_force <= IGB_INTR_MSIX)) { 3729 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 3730 3731 if (rc == IGB_SUCCESS) 3732 return (IGB_SUCCESS); 3733 3734 igb_log(igb, 3735 "Allocate MSI-X failed, trying MSI interrupts..."); 3736 } 3737 3738 /* MSI-X not used, force rings to 1 */ 3739 igb->num_rx_rings = 1; 3740 igb->num_tx_rings = 1; 3741 igb_log(igb, 3742 "MSI-X not used, force rx and tx queue number to 1"); 3743 3744 /* Install MSI interrupts */ 3745 if ((intr_types & DDI_INTR_TYPE_MSI) && 3746 (igb->intr_force <= IGB_INTR_MSI)) { 3747 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 3748 3749 if (rc == IGB_SUCCESS) 3750 return (IGB_SUCCESS); 3751 3752 igb_log(igb, 3753 "Allocate MSI failed, trying Legacy interrupts..."); 3754 } 3755 3756 /* Install legacy interrupts */ 3757 if (intr_types & DDI_INTR_TYPE_FIXED) { 3758 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 3759 3760 if (rc == IGB_SUCCESS) 3761 return (IGB_SUCCESS); 3762 3763 igb_log(igb, 3764 "Allocate Legacy interrupts failed"); 3765 } 3766 3767 /* If none of the 3 types succeeded, return failure */ 3768 return (IGB_FAILURE); 3769 } 3770 3771 /* 3772 * igb_alloc_intr_handles - Allocate interrupt handles. 3773 * 3774 * For legacy and MSI, only 1 handle is needed. For MSI-X, 3775 * if fewer than 2 handles are available, return failure. 3776 * Upon success, this sets the number of Rx rings to a number that 3777 * matches the handles available for Rx interrupts. 3778 */ 3779 static int 3780 igb_alloc_intr_handles(igb_t *igb, int intr_type) 3781 { 3782 dev_info_t *devinfo; 3783 int orig, request, count, avail, actual; 3784 int diff, minimum; 3785 int rc; 3786 3787 devinfo = igb->dip; 3788 3789 switch (intr_type) { 3790 case DDI_INTR_TYPE_FIXED: 3791 request = 1; /* Request 1 legacy interrupt handle */ 3792 minimum = 1; 3793 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 3794 break; 3795 3796 case DDI_INTR_TYPE_MSI: 3797 request = 1; /* Request 1 MSI interrupt handle */ 3798 minimum = 1; 3799 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 3800 break; 3801 3802 case DDI_INTR_TYPE_MSIX: 3803 /* 3804 * Number of vectors for the adapter is 3805 * # rx rings + # tx rings 3806 * One of tx vectors is for tx & other 3807 */ 3808 request = igb->num_rx_rings + igb->num_tx_rings; 3809 orig = request; 3810 minimum = 2; 3811 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 3812 break; 3813 3814 default: 3815 igb_log(igb, 3816 "invalid call to igb_alloc_intr_handles(): %d\n", 3817 intr_type); 3818 return (IGB_FAILURE); 3819 } 3820 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 3821 request, minimum); 3822 3823 /* 3824 * Get number of supported interrupts 3825 */ 3826 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3827 if ((rc != DDI_SUCCESS) || (count < minimum)) { 3828 igb_log(igb, 3829 "Get supported interrupt number failed. " 3830 "Return: %d, count: %d", rc, count); 3831 return (IGB_FAILURE); 3832 } 3833 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 3834 3835 /* 3836 * Get number of available interrupts 3837 */ 3838 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3839 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 3840 igb_log(igb, 3841 "Get available interrupt number failed. " 3842 "Return: %d, available: %d", rc, avail); 3843 return (IGB_FAILURE); 3844 } 3845 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 3846 3847 if (avail < request) { 3848 igb_log(igb, "Request %d handles, %d available", 3849 request, avail); 3850 request = avail; 3851 } 3852 3853 actual = 0; 3854 igb->intr_cnt = 0; 3855 3856 /* 3857 * Allocate an array of interrupt handles 3858 */ 3859 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3860 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3861 3862 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 3863 request, &actual, DDI_INTR_ALLOC_NORMAL); 3864 if (rc != DDI_SUCCESS) { 3865 igb_log(igb, "Allocate interrupts failed. " 3866 "return: %d, request: %d, actual: %d", 3867 rc, request, actual); 3868 goto alloc_handle_fail; 3869 } 3870 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 3871 3872 igb->intr_cnt = actual; 3873 3874 if (actual < minimum) { 3875 igb_log(igb, "Insufficient interrupt handles allocated: %d", 3876 actual); 3877 goto alloc_handle_fail; 3878 } 3879 3880 /* 3881 * For MSI-X, actual might force us to reduce number of tx & rx rings 3882 */ 3883 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 3884 diff = orig - actual; 3885 if (diff < igb->num_tx_rings) { 3886 igb_log(igb, 3887 "MSI-X vectors force Tx queue number to %d", 3888 igb->num_tx_rings - diff); 3889 igb->num_tx_rings -= diff; 3890 } else { 3891 igb_log(igb, 3892 "MSI-X vectors force Tx queue number to 1"); 3893 igb->num_tx_rings = 1; 3894 3895 igb_log(igb, 3896 "MSI-X vectors force Rx queue number to %d", 3897 actual - 1); 3898 igb->num_rx_rings = actual - 1; 3899 } 3900 } 3901 3902 /* 3903 * Get priority for first vector, assume remaining are all the same 3904 */ 3905 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3906 if (rc != DDI_SUCCESS) { 3907 igb_log(igb, 3908 "Get interrupt priority failed: %d", rc); 3909 goto alloc_handle_fail; 3910 } 3911 3912 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3913 if (rc != DDI_SUCCESS) { 3914 igb_log(igb, 3915 "Get interrupt cap failed: %d", rc); 3916 goto alloc_handle_fail; 3917 } 3918 3919 igb->intr_type = intr_type; 3920 3921 return (IGB_SUCCESS); 3922 3923 alloc_handle_fail: 3924 igb_rem_intrs(igb); 3925 3926 return (IGB_FAILURE); 3927 } 3928 3929 /* 3930 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 3931 * 3932 * Before adding the interrupt handlers, the interrupt vectors have 3933 * been allocated, and the rx/tx rings have also been allocated. 3934 */ 3935 static int 3936 igb_add_intr_handlers(igb_t *igb) 3937 { 3938 igb_rx_ring_t *rx_ring; 3939 igb_tx_ring_t *tx_ring; 3940 int vector; 3941 int rc; 3942 int i; 3943 3944 vector = 0; 3945 3946 switch (igb->intr_type) { 3947 case DDI_INTR_TYPE_MSIX: 3948 /* Add interrupt handler for tx + other */ 3949 tx_ring = &igb->tx_rings[0]; 3950 rc = ddi_intr_add_handler(igb->htable[vector], 3951 (ddi_intr_handler_t *)igb_intr_tx_other, 3952 (void *)igb, NULL); 3953 3954 if (rc != DDI_SUCCESS) { 3955 igb_log(igb, 3956 "Add tx/other interrupt handler failed: %d", rc); 3957 return (IGB_FAILURE); 3958 } 3959 tx_ring->intr_vector = vector; 3960 vector++; 3961 3962 /* Add interrupt handler for each rx ring */ 3963 for (i = 0; i < igb->num_rx_rings; i++) { 3964 rx_ring = &igb->rx_rings[i]; 3965 3966 rc = ddi_intr_add_handler(igb->htable[vector], 3967 (ddi_intr_handler_t *)igb_intr_rx, 3968 (void *)rx_ring, NULL); 3969 3970 if (rc != DDI_SUCCESS) { 3971 igb_log(igb, 3972 "Add rx interrupt handler failed. " 3973 "return: %d, rx ring: %d", rc, i); 3974 for (vector--; vector >= 0; vector--) { 3975 (void) ddi_intr_remove_handler( 3976 igb->htable[vector]); 3977 } 3978 return (IGB_FAILURE); 3979 } 3980 3981 rx_ring->intr_vector = vector; 3982 3983 vector++; 3984 } 3985 3986 /* Add interrupt handler for each tx ring from 2nd ring */ 3987 for (i = 1; i < igb->num_tx_rings; i++) { 3988 tx_ring = &igb->tx_rings[i]; 3989 3990 rc = ddi_intr_add_handler(igb->htable[vector], 3991 (ddi_intr_handler_t *)igb_intr_tx, 3992 (void *)tx_ring, NULL); 3993 3994 if (rc != DDI_SUCCESS) { 3995 igb_log(igb, 3996 "Add tx interrupt handler failed. " 3997 "return: %d, tx ring: %d", rc, i); 3998 for (vector--; vector >= 0; vector--) { 3999 (void) ddi_intr_remove_handler( 4000 igb->htable[vector]); 4001 } 4002 return (IGB_FAILURE); 4003 } 4004 4005 tx_ring->intr_vector = vector; 4006 4007 vector++; 4008 } 4009 4010 break; 4011 4012 case DDI_INTR_TYPE_MSI: 4013 /* Add interrupt handlers for the only vector */ 4014 rc = ddi_intr_add_handler(igb->htable[vector], 4015 (ddi_intr_handler_t *)igb_intr_msi, 4016 (void *)igb, NULL); 4017 4018 if (rc != DDI_SUCCESS) { 4019 igb_log(igb, 4020 "Add MSI interrupt handler failed: %d", rc); 4021 return (IGB_FAILURE); 4022 } 4023 4024 rx_ring = &igb->rx_rings[0]; 4025 rx_ring->intr_vector = vector; 4026 4027 vector++; 4028 break; 4029 4030 case DDI_INTR_TYPE_FIXED: 4031 /* Add interrupt handlers for the only vector */ 4032 rc = ddi_intr_add_handler(igb->htable[vector], 4033 (ddi_intr_handler_t *)igb_intr_legacy, 4034 (void *)igb, NULL); 4035 4036 if (rc != DDI_SUCCESS) { 4037 igb_log(igb, 4038 "Add legacy interrupt handler failed: %d", rc); 4039 return (IGB_FAILURE); 4040 } 4041 4042 rx_ring = &igb->rx_rings[0]; 4043 rx_ring->intr_vector = vector; 4044 4045 vector++; 4046 break; 4047 4048 default: 4049 return (IGB_FAILURE); 4050 } 4051 4052 ASSERT(vector == igb->intr_cnt); 4053 4054 return (IGB_SUCCESS); 4055 } 4056 4057 /* 4058 * igb_setup_adapter_msix - setup the adapter to use MSI-X interrupts 4059 * 4060 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4061 */ 4062 static void 4063 igb_setup_adapter_msix(igb_t *igb) 4064 { 4065 uint32_t eims = 0; 4066 int i, vector; 4067 struct e1000_hw *hw = &igb->hw; 4068 4069 /* 4070 * Set vector for other causes, NOTE assumption that it is vector 0 4071 */ 4072 vector = 0; 4073 4074 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4075 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4076 vector++; 4077 4078 for (i = 0; i < igb->num_rx_rings; i++) { 4079 /* 4080 * Set vector for each rx ring 4081 */ 4082 eims = (E1000_EICR_RX_QUEUE0 << i); 4083 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4084 4085 /* 4086 * Accumulate bits to enable in igb_enable_adapter_interrupts() 4087 */ 4088 igb->eims_mask |= eims; 4089 4090 vector++; 4091 } 4092 4093 for (i = 1; i < igb->num_tx_rings; i++) { 4094 /* 4095 * Set vector for each tx ring from 2nd tx ring 4096 */ 4097 eims = (E1000_EICR_TX_QUEUE0 << i); 4098 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4099 4100 /* 4101 * Accumulate bits to enable in igb_enable_adapter_interrupts() 4102 */ 4103 igb->eims_mask |= eims; 4104 4105 vector++; 4106 } 4107 4108 ASSERT(vector == igb->intr_cnt); 4109 4110 /* 4111 * Disable IAM for ICR interrupt bits 4112 */ 4113 E1000_WRITE_REG(hw, E1000_IAM, 0); 4114 E1000_WRITE_FLUSH(hw); 4115 } 4116 4117 /* 4118 * igb_rem_intr_handlers - remove the interrupt handlers 4119 */ 4120 static void 4121 igb_rem_intr_handlers(igb_t *igb) 4122 { 4123 int i; 4124 int rc; 4125 4126 for (i = 0; i < igb->intr_cnt; i++) { 4127 rc = ddi_intr_remove_handler(igb->htable[i]); 4128 if (rc != DDI_SUCCESS) { 4129 IGB_DEBUGLOG_1(igb, 4130 "Remove intr handler failed: %d", rc); 4131 } 4132 } 4133 } 4134 4135 /* 4136 * igb_rem_intrs - remove the allocated interrupts 4137 */ 4138 static void 4139 igb_rem_intrs(igb_t *igb) 4140 { 4141 int i; 4142 int rc; 4143 4144 for (i = 0; i < igb->intr_cnt; i++) { 4145 rc = ddi_intr_free(igb->htable[i]); 4146 if (rc != DDI_SUCCESS) { 4147 IGB_DEBUGLOG_1(igb, 4148 "Free intr failed: %d", rc); 4149 } 4150 } 4151 4152 kmem_free(igb->htable, igb->intr_size); 4153 igb->htable = NULL; 4154 } 4155 4156 /* 4157 * igb_enable_intrs - enable all the ddi interrupts 4158 */ 4159 static int 4160 igb_enable_intrs(igb_t *igb) 4161 { 4162 int i; 4163 int rc; 4164 4165 /* Enable interrupts */ 4166 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4167 /* Call ddi_intr_block_enable() for MSI */ 4168 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4169 if (rc != DDI_SUCCESS) { 4170 igb_log(igb, 4171 "Enable block intr failed: %d", rc); 4172 return (IGB_FAILURE); 4173 } 4174 } else { 4175 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4176 for (i = 0; i < igb->intr_cnt; i++) { 4177 rc = ddi_intr_enable(igb->htable[i]); 4178 if (rc != DDI_SUCCESS) { 4179 igb_log(igb, 4180 "Enable intr failed: %d", rc); 4181 return (IGB_FAILURE); 4182 } 4183 } 4184 } 4185 4186 return (IGB_SUCCESS); 4187 } 4188 4189 /* 4190 * igb_disable_intrs - disable all the ddi interrupts 4191 */ 4192 static int 4193 igb_disable_intrs(igb_t *igb) 4194 { 4195 int i; 4196 int rc; 4197 4198 /* Disable all interrupts */ 4199 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4200 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 4201 if (rc != DDI_SUCCESS) { 4202 igb_log(igb, 4203 "Disable block intr failed: %d", rc); 4204 return (IGB_FAILURE); 4205 } 4206 } else { 4207 for (i = 0; i < igb->intr_cnt; i++) { 4208 rc = ddi_intr_disable(igb->htable[i]); 4209 if (rc != DDI_SUCCESS) { 4210 igb_log(igb, 4211 "Disable intr failed: %d", rc); 4212 return (IGB_FAILURE); 4213 } 4214 } 4215 } 4216 4217 return (IGB_SUCCESS); 4218 } 4219 4220 /* 4221 * igb_get_phy_state - Get and save the parameters read from PHY registers 4222 */ 4223 static void 4224 igb_get_phy_state(igb_t *igb) 4225 { 4226 struct e1000_hw *hw = &igb->hw; 4227 uint16_t phy_ctrl; 4228 uint16_t phy_status; 4229 uint16_t phy_an_adv; 4230 uint16_t phy_an_exp; 4231 uint16_t phy_ext_status; 4232 uint16_t phy_1000t_ctrl; 4233 uint16_t phy_1000t_status; 4234 uint16_t phy_lp_able; 4235 4236 ASSERT(mutex_owned(&igb->gen_lock)); 4237 4238 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4239 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 4240 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4241 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4242 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4243 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4244 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 4245 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4246 4247 igb->param_autoneg_cap = 4248 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4249 igb->param_pause_cap = 4250 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4251 igb->param_asym_pause_cap = 4252 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4253 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4254 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4255 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4256 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4257 igb->param_100t4_cap = 4258 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4259 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4260 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4261 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4262 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4263 igb->param_10fdx_cap = 4264 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4265 igb->param_10hdx_cap = 4266 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4267 igb->param_rem_fault = 4268 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4269 4270 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4271 igb->param_adv_pause_cap = 4272 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4273 igb->param_adv_asym_pause_cap = 4274 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4275 igb->param_adv_1000hdx_cap = 4276 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4277 igb->param_adv_100t4_cap = 4278 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4279 igb->param_adv_rem_fault = 4280 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4281 if (igb->param_adv_autoneg_cap == 1) { 4282 igb->param_adv_1000fdx_cap = 4283 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 4284 igb->param_adv_100fdx_cap = 4285 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 4286 igb->param_adv_100hdx_cap = 4287 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 4288 igb->param_adv_10fdx_cap = 4289 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 4290 igb->param_adv_10hdx_cap = 4291 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 4292 } 4293 4294 igb->param_lp_autoneg_cap = 4295 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 4296 igb->param_lp_pause_cap = 4297 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 4298 igb->param_lp_asym_pause_cap = 4299 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 4300 igb->param_lp_1000fdx_cap = 4301 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 4302 igb->param_lp_1000hdx_cap = 4303 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 4304 igb->param_lp_100t4_cap = 4305 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 4306 igb->param_lp_100fdx_cap = 4307 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 4308 igb->param_lp_100hdx_cap = 4309 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 4310 igb->param_lp_10fdx_cap = 4311 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 4312 igb->param_lp_10hdx_cap = 4313 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 4314 igb->param_lp_rem_fault = 4315 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 4316 } 4317 4318 /* 4319 * igb_get_driver_control 4320 */ 4321 static void 4322 igb_get_driver_control(struct e1000_hw *hw) 4323 { 4324 uint32_t ctrl_ext; 4325 4326 /* Notify firmware that driver is in control of device */ 4327 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4328 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 4329 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4330 } 4331 4332 /* 4333 * igb_release_driver_control 4334 */ 4335 static void 4336 igb_release_driver_control(struct e1000_hw *hw) 4337 { 4338 uint32_t ctrl_ext; 4339 4340 /* Notify firmware that driver is no longer in control of device */ 4341 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4342 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 4343 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4344 } 4345 4346 /* 4347 * igb_atomic_reserve - Atomic decrease operation 4348 */ 4349 int 4350 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4351 { 4352 uint32_t oldval; 4353 uint32_t newval; 4354 4355 /* ATOMICALLY */ 4356 do { 4357 oldval = *count_p; 4358 if (oldval < n) 4359 return (-1); 4360 newval = oldval - n; 4361 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4362 4363 return (newval); 4364 } 4365 4366 /* 4367 * FMA support 4368 */ 4369 4370 int 4371 igb_check_acc_handle(ddi_acc_handle_t handle) 4372 { 4373 ddi_fm_error_t de; 4374 4375 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4376 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4377 return (de.fme_status); 4378 } 4379 4380 int 4381 igb_check_dma_handle(ddi_dma_handle_t handle) 4382 { 4383 ddi_fm_error_t de; 4384 4385 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4386 return (de.fme_status); 4387 } 4388 4389 /* 4390 * The IO fault service error handling callback function 4391 */ 4392 /*ARGSUSED*/ 4393 static int 4394 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4395 { 4396 /* 4397 * as the driver can always deal with an error in any dma or 4398 * access handle, we can just return the fme_status value. 4399 */ 4400 pci_ereport_post(dip, err, NULL); 4401 return (err->fme_status); 4402 } 4403 4404 static void 4405 igb_fm_init(igb_t *igb) 4406 { 4407 ddi_iblock_cookie_t iblk; 4408 int fma_acc_flag, fma_dma_flag; 4409 4410 /* Only register with IO Fault Services if we have some capability */ 4411 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4412 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4413 fma_acc_flag = 1; 4414 } else { 4415 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4416 fma_acc_flag = 0; 4417 } 4418 4419 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4420 fma_dma_flag = 1; 4421 } else { 4422 fma_dma_flag = 0; 4423 } 4424 4425 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4426 4427 if (igb->fm_capabilities) { 4428 4429 /* Register capabilities with IO Fault Services */ 4430 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4431 4432 /* 4433 * Initialize pci ereport capabilities if ereport capable 4434 */ 4435 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4436 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4437 pci_ereport_setup(igb->dip); 4438 4439 /* 4440 * Register error callback if error callback capable 4441 */ 4442 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4443 ddi_fm_handler_register(igb->dip, 4444 igb_fm_error_cb, (void*) igb); 4445 } 4446 } 4447 4448 static void 4449 igb_fm_fini(igb_t *igb) 4450 { 4451 /* Only unregister FMA capabilities if we registered some */ 4452 if (igb->fm_capabilities) { 4453 4454 /* 4455 * Release any resources allocated by pci_ereport_setup() 4456 */ 4457 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4458 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4459 pci_ereport_teardown(igb->dip); 4460 4461 /* 4462 * Un-register error callback if error callback capable 4463 */ 4464 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4465 ddi_fm_handler_unregister(igb->dip); 4466 4467 /* Unregister from IO Fault Services */ 4468 ddi_fm_fini(igb->dip); 4469 } 4470 } 4471 4472 void 4473 igb_fm_ereport(igb_t *igb, char *detail) 4474 { 4475 uint64_t ena; 4476 char buf[FM_MAX_CLASS]; 4477 4478 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4479 ena = fm_ena_generate(0, FM_ENA_FMT1); 4480 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4481 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4482 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4483 } 4484 } 4485