1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #include "igb_sw.h" 30 31 static char ident[] = "Intel 1Gb Ethernet"; 32 static char igb_version[] = "igb 1.1.6"; 33 34 /* 35 * Local function protoypes 36 */ 37 static int igb_register_mac(igb_t *); 38 static int igb_identify_hardware(igb_t *); 39 static int igb_regs_map(igb_t *); 40 static void igb_init_properties(igb_t *); 41 static int igb_init_driver_settings(igb_t *); 42 static void igb_init_locks(igb_t *); 43 static void igb_destroy_locks(igb_t *); 44 static int igb_init_mac_address(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_init_adapter(igb_t *); 47 static void igb_stop_adapter(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static void igb_free_rings(igb_t *); 54 static void igb_setup_rings(igb_t *); 55 static void igb_setup_rx(igb_t *); 56 static void igb_setup_tx(igb_t *); 57 static void igb_setup_rx_ring(igb_rx_ring_t *); 58 static void igb_setup_tx_ring(igb_tx_ring_t *); 59 static void igb_setup_rss(igb_t *); 60 static void igb_setup_mac_rss_classify(igb_t *); 61 static void igb_setup_mac_classify(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts_82575(igb_t *); 76 static void igb_enable_adapter_interrupts_82576(igb_t *); 77 static boolean_t is_valid_mac_addr(uint8_t *); 78 static boolean_t igb_stall_check(igb_t *); 79 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 80 static void igb_set_external_loopback(igb_t *); 81 static void igb_set_internal_mac_loopback(igb_t *); 82 static void igb_set_internal_phy_loopback(igb_t *); 83 static void igb_set_internal_serdes_loopback(igb_t *); 84 static boolean_t igb_find_mac_address(igb_t *); 85 static int igb_alloc_intrs(igb_t *); 86 static int igb_alloc_intr_handles(igb_t *, int); 87 static int igb_add_intr_handlers(igb_t *); 88 static void igb_rem_intr_handlers(igb_t *); 89 static void igb_rem_intrs(igb_t *); 90 static int igb_enable_intrs(igb_t *); 91 static int igb_disable_intrs(igb_t *); 92 static void igb_setup_msix_82575(igb_t *); 93 static void igb_setup_msix_82576(igb_t *); 94 static uint_t igb_intr_legacy(void *, void *); 95 static uint_t igb_intr_msi(void *, void *); 96 static uint_t igb_intr_rx(void *, void *); 97 static uint_t igb_intr_tx(void *, void *); 98 static uint_t igb_intr_tx_other(void *, void *); 99 static void igb_intr_rx_work(igb_rx_ring_t *); 100 static void igb_intr_tx_work(igb_tx_ring_t *); 101 static void igb_intr_link_work(igb_t *); 102 static void igb_get_driver_control(struct e1000_hw *); 103 static void igb_release_driver_control(struct e1000_hw *); 104 105 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 106 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 107 static int igb_resume(dev_info_t *); 108 static int igb_suspend(dev_info_t *); 109 static int igb_quiesce(dev_info_t *); 110 static void igb_unconfigure(dev_info_t *, igb_t *); 111 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 112 const void *); 113 static void igb_fm_init(igb_t *); 114 static void igb_fm_fini(igb_t *); 115 116 117 static struct cb_ops igb_cb_ops = { 118 nulldev, /* cb_open */ 119 nulldev, /* cb_close */ 120 nodev, /* cb_strategy */ 121 nodev, /* cb_print */ 122 nodev, /* cb_dump */ 123 nodev, /* cb_read */ 124 nodev, /* cb_write */ 125 nodev, /* cb_ioctl */ 126 nodev, /* cb_devmap */ 127 nodev, /* cb_mmap */ 128 nodev, /* cb_segmap */ 129 nochpoll, /* cb_chpoll */ 130 ddi_prop_op, /* cb_prop_op */ 131 NULL, /* cb_stream */ 132 D_MP | D_HOTPLUG, /* cb_flag */ 133 CB_REV, /* cb_rev */ 134 nodev, /* cb_aread */ 135 nodev /* cb_awrite */ 136 }; 137 138 static struct dev_ops igb_dev_ops = { 139 DEVO_REV, /* devo_rev */ 140 0, /* devo_refcnt */ 141 NULL, /* devo_getinfo */ 142 nulldev, /* devo_identify */ 143 nulldev, /* devo_probe */ 144 igb_attach, /* devo_attach */ 145 igb_detach, /* devo_detach */ 146 nodev, /* devo_reset */ 147 &igb_cb_ops, /* devo_cb_ops */ 148 NULL, /* devo_bus_ops */ 149 ddi_power, /* devo_power */ 150 igb_quiesce, /* devo_quiesce */ 151 }; 152 153 static struct modldrv igb_modldrv = { 154 &mod_driverops, /* Type of module. This one is a driver */ 155 ident, /* Discription string */ 156 &igb_dev_ops, /* driver ops */ 157 }; 158 159 static struct modlinkage igb_modlinkage = { 160 MODREV_1, &igb_modldrv, NULL 161 }; 162 163 /* Access attributes for register mapping */ 164 ddi_device_acc_attr_t igb_regs_acc_attr = { 165 DDI_DEVICE_ATTR_V0, 166 DDI_STRUCTURE_LE_ACC, 167 DDI_STRICTORDER_ACC, 168 DDI_FLAGERR_ACC 169 }; 170 171 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 172 173 static mac_callbacks_t igb_m_callbacks = { 174 IGB_M_CALLBACK_FLAGS, 175 igb_m_stat, 176 igb_m_start, 177 igb_m_stop, 178 igb_m_promisc, 179 igb_m_multicst, 180 NULL, 181 NULL, 182 igb_m_ioctl, 183 igb_m_getcapab 184 }; 185 186 /* 187 * Initialize capabilities of each supported adapter type 188 */ 189 static adapter_info_t igb_82575_cap = { 190 /* limits */ 191 4, /* maximum number of rx queues */ 192 1, /* minimum number of rx queues */ 193 4, /* default number of rx queues */ 194 4, /* maximum number of tx queues */ 195 1, /* minimum number of tx queues */ 196 4, /* default number of tx queues */ 197 65535, /* maximum interrupt throttle rate */ 198 0, /* minimum interrupt throttle rate */ 199 200, /* default interrupt throttle rate */ 200 201 /* function pointers */ 202 igb_enable_adapter_interrupts_82575, 203 igb_setup_msix_82575, 204 205 /* capabilities */ 206 (IGB_FLAG_HAS_DCA | /* capability flags */ 207 IGB_FLAG_VMDQ_POOL), 208 209 0xffc00000 /* mask for RXDCTL register */ 210 }; 211 212 static adapter_info_t igb_82576_cap = { 213 /* limits */ 214 16, /* maximum number of rx queues */ 215 1, /* minimum number of rx queues */ 216 4, /* default number of rx queues */ 217 16, /* maximum number of tx queues */ 218 1, /* minimum number of tx queues */ 219 4, /* default number of tx queues */ 220 65535, /* maximum interrupt throttle rate */ 221 0, /* minimum interrupt throttle rate */ 222 200, /* default interrupt throttle rate */ 223 224 /* function pointers */ 225 igb_enable_adapter_interrupts_82576, 226 igb_setup_msix_82576, 227 228 /* capabilities */ 229 (IGB_FLAG_HAS_DCA | /* capability flags */ 230 IGB_FLAG_VMDQ_POOL | 231 IGB_FLAG_NEED_CTX_IDX), 232 233 0xffe00000 /* mask for RXDCTL register */ 234 }; 235 236 /* 237 * Module Initialization Functions 238 */ 239 240 int 241 _init(void) 242 { 243 int status; 244 245 mac_init_ops(&igb_dev_ops, MODULE_NAME); 246 247 status = mod_install(&igb_modlinkage); 248 249 if (status != DDI_SUCCESS) { 250 mac_fini_ops(&igb_dev_ops); 251 } 252 253 return (status); 254 } 255 256 int 257 _fini(void) 258 { 259 int status; 260 261 status = mod_remove(&igb_modlinkage); 262 263 if (status == DDI_SUCCESS) { 264 mac_fini_ops(&igb_dev_ops); 265 } 266 267 return (status); 268 269 } 270 271 int 272 _info(struct modinfo *modinfop) 273 { 274 int status; 275 276 status = mod_info(&igb_modlinkage, modinfop); 277 278 return (status); 279 } 280 281 /* 282 * igb_attach - driver attach 283 * 284 * This function is the device specific initialization entry 285 * point. This entry point is required and must be written. 286 * The DDI_ATTACH command must be provided in the attach entry 287 * point. When attach() is called with cmd set to DDI_ATTACH, 288 * all normal kernel services (such as kmem_alloc(9F)) are 289 * available for use by the driver. 290 * 291 * The attach() function will be called once for each instance 292 * of the device on the system with cmd set to DDI_ATTACH. 293 * Until attach() succeeds, the only driver entry points which 294 * may be called are open(9E) and getinfo(9E). 295 */ 296 static int 297 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 298 { 299 igb_t *igb; 300 struct igb_osdep *osdep; 301 struct e1000_hw *hw; 302 int instance; 303 304 /* 305 * Check the command and perform corresponding operations 306 */ 307 switch (cmd) { 308 default: 309 return (DDI_FAILURE); 310 311 case DDI_RESUME: 312 return (igb_resume(devinfo)); 313 314 case DDI_ATTACH: 315 break; 316 } 317 318 /* Get the device instance */ 319 instance = ddi_get_instance(devinfo); 320 321 /* Allocate memory for the instance data structure */ 322 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 323 324 igb->dip = devinfo; 325 igb->instance = instance; 326 327 hw = &igb->hw; 328 osdep = &igb->osdep; 329 hw->back = osdep; 330 osdep->igb = igb; 331 332 /* Attach the instance pointer to the dev_info data structure */ 333 ddi_set_driver_private(devinfo, igb); 334 335 336 /* Initialize for fma support */ 337 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 338 0, 0x0f, 339 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 340 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 341 igb_fm_init(igb); 342 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 343 344 /* 345 * Map PCI config space registers 346 */ 347 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 348 igb_error(igb, "Failed to map PCI configurations"); 349 goto attach_fail; 350 } 351 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 352 353 /* 354 * Identify the chipset family 355 */ 356 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 357 igb_error(igb, "Failed to identify hardware"); 358 goto attach_fail; 359 } 360 361 /* 362 * Map device registers 363 */ 364 if (igb_regs_map(igb) != IGB_SUCCESS) { 365 igb_error(igb, "Failed to map device registers"); 366 goto attach_fail; 367 } 368 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 369 370 /* 371 * Initialize driver parameters 372 */ 373 igb_init_properties(igb); 374 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 375 376 /* 377 * Allocate interrupts 378 */ 379 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 380 igb_error(igb, "Failed to allocate interrupts"); 381 goto attach_fail; 382 } 383 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 384 385 /* 386 * Allocate rx/tx rings based on the ring numbers. 387 * The actual numbers of rx/tx rings are decided by the number of 388 * allocated interrupt vectors, so we should allocate the rings after 389 * interrupts are allocated. 390 */ 391 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 392 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 393 goto attach_fail; 394 } 395 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 396 397 /* 398 * Add interrupt handlers 399 */ 400 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 401 igb_error(igb, "Failed to add interrupt handlers"); 402 goto attach_fail; 403 } 404 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 405 406 /* 407 * Initialize driver parameters 408 */ 409 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 410 igb_error(igb, "Failed to initialize driver settings"); 411 goto attach_fail; 412 } 413 414 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 415 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 416 goto attach_fail; 417 } 418 419 /* 420 * Initialize mutexes for this device. 421 * Do this before enabling the interrupt handler and 422 * register the softint to avoid the condition where 423 * interrupt handler can try using uninitialized mutex 424 */ 425 igb_init_locks(igb); 426 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 427 428 /* 429 * Allocate DMA resources 430 */ 431 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 432 igb_error(igb, "Failed to allocate DMA resources"); 433 goto attach_fail; 434 } 435 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_DMA; 436 437 /* 438 * Initialize the adapter and setup the rx/tx rings 439 */ 440 if (igb_init(igb) != IGB_SUCCESS) { 441 igb_error(igb, "Failed to initialize adapter"); 442 goto attach_fail; 443 } 444 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 445 446 /* 447 * Initialize statistics 448 */ 449 if (igb_init_stats(igb) != IGB_SUCCESS) { 450 igb_error(igb, "Failed to initialize statistics"); 451 goto attach_fail; 452 } 453 igb->attach_progress |= ATTACH_PROGRESS_STATS; 454 455 /* 456 * Initialize NDD parameters 457 */ 458 if (igb_nd_init(igb) != IGB_SUCCESS) { 459 igb_error(igb, "Failed to initialize ndd"); 460 goto attach_fail; 461 } 462 igb->attach_progress |= ATTACH_PROGRESS_NDD; 463 464 /* 465 * Register the driver to the MAC 466 */ 467 if (igb_register_mac(igb) != IGB_SUCCESS) { 468 igb_error(igb, "Failed to register MAC"); 469 goto attach_fail; 470 } 471 igb->attach_progress |= ATTACH_PROGRESS_MAC; 472 473 /* 474 * Now that mutex locks are initialized, and the chip is also 475 * initialized, enable interrupts. 476 */ 477 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 478 igb_error(igb, "Failed to enable DDI interrupts"); 479 goto attach_fail; 480 } 481 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 482 483 igb_log(igb, "%s", igb_version); 484 igb->igb_state |= IGB_INITIALIZED; 485 486 return (DDI_SUCCESS); 487 488 attach_fail: 489 igb_unconfigure(devinfo, igb); 490 return (DDI_FAILURE); 491 } 492 493 /* 494 * igb_detach - driver detach 495 * 496 * The detach() function is the complement of the attach routine. 497 * If cmd is set to DDI_DETACH, detach() is used to remove the 498 * state associated with a given instance of a device node 499 * prior to the removal of that instance from the system. 500 * 501 * The detach() function will be called once for each instance 502 * of the device for which there has been a successful attach() 503 * once there are no longer any opens on the device. 504 * 505 * Interrupts routine are disabled, All memory allocated by this 506 * driver are freed. 507 */ 508 static int 509 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 510 { 511 igb_t *igb; 512 513 /* 514 * Check detach command 515 */ 516 switch (cmd) { 517 default: 518 return (DDI_FAILURE); 519 520 case DDI_SUSPEND: 521 return (igb_suspend(devinfo)); 522 523 case DDI_DETACH: 524 break; 525 } 526 527 528 /* 529 * Get the pointer to the driver private data structure 530 */ 531 igb = (igb_t *)ddi_get_driver_private(devinfo); 532 if (igb == NULL) 533 return (DDI_FAILURE); 534 535 /* 536 * Unregister MAC. If failed, we have to fail the detach 537 */ 538 if (mac_unregister(igb->mac_hdl) != 0) { 539 igb_error(igb, "Failed to unregister MAC"); 540 return (DDI_FAILURE); 541 } 542 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 543 544 /* 545 * If the device is still running, it needs to be stopped first. 546 * This check is necessary because under some specific circumstances, 547 * the detach routine can be called without stopping the interface 548 * first. 549 */ 550 mutex_enter(&igb->gen_lock); 551 if (igb->igb_state & IGB_STARTED) { 552 igb->igb_state &= ~IGB_STARTED; 553 igb_stop(igb); 554 mutex_exit(&igb->gen_lock); 555 /* Disable and stop the watchdog timer */ 556 igb_disable_watchdog_timer(igb); 557 } else 558 mutex_exit(&igb->gen_lock); 559 560 /* 561 * Check if there are still rx buffers held by the upper layer. 562 * If so, fail the detach. 563 */ 564 if (!igb_rx_drain(igb)) 565 return (DDI_FAILURE); 566 567 /* 568 * Do the remaining unconfigure routines 569 */ 570 igb_unconfigure(devinfo, igb); 571 572 return (DDI_SUCCESS); 573 } 574 575 /* 576 * quiesce(9E) entry point. 577 * 578 * This function is called when the system is single-threaded at high 579 * PIL with preemption disabled. Therefore, this function must not be 580 * blocked. 581 * 582 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 583 * DDI_FAILURE indicates an error condition and should almost never happen. 584 */ 585 static int 586 igb_quiesce(dev_info_t *devinfo) 587 { 588 igb_t *igb; 589 struct e1000_hw *hw; 590 591 igb = (igb_t *)ddi_get_driver_private(devinfo); 592 593 if (igb == NULL) 594 return (DDI_FAILURE); 595 596 hw = &igb->hw; 597 598 /* 599 * Disable the adapter interrupts 600 */ 601 igb_disable_adapter_interrupts(igb); 602 603 /* Tell firmware driver is no longer in control */ 604 igb_release_driver_control(hw); 605 606 /* 607 * Reset the chipset 608 */ 609 (void) e1000_reset_hw(hw); 610 611 /* 612 * Reset PHY if possible 613 */ 614 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 615 (void) e1000_phy_hw_reset(hw); 616 617 return (DDI_SUCCESS); 618 } 619 620 /* 621 * igb_unconfigure - release all resources held by this instance 622 */ 623 static void 624 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 625 { 626 /* 627 * Disable interrupt 628 */ 629 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 630 (void) igb_disable_intrs(igb); 631 } 632 633 /* 634 * Unregister MAC 635 */ 636 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 637 (void) mac_unregister(igb->mac_hdl); 638 } 639 640 /* 641 * Free ndd parameters 642 */ 643 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 644 igb_nd_cleanup(igb); 645 } 646 647 /* 648 * Free statistics 649 */ 650 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 651 kstat_delete((kstat_t *)igb->igb_ks); 652 } 653 654 /* 655 * Remove interrupt handlers 656 */ 657 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 658 igb_rem_intr_handlers(igb); 659 } 660 661 /* 662 * Remove interrupts 663 */ 664 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 665 igb_rem_intrs(igb); 666 } 667 668 /* 669 * Remove driver properties 670 */ 671 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 672 (void) ddi_prop_remove_all(devinfo); 673 } 674 675 /* 676 * Release the DMA resources of rx/tx rings 677 */ 678 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_DMA) { 679 igb_free_dma(igb); 680 } 681 682 /* 683 * Stop the adapter 684 */ 685 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 686 mutex_enter(&igb->gen_lock); 687 igb_stop_adapter(igb); 688 mutex_exit(&igb->gen_lock); 689 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 690 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 691 } 692 693 /* 694 * Free register handle 695 */ 696 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 697 if (igb->osdep.reg_handle != NULL) 698 ddi_regs_map_free(&igb->osdep.reg_handle); 699 } 700 701 /* 702 * Free PCI config handle 703 */ 704 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 705 if (igb->osdep.cfg_handle != NULL) 706 pci_config_teardown(&igb->osdep.cfg_handle); 707 } 708 709 /* 710 * Free locks 711 */ 712 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 713 igb_destroy_locks(igb); 714 } 715 716 /* 717 * Free the rx/tx rings 718 */ 719 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 720 igb_free_rings(igb); 721 } 722 723 /* 724 * Remove FMA 725 */ 726 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 727 igb_fm_fini(igb); 728 } 729 730 /* 731 * Free the driver data structure 732 */ 733 kmem_free(igb, sizeof (igb_t)); 734 735 ddi_set_driver_private(devinfo, NULL); 736 } 737 738 /* 739 * igb_register_mac - Register the driver and its function pointers with 740 * the GLD interface 741 */ 742 static int 743 igb_register_mac(igb_t *igb) 744 { 745 struct e1000_hw *hw = &igb->hw; 746 mac_register_t *mac; 747 int status; 748 749 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 750 return (IGB_FAILURE); 751 752 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 753 mac->m_driver = igb; 754 mac->m_dip = igb->dip; 755 mac->m_src_addr = hw->mac.addr; 756 mac->m_callbacks = &igb_m_callbacks; 757 mac->m_min_sdu = 0; 758 mac->m_max_sdu = igb->max_frame_size - 759 sizeof (struct ether_vlan_header) - ETHERFCSL; 760 mac->m_margin = VLAN_TAGSZ; 761 mac->m_v12n = MAC_VIRT_LEVEL1; 762 763 status = mac_register(mac, &igb->mac_hdl); 764 765 mac_free(mac); 766 767 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 768 } 769 770 /* 771 * igb_identify_hardware - Identify the type of the chipset 772 */ 773 static int 774 igb_identify_hardware(igb_t *igb) 775 { 776 struct e1000_hw *hw = &igb->hw; 777 struct igb_osdep *osdep = &igb->osdep; 778 779 /* 780 * Get the device id 781 */ 782 hw->vendor_id = 783 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 784 hw->device_id = 785 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 786 hw->revision_id = 787 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 788 hw->subsystem_device_id = 789 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 790 hw->subsystem_vendor_id = 791 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 792 793 /* 794 * Set the mac type of the adapter based on the device id 795 */ 796 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 797 return (IGB_FAILURE); 798 } 799 800 /* 801 * Install adapter capabilities based on mac type 802 */ 803 switch (hw->mac.type) { 804 case e1000_82575: 805 igb->capab = &igb_82575_cap; 806 break; 807 case e1000_82576: 808 igb->capab = &igb_82576_cap; 809 break; 810 default: 811 return (IGB_FAILURE); 812 } 813 814 return (IGB_SUCCESS); 815 } 816 817 /* 818 * igb_regs_map - Map the device registers 819 */ 820 static int 821 igb_regs_map(igb_t *igb) 822 { 823 dev_info_t *devinfo = igb->dip; 824 struct e1000_hw *hw = &igb->hw; 825 struct igb_osdep *osdep = &igb->osdep; 826 off_t mem_size; 827 828 /* 829 * First get the size of device registers to be mapped. 830 */ 831 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 832 DDI_SUCCESS) { 833 return (IGB_FAILURE); 834 } 835 836 /* 837 * Call ddi_regs_map_setup() to map registers 838 */ 839 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 840 (caddr_t *)&hw->hw_addr, 0, 841 mem_size, &igb_regs_acc_attr, 842 &osdep->reg_handle)) != DDI_SUCCESS) { 843 return (IGB_FAILURE); 844 } 845 846 return (IGB_SUCCESS); 847 } 848 849 /* 850 * igb_init_properties - Initialize driver properties 851 */ 852 static void 853 igb_init_properties(igb_t *igb) 854 { 855 /* 856 * Get conf file properties, including link settings 857 * jumbo frames, ring number, descriptor number, etc. 858 */ 859 igb_get_conf(igb); 860 } 861 862 /* 863 * igb_init_driver_settings - Initialize driver settings 864 * 865 * The settings include hardware function pointers, bus information, 866 * rx/tx rings settings, link state, and any other parameters that 867 * need to be setup during driver initialization. 868 */ 869 static int 870 igb_init_driver_settings(igb_t *igb) 871 { 872 struct e1000_hw *hw = &igb->hw; 873 igb_rx_ring_t *rx_ring; 874 igb_tx_ring_t *tx_ring; 875 uint32_t rx_size; 876 uint32_t tx_size; 877 int i; 878 879 /* 880 * Initialize chipset specific hardware function pointers 881 */ 882 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 883 return (IGB_FAILURE); 884 } 885 886 /* 887 * Get bus information 888 */ 889 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 890 return (IGB_FAILURE); 891 } 892 893 /* 894 * Get the system page size 895 */ 896 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1); 897 898 /* 899 * Set rx buffer size 900 * The IP header alignment room is counted in the calculation. 901 * The rx buffer size is in unit of 1K that is required by the 902 * chipset hardware. 903 */ 904 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 905 igb->rx_buf_size = ((rx_size >> 10) + 906 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 907 908 /* 909 * Set tx buffer size 910 */ 911 tx_size = igb->max_frame_size; 912 igb->tx_buf_size = ((tx_size >> 10) + 913 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 914 915 /* 916 * Initialize rx/tx rings parameters 917 */ 918 for (i = 0; i < igb->num_rx_rings; i++) { 919 rx_ring = &igb->rx_rings[i]; 920 rx_ring->index = i; 921 rx_ring->igb = igb; 922 923 rx_ring->ring_size = igb->rx_ring_size; 924 rx_ring->free_list_size = igb->rx_ring_size; 925 rx_ring->copy_thresh = igb->rx_copy_thresh; 926 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 927 } 928 929 for (i = 0; i < igb->num_tx_rings; i++) { 930 tx_ring = &igb->tx_rings[i]; 931 tx_ring->index = i; 932 tx_ring->igb = igb; 933 if (igb->tx_head_wb_enable) 934 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 935 else 936 tx_ring->tx_recycle = igb_tx_recycle_legacy; 937 938 tx_ring->ring_size = igb->tx_ring_size; 939 tx_ring->free_list_size = igb->tx_ring_size + 940 (igb->tx_ring_size >> 1); 941 tx_ring->copy_thresh = igb->tx_copy_thresh; 942 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 943 tx_ring->overload_thresh = igb->tx_overload_thresh; 944 tx_ring->resched_thresh = igb->tx_resched_thresh; 945 } 946 947 /* 948 * Initialize values of interrupt throttling rates 949 */ 950 for (i = 1; i < MAX_NUM_EITR; i++) 951 igb->intr_throttling[i] = igb->intr_throttling[0]; 952 953 /* 954 * The initial link state should be "unknown" 955 */ 956 igb->link_state = LINK_STATE_UNKNOWN; 957 958 return (IGB_SUCCESS); 959 } 960 961 /* 962 * igb_init_locks - Initialize locks 963 */ 964 static void 965 igb_init_locks(igb_t *igb) 966 { 967 igb_rx_ring_t *rx_ring; 968 igb_tx_ring_t *tx_ring; 969 int i; 970 971 for (i = 0; i < igb->num_rx_rings; i++) { 972 rx_ring = &igb->rx_rings[i]; 973 mutex_init(&rx_ring->rx_lock, NULL, 974 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 975 mutex_init(&rx_ring->recycle_lock, NULL, 976 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 977 } 978 979 for (i = 0; i < igb->num_tx_rings; i++) { 980 tx_ring = &igb->tx_rings[i]; 981 mutex_init(&tx_ring->tx_lock, NULL, 982 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 983 mutex_init(&tx_ring->recycle_lock, NULL, 984 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 985 mutex_init(&tx_ring->tcb_head_lock, NULL, 986 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 987 mutex_init(&tx_ring->tcb_tail_lock, NULL, 988 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 989 } 990 991 mutex_init(&igb->gen_lock, NULL, 992 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 993 994 mutex_init(&igb->watchdog_lock, NULL, 995 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 996 } 997 998 /* 999 * igb_destroy_locks - Destroy locks 1000 */ 1001 static void 1002 igb_destroy_locks(igb_t *igb) 1003 { 1004 igb_rx_ring_t *rx_ring; 1005 igb_tx_ring_t *tx_ring; 1006 int i; 1007 1008 for (i = 0; i < igb->num_rx_rings; i++) { 1009 rx_ring = &igb->rx_rings[i]; 1010 mutex_destroy(&rx_ring->rx_lock); 1011 mutex_destroy(&rx_ring->recycle_lock); 1012 } 1013 1014 for (i = 0; i < igb->num_tx_rings; i++) { 1015 tx_ring = &igb->tx_rings[i]; 1016 mutex_destroy(&tx_ring->tx_lock); 1017 mutex_destroy(&tx_ring->recycle_lock); 1018 mutex_destroy(&tx_ring->tcb_head_lock); 1019 mutex_destroy(&tx_ring->tcb_tail_lock); 1020 } 1021 1022 mutex_destroy(&igb->gen_lock); 1023 mutex_destroy(&igb->watchdog_lock); 1024 } 1025 1026 static int 1027 igb_resume(dev_info_t *devinfo) 1028 { 1029 igb_t *igb; 1030 1031 igb = (igb_t *)ddi_get_driver_private(devinfo); 1032 if (igb == NULL) 1033 return (DDI_FAILURE); 1034 1035 mutex_enter(&igb->gen_lock); 1036 1037 if (igb->igb_state & IGB_STARTED) { 1038 if (igb_start(igb) != IGB_SUCCESS) { 1039 mutex_exit(&igb->gen_lock); 1040 return (DDI_FAILURE); 1041 } 1042 1043 /* 1044 * Enable and start the watchdog timer 1045 */ 1046 igb_enable_watchdog_timer(igb); 1047 } 1048 1049 igb->igb_state &= ~IGB_SUSPENDED; 1050 1051 mutex_exit(&igb->gen_lock); 1052 1053 return (DDI_SUCCESS); 1054 } 1055 1056 static int 1057 igb_suspend(dev_info_t *devinfo) 1058 { 1059 igb_t *igb; 1060 1061 igb = (igb_t *)ddi_get_driver_private(devinfo); 1062 if (igb == NULL) 1063 return (DDI_FAILURE); 1064 1065 mutex_enter(&igb->gen_lock); 1066 1067 igb->igb_state |= IGB_SUSPENDED; 1068 1069 if (!(igb->igb_state & IGB_STARTED)) { 1070 mutex_exit(&igb->gen_lock); 1071 return (DDI_SUCCESS); 1072 } 1073 1074 igb_stop(igb); 1075 1076 mutex_exit(&igb->gen_lock); 1077 1078 /* 1079 * Disable and stop the watchdog timer 1080 */ 1081 igb_disable_watchdog_timer(igb); 1082 1083 return (DDI_SUCCESS); 1084 } 1085 1086 static int 1087 igb_init(igb_t *igb) 1088 { 1089 int i; 1090 1091 mutex_enter(&igb->gen_lock); 1092 1093 /* 1094 * Initilize the adapter 1095 */ 1096 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1097 mutex_exit(&igb->gen_lock); 1098 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1099 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1100 return (IGB_FAILURE); 1101 } 1102 1103 /* 1104 * Setup the rx/tx rings 1105 */ 1106 for (i = 0; i < igb->num_rx_rings; i++) 1107 mutex_enter(&igb->rx_rings[i].rx_lock); 1108 for (i = 0; i < igb->num_tx_rings; i++) 1109 mutex_enter(&igb->tx_rings[i].tx_lock); 1110 1111 igb_setup_rings(igb); 1112 1113 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1114 mutex_exit(&igb->tx_rings[i].tx_lock); 1115 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1116 mutex_exit(&igb->rx_rings[i].rx_lock); 1117 1118 mutex_exit(&igb->gen_lock); 1119 1120 return (IGB_SUCCESS); 1121 } 1122 1123 /* 1124 * igb_init_mac_address - Initialize the default MAC address 1125 * 1126 * On success, the MAC address is entered in the igb->hw.mac.addr 1127 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1128 * address register. 1129 * 1130 * Important side effects: 1131 * 1. adapter is reset - this is required to put it in a known state. 1132 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1133 * MAC address and all default settings are stored, so a valid checksum 1134 * is required. 1135 */ 1136 static int 1137 igb_init_mac_address(igb_t *igb) 1138 { 1139 struct e1000_hw *hw = &igb->hw; 1140 1141 ASSERT(mutex_owned(&igb->gen_lock)); 1142 1143 /* 1144 * Reset chipset to put the hardware in a known state 1145 * before we try to get MAC address from NVM. 1146 */ 1147 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1148 igb_error(igb, "Adapter reset failed."); 1149 goto init_mac_fail; 1150 } 1151 1152 /* 1153 * NVM validation 1154 */ 1155 if (e1000_validate_nvm_checksum(hw) < 0) { 1156 /* 1157 * Some PCI-E parts fail the first check due to 1158 * the link being in sleep state. Call it again, 1159 * if it fails a second time its a real issue. 1160 */ 1161 if (e1000_validate_nvm_checksum(hw) < 0) { 1162 igb_error(igb, 1163 "Invalid NVM checksum. Please contact " 1164 "the vendor to update the NVM."); 1165 goto init_mac_fail; 1166 } 1167 } 1168 1169 /* 1170 * Get the mac address 1171 * This function should handle SPARC case correctly. 1172 */ 1173 if (!igb_find_mac_address(igb)) { 1174 igb_error(igb, "Failed to get the mac address"); 1175 goto init_mac_fail; 1176 } 1177 1178 /* Validate mac address */ 1179 if (!is_valid_mac_addr(hw->mac.addr)) { 1180 igb_error(igb, "Invalid mac address"); 1181 goto init_mac_fail; 1182 } 1183 1184 return (IGB_SUCCESS); 1185 1186 init_mac_fail: 1187 return (IGB_FAILURE); 1188 } 1189 1190 /* 1191 * igb_init_adapter - Initialize the adapter 1192 */ 1193 static int 1194 igb_init_adapter(igb_t *igb) 1195 { 1196 struct e1000_hw *hw = &igb->hw; 1197 uint32_t pba; 1198 uint32_t high_water; 1199 int i; 1200 1201 ASSERT(mutex_owned(&igb->gen_lock)); 1202 1203 /* 1204 * In order to obtain the default MAC address, this will reset the 1205 * adapter and validate the NVM that the address and many other 1206 * default settings come from. 1207 */ 1208 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1209 igb_error(igb, "Failed to initialize MAC address"); 1210 goto init_adapter_fail; 1211 } 1212 1213 /* 1214 * Setup flow control 1215 * 1216 * These parameters set thresholds for the adapter's generation(Tx) 1217 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1218 * settings. Flow control is enabled or disabled in the configuration 1219 * file. 1220 * High-water mark is set down from the top of the rx fifo (not 1221 * sensitive to max_frame_size) and low-water is set just below 1222 * high-water mark. 1223 * The high water mark must be low enough to fit one full frame above 1224 * it in the rx FIFO. Should be the lower of: 1225 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1226 * frame. 1227 */ 1228 /* 1229 * The default setting of PBA is correct for 82575 and other supported 1230 * adapters do not have the E1000_PBA register, so PBA value is only 1231 * used for calculation here and is never written to the adapter. 1232 */ 1233 if (hw->mac.type == e1000_82575) { 1234 pba = E1000_PBA_34K; 1235 } else { 1236 pba = E1000_PBA_64K; 1237 } 1238 1239 high_water = min(((pba << 10) * 9 / 10), 1240 ((pba << 10) - igb->max_frame_size)); 1241 1242 if (hw->mac.type == e1000_82575) { 1243 /* 8-byte granularity */ 1244 hw->fc.high_water = high_water & 0xFFF8; 1245 hw->fc.low_water = hw->fc.high_water - 8; 1246 } else { 1247 /* 16-byte granularity */ 1248 hw->fc.high_water = high_water & 0xFFF0; 1249 hw->fc.low_water = hw->fc.high_water - 16; 1250 } 1251 1252 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1253 hw->fc.send_xon = B_TRUE; 1254 1255 e1000_validate_mdi_setting(hw); 1256 1257 /* 1258 * Reset the chipset hardware the second time to put PBA settings 1259 * into effect. 1260 */ 1261 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1262 igb_error(igb, "Second reset failed"); 1263 goto init_adapter_fail; 1264 } 1265 1266 /* 1267 * Don't wait for auto-negotiation to complete 1268 */ 1269 hw->phy.autoneg_wait_to_complete = B_FALSE; 1270 1271 /* 1272 * Copper options 1273 */ 1274 if (hw->phy.media_type == e1000_media_type_copper) { 1275 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1276 hw->phy.disable_polarity_correction = B_FALSE; 1277 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1278 } 1279 1280 /* 1281 * Initialize link settings 1282 */ 1283 (void) igb_setup_link(igb, B_FALSE); 1284 1285 /* 1286 * Configure/Initialize hardware 1287 */ 1288 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1289 igb_error(igb, "Failed to initialize hardware"); 1290 goto init_adapter_fail; 1291 } 1292 1293 /* 1294 * Disable wakeup control by default 1295 */ 1296 E1000_WRITE_REG(hw, E1000_WUC, 0); 1297 1298 /* 1299 * Record phy info in hw struct 1300 */ 1301 (void) e1000_get_phy_info(hw); 1302 1303 /* 1304 * Make sure driver has control 1305 */ 1306 igb_get_driver_control(hw); 1307 1308 /* 1309 * Restore LED settings to the default from EEPROM 1310 * to meet the standard for Sun platforms. 1311 */ 1312 (void) e1000_cleanup_led(hw); 1313 1314 /* 1315 * Setup MSI-X interrupts 1316 */ 1317 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1318 igb->capab->setup_msix(igb); 1319 1320 /* 1321 * Initialize unicast addresses. 1322 */ 1323 igb_init_unicst(igb); 1324 1325 /* 1326 * Setup and initialize the mctable structures. 1327 */ 1328 igb_setup_multicst(igb); 1329 1330 /* 1331 * Set interrupt throttling rate 1332 */ 1333 for (i = 0; i < igb->intr_cnt; i++) 1334 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1335 1336 /* 1337 * Save the state of the phy 1338 */ 1339 igb_get_phy_state(igb); 1340 1341 return (IGB_SUCCESS); 1342 1343 init_adapter_fail: 1344 /* 1345 * Reset PHY if possible 1346 */ 1347 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1348 (void) e1000_phy_hw_reset(hw); 1349 1350 return (IGB_FAILURE); 1351 } 1352 1353 /* 1354 * igb_stop_adapter - Stop the adapter 1355 */ 1356 static void 1357 igb_stop_adapter(igb_t *igb) 1358 { 1359 struct e1000_hw *hw = &igb->hw; 1360 1361 ASSERT(mutex_owned(&igb->gen_lock)); 1362 1363 /* Tell firmware driver is no longer in control */ 1364 igb_release_driver_control(hw); 1365 1366 /* 1367 * Reset the chipset 1368 */ 1369 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1370 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1371 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1372 } 1373 1374 /* 1375 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1376 */ 1377 } 1378 1379 /* 1380 * igb_reset - Reset the chipset and restart the driver. 1381 * 1382 * It involves stopping and re-starting the chipset, 1383 * and re-configuring the rx/tx rings. 1384 */ 1385 static int 1386 igb_reset(igb_t *igb) 1387 { 1388 int i; 1389 1390 mutex_enter(&igb->gen_lock); 1391 1392 ASSERT(igb->igb_state & IGB_STARTED); 1393 1394 /* 1395 * Disable the adapter interrupts to stop any rx/tx activities 1396 * before draining pending data and resetting hardware. 1397 */ 1398 igb_disable_adapter_interrupts(igb); 1399 1400 /* 1401 * Drain the pending transmit packets 1402 */ 1403 (void) igb_tx_drain(igb); 1404 1405 for (i = 0; i < igb->num_rx_rings; i++) 1406 mutex_enter(&igb->rx_rings[i].rx_lock); 1407 for (i = 0; i < igb->num_tx_rings; i++) 1408 mutex_enter(&igb->tx_rings[i].tx_lock); 1409 1410 /* 1411 * Stop the adapter 1412 */ 1413 igb_stop_adapter(igb); 1414 1415 /* 1416 * Clean the pending tx data/resources 1417 */ 1418 igb_tx_clean(igb); 1419 1420 /* 1421 * Start the adapter 1422 */ 1423 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1424 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1425 goto reset_failure; 1426 } 1427 1428 /* 1429 * Setup the rx/tx rings 1430 */ 1431 igb_setup_rings(igb); 1432 1433 /* 1434 * Enable adapter interrupts 1435 * The interrupts must be enabled after the driver state is START 1436 */ 1437 igb->capab->enable_intr(igb); 1438 1439 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1440 goto reset_failure; 1441 1442 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1443 goto reset_failure; 1444 1445 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1446 mutex_exit(&igb->tx_rings[i].tx_lock); 1447 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1448 mutex_exit(&igb->rx_rings[i].rx_lock); 1449 1450 mutex_exit(&igb->gen_lock); 1451 1452 return (IGB_SUCCESS); 1453 1454 reset_failure: 1455 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1456 mutex_exit(&igb->tx_rings[i].tx_lock); 1457 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1458 mutex_exit(&igb->rx_rings[i].rx_lock); 1459 1460 mutex_exit(&igb->gen_lock); 1461 1462 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1463 1464 return (IGB_FAILURE); 1465 } 1466 1467 /* 1468 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1469 */ 1470 static void 1471 igb_tx_clean(igb_t *igb) 1472 { 1473 igb_tx_ring_t *tx_ring; 1474 tx_control_block_t *tcb; 1475 link_list_t pending_list; 1476 uint32_t desc_num; 1477 int i, j; 1478 1479 LINK_LIST_INIT(&pending_list); 1480 1481 for (i = 0; i < igb->num_tx_rings; i++) { 1482 tx_ring = &igb->tx_rings[i]; 1483 1484 mutex_enter(&tx_ring->recycle_lock); 1485 1486 /* 1487 * Clean the pending tx data - the pending packets in the 1488 * work_list that have no chances to be transmitted again. 1489 * 1490 * We must ensure the chipset is stopped or the link is down 1491 * before cleaning the transmit packets. 1492 */ 1493 desc_num = 0; 1494 for (j = 0; j < tx_ring->ring_size; j++) { 1495 tcb = tx_ring->work_list[j]; 1496 if (tcb != NULL) { 1497 desc_num += tcb->desc_num; 1498 1499 tx_ring->work_list[j] = NULL; 1500 1501 igb_free_tcb(tcb); 1502 1503 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1504 } 1505 } 1506 1507 if (desc_num > 0) { 1508 atomic_add_32(&tx_ring->tbd_free, desc_num); 1509 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1510 1511 /* 1512 * Reset the head and tail pointers of the tbd ring; 1513 * Reset the head write-back if it is enabled. 1514 */ 1515 tx_ring->tbd_head = 0; 1516 tx_ring->tbd_tail = 0; 1517 if (igb->tx_head_wb_enable) 1518 *tx_ring->tbd_head_wb = 0; 1519 1520 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1521 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1522 } 1523 1524 mutex_exit(&tx_ring->recycle_lock); 1525 1526 /* 1527 * Add the tx control blocks in the pending list to 1528 * the free list. 1529 */ 1530 igb_put_free_list(tx_ring, &pending_list); 1531 } 1532 } 1533 1534 /* 1535 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1536 */ 1537 static boolean_t 1538 igb_tx_drain(igb_t *igb) 1539 { 1540 igb_tx_ring_t *tx_ring; 1541 boolean_t done; 1542 int i, j; 1543 1544 /* 1545 * Wait for a specific time to allow pending tx packets 1546 * to be transmitted. 1547 * 1548 * Check the counter tbd_free to see if transmission is done. 1549 * No lock protection is needed here. 1550 * 1551 * Return B_TRUE if all pending packets have been transmitted; 1552 * Otherwise return B_FALSE; 1553 */ 1554 for (i = 0; i < TX_DRAIN_TIME; i++) { 1555 1556 done = B_TRUE; 1557 for (j = 0; j < igb->num_tx_rings; j++) { 1558 tx_ring = &igb->tx_rings[j]; 1559 done = done && 1560 (tx_ring->tbd_free == tx_ring->ring_size); 1561 } 1562 1563 if (done) 1564 break; 1565 1566 msec_delay(1); 1567 } 1568 1569 return (done); 1570 } 1571 1572 /* 1573 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1574 */ 1575 static boolean_t 1576 igb_rx_drain(igb_t *igb) 1577 { 1578 igb_rx_ring_t *rx_ring; 1579 boolean_t done; 1580 int i, j; 1581 1582 /* 1583 * Polling the rx free list to check if those rx buffers held by 1584 * the upper layer are released. 1585 * 1586 * Check the counter rcb_free to see if all pending buffers are 1587 * released. No lock protection is needed here. 1588 * 1589 * Return B_TRUE if all pending buffers have been released; 1590 * Otherwise return B_FALSE; 1591 */ 1592 for (i = 0; i < RX_DRAIN_TIME; i++) { 1593 1594 done = B_TRUE; 1595 for (j = 0; j < igb->num_rx_rings; j++) { 1596 rx_ring = &igb->rx_rings[j]; 1597 done = done && 1598 (rx_ring->rcb_free == rx_ring->free_list_size); 1599 } 1600 1601 if (done) 1602 break; 1603 1604 msec_delay(1); 1605 } 1606 1607 return (done); 1608 } 1609 1610 /* 1611 * igb_start - Start the driver/chipset 1612 */ 1613 int 1614 igb_start(igb_t *igb) 1615 { 1616 int i; 1617 1618 ASSERT(mutex_owned(&igb->gen_lock)); 1619 1620 for (i = 0; i < igb->num_rx_rings; i++) 1621 mutex_enter(&igb->rx_rings[i].rx_lock); 1622 for (i = 0; i < igb->num_tx_rings; i++) 1623 mutex_enter(&igb->tx_rings[i].tx_lock); 1624 1625 /* 1626 * Start the adapter 1627 */ 1628 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1629 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1630 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1631 goto start_failure; 1632 } 1633 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1634 1635 /* 1636 * Setup the rx/tx rings 1637 */ 1638 igb_setup_rings(igb); 1639 } 1640 1641 /* 1642 * Enable adapter interrupts 1643 * The interrupts must be enabled after the driver state is START 1644 */ 1645 igb->capab->enable_intr(igb); 1646 1647 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1648 goto start_failure; 1649 1650 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1651 goto start_failure; 1652 1653 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1654 mutex_exit(&igb->tx_rings[i].tx_lock); 1655 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1656 mutex_exit(&igb->rx_rings[i].rx_lock); 1657 1658 return (IGB_SUCCESS); 1659 1660 start_failure: 1661 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1662 mutex_exit(&igb->tx_rings[i].tx_lock); 1663 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1664 mutex_exit(&igb->rx_rings[i].rx_lock); 1665 1666 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1667 1668 return (IGB_FAILURE); 1669 } 1670 1671 /* 1672 * igb_stop - Stop the driver/chipset 1673 */ 1674 void 1675 igb_stop(igb_t *igb) 1676 { 1677 int i; 1678 1679 ASSERT(mutex_owned(&igb->gen_lock)); 1680 1681 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1682 1683 /* 1684 * Disable the adapter interrupts 1685 */ 1686 igb_disable_adapter_interrupts(igb); 1687 1688 /* 1689 * Drain the pending tx packets 1690 */ 1691 (void) igb_tx_drain(igb); 1692 1693 for (i = 0; i < igb->num_rx_rings; i++) 1694 mutex_enter(&igb->rx_rings[i].rx_lock); 1695 for (i = 0; i < igb->num_tx_rings; i++) 1696 mutex_enter(&igb->tx_rings[i].tx_lock); 1697 1698 /* 1699 * Stop the adapter 1700 */ 1701 igb_stop_adapter(igb); 1702 1703 /* 1704 * Clean the pending tx data/resources 1705 */ 1706 igb_tx_clean(igb); 1707 1708 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1709 mutex_exit(&igb->tx_rings[i].tx_lock); 1710 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1711 mutex_exit(&igb->rx_rings[i].rx_lock); 1712 1713 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1714 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1715 } 1716 1717 /* 1718 * igb_alloc_rings - Allocate memory space for rx/tx rings 1719 */ 1720 static int 1721 igb_alloc_rings(igb_t *igb) 1722 { 1723 /* 1724 * Allocate memory space for rx rings 1725 */ 1726 igb->rx_rings = kmem_zalloc( 1727 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1728 KM_NOSLEEP); 1729 1730 if (igb->rx_rings == NULL) { 1731 return (IGB_FAILURE); 1732 } 1733 1734 /* 1735 * Allocate memory space for tx rings 1736 */ 1737 igb->tx_rings = kmem_zalloc( 1738 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1739 KM_NOSLEEP); 1740 1741 if (igb->tx_rings == NULL) { 1742 kmem_free(igb->rx_rings, 1743 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1744 igb->rx_rings = NULL; 1745 return (IGB_FAILURE); 1746 } 1747 1748 /* 1749 * Allocate memory space for rx ring groups 1750 */ 1751 igb->rx_groups = kmem_zalloc( 1752 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1753 KM_NOSLEEP); 1754 1755 if (igb->rx_groups == NULL) { 1756 kmem_free(igb->rx_rings, 1757 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1758 kmem_free(igb->tx_rings, 1759 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1760 igb->rx_rings = NULL; 1761 igb->tx_rings = NULL; 1762 return (IGB_FAILURE); 1763 } 1764 1765 return (IGB_SUCCESS); 1766 } 1767 1768 /* 1769 * igb_free_rings - Free the memory space of rx/tx rings. 1770 */ 1771 static void 1772 igb_free_rings(igb_t *igb) 1773 { 1774 if (igb->rx_rings != NULL) { 1775 kmem_free(igb->rx_rings, 1776 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1777 igb->rx_rings = NULL; 1778 } 1779 1780 if (igb->tx_rings != NULL) { 1781 kmem_free(igb->tx_rings, 1782 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1783 igb->tx_rings = NULL; 1784 } 1785 1786 if (igb->rx_groups != NULL) { 1787 kmem_free(igb->rx_groups, 1788 sizeof (igb_rx_group_t) * igb->num_rx_groups); 1789 igb->rx_groups = NULL; 1790 } 1791 } 1792 1793 /* 1794 * igb_setup_rings - Setup rx/tx rings 1795 */ 1796 static void 1797 igb_setup_rings(igb_t *igb) 1798 { 1799 /* 1800 * Setup the rx/tx rings, including the following: 1801 * 1802 * 1. Setup the descriptor ring and the control block buffers; 1803 * 2. Initialize necessary registers for receive/transmit; 1804 * 3. Initialize software pointers/parameters for receive/transmit; 1805 */ 1806 igb_setup_rx(igb); 1807 1808 igb_setup_tx(igb); 1809 1810 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1811 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1812 } 1813 1814 static void 1815 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1816 { 1817 igb_t *igb = rx_ring->igb; 1818 struct e1000_hw *hw = &igb->hw; 1819 rx_control_block_t *rcb; 1820 union e1000_adv_rx_desc *rbd; 1821 uint32_t size; 1822 uint32_t buf_low; 1823 uint32_t buf_high; 1824 uint32_t rxdctl; 1825 int i; 1826 1827 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1828 ASSERT(mutex_owned(&igb->gen_lock)); 1829 1830 /* 1831 * Initialize descriptor ring with buffer addresses 1832 */ 1833 for (i = 0; i < igb->rx_ring_size; i++) { 1834 rcb = rx_ring->work_list[i]; 1835 rbd = &rx_ring->rbd_ring[i]; 1836 1837 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1838 rbd->read.hdr_addr = NULL; 1839 } 1840 1841 /* 1842 * Initialize the base address registers 1843 */ 1844 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1845 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1846 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1847 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1848 1849 /* 1850 * Initialize the length register 1851 */ 1852 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1853 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1854 1855 /* 1856 * Initialize buffer size & descriptor type 1857 */ 1858 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 1859 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1860 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 1861 1862 /* 1863 * Setup the Receive Descriptor Control Register (RXDCTL) 1864 */ 1865 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1866 rxdctl &= igb->capab->rxdctl_mask; 1867 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 1868 rxdctl |= 16; /* pthresh */ 1869 rxdctl |= 8 << 8; /* hthresh */ 1870 rxdctl |= 1 << 16; /* wthresh */ 1871 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 1872 1873 rx_ring->rbd_next = 0; 1874 1875 /* 1876 * Note: Considering the case that the chipset is being reset 1877 * and there are still some buffers held by the upper layer, 1878 * we should not reset the values of rcb_head, rcb_tail and 1879 * rcb_free; 1880 */ 1881 if (igb->igb_state == IGB_UNKNOWN) { 1882 rx_ring->rcb_head = 0; 1883 rx_ring->rcb_tail = 0; 1884 rx_ring->rcb_free = rx_ring->free_list_size; 1885 } 1886 } 1887 1888 static void 1889 igb_setup_rx(igb_t *igb) 1890 { 1891 igb_rx_ring_t *rx_ring; 1892 igb_rx_group_t *rx_group; 1893 struct e1000_hw *hw = &igb->hw; 1894 uint32_t rctl, rxcsum; 1895 uint32_t ring_per_group; 1896 int i; 1897 1898 /* 1899 * Setup the Receive Control Register (RCTL), and enable the 1900 * receiver. The initial configuration is to: enable the receiver, 1901 * accept broadcasts, discard bad packets, accept long packets, 1902 * disable VLAN filter checking, and set receive buffer size to 1903 * 2k. For 82575, also set the receive descriptor minimum 1904 * threshold size to 1/2 the ring. 1905 */ 1906 rctl = E1000_READ_REG(hw, E1000_RCTL); 1907 1908 /* 1909 * Clear the field used for wakeup control. This driver doesn't do 1910 * wakeup but leave this here for completeness. 1911 */ 1912 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 1913 1914 switch (hw->mac.type) { 1915 case e1000_82575: 1916 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1917 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1918 E1000_RCTL_LPE | /* Large Packet Enable */ 1919 /* Multicast filter offset */ 1920 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1921 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 1922 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1923 break; 1924 1925 case e1000_82576: 1926 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 1927 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1928 E1000_RCTL_LPE | /* Large Packet Enable */ 1929 /* Multicast filter offset */ 1930 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1931 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 1932 break; 1933 1934 default: 1935 igb_log(igb, "unsupported MAC type: %d", hw->mac.type); 1936 return; /* should never come here; this will cause rx failure */ 1937 } 1938 1939 for (i = 0; i < igb->num_rx_groups; i++) { 1940 rx_group = &igb->rx_groups[i]; 1941 rx_group->index = i; 1942 rx_group->igb = igb; 1943 } 1944 1945 /* 1946 * Set up all rx descriptor rings - must be called before receive unit 1947 * enabled. 1948 */ 1949 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 1950 for (i = 0; i < igb->num_rx_rings; i++) { 1951 rx_ring = &igb->rx_rings[i]; 1952 igb_setup_rx_ring(rx_ring); 1953 1954 /* 1955 * Map a ring to a group by assigning a group index 1956 */ 1957 rx_ring->group_index = i / ring_per_group; 1958 } 1959 1960 /* 1961 * Setup the Rx Long Packet Max Length register 1962 */ 1963 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1964 1965 /* 1966 * Hardware checksum settings 1967 */ 1968 if (igb->rx_hcksum_enable) { 1969 rxcsum = 1970 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1971 E1000_RXCSUM_IPOFL; /* IP checksum */ 1972 1973 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1974 } 1975 1976 /* 1977 * Setup classify and RSS for multiple receive queues 1978 */ 1979 switch (igb->vmdq_mode) { 1980 case E1000_VMDQ_OFF: 1981 /* 1982 * One ring group, only RSS is needed when more than 1983 * one ring enabled. 1984 */ 1985 if (igb->num_rx_rings > 1) 1986 igb_setup_rss(igb); 1987 break; 1988 case E1000_VMDQ_MAC: 1989 /* 1990 * Multiple groups, each group has one ring, 1991 * only the MAC classification is needed. 1992 */ 1993 igb_setup_mac_classify(igb); 1994 break; 1995 case E1000_VMDQ_MAC_RSS: 1996 /* 1997 * Multiple groups and multiple rings, both 1998 * MAC classification and RSS are needed. 1999 */ 2000 igb_setup_mac_rss_classify(igb); 2001 break; 2002 } 2003 2004 /* 2005 * Enable the receive unit - must be done after all 2006 * the rx setup above. 2007 */ 2008 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2009 2010 /* 2011 * Initialize all adapter ring head & tail pointers - must 2012 * be done after receive unit is enabled 2013 */ 2014 for (i = 0; i < igb->num_rx_rings; i++) { 2015 rx_ring = &igb->rx_rings[i]; 2016 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2017 E1000_WRITE_REG(hw, E1000_RDT(i), rx_ring->ring_size - 1); 2018 } 2019 2020 /* 2021 * 82575 with manageability enabled needs a special flush to make 2022 * sure the fifos start clean. 2023 */ 2024 if ((hw->mac.type == e1000_82575) && 2025 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2026 e1000_rx_fifo_flush_82575(hw); 2027 } 2028 } 2029 2030 static void 2031 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2032 { 2033 igb_t *igb = tx_ring->igb; 2034 struct e1000_hw *hw = &igb->hw; 2035 uint32_t size; 2036 uint32_t buf_low; 2037 uint32_t buf_high; 2038 uint32_t reg_val; 2039 2040 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2041 ASSERT(mutex_owned(&igb->gen_lock)); 2042 2043 2044 /* 2045 * Initialize the length register 2046 */ 2047 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2048 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2049 2050 /* 2051 * Initialize the base address registers 2052 */ 2053 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2054 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2055 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2056 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2057 2058 /* 2059 * Setup head & tail pointers 2060 */ 2061 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2062 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2063 2064 /* 2065 * Setup head write-back 2066 */ 2067 if (igb->tx_head_wb_enable) { 2068 /* 2069 * The memory of the head write-back is allocated using 2070 * the extra tbd beyond the tail of the tbd ring. 2071 */ 2072 tx_ring->tbd_head_wb = (uint32_t *) 2073 ((uintptr_t)tx_ring->tbd_area.address + size); 2074 *tx_ring->tbd_head_wb = 0; 2075 2076 buf_low = (uint32_t) 2077 (tx_ring->tbd_area.dma_address + size); 2078 buf_high = (uint32_t) 2079 ((tx_ring->tbd_area.dma_address + size) >> 32); 2080 2081 /* Set the head write-back enable bit */ 2082 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2083 2084 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2085 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2086 2087 /* 2088 * Turn off relaxed ordering for head write back or it will 2089 * cause problems with the tx recycling 2090 */ 2091 reg_val = E1000_READ_REG(hw, 2092 E1000_DCA_TXCTRL(tx_ring->index)); 2093 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2094 E1000_WRITE_REG(hw, 2095 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2096 } else { 2097 tx_ring->tbd_head_wb = NULL; 2098 } 2099 2100 tx_ring->tbd_head = 0; 2101 tx_ring->tbd_tail = 0; 2102 tx_ring->tbd_free = tx_ring->ring_size; 2103 2104 /* 2105 * Note: for the case that the chipset is being reset, we should not 2106 * reset the values of tcb_head, tcb_tail. And considering there might 2107 * still be some packets kept in the pending_list, we should not assert 2108 * (tcb_free == free_list_size) here. 2109 */ 2110 if (igb->igb_state == IGB_UNKNOWN) { 2111 tx_ring->tcb_head = 0; 2112 tx_ring->tcb_tail = 0; 2113 tx_ring->tcb_free = tx_ring->free_list_size; 2114 } 2115 2116 /* 2117 * Enable TXDCTL per queue 2118 */ 2119 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2120 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2121 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2122 2123 /* 2124 * Initialize hardware checksum offload settings 2125 */ 2126 bzero(&tx_ring->tx_context, sizeof (tx_context_t)); 2127 } 2128 2129 static void 2130 igb_setup_tx(igb_t *igb) 2131 { 2132 igb_tx_ring_t *tx_ring; 2133 struct e1000_hw *hw = &igb->hw; 2134 uint32_t reg_val; 2135 int i; 2136 2137 for (i = 0; i < igb->num_tx_rings; i++) { 2138 tx_ring = &igb->tx_rings[i]; 2139 igb_setup_tx_ring(tx_ring); 2140 } 2141 2142 /* 2143 * Setup the Transmit Control Register (TCTL) 2144 */ 2145 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2146 reg_val &= ~E1000_TCTL_CT; 2147 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2148 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2149 2150 /* Enable transmits */ 2151 reg_val |= E1000_TCTL_EN; 2152 2153 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2154 } 2155 2156 /* 2157 * igb_setup_rss - Setup receive-side scaling feature 2158 */ 2159 static void 2160 igb_setup_rss(igb_t *igb) 2161 { 2162 struct e1000_hw *hw = &igb->hw; 2163 uint32_t i, mrqc, rxcsum; 2164 int shift = 0; 2165 uint32_t random; 2166 union e1000_reta { 2167 uint32_t dword; 2168 uint8_t bytes[4]; 2169 } reta; 2170 2171 /* Setup the Redirection Table */ 2172 if (hw->mac.type == e1000_82576) { 2173 shift = 0; 2174 } else if (hw->mac.type == e1000_82575) { 2175 shift = 6; 2176 } 2177 for (i = 0; i < (32 * 4); i++) { 2178 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2179 if ((i & 3) == 3) { 2180 E1000_WRITE_REG(hw, 2181 (E1000_RETA(0) + (i & ~3)), reta.dword); 2182 } 2183 } 2184 2185 /* Fill out hash function seeds */ 2186 for (i = 0; i < 10; i++) { 2187 (void) random_get_pseudo_bytes((uint8_t *)&random, 2188 sizeof (uint32_t)); 2189 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2190 } 2191 2192 /* Setup the Multiple Receive Queue Control register */ 2193 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2194 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2195 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2196 E1000_MRQC_RSS_FIELD_IPV6 | 2197 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2198 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2199 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2200 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2201 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2202 2203 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2204 2205 /* 2206 * Disable Packet Checksum to enable RSS for multiple receive queues. 2207 * 2208 * The Packet Checksum is not ethernet CRC. It is another kind of 2209 * checksum offloading provided by the 82575 chipset besides the IP 2210 * header checksum offloading and the TCP/UDP checksum offloading. 2211 * The Packet Checksum is by default computed over the entire packet 2212 * from the first byte of the DA through the last byte of the CRC, 2213 * including the Ethernet and IP headers. 2214 * 2215 * It is a hardware limitation that Packet Checksum is mutually 2216 * exclusive with RSS. 2217 */ 2218 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2219 rxcsum |= E1000_RXCSUM_PCSD; 2220 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2221 } 2222 2223 /* 2224 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2225 */ 2226 static void 2227 igb_setup_mac_rss_classify(igb_t *igb) 2228 { 2229 struct e1000_hw *hw = &igb->hw; 2230 uint32_t i, mrqc, vmdctl, rxcsum; 2231 uint32_t ring_per_group; 2232 int shift_group0, shift_group1; 2233 uint32_t random; 2234 union e1000_reta { 2235 uint32_t dword; 2236 uint8_t bytes[4]; 2237 } reta; 2238 2239 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2240 2241 /* Setup the Redirection Table, it is shared between two groups */ 2242 shift_group0 = 2; 2243 shift_group1 = 6; 2244 for (i = 0; i < (32 * 4); i++) { 2245 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2246 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2247 if ((i & 3) == 3) { 2248 E1000_WRITE_REG(hw, 2249 (E1000_RETA(0) + (i & ~3)), reta.dword); 2250 } 2251 } 2252 2253 /* Fill out hash function seeds */ 2254 for (i = 0; i < 10; i++) { 2255 (void) random_get_pseudo_bytes((uint8_t *)&random, 2256 sizeof (uint32_t)); 2257 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2258 } 2259 2260 /* 2261 * Setup the Multiple Receive Queue Control register, 2262 * enable VMDq based on packet destination MAC address and RSS. 2263 */ 2264 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2265 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2266 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2267 E1000_MRQC_RSS_FIELD_IPV6 | 2268 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2269 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2270 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2271 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2272 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2273 2274 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2275 2276 2277 /* Define the default group and default queues */ 2278 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2279 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2280 2281 /* 2282 * Disable Packet Checksum to enable RSS for multiple receive queues. 2283 * 2284 * The Packet Checksum is not ethernet CRC. It is another kind of 2285 * checksum offloading provided by the 82575 chipset besides the IP 2286 * header checksum offloading and the TCP/UDP checksum offloading. 2287 * The Packet Checksum is by default computed over the entire packet 2288 * from the first byte of the DA through the last byte of the CRC, 2289 * including the Ethernet and IP headers. 2290 * 2291 * It is a hardware limitation that Packet Checksum is mutually 2292 * exclusive with RSS. 2293 */ 2294 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2295 rxcsum |= E1000_RXCSUM_PCSD; 2296 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2297 } 2298 2299 /* 2300 * igb_setup_mac_classify - Setup MAC classification feature 2301 */ 2302 static void 2303 igb_setup_mac_classify(igb_t *igb) 2304 { 2305 struct e1000_hw *hw = &igb->hw; 2306 uint32_t mrqc, rxcsum; 2307 2308 /* 2309 * Setup the Multiple Receive Queue Control register, 2310 * enable VMDq based on packet destination MAC address. 2311 */ 2312 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2313 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2314 2315 /* 2316 * Disable Packet Checksum to enable RSS for multiple receive queues. 2317 * 2318 * The Packet Checksum is not ethernet CRC. It is another kind of 2319 * checksum offloading provided by the 82575 chipset besides the IP 2320 * header checksum offloading and the TCP/UDP checksum offloading. 2321 * The Packet Checksum is by default computed over the entire packet 2322 * from the first byte of the DA through the last byte of the CRC, 2323 * including the Ethernet and IP headers. 2324 * 2325 * It is a hardware limitation that Packet Checksum is mutually 2326 * exclusive with RSS. 2327 */ 2328 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2329 rxcsum |= E1000_RXCSUM_PCSD; 2330 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2331 2332 } 2333 2334 /* 2335 * igb_init_unicst - Initialize the unicast addresses 2336 */ 2337 static void 2338 igb_init_unicst(igb_t *igb) 2339 { 2340 struct e1000_hw *hw = &igb->hw; 2341 int slot; 2342 2343 /* 2344 * Here we should consider two situations: 2345 * 2346 * 1. Chipset is initialized the first time 2347 * Initialize the multiple unicast addresses, and 2348 * save the default MAC address. 2349 * 2350 * 2. Chipset is reset 2351 * Recover the multiple unicast addresses from the 2352 * software data structure to the RAR registers. 2353 */ 2354 2355 /* 2356 * Clear the default MAC address in the RAR0 rgister, 2357 * which is loaded from EEPROM when system boot or chipreset, 2358 * this will cause the conficts with add_mac/rem_mac entry 2359 * points when VMDq is enabled. For this reason, the RAR0 2360 * must be cleared for both cases mentioned above. 2361 */ 2362 e1000_rar_clear(hw, 0); 2363 2364 if (!igb->unicst_init) { 2365 2366 /* Initialize the multiple unicast addresses */ 2367 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2368 igb->unicst_avail = igb->unicst_total; 2369 2370 for (slot = 0; slot < igb->unicst_total; slot++) 2371 igb->unicst_addr[slot].mac.set = 0; 2372 2373 igb->unicst_init = B_TRUE; 2374 } else { 2375 /* Re-configure the RAR registers */ 2376 for (slot = 0; slot < igb->unicst_total; slot++) { 2377 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2378 slot, igb->vmdq_mode, 2379 igb->unicst_addr[slot].mac.group_index); 2380 } 2381 } 2382 2383 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2384 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2385 } 2386 2387 /* 2388 * igb_unicst_find - Find the slot for the specified unicast address 2389 */ 2390 int 2391 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2392 { 2393 int slot; 2394 2395 ASSERT(mutex_owned(&igb->gen_lock)); 2396 2397 for (slot = 0; slot < igb->unicst_total; slot++) { 2398 if (bcmp(igb->unicst_addr[slot].mac.addr, 2399 mac_addr, ETHERADDRL) == 0) 2400 return (slot); 2401 } 2402 2403 return (-1); 2404 } 2405 2406 /* 2407 * igb_unicst_set - Set the unicast address to the specified slot 2408 */ 2409 int 2410 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2411 int slot) 2412 { 2413 struct e1000_hw *hw = &igb->hw; 2414 2415 ASSERT(mutex_owned(&igb->gen_lock)); 2416 2417 /* 2418 * Save the unicast address in the software data structure 2419 */ 2420 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2421 2422 /* 2423 * Set the unicast address to the RAR register 2424 */ 2425 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2426 2427 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2428 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2429 return (EIO); 2430 } 2431 2432 return (0); 2433 } 2434 2435 /* 2436 * igb_multicst_add - Add a multicst address 2437 */ 2438 int 2439 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2440 { 2441 ASSERT(mutex_owned(&igb->gen_lock)); 2442 2443 if ((multiaddr[0] & 01) == 0) { 2444 return (EINVAL); 2445 } 2446 2447 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2448 return (ENOENT); 2449 } 2450 2451 bcopy(multiaddr, 2452 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2453 igb->mcast_count++; 2454 2455 /* 2456 * Update the multicast table in the hardware 2457 */ 2458 igb_setup_multicst(igb); 2459 2460 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2461 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2462 return (EIO); 2463 } 2464 2465 return (0); 2466 } 2467 2468 /* 2469 * igb_multicst_remove - Remove a multicst address 2470 */ 2471 int 2472 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2473 { 2474 int i; 2475 2476 ASSERT(mutex_owned(&igb->gen_lock)); 2477 2478 for (i = 0; i < igb->mcast_count; i++) { 2479 if (bcmp(multiaddr, &igb->mcast_table[i], 2480 ETHERADDRL) == 0) { 2481 for (i++; i < igb->mcast_count; i++) { 2482 igb->mcast_table[i - 1] = 2483 igb->mcast_table[i]; 2484 } 2485 igb->mcast_count--; 2486 break; 2487 } 2488 } 2489 2490 /* 2491 * Update the multicast table in the hardware 2492 */ 2493 igb_setup_multicst(igb); 2494 2495 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2496 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2497 return (EIO); 2498 } 2499 2500 return (0); 2501 } 2502 2503 /* 2504 * igb_setup_multicast - setup multicast data structures 2505 * 2506 * This routine initializes all of the multicast related structures 2507 * and save them in the hardware registers. 2508 */ 2509 static void 2510 igb_setup_multicst(igb_t *igb) 2511 { 2512 uint8_t *mc_addr_list; 2513 uint32_t mc_addr_count; 2514 struct e1000_hw *hw = &igb->hw; 2515 2516 ASSERT(mutex_owned(&igb->gen_lock)); 2517 2518 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2519 2520 mc_addr_list = (uint8_t *)igb->mcast_table; 2521 mc_addr_count = igb->mcast_count; 2522 2523 /* 2524 * Update the multicase addresses to the MTA registers 2525 */ 2526 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2527 igb->unicst_total, hw->mac.rar_entry_count); 2528 } 2529 2530 /* 2531 * igb_get_conf - Get driver configurations set in driver.conf 2532 * 2533 * This routine gets user-configured values out of the configuration 2534 * file igb.conf. 2535 * 2536 * For each configurable value, there is a minimum, a maximum, and a 2537 * default. 2538 * If user does not configure a value, use the default. 2539 * If user configures below the minimum, use the minumum. 2540 * If user configures above the maximum, use the maxumum. 2541 */ 2542 static void 2543 igb_get_conf(igb_t *igb) 2544 { 2545 struct e1000_hw *hw = &igb->hw; 2546 uint32_t default_mtu; 2547 uint32_t flow_control; 2548 uint32_t ring_per_group; 2549 int i; 2550 2551 /* 2552 * igb driver supports the following user configurations: 2553 * 2554 * Link configurations: 2555 * adv_autoneg_cap 2556 * adv_1000fdx_cap 2557 * adv_100fdx_cap 2558 * adv_100hdx_cap 2559 * adv_10fdx_cap 2560 * adv_10hdx_cap 2561 * Note: 1000hdx is not supported. 2562 * 2563 * Jumbo frame configuration: 2564 * default_mtu 2565 * 2566 * Ethernet flow control configuration: 2567 * flow_control 2568 * 2569 * Multiple rings configurations: 2570 * tx_queue_number 2571 * tx_ring_size 2572 * rx_queue_number 2573 * rx_ring_size 2574 * 2575 * Call igb_get_prop() to get the value for a specific 2576 * configuration parameter. 2577 */ 2578 2579 /* 2580 * Link configurations 2581 */ 2582 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2583 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2584 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2585 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2586 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2587 PROP_ADV_100FDX_CAP, 0, 1, 1); 2588 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2589 PROP_ADV_100HDX_CAP, 0, 1, 1); 2590 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2591 PROP_ADV_10FDX_CAP, 0, 1, 1); 2592 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2593 PROP_ADV_10HDX_CAP, 0, 1, 1); 2594 2595 /* 2596 * Jumbo frame configurations 2597 */ 2598 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2599 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2600 2601 igb->max_frame_size = default_mtu + 2602 sizeof (struct ether_vlan_header) + ETHERFCSL; 2603 2604 /* 2605 * Ethernet flow control configuration 2606 */ 2607 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2608 e1000_fc_none, 4, e1000_fc_full); 2609 if (flow_control == 4) 2610 flow_control = e1000_fc_default; 2611 2612 hw->fc.requested_mode = flow_control; 2613 2614 /* 2615 * Multiple rings configurations 2616 */ 2617 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2618 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2619 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2620 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2621 2622 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 1); 2623 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2624 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2625 /* 2626 * Currently we do not support VMDq for 82576. 2627 * If it is e1000_82576, set num_rx_groups to 1. 2628 */ 2629 if (hw->mac.type == e1000_82576) 2630 igb->num_rx_groups = 1; 2631 2632 if (igb->mr_enable) { 2633 igb->num_tx_rings = igb->capab->def_tx_que_num; 2634 igb->num_rx_rings = igb->capab->def_rx_que_num; 2635 } else { 2636 igb->num_tx_rings = 1; 2637 igb->num_rx_rings = 1; 2638 2639 if (igb->num_rx_groups > 1) { 2640 igb_error(igb, 2641 "Invalid rx groups number. Please enable multiple " 2642 "rings first"); 2643 igb->num_rx_groups = 1; 2644 } 2645 } 2646 2647 /* 2648 * Check the divisibility between rx rings and rx groups. 2649 */ 2650 for (i = igb->num_rx_groups; i > 0; i--) { 2651 if ((igb->num_rx_rings % i) == 0) 2652 break; 2653 } 2654 if (i != igb->num_rx_groups) { 2655 igb_error(igb, 2656 "Invalid rx groups number. Downgrade the rx group " 2657 "number to %d.", i); 2658 igb->num_rx_groups = i; 2659 } 2660 2661 /* 2662 * Get the ring number per group. 2663 */ 2664 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2665 2666 if (igb->num_rx_groups == 1) { 2667 /* 2668 * One rx ring group, the rx ring number is num_rx_rings. 2669 */ 2670 igb->vmdq_mode = E1000_VMDQ_OFF; 2671 } else if (ring_per_group == 1) { 2672 /* 2673 * Multiple rx groups, each group has one rx ring. 2674 */ 2675 igb->vmdq_mode = E1000_VMDQ_MAC; 2676 } else { 2677 /* 2678 * Multiple groups and multiple rings. 2679 */ 2680 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2681 } 2682 2683 /* 2684 * Tunable used to force an interrupt type. The only use is 2685 * for testing of the lesser interrupt types. 2686 * 0 = don't force interrupt type 2687 * 1 = force interrupt type MSIX 2688 * 2 = force interrupt type MSI 2689 * 3 = force interrupt type Legacy 2690 */ 2691 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2692 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2693 2694 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2695 0, 1, 1); 2696 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2697 0, 1, 1); 2698 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2699 0, 1, 1); 2700 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2701 0, 1, 1); 2702 2703 /* 2704 * igb LSO needs the tx h/w checksum support. 2705 * Here LSO will be disabled if tx h/w checksum has been disabled. 2706 */ 2707 if (igb->tx_hcksum_enable == B_FALSE) 2708 igb->lso_enable = B_FALSE; 2709 2710 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2711 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2712 DEFAULT_TX_COPY_THRESHOLD); 2713 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2714 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2715 DEFAULT_TX_RECYCLE_THRESHOLD); 2716 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2717 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2718 DEFAULT_TX_OVERLOAD_THRESHOLD); 2719 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2720 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2721 DEFAULT_TX_RESCHED_THRESHOLD); 2722 2723 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2724 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2725 DEFAULT_RX_COPY_THRESHOLD); 2726 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2727 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2728 DEFAULT_RX_LIMIT_PER_INTR); 2729 2730 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2731 igb->capab->min_intr_throttle, 2732 igb->capab->max_intr_throttle, 2733 igb->capab->def_intr_throttle); 2734 } 2735 2736 /* 2737 * igb_get_prop - Get a property value out of the configuration file igb.conf 2738 * 2739 * Caller provides the name of the property, a default value, a minimum 2740 * value, and a maximum value. 2741 * 2742 * Return configured value of the property, with default, minimum and 2743 * maximum properly applied. 2744 */ 2745 static int 2746 igb_get_prop(igb_t *igb, 2747 char *propname, /* name of the property */ 2748 int minval, /* minimum acceptable value */ 2749 int maxval, /* maximim acceptable value */ 2750 int defval) /* default value */ 2751 { 2752 int value; 2753 2754 /* 2755 * Call ddi_prop_get_int() to read the conf settings 2756 */ 2757 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2758 DDI_PROP_DONTPASS, propname, defval); 2759 2760 if (value > maxval) 2761 value = maxval; 2762 2763 if (value < minval) 2764 value = minval; 2765 2766 return (value); 2767 } 2768 2769 /* 2770 * igb_setup_link - Using the link properties to setup the link 2771 */ 2772 int 2773 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2774 { 2775 struct e1000_mac_info *mac; 2776 struct e1000_phy_info *phy; 2777 boolean_t invalid; 2778 2779 mac = &igb->hw.mac; 2780 phy = &igb->hw.phy; 2781 invalid = B_FALSE; 2782 2783 if (igb->param_adv_autoneg_cap == 1) { 2784 mac->autoneg = B_TRUE; 2785 phy->autoneg_advertised = 0; 2786 2787 /* 2788 * 1000hdx is not supported for autonegotiation 2789 */ 2790 if (igb->param_adv_1000fdx_cap == 1) 2791 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2792 2793 if (igb->param_adv_100fdx_cap == 1) 2794 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2795 2796 if (igb->param_adv_100hdx_cap == 1) 2797 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2798 2799 if (igb->param_adv_10fdx_cap == 1) 2800 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2801 2802 if (igb->param_adv_10hdx_cap == 1) 2803 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2804 2805 if (phy->autoneg_advertised == 0) 2806 invalid = B_TRUE; 2807 } else { 2808 mac->autoneg = B_FALSE; 2809 2810 /* 2811 * 1000fdx and 1000hdx are not supported for forced link 2812 */ 2813 if (igb->param_adv_100fdx_cap == 1) 2814 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2815 else if (igb->param_adv_100hdx_cap == 1) 2816 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2817 else if (igb->param_adv_10fdx_cap == 1) 2818 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2819 else if (igb->param_adv_10hdx_cap == 1) 2820 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2821 else 2822 invalid = B_TRUE; 2823 } 2824 2825 if (invalid) { 2826 igb_notice(igb, "Invalid link settings. Setup link to " 2827 "autonegotiation with full link capabilities."); 2828 mac->autoneg = B_TRUE; 2829 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2830 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2831 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2832 } 2833 2834 if (setup_hw) { 2835 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2836 return (IGB_FAILURE); 2837 } 2838 2839 return (IGB_SUCCESS); 2840 } 2841 2842 2843 /* 2844 * igb_is_link_up - Check if the link is up 2845 */ 2846 static boolean_t 2847 igb_is_link_up(igb_t *igb) 2848 { 2849 struct e1000_hw *hw = &igb->hw; 2850 boolean_t link_up = B_FALSE; 2851 2852 ASSERT(mutex_owned(&igb->gen_lock)); 2853 2854 /* 2855 * get_link_status is set in the interrupt handler on link-status-change 2856 * or rx sequence error interrupt. get_link_status will stay 2857 * false until the e1000_check_for_link establishes link only 2858 * for copper adapters. 2859 */ 2860 switch (hw->phy.media_type) { 2861 case e1000_media_type_copper: 2862 if (hw->mac.get_link_status) { 2863 (void) e1000_check_for_link(hw); 2864 link_up = !hw->mac.get_link_status; 2865 } else { 2866 link_up = B_TRUE; 2867 } 2868 break; 2869 case e1000_media_type_fiber: 2870 (void) e1000_check_for_link(hw); 2871 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2872 break; 2873 case e1000_media_type_internal_serdes: 2874 (void) e1000_check_for_link(hw); 2875 link_up = hw->mac.serdes_has_link; 2876 break; 2877 } 2878 2879 return (link_up); 2880 } 2881 2882 /* 2883 * igb_link_check - Link status processing 2884 */ 2885 static boolean_t 2886 igb_link_check(igb_t *igb) 2887 { 2888 struct e1000_hw *hw = &igb->hw; 2889 uint16_t speed = 0, duplex = 0; 2890 boolean_t link_changed = B_FALSE; 2891 2892 ASSERT(mutex_owned(&igb->gen_lock)); 2893 2894 if (igb_is_link_up(igb)) { 2895 /* 2896 * The Link is up, check whether it was marked as down earlier 2897 */ 2898 if (igb->link_state != LINK_STATE_UP) { 2899 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2900 igb->link_speed = speed; 2901 igb->link_duplex = duplex; 2902 igb->link_state = LINK_STATE_UP; 2903 igb->link_down_timeout = 0; 2904 link_changed = B_TRUE; 2905 } 2906 } else { 2907 if (igb->link_state != LINK_STATE_DOWN) { 2908 igb->link_speed = 0; 2909 igb->link_duplex = 0; 2910 igb->link_state = LINK_STATE_DOWN; 2911 link_changed = B_TRUE; 2912 } 2913 2914 if (igb->igb_state & IGB_STARTED) { 2915 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2916 igb->link_down_timeout++; 2917 } else if (igb->link_down_timeout == 2918 MAX_LINK_DOWN_TIMEOUT) { 2919 igb_tx_clean(igb); 2920 igb->link_down_timeout++; 2921 } 2922 } 2923 } 2924 2925 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2926 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2927 2928 return (link_changed); 2929 } 2930 2931 /* 2932 * igb_local_timer - driver watchdog function 2933 * 2934 * This function will handle the transmit stall check, link status check and 2935 * other routines. 2936 */ 2937 static void 2938 igb_local_timer(void *arg) 2939 { 2940 igb_t *igb = (igb_t *)arg; 2941 boolean_t link_changed = B_FALSE; 2942 2943 if (igb_stall_check(igb)) { 2944 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 2945 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 2946 igb->reset_count++; 2947 if (igb_reset(igb) == IGB_SUCCESS) 2948 ddi_fm_service_impact(igb->dip, 2949 DDI_SERVICE_RESTORED); 2950 } 2951 2952 mutex_enter(&igb->gen_lock); 2953 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 2954 link_changed = igb_link_check(igb); 2955 mutex_exit(&igb->gen_lock); 2956 2957 if (link_changed) 2958 mac_link_update(igb->mac_hdl, igb->link_state); 2959 2960 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2961 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2962 2963 igb_restart_watchdog_timer(igb); 2964 } 2965 2966 /* 2967 * igb_stall_check - check for transmit stall 2968 * 2969 * This function checks if the adapter is stalled (in transmit). 2970 * 2971 * It is called each time the watchdog timeout is invoked. 2972 * If the transmit descriptor reclaim continuously fails, 2973 * the watchdog value will increment by 1. If the watchdog 2974 * value exceeds the threshold, the igb is assumed to 2975 * have stalled and need to be reset. 2976 */ 2977 static boolean_t 2978 igb_stall_check(igb_t *igb) 2979 { 2980 igb_tx_ring_t *tx_ring; 2981 boolean_t result; 2982 int i; 2983 2984 if (igb->link_state != LINK_STATE_UP) 2985 return (B_FALSE); 2986 2987 /* 2988 * If any tx ring is stalled, we'll reset the chipset 2989 */ 2990 result = B_FALSE; 2991 for (i = 0; i < igb->num_tx_rings; i++) { 2992 tx_ring = &igb->tx_rings[i]; 2993 2994 if (tx_ring->recycle_fail > 0) 2995 tx_ring->stall_watchdog++; 2996 else 2997 tx_ring->stall_watchdog = 0; 2998 2999 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 3000 result = B_TRUE; 3001 break; 3002 } 3003 } 3004 3005 if (result) { 3006 tx_ring->stall_watchdog = 0; 3007 tx_ring->recycle_fail = 0; 3008 } 3009 3010 return (result); 3011 } 3012 3013 3014 /* 3015 * is_valid_mac_addr - Check if the mac address is valid 3016 */ 3017 static boolean_t 3018 is_valid_mac_addr(uint8_t *mac_addr) 3019 { 3020 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3021 const uint8_t addr_test2[6] = 3022 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3023 3024 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3025 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3026 return (B_FALSE); 3027 3028 return (B_TRUE); 3029 } 3030 3031 static boolean_t 3032 igb_find_mac_address(igb_t *igb) 3033 { 3034 struct e1000_hw *hw = &igb->hw; 3035 #ifdef __sparc 3036 uchar_t *bytes; 3037 struct ether_addr sysaddr; 3038 uint_t nelts; 3039 int err; 3040 boolean_t found = B_FALSE; 3041 3042 /* 3043 * The "vendor's factory-set address" may already have 3044 * been extracted from the chip, but if the property 3045 * "local-mac-address" is set we use that instead. 3046 * 3047 * We check whether it looks like an array of 6 3048 * bytes (which it should, if OBP set it). If we can't 3049 * make sense of it this way, we'll ignore it. 3050 */ 3051 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3052 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3053 if (err == DDI_PROP_SUCCESS) { 3054 if (nelts == ETHERADDRL) { 3055 while (nelts--) 3056 hw->mac.addr[nelts] = bytes[nelts]; 3057 found = B_TRUE; 3058 } 3059 ddi_prop_free(bytes); 3060 } 3061 3062 /* 3063 * Look up the OBP property "local-mac-address?". If the user has set 3064 * 'local-mac-address? = false', use "the system address" instead. 3065 */ 3066 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3067 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3068 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3069 if (localetheraddr(NULL, &sysaddr) != 0) { 3070 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3071 found = B_TRUE; 3072 } 3073 } 3074 ddi_prop_free(bytes); 3075 } 3076 3077 /* 3078 * Finally(!), if there's a valid "mac-address" property (created 3079 * if we netbooted from this interface), we must use this instead 3080 * of any of the above to ensure that the NFS/install server doesn't 3081 * get confused by the address changing as Solaris takes over! 3082 */ 3083 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3084 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3085 if (err == DDI_PROP_SUCCESS) { 3086 if (nelts == ETHERADDRL) { 3087 while (nelts--) 3088 hw->mac.addr[nelts] = bytes[nelts]; 3089 found = B_TRUE; 3090 } 3091 ddi_prop_free(bytes); 3092 } 3093 3094 if (found) { 3095 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3096 return (B_TRUE); 3097 } 3098 #endif 3099 3100 /* 3101 * Read the device MAC address from the EEPROM 3102 */ 3103 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3104 return (B_FALSE); 3105 3106 return (B_TRUE); 3107 } 3108 3109 #pragma inline(igb_arm_watchdog_timer) 3110 3111 static void 3112 igb_arm_watchdog_timer(igb_t *igb) 3113 { 3114 /* 3115 * Fire a watchdog timer 3116 */ 3117 igb->watchdog_tid = 3118 timeout(igb_local_timer, 3119 (void *)igb, 1 * drv_usectohz(1000000)); 3120 3121 } 3122 3123 /* 3124 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3125 */ 3126 void 3127 igb_enable_watchdog_timer(igb_t *igb) 3128 { 3129 mutex_enter(&igb->watchdog_lock); 3130 3131 if (!igb->watchdog_enable) { 3132 igb->watchdog_enable = B_TRUE; 3133 igb->watchdog_start = B_TRUE; 3134 igb_arm_watchdog_timer(igb); 3135 } 3136 3137 mutex_exit(&igb->watchdog_lock); 3138 3139 } 3140 3141 /* 3142 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3143 */ 3144 void 3145 igb_disable_watchdog_timer(igb_t *igb) 3146 { 3147 timeout_id_t tid; 3148 3149 mutex_enter(&igb->watchdog_lock); 3150 3151 igb->watchdog_enable = B_FALSE; 3152 igb->watchdog_start = B_FALSE; 3153 tid = igb->watchdog_tid; 3154 igb->watchdog_tid = 0; 3155 3156 mutex_exit(&igb->watchdog_lock); 3157 3158 if (tid != 0) 3159 (void) untimeout(tid); 3160 3161 } 3162 3163 /* 3164 * igb_start_watchdog_timer - Start the driver watchdog timer 3165 */ 3166 static void 3167 igb_start_watchdog_timer(igb_t *igb) 3168 { 3169 mutex_enter(&igb->watchdog_lock); 3170 3171 if (igb->watchdog_enable) { 3172 if (!igb->watchdog_start) { 3173 igb->watchdog_start = B_TRUE; 3174 igb_arm_watchdog_timer(igb); 3175 } 3176 } 3177 3178 mutex_exit(&igb->watchdog_lock); 3179 } 3180 3181 /* 3182 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3183 */ 3184 static void 3185 igb_restart_watchdog_timer(igb_t *igb) 3186 { 3187 mutex_enter(&igb->watchdog_lock); 3188 3189 if (igb->watchdog_start) 3190 igb_arm_watchdog_timer(igb); 3191 3192 mutex_exit(&igb->watchdog_lock); 3193 } 3194 3195 /* 3196 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3197 */ 3198 static void 3199 igb_stop_watchdog_timer(igb_t *igb) 3200 { 3201 timeout_id_t tid; 3202 3203 mutex_enter(&igb->watchdog_lock); 3204 3205 igb->watchdog_start = B_FALSE; 3206 tid = igb->watchdog_tid; 3207 igb->watchdog_tid = 0; 3208 3209 mutex_exit(&igb->watchdog_lock); 3210 3211 if (tid != 0) 3212 (void) untimeout(tid); 3213 } 3214 3215 /* 3216 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3217 */ 3218 static void 3219 igb_disable_adapter_interrupts(igb_t *igb) 3220 { 3221 struct e1000_hw *hw = &igb->hw; 3222 3223 /* 3224 * Set the IMC register to mask all the interrupts, 3225 * including the tx interrupts. 3226 */ 3227 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3228 E1000_WRITE_REG(hw, E1000_IAM, 0); 3229 3230 /* 3231 * Additional disabling for MSI-X 3232 */ 3233 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3234 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3235 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3236 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3237 } 3238 3239 E1000_WRITE_FLUSH(hw); 3240 } 3241 3242 /* 3243 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3244 */ 3245 static void 3246 igb_enable_adapter_interrupts_82576(igb_t *igb) 3247 { 3248 struct e1000_hw *hw = &igb->hw; 3249 3250 /* Clear any pending interrupts */ 3251 (void) E1000_READ_REG(hw, E1000_ICR); 3252 3253 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3254 3255 /* Interrupt enabling for MSI-X */ 3256 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3257 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3258 igb->ims_mask = E1000_IMS_LSC; 3259 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3260 } else { 3261 /* Interrupt enabling for MSI and legacy */ 3262 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3263 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3264 E1000_WRITE_REG(hw, E1000_IMS, 3265 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3266 } 3267 3268 /* Disable auto-mask for ICR interrupt bits */ 3269 E1000_WRITE_REG(hw, E1000_IAM, 0); 3270 3271 E1000_WRITE_FLUSH(hw); 3272 } 3273 3274 /* 3275 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3276 */ 3277 static void 3278 igb_enable_adapter_interrupts_82575(igb_t *igb) 3279 { 3280 struct e1000_hw *hw = &igb->hw; 3281 uint32_t reg; 3282 3283 /* Clear any pending interrupts */ 3284 (void) E1000_READ_REG(hw, E1000_ICR); 3285 3286 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3287 /* Interrupt enabling for MSI-X */ 3288 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3289 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3290 igb->ims_mask = E1000_IMS_LSC; 3291 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3292 3293 /* Enable MSI-X PBA support */ 3294 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3295 reg |= E1000_CTRL_EXT_PBA_CLR; 3296 3297 /* Non-selective interrupt clear-on-read */ 3298 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3299 3300 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3301 } else { 3302 /* Interrupt enabling for MSI and legacy */ 3303 igb->ims_mask = IMS_ENABLE_MASK; 3304 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3305 } 3306 3307 E1000_WRITE_FLUSH(hw); 3308 } 3309 3310 /* 3311 * Loopback Support 3312 */ 3313 static lb_property_t lb_normal = 3314 { normal, "normal", IGB_LB_NONE }; 3315 static lb_property_t lb_external = 3316 { external, "External", IGB_LB_EXTERNAL }; 3317 static lb_property_t lb_mac = 3318 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 3319 static lb_property_t lb_phy = 3320 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3321 static lb_property_t lb_serdes = 3322 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3323 3324 enum ioc_reply 3325 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3326 { 3327 lb_info_sz_t *lbsp; 3328 lb_property_t *lbpp; 3329 struct e1000_hw *hw; 3330 uint32_t *lbmp; 3331 uint32_t size; 3332 uint32_t value; 3333 3334 hw = &igb->hw; 3335 3336 if (mp->b_cont == NULL) 3337 return (IOC_INVAL); 3338 3339 switch (iocp->ioc_cmd) { 3340 default: 3341 return (IOC_INVAL); 3342 3343 case LB_GET_INFO_SIZE: 3344 size = sizeof (lb_info_sz_t); 3345 if (iocp->ioc_count != size) 3346 return (IOC_INVAL); 3347 3348 value = sizeof (lb_normal); 3349 value += sizeof (lb_mac); 3350 if (hw->phy.media_type == e1000_media_type_copper) 3351 value += sizeof (lb_phy); 3352 else 3353 value += sizeof (lb_serdes); 3354 value += sizeof (lb_external); 3355 3356 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3357 *lbsp = value; 3358 break; 3359 3360 case LB_GET_INFO: 3361 value = sizeof (lb_normal); 3362 value += sizeof (lb_mac); 3363 if (hw->phy.media_type == e1000_media_type_copper) 3364 value += sizeof (lb_phy); 3365 else 3366 value += sizeof (lb_serdes); 3367 value += sizeof (lb_external); 3368 3369 size = value; 3370 if (iocp->ioc_count != size) 3371 return (IOC_INVAL); 3372 3373 value = 0; 3374 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3375 3376 lbpp[value++] = lb_normal; 3377 lbpp[value++] = lb_mac; 3378 if (hw->phy.media_type == e1000_media_type_copper) 3379 lbpp[value++] = lb_phy; 3380 else 3381 lbpp[value++] = lb_serdes; 3382 lbpp[value++] = lb_external; 3383 break; 3384 3385 case LB_GET_MODE: 3386 size = sizeof (uint32_t); 3387 if (iocp->ioc_count != size) 3388 return (IOC_INVAL); 3389 3390 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3391 *lbmp = igb->loopback_mode; 3392 break; 3393 3394 case LB_SET_MODE: 3395 size = 0; 3396 if (iocp->ioc_count != sizeof (uint32_t)) 3397 return (IOC_INVAL); 3398 3399 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3400 if (!igb_set_loopback_mode(igb, *lbmp)) 3401 return (IOC_INVAL); 3402 break; 3403 } 3404 3405 iocp->ioc_count = size; 3406 iocp->ioc_error = 0; 3407 3408 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3409 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3410 return (IOC_INVAL); 3411 } 3412 3413 return (IOC_REPLY); 3414 } 3415 3416 /* 3417 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3418 */ 3419 static boolean_t 3420 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3421 { 3422 struct e1000_hw *hw; 3423 3424 if (mode == igb->loopback_mode) 3425 return (B_TRUE); 3426 3427 hw = &igb->hw; 3428 3429 igb->loopback_mode = mode; 3430 3431 if (mode == IGB_LB_NONE) { 3432 /* Reset the chip */ 3433 hw->phy.autoneg_wait_to_complete = B_TRUE; 3434 (void) igb_reset(igb); 3435 hw->phy.autoneg_wait_to_complete = B_FALSE; 3436 return (B_TRUE); 3437 } 3438 3439 mutex_enter(&igb->gen_lock); 3440 3441 switch (mode) { 3442 default: 3443 mutex_exit(&igb->gen_lock); 3444 return (B_FALSE); 3445 3446 case IGB_LB_EXTERNAL: 3447 igb_set_external_loopback(igb); 3448 break; 3449 3450 case IGB_LB_INTERNAL_MAC: 3451 igb_set_internal_mac_loopback(igb); 3452 break; 3453 3454 case IGB_LB_INTERNAL_PHY: 3455 igb_set_internal_phy_loopback(igb); 3456 break; 3457 3458 case IGB_LB_INTERNAL_SERDES: 3459 igb_set_internal_serdes_loopback(igb); 3460 break; 3461 } 3462 3463 mutex_exit(&igb->gen_lock); 3464 3465 return (B_TRUE); 3466 } 3467 3468 /* 3469 * igb_set_external_loopback - Set the external loopback mode 3470 */ 3471 static void 3472 igb_set_external_loopback(igb_t *igb) 3473 { 3474 struct e1000_hw *hw; 3475 3476 hw = &igb->hw; 3477 3478 /* Set phy to known state */ 3479 (void) e1000_phy_hw_reset(hw); 3480 3481 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3482 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3483 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3484 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3485 } 3486 3487 /* 3488 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3489 */ 3490 static void 3491 igb_set_internal_mac_loopback(igb_t *igb) 3492 { 3493 struct e1000_hw *hw; 3494 uint32_t ctrl; 3495 uint32_t rctl; 3496 uint32_t ctrl_ext; 3497 uint16_t phy_ctrl; 3498 uint16_t phy_status; 3499 3500 hw = &igb->hw; 3501 3502 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3503 phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 3504 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3505 3506 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3507 3508 /* Set link mode to PHY (00b) in the Extended Control register */ 3509 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3510 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3511 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3512 3513 /* Set the Device Control register */ 3514 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3515 if (!(phy_status & MII_SR_LINK_STATUS)) 3516 ctrl |= E1000_CTRL_ILOS; /* Set ILOS when the link is down */ 3517 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3518 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3519 E1000_CTRL_FRCSPD | /* Force speed */ 3520 E1000_CTRL_FRCDPX | /* Force duplex */ 3521 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3522 E1000_CTRL_FD); /* Force full duplex */ 3523 3524 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3525 3526 /* Set the Receive Control register */ 3527 rctl = E1000_READ_REG(hw, E1000_RCTL); 3528 rctl &= ~E1000_RCTL_LBM_TCVR; 3529 rctl |= E1000_RCTL_LBM_MAC; 3530 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3531 } 3532 3533 /* 3534 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3535 */ 3536 static void 3537 igb_set_internal_phy_loopback(igb_t *igb) 3538 { 3539 struct e1000_hw *hw; 3540 uint32_t ctrl_ext; 3541 uint16_t phy_ctrl; 3542 uint16_t phy_pconf; 3543 3544 hw = &igb->hw; 3545 3546 /* Set link mode to PHY (00b) in the Extended Control register */ 3547 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3548 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3549 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3550 3551 /* 3552 * Set PHY control register (0x4140): 3553 * Set full duplex mode 3554 * Set loopback bit 3555 * Clear auto-neg enable bit 3556 * Set PHY speed 3557 */ 3558 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3559 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3560 3561 /* Set the link disable bit in the Port Configuration register */ 3562 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3563 phy_pconf |= (uint16_t)1 << 14; 3564 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3565 } 3566 3567 /* 3568 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3569 */ 3570 static void 3571 igb_set_internal_serdes_loopback(igb_t *igb) 3572 { 3573 struct e1000_hw *hw; 3574 uint32_t ctrl_ext; 3575 uint32_t ctrl; 3576 uint32_t pcs_lctl; 3577 uint32_t connsw; 3578 3579 hw = &igb->hw; 3580 3581 /* Set link mode to SerDes (11b) in the Extended Control register */ 3582 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3583 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3584 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3585 3586 /* Configure the SerDes to loopback */ 3587 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3588 3589 /* Set Device Control register */ 3590 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3591 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3592 E1000_CTRL_SLU); /* Force link up */ 3593 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3594 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3595 E1000_CTRL_LRST); /* Clear link reset */ 3596 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3597 3598 /* Set PCS Link Control register */ 3599 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3600 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3601 E1000_PCS_LCTL_FSD | 3602 E1000_PCS_LCTL_FDV_FULL | 3603 E1000_PCS_LCTL_FLV_LINK_UP); 3604 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3605 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3606 3607 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3608 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3609 connsw &= ~E1000_CONNSW_ENRGSRC; 3610 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3611 } 3612 3613 #pragma inline(igb_intr_rx_work) 3614 /* 3615 * igb_intr_rx_work - rx processing of ISR 3616 */ 3617 static void 3618 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3619 { 3620 mblk_t *mp; 3621 3622 mutex_enter(&rx_ring->rx_lock); 3623 mp = igb_rx(rx_ring, IGB_NO_POLL); 3624 mutex_exit(&rx_ring->rx_lock); 3625 3626 if (mp != NULL) 3627 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 3628 rx_ring->ring_gen_num); 3629 } 3630 3631 #pragma inline(igb_intr_tx_work) 3632 /* 3633 * igb_intr_tx_work - tx processing of ISR 3634 */ 3635 static void 3636 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3637 { 3638 /* Recycle the tx descriptors */ 3639 tx_ring->tx_recycle(tx_ring); 3640 3641 /* Schedule the re-transmit */ 3642 if (tx_ring->reschedule && 3643 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3644 tx_ring->reschedule = B_FALSE; 3645 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 3646 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3647 } 3648 } 3649 3650 #pragma inline(igb_intr_link_work) 3651 /* 3652 * igb_intr_link_work - link-status-change processing of ISR 3653 */ 3654 static void 3655 igb_intr_link_work(igb_t *igb) 3656 { 3657 boolean_t link_changed; 3658 3659 igb_stop_watchdog_timer(igb); 3660 3661 mutex_enter(&igb->gen_lock); 3662 3663 /* 3664 * Because we got a link-status-change interrupt, force 3665 * e1000_check_for_link() to look at phy 3666 */ 3667 igb->hw.mac.get_link_status = B_TRUE; 3668 3669 /* igb_link_check takes care of link status change */ 3670 link_changed = igb_link_check(igb); 3671 3672 /* Get new phy state */ 3673 igb_get_phy_state(igb); 3674 3675 mutex_exit(&igb->gen_lock); 3676 3677 if (link_changed) 3678 mac_link_update(igb->mac_hdl, igb->link_state); 3679 3680 igb_start_watchdog_timer(igb); 3681 } 3682 3683 /* 3684 * igb_intr_legacy - Interrupt handler for legacy interrupts 3685 */ 3686 static uint_t 3687 igb_intr_legacy(void *arg1, void *arg2) 3688 { 3689 igb_t *igb = (igb_t *)arg1; 3690 igb_tx_ring_t *tx_ring; 3691 uint32_t icr; 3692 mblk_t *mp; 3693 boolean_t tx_reschedule; 3694 boolean_t link_changed; 3695 uint_t result; 3696 3697 _NOTE(ARGUNUSED(arg2)); 3698 3699 mutex_enter(&igb->gen_lock); 3700 3701 if (igb->igb_state & IGB_SUSPENDED) { 3702 mutex_exit(&igb->gen_lock); 3703 return (DDI_INTR_UNCLAIMED); 3704 } 3705 3706 mp = NULL; 3707 tx_reschedule = B_FALSE; 3708 link_changed = B_FALSE; 3709 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3710 3711 if (icr & E1000_ICR_INT_ASSERTED) { 3712 /* 3713 * E1000_ICR_INT_ASSERTED bit was set: 3714 * Read(Clear) the ICR, claim this interrupt, 3715 * look for work to do. 3716 */ 3717 ASSERT(igb->num_rx_rings == 1); 3718 ASSERT(igb->num_tx_rings == 1); 3719 3720 /* Make sure all interrupt causes cleared */ 3721 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3722 3723 if (icr & E1000_ICR_RXT0) { 3724 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 3725 } 3726 3727 if (icr & E1000_ICR_TXDW) { 3728 tx_ring = &igb->tx_rings[0]; 3729 3730 /* Recycle the tx descriptors */ 3731 tx_ring->tx_recycle(tx_ring); 3732 3733 /* Schedule the re-transmit */ 3734 tx_reschedule = (tx_ring->reschedule && 3735 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3736 } 3737 3738 if (icr & E1000_ICR_LSC) { 3739 /* 3740 * Because we got a link-status-change interrupt, force 3741 * e1000_check_for_link() to look at phy 3742 */ 3743 igb->hw.mac.get_link_status = B_TRUE; 3744 3745 /* igb_link_check takes care of link status change */ 3746 link_changed = igb_link_check(igb); 3747 3748 /* Get new phy state */ 3749 igb_get_phy_state(igb); 3750 } 3751 3752 result = DDI_INTR_CLAIMED; 3753 } else { 3754 /* 3755 * E1000_ICR_INT_ASSERTED bit was not set: 3756 * Don't claim this interrupt. 3757 */ 3758 result = DDI_INTR_UNCLAIMED; 3759 } 3760 3761 mutex_exit(&igb->gen_lock); 3762 3763 /* 3764 * Do the following work outside of the gen_lock 3765 */ 3766 if (mp != NULL) 3767 mac_rx(igb->mac_hdl, NULL, mp); 3768 3769 if (tx_reschedule) { 3770 tx_ring->reschedule = B_FALSE; 3771 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 3772 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3773 } 3774 3775 if (link_changed) 3776 mac_link_update(igb->mac_hdl, igb->link_state); 3777 3778 return (result); 3779 } 3780 3781 /* 3782 * igb_intr_msi - Interrupt handler for MSI 3783 */ 3784 static uint_t 3785 igb_intr_msi(void *arg1, void *arg2) 3786 { 3787 igb_t *igb = (igb_t *)arg1; 3788 uint32_t icr; 3789 3790 _NOTE(ARGUNUSED(arg2)); 3791 3792 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3793 3794 /* Make sure all interrupt causes cleared */ 3795 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 3796 3797 /* 3798 * For MSI interrupt, we have only one vector, 3799 * so we have only one rx ring and one tx ring enabled. 3800 */ 3801 ASSERT(igb->num_rx_rings == 1); 3802 ASSERT(igb->num_tx_rings == 1); 3803 3804 if (icr & E1000_ICR_RXT0) { 3805 igb_intr_rx_work(&igb->rx_rings[0]); 3806 } 3807 3808 if (icr & E1000_ICR_TXDW) { 3809 igb_intr_tx_work(&igb->tx_rings[0]); 3810 } 3811 3812 if (icr & E1000_ICR_LSC) { 3813 igb_intr_link_work(igb); 3814 } 3815 3816 return (DDI_INTR_CLAIMED); 3817 } 3818 3819 /* 3820 * igb_intr_rx - Interrupt handler for rx 3821 */ 3822 static uint_t 3823 igb_intr_rx(void *arg1, void *arg2) 3824 { 3825 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3826 3827 _NOTE(ARGUNUSED(arg2)); 3828 3829 /* 3830 * Only used via MSI-X vector so don't check cause bits 3831 * and only clean the given ring. 3832 */ 3833 igb_intr_rx_work(rx_ring); 3834 3835 return (DDI_INTR_CLAIMED); 3836 } 3837 3838 /* 3839 * igb_intr_tx - Interrupt handler for tx 3840 */ 3841 static uint_t 3842 igb_intr_tx(void *arg1, void *arg2) 3843 { 3844 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 3845 3846 _NOTE(ARGUNUSED(arg2)); 3847 3848 /* 3849 * Only used via MSI-X vector so don't check cause bits 3850 * and only clean the given ring. 3851 */ 3852 igb_intr_tx_work(tx_ring); 3853 3854 return (DDI_INTR_CLAIMED); 3855 } 3856 3857 /* 3858 * igb_intr_tx_other - Interrupt handler for both tx and other 3859 * 3860 */ 3861 static uint_t 3862 igb_intr_tx_other(void *arg1, void *arg2) 3863 { 3864 igb_t *igb = (igb_t *)arg1; 3865 uint32_t icr; 3866 3867 _NOTE(ARGUNUSED(arg2)); 3868 3869 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3870 3871 /* 3872 * Look for tx reclaiming work first. Remember, in the 3873 * case of only interrupt sharing, only one tx ring is 3874 * used 3875 */ 3876 igb_intr_tx_work(&igb->tx_rings[0]); 3877 3878 /* 3879 * Check for "other" causes. 3880 */ 3881 if (icr & E1000_ICR_LSC) { 3882 igb_intr_link_work(igb); 3883 } 3884 3885 /* 3886 * The DOUTSYNC bit indicates a tx packet dropped because 3887 * DMA engine gets "out of sync". There isn't a real fix 3888 * for this. The Intel recommendation is to count the number 3889 * of occurrences so user can detect when it is happening. 3890 * The issue is non-fatal and there's no recovery action 3891 * available. 3892 */ 3893 if (icr & E1000_ICR_DOUTSYNC) { 3894 IGB_STAT(igb->dout_sync); 3895 } 3896 3897 return (DDI_INTR_CLAIMED); 3898 } 3899 3900 /* 3901 * igb_alloc_intrs - Allocate interrupts for the driver 3902 * 3903 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3904 * if not successful, try Legacy. 3905 * igb->intr_force can be used to force sequence to start with 3906 * any of the 3 types. 3907 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3908 */ 3909 static int 3910 igb_alloc_intrs(igb_t *igb) 3911 { 3912 dev_info_t *devinfo; 3913 int intr_types; 3914 int rc; 3915 3916 devinfo = igb->dip; 3917 3918 /* Get supported interrupt types */ 3919 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3920 3921 if (rc != DDI_SUCCESS) { 3922 igb_log(igb, 3923 "Get supported interrupt types failed: %d", rc); 3924 return (IGB_FAILURE); 3925 } 3926 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3927 3928 igb->intr_type = 0; 3929 3930 /* Install MSI-X interrupts */ 3931 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3932 (igb->intr_force <= IGB_INTR_MSIX)) { 3933 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 3934 3935 if (rc == IGB_SUCCESS) 3936 return (IGB_SUCCESS); 3937 3938 igb_log(igb, 3939 "Allocate MSI-X failed, trying MSI interrupts..."); 3940 } 3941 3942 /* MSI-X not used, force rings to 1 */ 3943 igb->num_rx_rings = 1; 3944 igb->num_tx_rings = 1; 3945 igb_log(igb, 3946 "MSI-X not used, force rx and tx queue number to 1"); 3947 3948 /* Install MSI interrupts */ 3949 if ((intr_types & DDI_INTR_TYPE_MSI) && 3950 (igb->intr_force <= IGB_INTR_MSI)) { 3951 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 3952 3953 if (rc == IGB_SUCCESS) 3954 return (IGB_SUCCESS); 3955 3956 igb_log(igb, 3957 "Allocate MSI failed, trying Legacy interrupts..."); 3958 } 3959 3960 /* Install legacy interrupts */ 3961 if (intr_types & DDI_INTR_TYPE_FIXED) { 3962 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 3963 3964 if (rc == IGB_SUCCESS) 3965 return (IGB_SUCCESS); 3966 3967 igb_log(igb, 3968 "Allocate Legacy interrupts failed"); 3969 } 3970 3971 /* If none of the 3 types succeeded, return failure */ 3972 return (IGB_FAILURE); 3973 } 3974 3975 /* 3976 * igb_alloc_intr_handles - Allocate interrupt handles. 3977 * 3978 * For legacy and MSI, only 1 handle is needed. For MSI-X, 3979 * if fewer than 2 handles are available, return failure. 3980 * Upon success, this sets the number of Rx rings to a number that 3981 * matches the handles available for Rx interrupts. 3982 */ 3983 static int 3984 igb_alloc_intr_handles(igb_t *igb, int intr_type) 3985 { 3986 dev_info_t *devinfo; 3987 int orig, request, count, avail, actual; 3988 int diff, minimum; 3989 int rc; 3990 3991 devinfo = igb->dip; 3992 3993 switch (intr_type) { 3994 case DDI_INTR_TYPE_FIXED: 3995 request = 1; /* Request 1 legacy interrupt handle */ 3996 minimum = 1; 3997 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 3998 break; 3999 4000 case DDI_INTR_TYPE_MSI: 4001 request = 1; /* Request 1 MSI interrupt handle */ 4002 minimum = 1; 4003 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 4004 break; 4005 4006 case DDI_INTR_TYPE_MSIX: 4007 /* 4008 * Number of vectors for the adapter is 4009 * # rx rings + # tx rings 4010 * One of tx vectors is for tx & other 4011 */ 4012 request = igb->num_rx_rings + igb->num_tx_rings; 4013 orig = request; 4014 minimum = 2; 4015 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4016 break; 4017 4018 default: 4019 igb_log(igb, 4020 "invalid call to igb_alloc_intr_handles(): %d\n", 4021 intr_type); 4022 return (IGB_FAILURE); 4023 } 4024 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4025 request, minimum); 4026 4027 /* 4028 * Get number of supported interrupts 4029 */ 4030 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4031 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4032 igb_log(igb, 4033 "Get supported interrupt number failed. " 4034 "Return: %d, count: %d", rc, count); 4035 return (IGB_FAILURE); 4036 } 4037 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4038 4039 /* 4040 * Get number of available interrupts 4041 */ 4042 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4043 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4044 igb_log(igb, 4045 "Get available interrupt number failed. " 4046 "Return: %d, available: %d", rc, avail); 4047 return (IGB_FAILURE); 4048 } 4049 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4050 4051 if (avail < request) { 4052 igb_log(igb, "Request %d handles, %d available", 4053 request, avail); 4054 request = avail; 4055 } 4056 4057 actual = 0; 4058 igb->intr_cnt = 0; 4059 4060 /* 4061 * Allocate an array of interrupt handles 4062 */ 4063 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4064 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4065 4066 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4067 request, &actual, DDI_INTR_ALLOC_NORMAL); 4068 if (rc != DDI_SUCCESS) { 4069 igb_log(igb, "Allocate interrupts failed. " 4070 "return: %d, request: %d, actual: %d", 4071 rc, request, actual); 4072 goto alloc_handle_fail; 4073 } 4074 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4075 4076 igb->intr_cnt = actual; 4077 4078 if (actual < minimum) { 4079 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4080 actual); 4081 goto alloc_handle_fail; 4082 } 4083 4084 /* 4085 * For MSI-X, actual might force us to reduce number of tx & rx rings 4086 */ 4087 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4088 diff = orig - actual; 4089 if (diff < igb->num_tx_rings) { 4090 igb_log(igb, 4091 "MSI-X vectors force Tx queue number to %d", 4092 igb->num_tx_rings - diff); 4093 igb->num_tx_rings -= diff; 4094 } else { 4095 igb_log(igb, 4096 "MSI-X vectors force Tx queue number to 1"); 4097 igb->num_tx_rings = 1; 4098 4099 igb_log(igb, 4100 "MSI-X vectors force Rx queue number to %d", 4101 actual - 1); 4102 igb->num_rx_rings = actual - 1; 4103 } 4104 } 4105 4106 /* 4107 * Get priority for first vector, assume remaining are all the same 4108 */ 4109 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4110 if (rc != DDI_SUCCESS) { 4111 igb_log(igb, 4112 "Get interrupt priority failed: %d", rc); 4113 goto alloc_handle_fail; 4114 } 4115 4116 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4117 if (rc != DDI_SUCCESS) { 4118 igb_log(igb, 4119 "Get interrupt cap failed: %d", rc); 4120 goto alloc_handle_fail; 4121 } 4122 4123 igb->intr_type = intr_type; 4124 4125 return (IGB_SUCCESS); 4126 4127 alloc_handle_fail: 4128 igb_rem_intrs(igb); 4129 4130 return (IGB_FAILURE); 4131 } 4132 4133 /* 4134 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4135 * 4136 * Before adding the interrupt handlers, the interrupt vectors have 4137 * been allocated, and the rx/tx rings have also been allocated. 4138 */ 4139 static int 4140 igb_add_intr_handlers(igb_t *igb) 4141 { 4142 igb_rx_ring_t *rx_ring; 4143 igb_tx_ring_t *tx_ring; 4144 int vector; 4145 int rc; 4146 int i; 4147 4148 vector = 0; 4149 4150 switch (igb->intr_type) { 4151 case DDI_INTR_TYPE_MSIX: 4152 /* Add interrupt handler for tx + other */ 4153 tx_ring = &igb->tx_rings[0]; 4154 rc = ddi_intr_add_handler(igb->htable[vector], 4155 (ddi_intr_handler_t *)igb_intr_tx_other, 4156 (void *)igb, NULL); 4157 4158 if (rc != DDI_SUCCESS) { 4159 igb_log(igb, 4160 "Add tx/other interrupt handler failed: %d", rc); 4161 return (IGB_FAILURE); 4162 } 4163 tx_ring->intr_vector = vector; 4164 vector++; 4165 4166 /* Add interrupt handler for each rx ring */ 4167 for (i = 0; i < igb->num_rx_rings; i++) { 4168 rx_ring = &igb->rx_rings[i]; 4169 4170 rc = ddi_intr_add_handler(igb->htable[vector], 4171 (ddi_intr_handler_t *)igb_intr_rx, 4172 (void *)rx_ring, NULL); 4173 4174 if (rc != DDI_SUCCESS) { 4175 igb_log(igb, 4176 "Add rx interrupt handler failed. " 4177 "return: %d, rx ring: %d", rc, i); 4178 for (vector--; vector >= 0; vector--) { 4179 (void) ddi_intr_remove_handler( 4180 igb->htable[vector]); 4181 } 4182 return (IGB_FAILURE); 4183 } 4184 4185 rx_ring->intr_vector = vector; 4186 4187 vector++; 4188 } 4189 4190 /* Add interrupt handler for each tx ring from 2nd ring */ 4191 for (i = 1; i < igb->num_tx_rings; i++) { 4192 tx_ring = &igb->tx_rings[i]; 4193 4194 rc = ddi_intr_add_handler(igb->htable[vector], 4195 (ddi_intr_handler_t *)igb_intr_tx, 4196 (void *)tx_ring, NULL); 4197 4198 if (rc != DDI_SUCCESS) { 4199 igb_log(igb, 4200 "Add tx interrupt handler failed. " 4201 "return: %d, tx ring: %d", rc, i); 4202 for (vector--; vector >= 0; vector--) { 4203 (void) ddi_intr_remove_handler( 4204 igb->htable[vector]); 4205 } 4206 return (IGB_FAILURE); 4207 } 4208 4209 tx_ring->intr_vector = vector; 4210 4211 vector++; 4212 } 4213 4214 break; 4215 4216 case DDI_INTR_TYPE_MSI: 4217 /* Add interrupt handlers for the only vector */ 4218 rc = ddi_intr_add_handler(igb->htable[vector], 4219 (ddi_intr_handler_t *)igb_intr_msi, 4220 (void *)igb, NULL); 4221 4222 if (rc != DDI_SUCCESS) { 4223 igb_log(igb, 4224 "Add MSI interrupt handler failed: %d", rc); 4225 return (IGB_FAILURE); 4226 } 4227 4228 rx_ring = &igb->rx_rings[0]; 4229 rx_ring->intr_vector = vector; 4230 4231 vector++; 4232 break; 4233 4234 case DDI_INTR_TYPE_FIXED: 4235 /* Add interrupt handlers for the only vector */ 4236 rc = ddi_intr_add_handler(igb->htable[vector], 4237 (ddi_intr_handler_t *)igb_intr_legacy, 4238 (void *)igb, NULL); 4239 4240 if (rc != DDI_SUCCESS) { 4241 igb_log(igb, 4242 "Add legacy interrupt handler failed: %d", rc); 4243 return (IGB_FAILURE); 4244 } 4245 4246 rx_ring = &igb->rx_rings[0]; 4247 rx_ring->intr_vector = vector; 4248 4249 vector++; 4250 break; 4251 4252 default: 4253 return (IGB_FAILURE); 4254 } 4255 4256 ASSERT(vector == igb->intr_cnt); 4257 4258 return (IGB_SUCCESS); 4259 } 4260 4261 /* 4262 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4263 * 4264 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4265 */ 4266 static void 4267 igb_setup_msix_82575(igb_t *igb) 4268 { 4269 uint32_t eims = 0; 4270 int i, vector; 4271 struct e1000_hw *hw = &igb->hw; 4272 4273 /* 4274 * Set vector for tx ring 0 and other causes. 4275 * NOTE assumption that it is vector 0. 4276 */ 4277 vector = 0; 4278 4279 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4280 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4281 vector++; 4282 4283 for (i = 0; i < igb->num_rx_rings; i++) { 4284 /* 4285 * Set vector for each rx ring 4286 */ 4287 eims = (E1000_EICR_RX_QUEUE0 << i); 4288 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4289 4290 /* 4291 * Accumulate bits to enable in 4292 * igb_enable_adapter_interrupts_82575() 4293 */ 4294 igb->eims_mask |= eims; 4295 4296 vector++; 4297 } 4298 4299 for (i = 1; i < igb->num_tx_rings; i++) { 4300 /* 4301 * Set vector for each tx ring from 2nd tx ring 4302 */ 4303 eims = (E1000_EICR_TX_QUEUE0 << i); 4304 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4305 4306 /* 4307 * Accumulate bits to enable in 4308 * igb_enable_adapter_interrupts_82575() 4309 */ 4310 igb->eims_mask |= eims; 4311 4312 vector++; 4313 } 4314 4315 ASSERT(vector == igb->intr_cnt); 4316 4317 /* 4318 * Disable IAM for ICR interrupt bits 4319 */ 4320 E1000_WRITE_REG(hw, E1000_IAM, 0); 4321 E1000_WRITE_FLUSH(hw); 4322 } 4323 4324 /* 4325 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4326 * 4327 * 82576 uses a table based method for assigning vectors. Each queue has a 4328 * single entry in the table to which we write a vector number along with a 4329 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4330 * take a different position in the 4-byte register depending on whether 4331 * they are numbered above or below 8. 4332 */ 4333 static void 4334 igb_setup_msix_82576(igb_t *igb) 4335 { 4336 struct e1000_hw *hw = &igb->hw; 4337 uint32_t ivar, index, vector; 4338 int i; 4339 4340 /* must enable msi-x capability before IVAR settings */ 4341 E1000_WRITE_REG(hw, E1000_GPIE, 4342 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4343 4344 /* 4345 * Set vector for tx ring 0 and other causes. 4346 * NOTE assumption that it is vector 0. 4347 * This is also interdependent with installation of interrupt service 4348 * routines in igb_add_intr_handlers(). 4349 */ 4350 4351 /* assign "other" causes to vector 0 */ 4352 vector = 0; 4353 ivar = ((vector | E1000_IVAR_VALID) << 8); 4354 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4355 4356 /* assign tx ring 0 to vector 0 */ 4357 ivar = ((vector | E1000_IVAR_VALID) << 8); 4358 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4359 4360 /* prepare to enable tx & other interrupt causes */ 4361 igb->eims_mask = (1 << vector); 4362 4363 vector ++; 4364 for (i = 0; i < igb->num_rx_rings; i++) { 4365 /* 4366 * Set vector for each rx ring 4367 */ 4368 index = (i & 0x7); 4369 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4370 4371 if (i < 8) { 4372 /* vector goes into low byte of register */ 4373 ivar = ivar & 0xFFFFFF00; 4374 ivar |= (vector | E1000_IVAR_VALID); 4375 } else { 4376 /* vector goes into third byte of register */ 4377 ivar = ivar & 0xFF00FFFF; 4378 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4379 } 4380 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4381 4382 /* Accumulate interrupt-cause bits to enable */ 4383 igb->eims_mask |= (1 << vector); 4384 4385 vector ++; 4386 } 4387 4388 for (i = 1; i < igb->num_tx_rings; i++) { 4389 /* 4390 * Set vector for each tx ring from 2nd tx ring. 4391 * Note assumption that tx vectors numericall follow rx vectors. 4392 */ 4393 index = (i & 0x7); 4394 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4395 4396 if (i < 8) { 4397 /* vector goes into second byte of register */ 4398 ivar = ivar & 0xFFFF00FF; 4399 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4400 } else { 4401 /* vector goes into fourth byte of register */ 4402 ivar = ivar & 0x00FFFFFF; 4403 ivar |= (vector | E1000_IVAR_VALID) << 24; 4404 } 4405 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4406 4407 /* Accumulate interrupt-cause bits to enable */ 4408 igb->eims_mask |= (1 << vector); 4409 4410 vector ++; 4411 } 4412 4413 ASSERT(vector == igb->intr_cnt); 4414 } 4415 4416 /* 4417 * igb_rem_intr_handlers - remove the interrupt handlers 4418 */ 4419 static void 4420 igb_rem_intr_handlers(igb_t *igb) 4421 { 4422 int i; 4423 int rc; 4424 4425 for (i = 0; i < igb->intr_cnt; i++) { 4426 rc = ddi_intr_remove_handler(igb->htable[i]); 4427 if (rc != DDI_SUCCESS) { 4428 IGB_DEBUGLOG_1(igb, 4429 "Remove intr handler failed: %d", rc); 4430 } 4431 } 4432 } 4433 4434 /* 4435 * igb_rem_intrs - remove the allocated interrupts 4436 */ 4437 static void 4438 igb_rem_intrs(igb_t *igb) 4439 { 4440 int i; 4441 int rc; 4442 4443 for (i = 0; i < igb->intr_cnt; i++) { 4444 rc = ddi_intr_free(igb->htable[i]); 4445 if (rc != DDI_SUCCESS) { 4446 IGB_DEBUGLOG_1(igb, 4447 "Free intr failed: %d", rc); 4448 } 4449 } 4450 4451 kmem_free(igb->htable, igb->intr_size); 4452 igb->htable = NULL; 4453 } 4454 4455 /* 4456 * igb_enable_intrs - enable all the ddi interrupts 4457 */ 4458 static int 4459 igb_enable_intrs(igb_t *igb) 4460 { 4461 int i; 4462 int rc; 4463 4464 /* Enable interrupts */ 4465 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4466 /* Call ddi_intr_block_enable() for MSI */ 4467 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4468 if (rc != DDI_SUCCESS) { 4469 igb_log(igb, 4470 "Enable block intr failed: %d", rc); 4471 return (IGB_FAILURE); 4472 } 4473 } else { 4474 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4475 for (i = 0; i < igb->intr_cnt; i++) { 4476 rc = ddi_intr_enable(igb->htable[i]); 4477 if (rc != DDI_SUCCESS) { 4478 igb_log(igb, 4479 "Enable intr failed: %d", rc); 4480 return (IGB_FAILURE); 4481 } 4482 } 4483 } 4484 4485 return (IGB_SUCCESS); 4486 } 4487 4488 /* 4489 * igb_disable_intrs - disable all the ddi interrupts 4490 */ 4491 static int 4492 igb_disable_intrs(igb_t *igb) 4493 { 4494 int i; 4495 int rc; 4496 4497 /* Disable all interrupts */ 4498 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4499 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 4500 if (rc != DDI_SUCCESS) { 4501 igb_log(igb, 4502 "Disable block intr failed: %d", rc); 4503 return (IGB_FAILURE); 4504 } 4505 } else { 4506 for (i = 0; i < igb->intr_cnt; i++) { 4507 rc = ddi_intr_disable(igb->htable[i]); 4508 if (rc != DDI_SUCCESS) { 4509 igb_log(igb, 4510 "Disable intr failed: %d", rc); 4511 return (IGB_FAILURE); 4512 } 4513 } 4514 } 4515 4516 return (IGB_SUCCESS); 4517 } 4518 4519 /* 4520 * igb_get_phy_state - Get and save the parameters read from PHY registers 4521 */ 4522 static void 4523 igb_get_phy_state(igb_t *igb) 4524 { 4525 struct e1000_hw *hw = &igb->hw; 4526 uint16_t phy_ctrl; 4527 uint16_t phy_status; 4528 uint16_t phy_an_adv; 4529 uint16_t phy_an_exp; 4530 uint16_t phy_ext_status; 4531 uint16_t phy_1000t_ctrl; 4532 uint16_t phy_1000t_status; 4533 uint16_t phy_lp_able; 4534 4535 ASSERT(mutex_owned(&igb->gen_lock)); 4536 4537 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4538 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 4539 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4540 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4541 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4542 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4543 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 4544 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4545 4546 igb->param_autoneg_cap = 4547 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4548 igb->param_pause_cap = 4549 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4550 igb->param_asym_pause_cap = 4551 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4552 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4553 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4554 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4555 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4556 igb->param_100t4_cap = 4557 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4558 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4559 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4560 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4561 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4562 igb->param_10fdx_cap = 4563 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4564 igb->param_10hdx_cap = 4565 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4566 igb->param_rem_fault = 4567 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4568 4569 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4570 igb->param_adv_pause_cap = 4571 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4572 igb->param_adv_asym_pause_cap = 4573 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4574 igb->param_adv_1000hdx_cap = 4575 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4576 igb->param_adv_100t4_cap = 4577 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4578 igb->param_adv_rem_fault = 4579 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4580 if (igb->param_adv_autoneg_cap == 1) { 4581 igb->param_adv_1000fdx_cap = 4582 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 4583 igb->param_adv_100fdx_cap = 4584 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 4585 igb->param_adv_100hdx_cap = 4586 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 4587 igb->param_adv_10fdx_cap = 4588 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 4589 igb->param_adv_10hdx_cap = 4590 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 4591 } 4592 4593 igb->param_lp_autoneg_cap = 4594 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 4595 igb->param_lp_pause_cap = 4596 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 4597 igb->param_lp_asym_pause_cap = 4598 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 4599 igb->param_lp_1000fdx_cap = 4600 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 4601 igb->param_lp_1000hdx_cap = 4602 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 4603 igb->param_lp_100t4_cap = 4604 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 4605 igb->param_lp_100fdx_cap = 4606 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 4607 igb->param_lp_100hdx_cap = 4608 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 4609 igb->param_lp_10fdx_cap = 4610 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 4611 igb->param_lp_10hdx_cap = 4612 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 4613 igb->param_lp_rem_fault = 4614 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 4615 } 4616 4617 /* 4618 * igb_get_driver_control 4619 */ 4620 static void 4621 igb_get_driver_control(struct e1000_hw *hw) 4622 { 4623 uint32_t ctrl_ext; 4624 4625 /* Notify firmware that driver is in control of device */ 4626 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4627 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 4628 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4629 } 4630 4631 /* 4632 * igb_release_driver_control 4633 */ 4634 static void 4635 igb_release_driver_control(struct e1000_hw *hw) 4636 { 4637 uint32_t ctrl_ext; 4638 4639 /* Notify firmware that driver is no longer in control of device */ 4640 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4641 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 4642 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4643 } 4644 4645 /* 4646 * igb_atomic_reserve - Atomic decrease operation 4647 */ 4648 int 4649 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4650 { 4651 uint32_t oldval; 4652 uint32_t newval; 4653 4654 /* ATOMICALLY */ 4655 do { 4656 oldval = *count_p; 4657 if (oldval < n) 4658 return (-1); 4659 newval = oldval - n; 4660 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4661 4662 return (newval); 4663 } 4664 4665 /* 4666 * FMA support 4667 */ 4668 4669 int 4670 igb_check_acc_handle(ddi_acc_handle_t handle) 4671 { 4672 ddi_fm_error_t de; 4673 4674 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4675 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4676 return (de.fme_status); 4677 } 4678 4679 int 4680 igb_check_dma_handle(ddi_dma_handle_t handle) 4681 { 4682 ddi_fm_error_t de; 4683 4684 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4685 return (de.fme_status); 4686 } 4687 4688 /* 4689 * The IO fault service error handling callback function 4690 */ 4691 /*ARGSUSED*/ 4692 static int 4693 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4694 { 4695 /* 4696 * as the driver can always deal with an error in any dma or 4697 * access handle, we can just return the fme_status value. 4698 */ 4699 pci_ereport_post(dip, err, NULL); 4700 return (err->fme_status); 4701 } 4702 4703 static void 4704 igb_fm_init(igb_t *igb) 4705 { 4706 ddi_iblock_cookie_t iblk; 4707 int fma_acc_flag, fma_dma_flag; 4708 4709 /* Only register with IO Fault Services if we have some capability */ 4710 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4711 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4712 fma_acc_flag = 1; 4713 } else { 4714 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4715 fma_acc_flag = 0; 4716 } 4717 4718 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4719 fma_dma_flag = 1; 4720 } else { 4721 fma_dma_flag = 0; 4722 } 4723 4724 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4725 4726 if (igb->fm_capabilities) { 4727 4728 /* Register capabilities with IO Fault Services */ 4729 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4730 4731 /* 4732 * Initialize pci ereport capabilities if ereport capable 4733 */ 4734 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4735 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4736 pci_ereport_setup(igb->dip); 4737 4738 /* 4739 * Register error callback if error callback capable 4740 */ 4741 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4742 ddi_fm_handler_register(igb->dip, 4743 igb_fm_error_cb, (void*) igb); 4744 } 4745 } 4746 4747 static void 4748 igb_fm_fini(igb_t *igb) 4749 { 4750 /* Only unregister FMA capabilities if we registered some */ 4751 if (igb->fm_capabilities) { 4752 4753 /* 4754 * Release any resources allocated by pci_ereport_setup() 4755 */ 4756 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4757 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4758 pci_ereport_teardown(igb->dip); 4759 4760 /* 4761 * Un-register error callback if error callback capable 4762 */ 4763 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4764 ddi_fm_handler_unregister(igb->dip); 4765 4766 /* Unregister from IO Fault Services */ 4767 ddi_fm_fini(igb->dip); 4768 } 4769 } 4770 4771 void 4772 igb_fm_ereport(igb_t *igb, char *detail) 4773 { 4774 uint64_t ena; 4775 char buf[FM_MAX_CLASS]; 4776 4777 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4778 ena = fm_ena_generate(0, FM_ENA_FMT1); 4779 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4780 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4781 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4782 } 4783 } 4784