1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 #include "igb_debug.h" 33 34 #ifdef IGB_DEBUG 35 extern ddi_device_acc_attr_t igb_regs_acc_attr; 36 37 void 38 pci_dump(void *arg) 39 { 40 igb_t *igb = (igb_t *)arg; 41 ddi_acc_handle_t handle; 42 uint8_t cap_ptr; 43 uint8_t next_ptr; 44 uint32_t msix_bar; 45 uint32_t msix_ctrl; 46 uint32_t msix_tbl_sz; 47 uint32_t tbl_offset; 48 uint32_t tbl_bir; 49 uint32_t pba_offset; 50 uint32_t pba_bir; 51 off_t offset; 52 off_t mem_size; 53 uintptr_t base; 54 ddi_acc_handle_t acc_hdl; 55 int i; 56 57 handle = igb->osdep.cfg_handle; 58 59 igb_log(igb, "Begin dump PCI config space"); 60 61 igb_log(igb, 62 "PCI_CONF_VENID:\t0x%x\n", 63 pci_config_get16(handle, PCI_CONF_VENID)); 64 igb_log(igb, 65 "PCI_CONF_DEVID:\t0x%x\n", 66 pci_config_get16(handle, PCI_CONF_DEVID)); 67 igb_log(igb, 68 "PCI_CONF_COMMAND:\t0x%x\n", 69 pci_config_get16(handle, PCI_CONF_COMM)); 70 igb_log(igb, 71 "PCI_CONF_STATUS:\t0x%x\n", 72 pci_config_get16(handle, PCI_CONF_STAT)); 73 igb_log(igb, 74 "PCI_CONF_REVID:\t0x%x\n", 75 pci_config_get8(handle, PCI_CONF_REVID)); 76 igb_log(igb, 77 "PCI_CONF_PROG_CLASS:\t0x%x\n", 78 pci_config_get8(handle, PCI_CONF_PROGCLASS)); 79 igb_log(igb, 80 "PCI_CONF_SUB_CLASS:\t0x%x\n", 81 pci_config_get8(handle, PCI_CONF_SUBCLASS)); 82 igb_log(igb, 83 "PCI_CONF_BAS_CLASS:\t0x%x\n", 84 pci_config_get8(handle, PCI_CONF_BASCLASS)); 85 igb_log(igb, 86 "PCI_CONF_CACHE_LINESZ:\t0x%x\n", 87 pci_config_get8(handle, PCI_CONF_CACHE_LINESZ)); 88 igb_log(igb, 89 "PCI_CONF_LATENCY_TIMER:\t0x%x\n", 90 pci_config_get8(handle, PCI_CONF_LATENCY_TIMER)); 91 igb_log(igb, 92 "PCI_CONF_HEADER_TYPE:\t0x%x\n", 93 pci_config_get8(handle, PCI_CONF_HEADER)); 94 igb_log(igb, 95 "PCI_CONF_BIST:\t0x%x\n", 96 pci_config_get8(handle, PCI_CONF_BIST)); 97 igb_log(igb, 98 "PCI_CONF_BASE0:\t0x%x\n", 99 pci_config_get32(handle, PCI_CONF_BASE0)); 100 igb_log(igb, 101 "PCI_CONF_BASE1:\t0x%x\n", 102 pci_config_get32(handle, PCI_CONF_BASE1)); 103 igb_log(igb, 104 "PCI_CONF_BASE2:\t0x%x\n", 105 pci_config_get32(handle, PCI_CONF_BASE2)); 106 107 /* MSI-X BAR */ 108 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); 109 igb_log(igb, 110 "PCI_CONF_BASE3:\t0x%x\n", msix_bar); 111 112 igb_log(igb, 113 "PCI_CONF_BASE4:\t0x%x\n", 114 pci_config_get32(handle, PCI_CONF_BASE4)); 115 igb_log(igb, 116 "PCI_CONF_BASE5:\t0x%x\n", 117 pci_config_get32(handle, PCI_CONF_BASE5)); 118 igb_log(igb, 119 "PCI_CONF_CIS:\t0x%x\n", 120 pci_config_get32(handle, PCI_CONF_CIS)); 121 igb_log(igb, 122 "PCI_CONF_SUBVENID:\t0x%x\n", 123 pci_config_get16(handle, PCI_CONF_SUBVENID)); 124 igb_log(igb, 125 "PCI_CONF_SUBSYSID:\t0x%x\n", 126 pci_config_get16(handle, PCI_CONF_SUBSYSID)); 127 igb_log(igb, 128 "PCI_CONF_ROM:\t0x%x\n", 129 pci_config_get32(handle, PCI_CONF_ROM)); 130 131 cap_ptr = pci_config_get8(handle, PCI_CONF_CAP_PTR); 132 133 igb_log(igb, 134 "PCI_CONF_CAP_PTR:\t0x%x\n", cap_ptr); 135 igb_log(igb, 136 "PCI_CONF_ILINE:\t0x%x\n", 137 pci_config_get8(handle, PCI_CONF_ILINE)); 138 igb_log(igb, 139 "PCI_CONF_IPIN:\t0x%x\n", 140 pci_config_get8(handle, PCI_CONF_IPIN)); 141 igb_log(igb, 142 "PCI_CONF_MIN_G:\t0x%x\n", 143 pci_config_get8(handle, PCI_CONF_MIN_G)); 144 igb_log(igb, 145 "PCI_CONF_MAX_L:\t0x%x\n", 146 pci_config_get8(handle, PCI_CONF_MAX_L)); 147 148 /* Power Management */ 149 offset = cap_ptr; 150 151 igb_log(igb, 152 "PCI_PM_CAP_ID:\t0x%x\n", 153 pci_config_get8(handle, offset)); 154 155 next_ptr = pci_config_get8(handle, offset + 1); 156 157 igb_log(igb, 158 "PCI_PM_NEXT_PTR:\t0x%x\n", next_ptr); 159 igb_log(igb, 160 "PCI_PM_CAP:\t0x%x\n", 161 pci_config_get16(handle, offset + PCI_PMCAP)); 162 igb_log(igb, 163 "PCI_PM_CSR:\t0x%x\n", 164 pci_config_get16(handle, offset + PCI_PMCSR)); 165 igb_log(igb, 166 "PCI_PM_CSR_BSE:\t0x%x\n", 167 pci_config_get8(handle, offset + PCI_PMCSR_BSE)); 168 igb_log(igb, 169 "PCI_PM_DATA:\t0x%x\n", 170 pci_config_get8(handle, offset + PCI_PMDATA)); 171 172 /* MSI Configuration */ 173 offset = next_ptr; 174 175 igb_log(igb, 176 "PCI_MSI_CAP_ID:\t0x%x\n", 177 pci_config_get8(handle, offset)); 178 179 next_ptr = pci_config_get8(handle, offset + 1); 180 181 igb_log(igb, 182 "PCI_MSI_NEXT_PTR:\t0x%x\n", next_ptr); 183 igb_log(igb, 184 "PCI_MSI_CTRL:\t0x%x\n", 185 pci_config_get16(handle, offset + PCI_MSI_CTRL)); 186 igb_log(igb, 187 "PCI_MSI_ADDR:\t0x%x\n", 188 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET)); 189 igb_log(igb, 190 "PCI_MSI_ADDR_HI:\t0x%x\n", 191 pci_config_get32(handle, offset + 0x8)); 192 igb_log(igb, 193 "PCI_MSI_DATA:\t0x%x\n", 194 pci_config_get16(handle, offset + 0xC)); 195 196 /* MSI-X Configuration */ 197 offset = next_ptr; 198 199 igb_log(igb, 200 "PCI_MSIX_CAP_ID:\t0x%x\n", 201 pci_config_get8(handle, offset)); 202 203 next_ptr = pci_config_get8(handle, offset + 1); 204 igb_log(igb, 205 "PCI_MSIX_NEXT_PTR:\t0x%x\n", next_ptr); 206 207 msix_ctrl = pci_config_get16(handle, offset + PCI_MSIX_CTRL); 208 msix_tbl_sz = msix_ctrl & 0x7ff; 209 igb_log(igb, 210 "PCI_MSIX_CTRL:\t0x%x\n", msix_ctrl); 211 212 tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET); 213 tbl_bir = tbl_offset & PCI_MSIX_TBL_BIR_MASK; 214 tbl_offset = tbl_offset & ~PCI_MSIX_TBL_BIR_MASK; 215 igb_log(igb, 216 "PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset); 217 igb_log(igb, 218 "PCI_MSIX_TBL_BIR:\t0x%x\n", tbl_bir); 219 220 pba_offset = pci_config_get32(handle, offset + PCI_MSIX_PBA_OFFSET); 221 pba_bir = pba_offset & PCI_MSIX_PBA_BIR_MASK; 222 pba_offset = pba_offset & ~PCI_MSIX_PBA_BIR_MASK; 223 igb_log(igb, 224 "PCI_MSIX_PBA_OFFSET:\t0x%x\n", pba_offset); 225 igb_log(igb, 226 "PCI_MSIX_PBA_BIR:\t0x%x\n", pba_bir); 227 228 /* PCI Express Configuration */ 229 offset = next_ptr; 230 231 igb_log(igb, 232 "PCIE_CAP_ID:\t0x%x\n", 233 pci_config_get8(handle, offset + PCIE_CAP_ID)); 234 235 next_ptr = pci_config_get8(handle, offset + PCIE_CAP_NEXT_PTR); 236 237 igb_log(igb, 238 "PCIE_CAP_NEXT_PTR:\t0x%x\n", next_ptr); 239 igb_log(igb, 240 "PCIE_PCIECAP:\t0x%x\n", 241 pci_config_get16(handle, offset + PCIE_PCIECAP)); 242 igb_log(igb, 243 "PCIE_DEVCAP:\t0x%x\n", 244 pci_config_get32(handle, offset + PCIE_DEVCAP)); 245 igb_log(igb, 246 "PCIE_DEVCTL:\t0x%x\n", 247 pci_config_get16(handle, offset + PCIE_DEVCTL)); 248 igb_log(igb, 249 "PCIE_DEVSTS:\t0x%x\n", 250 pci_config_get16(handle, offset + PCIE_DEVSTS)); 251 igb_log(igb, 252 "PCIE_LINKCAP:\t0x%x\n", 253 pci_config_get32(handle, offset + PCIE_LINKCAP)); 254 igb_log(igb, 255 "PCIE_LINKCTL:\t0x%x\n", 256 pci_config_get16(handle, offset + PCIE_LINKCTL)); 257 igb_log(igb, 258 "PCIE_LINKSTS:\t0x%x\n", 259 pci_config_get16(handle, offset + PCIE_LINKSTS)); 260 261 /* MSI-X Memory Space */ 262 if (ddi_dev_regsize(igb->dip, 4, &mem_size) != DDI_SUCCESS) { 263 igb_log(igb, "ddi_dev_regsize() failed"); 264 return; 265 } 266 267 if ((ddi_regs_map_setup(igb->dip, 4, (caddr_t *)&base, 0, mem_size, 268 &igb_regs_acc_attr, &acc_hdl)) != DDI_SUCCESS) { 269 igb_log(igb, "ddi_regs_map_setup() failed"); 270 return; 271 } 272 273 igb_log(igb, "MSI-X Memory Space: (mem_size = %d, base = %x)", 274 mem_size, base); 275 276 for (i = 0; i <= msix_tbl_sz; i++) { 277 igb_log(igb, "MSI-X Table Entry(%d):", i); 278 igb_log(igb, "lo_addr:\t%x", 279 ddi_get32(acc_hdl, 280 (uint32_t *)(base + tbl_offset + (i * 16)))); 281 igb_log(igb, "up_addr:\t%x", 282 ddi_get32(acc_hdl, 283 (uint32_t *)(base + tbl_offset + (i * 16) + 4))); 284 igb_log(igb, "msg_data:\t%x", 285 ddi_get32(acc_hdl, 286 (uint32_t *)(base + tbl_offset + (i * 16) + 8))); 287 igb_log(igb, "vct_ctrl:\t%x", 288 ddi_get32(acc_hdl, 289 (uint32_t *)(base + tbl_offset + (i * 16) + 12))); 290 } 291 292 igb_log(igb, "MSI-X Pending Bits:\t%x", 293 ddi_get32(acc_hdl, (uint32_t *)(base + pba_offset))); 294 295 ddi_regs_map_free(&acc_hdl); 296 } 297 #endif 298