1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_TXDMA_H 27 #define _SYS_HXGE_HXGE_TXDMA_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <hxge_txdma_hw.h> 34 #include <hpi_txdma.h> 35 36 #define TXDMA_RECLAIM_PENDING_DEFAULT 64 37 #define TX_FULL_MARK 3 38 39 /* 40 * Transmit load balancing definitions. 41 */ 42 #define HXGE_TX_LB_TCPUDP 0 /* default policy */ 43 #define HXGE_TX_LB_HASH 1 /* from the hint data */ 44 #define HXGE_TX_LB_DEST_MAC 2 /* Dest. MAC */ 45 46 /* 47 * Descriptor ring empty: 48 * (1) head index is equal to tail index. 49 * (2) wrapped around bits are the same. 50 * Descriptor ring full: 51 * (1) head index is equal to tail index. 52 * (2) wrapped around bits are different. 53 * 54 */ 55 #define TXDMA_RING_EMPTY(head, head_wrap, tail, tail_wrap) \ 56 ((head == tail && head_wrap == tail_wrap) ? B_TRUE : B_FALSE) 57 58 #define TXDMA_RING_FULL(head, head_wrap, tail, tail_wrap) \ 59 ((head == tail && head_wrap != tail_wrap) ? B_TRUE : B_FALSE) 60 61 #define TXDMA_DESC_NEXT_INDEX(index, entries, wrap_mask) \ 62 ((index + entries) & wrap_mask) 63 64 typedef struct _tx_msg_t { 65 hxge_os_block_mv_t flags; /* DMA, BCOPY, DVMA (?) */ 66 hxge_os_dma_common_t buf_dma; /* premapped buffer blocks */ 67 hxge_os_dma_handle_t buf_dma_handle; /* premapped buffer handle */ 68 hxge_os_dma_handle_t dma_handle; /* DMA handle for normal send */ 69 hxge_os_dma_handle_t dvma_handle; /* Fast DVMA handle */ 70 71 p_mblk_t tx_message; 72 uint32_t tx_msg_size; 73 size_t bytes_used; 74 int head; 75 int tail; 76 } tx_msg_t, *p_tx_msg_t; 77 78 /* 79 * TX Statistics. 80 */ 81 typedef struct _hxge_tx_ring_stats_t { 82 uint64_t opackets; 83 uint64_t obytes; 84 uint64_t obytes_with_pad; 85 uint64_t oerrors; 86 87 uint32_t tx_inits; 88 uint32_t tx_no_buf; 89 90 uint32_t peu_resp_err; 91 uint32_t pkt_size_hdr_err; 92 uint32_t runt_pkt_drop_err; 93 uint32_t pkt_size_err; 94 uint32_t tx_rng_oflow; 95 uint32_t pref_par_err; 96 uint32_t tdr_pref_cpl_to; 97 uint32_t pkt_cpl_to; 98 uint32_t invalid_sop; 99 uint32_t unexpected_sop; 100 101 uint64_t count_hdr_size_err; 102 uint64_t count_runt; 103 uint64_t count_abort; 104 105 uint32_t tx_starts; 106 uint32_t tx_no_desc; 107 uint32_t tx_dma_bind_fail; 108 uint32_t tx_hdr_pkts; 109 uint32_t tx_ddi_pkts; 110 uint32_t tx_jumbo_pkts; 111 uint32_t tx_max_pend; 112 uint32_t tx_marks; 113 tdc_pref_par_log_t errlog; 114 } hxge_tx_ring_stats_t, *p_hxge_tx_ring_stats_t; 115 116 typedef struct _hxge_tdc_sys_stats { 117 uint32_t reord_tbl_par_err; 118 uint32_t reord_buf_ded_err; 119 uint32_t reord_buf_sec_err; 120 } hxge_tdc_sys_stats_t, *p_hxge_tdc_sys_stats_t; 121 122 typedef struct _tx_ring_t { 123 hxge_os_dma_common_t tdc_desc; 124 struct _hxge_t *hxgep; 125 p_tx_msg_t tx_msg_ring; 126 uint32_t tnblocks; 127 tdc_tdr_cfg_t tx_ring_cfig; 128 tdc_tdr_kick_t tx_ring_kick; 129 tdc_tdr_cfg_t tx_cs; 130 tdc_int_mask_t tx_evmask; 131 tdc_mbh_t tx_mbox_mbh; 132 tdc_mbl_t tx_mbox_mbl; 133 134 tdc_page_handle_t page_hdl; 135 136 hxge_os_mutex_t lock; 137 uint16_t index; 138 uint16_t tdc; 139 struct hxge_tdc_cfg *tdc_p; 140 uint_t tx_ring_size; 141 uint32_t num_chunks; 142 143 uint_t tx_wrap_mask; 144 uint_t rd_index; 145 uint_t wr_index; 146 boolean_t wr_index_wrap; 147 uint_t head_index; 148 boolean_t head_wrap; 149 tdc_tdr_head_t ring_head; 150 tdc_tdr_kick_t ring_kick_tail; 151 txdma_mailbox_t tx_mbox; 152 153 uint_t descs_pending; 154 boolean_t queueing; 155 156 p_mblk_t head; 157 p_mblk_t tail; 158 159 p_hxge_tx_ring_stats_t tdc_stats; 160 161 uint_t dvma_wr_index; 162 uint_t dvma_rd_index; 163 uint_t dvma_pending; 164 uint_t dvma_available; 165 uint_t dvma_wrap_mask; 166 167 hxge_os_dma_handle_t *dvma_ring; 168 169 mac_resource_handle_t tx_mac_resource_handle; 170 } tx_ring_t, *p_tx_ring_t; 171 172 173 /* Transmit Mailbox */ 174 typedef struct _tx_mbox_t { 175 hxge_os_mutex_t lock; 176 uint16_t index; 177 struct _hxge_t *hxgep; 178 uint16_t tdc; 179 hxge_os_dma_common_t tx_mbox; 180 tdc_mbl_t tx_mbox_l; 181 tdc_mbh_t tx_mbox_h; 182 } tx_mbox_t, *p_tx_mbox_t; 183 184 typedef struct _tx_rings_t { 185 p_tx_ring_t *rings; 186 boolean_t txdesc_allocated; 187 uint32_t ndmas; 188 hxge_os_dma_common_t tdc_dma; 189 hxge_os_dma_common_t tdc_mbox; 190 } tx_rings_t, *p_tx_rings_t; 191 192 typedef struct _tx_mbox_areas_t { 193 p_tx_mbox_t *txmbox_areas_p; 194 boolean_t txmbox_allocated; 195 } tx_mbox_areas_t, *p_tx_mbox_areas_t; 196 197 /* 198 * Transmit prototypes. 199 */ 200 hxge_status_t hxge_init_txdma_channels(p_hxge_t hxgep); 201 void hxge_uninit_txdma_channels(p_hxge_t hxgep); 202 void hxge_setup_dma_common(p_hxge_dma_common_t, p_hxge_dma_common_t, 203 uint32_t, uint32_t); 204 hxge_status_t hxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, 205 uint64_t reg_data); 206 hxge_status_t hxge_init_txdma_channel_event_mask(p_hxge_t hxgep, 207 uint16_t channel, tdc_int_mask_t *mask_p); 208 hxge_status_t hxge_enable_txdma_channel(p_hxge_t hxgep, uint16_t channel, 209 p_tx_ring_t tx_desc_p, p_tx_mbox_t mbox_p); 210 211 p_mblk_t hxge_tx_pkt_header_reserve(p_mblk_t mp, uint8_t *npads); 212 int hxge_tx_pkt_nmblocks(p_mblk_t mp, int *tot_xfer_len_p); 213 boolean_t hxge_txdma_reclaim(p_hxge_t hxgep, 214 p_tx_ring_t tx_ring_p, int nmblks); 215 216 void hxge_fill_tx_hdr(p_mblk_t mp, boolean_t fill_len, boolean_t l4_cksum, 217 int pkt_len, uint8_t npads, p_tx_pkt_hdr_all_t pkthdrp); 218 219 hxge_status_t hxge_txdma_hw_mode(p_hxge_t hxgep, boolean_t enable); 220 void hxge_txdma_stop(p_hxge_t hxgep); 221 void hxge_fixup_txdma_rings(p_hxge_t hxgep); 222 void hxge_txdma_hw_kick(p_hxge_t hxgep); 223 void hxge_txdma_fix_channel(p_hxge_t hxgep, uint16_t channel); 224 void hxge_txdma_fixup_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, 225 uint16_t channel); 226 void hxge_txdma_hw_kick_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, 227 uint16_t channel); 228 229 void hxge_check_tx_hang(p_hxge_t hxgep); 230 void hxge_fixup_hung_txdma_rings(p_hxge_t hxgep); 231 void hxge_txdma_fix_hung_channel(p_hxge_t hxgep, uint16_t channel); 232 void hxge_txdma_fixup_hung_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, 233 uint16_t channel); 234 235 void hxge_reclaim_rings(p_hxge_t hxgep); 236 int hxge_txdma_channel_hung(p_hxge_t hxgep, 237 p_tx_ring_t tx_ring_p, uint16_t channel); 238 int hxge_txdma_hung(p_hxge_t hxgep); 239 int hxge_txdma_stop_inj_err(p_hxge_t hxgep, int channel); 240 hxge_status_t hxge_txdma_handle_sys_errors(p_hxge_t hxgep); 241 242 #ifdef __cplusplus 243 } 244 #endif 245 246 #endif /* _SYS_HXGE_HXGE_TXDMA_H */ 247