1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_RXDMA_H 27 #define _SYS_HXGE_HXGE_RXDMA_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <hxge_rdc_hw.h> 36 #include <hpi_rxdma.h> 37 38 #define RXDMA_CK_DIV_DEFAULT 7500 /* 25 usec */ 39 #define RXDMA_RCR_PTHRES_DEFAULT 0x20 40 #define RXDMA_RCR_TO_DEFAULT 0x8 41 #define RXDMA_HDR_SIZE_DEFAULT 2 42 #define RXDMA_HDR_SIZE_FULL 6 /* entire header of 6B */ 43 44 /* 45 * Receive Completion Ring (RCR) 46 */ 47 #define RCR_PKT_BUF_ADDR_SHIFT 0 /* bit 37:0 */ 48 #define RCR_PKT_BUF_ADDR_SHIFT_FULL 6 /* fulll buffer address */ 49 #define RCR_PKT_BUF_ADDR_MASK 0x0000003FFFFFFFFFULL 50 #define RCR_PKTBUFSZ_SHIFT 38 /* bit 39:38 */ 51 #define RCR_PKTBUFSZ_MASK 0x000000C000000000ULL 52 #define RCR_L2_LEN_SHIFT 40 /* bit 53:40 */ 53 #define RCR_L2_LEN_MASK 0x003fff0000000000ULL 54 #define RCR_ERROR_SHIFT 54 /* bit 57:54 */ 55 #define RCR_ERROR_MASK 0x03C0000000000000ULL 56 #define RCR_PKT_TYPE_SHIFT 61 /* bit 62:61 */ 57 #define RCR_PKT_TYPE_MASK 0x6000000000000000ULL 58 #define RCR_MULTI_SHIFT 63 /* bit 63 */ 59 #define RCR_MULTI_MASK 0x8000000000000000ULL 60 61 #define RCR_PKTBUFSZ_0 0x00 62 #define RCR_PKTBUFSZ_1 0x01 63 #define RCR_PKTBUFSZ_2 0x02 64 #define RCR_SINGLE_BLOCK 0x03 65 66 #define RCR_NO_ERROR 0x0 67 #define RCR_CTRL_FIFO_DED 0x1 68 #define RCR_DATA_FIFO_DED 0x2 69 #define RCR_ERROR_RESERVE 0x4 70 71 #define RCR_PKT_IS_TCP 0x2000000000000000ULL 72 #define RCR_PKT_IS_UDP 0x4000000000000000ULL 73 #define RCR_PKT_IS_SCTP 0x6000000000000000ULL 74 75 #define RDC_INT_MASK_RBRFULL_SHIFT 34 76 #define RDC_INT_MASK_RBRFULL_MASK 0x0000000400000000ULL 77 #define RDC_INT_MASK_RBREMPTY_SHIFT 35 78 #define RDC_INT_MASK_RBREMPTY_MASK 0x0000000800000000ULL 79 #define RDC_INT_MASK_RCRFULL_SHIFT 36 80 #define RDC_INT_MASK_RCRFULL_MASK 0x0000001000000000ULL 81 #define RDC_INT_MASK_RCRSH_FULL_SHIFT 39 82 #define RDC_INT_MASK_RCRSH_FULL_MASK 0x0000008000000000ULL 83 #define RDC_INT_MASK_RBR_PRE_EMPTY_SHIFT 40 84 #define RDC_INT_MASK_RBR_PRE_EMPTY_MASK 0x0000010000000000ULL 85 #define RDC_INT_MASK_RBR_PRE_PAR_SHIFT 43 86 #define RDC_INT_MASK_RBR_PRE_PAR_MASK 0x0000080000000000ULL 87 #define RDC_INT_MASK_RCR_SHA_PAR_SHIFT 44 88 #define RDC_INT_MASK_RCR_SHA_PAR_MASK 0x0000100000000000ULL 89 #define RDC_INT_MASK_RCRTO_SHIFT 45 90 #define RDC_INT_MASK_RCRTO_MASK 0x0000200000000000ULL 91 #define RDC_INT_MASK_THRES_SHIFT 46 92 #define RDC_INT_MASK_THRES_MASK 0x0000400000000000ULL 93 #define RDC_INT_MASK_PEU_ERR_SHIFT 52 94 #define RDC_INT_MASK_PEU_ERR_MASK 0x0010000000000000ULL 95 #define RDC_INT_MASK_RBR_CPL_SHIFT 53 96 #define RDC_INT_MASK_RBR_CPL_MASK 0x0020000000000000ULL 97 #define RDC_INT_MASK_ALL (RDC_INT_MASK_RBRFULL_MASK | \ 98 RDC_INT_MASK_RBREMPTY_MASK | \ 99 RDC_INT_MASK_RCRFULL_MASK | \ 100 RDC_INT_MASK_RCRSH_FULL_MASK | \ 101 RDC_INT_MASK_RBR_PRE_EMPTY_MASK | \ 102 RDC_INT_MASK_RBR_PRE_PAR_MASK | \ 103 RDC_INT_MASK_RCR_SHA_PAR_MASK | \ 104 RDC_INT_MASK_RCRTO_MASK | \ 105 RDC_INT_MASK_THRES_MASK | \ 106 RDC_INT_MASK_PEU_ERR_MASK | \ 107 RDC_INT_MASK_RBR_CPL_MASK) 108 109 #define RDC_STAT_PKTREAD_SHIFT 0 /* WO, bit 15:0 */ 110 #define RDC_STAT_PKTREAD_MASK 0x000000000000ffffULL 111 #define RDC_STAT_PTRREAD_SHIFT 16 /* WO, bit 31:16 */ 112 #define RDC_STAT_PTRREAD_MASK 0x00000000FFFF0000ULL 113 114 #define RDC_STAT_RBRFULL_SHIFT 34 /* RO, bit 34 */ 115 #define RDC_STAT_RBRFULL 0x0000000400000000ULL 116 #define RDC_STAT_RBRFULL_MASK 0x0000000400000000ULL 117 #define RDC_STAT_RBREMPTY_SHIFT 35 /* RW1C, bit 35 */ 118 #define RDC_STAT_RBREMPTY 0x0000000800000000ULL 119 #define RDC_STAT_RBREMPTY_MASK 0x0000000800000000ULL 120 #define RDC_STAT_RCR_FULL_SHIFT 36 /* RW1C, bit 36 */ 121 #define RDC_STAT_RCR_FULL 0x0000001000000000ULL 122 #define RDC_STAT_RCR_FULL_MASK 0x0000001000000000ULL 123 124 #define RDC_STAT_RCR_SHDW_FULL_SHIFT 39 /* RW1C, bit 39 */ 125 #define RDC_STAT_RCR_SHDW_FULL 0x0000008000000000ULL 126 #define RDC_STAT_RCR_SHDW_FULL_MASK 0x0000008000000000ULL 127 #define RDC_STAT_RBR_PRE_EMPTY_SHIFT 40 /* RO, bit 40 */ 128 #define RDC_STAT_RBR_PRE_EMPTY 0x0000010000000000ULL 129 #define RDC_STAT_RBR_PRE_EMPTY_MASK 0x0000010000000000ULL 130 131 #define RDC_STAT_RBR_PRE_PAR_SHIFT 43 /* RO, bit 43 */ 132 #define RDC_STAT_RBR_PRE_PAR 0x0000080000000000ULL 133 #define RDC_STAT_RBR_PRE_PAR_MASK 0x0000080000000000ULL 134 #define RDC_STAT_RCR_SHA_PAR_SHIFT 44 /* RO, bit 44 */ 135 #define RDC_STAT_RCR_SHA_PAR 0x0000100000000000ULL 136 #define RDC_STAT_RCR_SHA_PAR_MASK 0x0000100000000000ULL 137 138 #define RDC_STAT_RCR_TO_SHIFT 45 /* RW1C, bit 45 */ 139 #define RDC_STAT_RCR_TO 0x0000200000000000ULL 140 #define RDC_STAT_RCR_TO_MASK 0x0000200000000000ULL 141 #define RDC_STAT_RCR_THRES_SHIFT 46 /* RO, bit 46 */ 142 #define RDC_STAT_RCR_THRES 0x0000400000000000ULL 143 #define RDC_STAT_RCR_THRES_MASK 0x0000400000000000ULL 144 #define RDC_STAT_RCR_MEX_SHIFT 47 /* RW, bit 47 */ 145 #define RDC_STAT_RCR_MEX 0x0000800000000000ULL 146 #define RDC_STAT_RCR_MEX_MASK 0x0000800000000000ULL 147 148 #define RDC_STAT_PEU_ERR_SHIFT 52 /* RO, bit 52 */ 149 #define RDC_STAT_PEU_ERR 0x0010000000000000ULL 150 #define RDC_STAT_PEU_ERR_MASK 0x0010000000000000ULL 151 152 #define RDC_STAT_RBR_CPL_SHIFT 53 /* RO, bit 53 */ 153 #define RDC_STAT_RBR_CPL 0x0020000000000000ULL 154 #define RDC_STAT_RBR_CPL_MASK 0x0020000000000000ULL 155 156 #define RDC_STAT_ERROR RDC_INT_MASK_ALL 157 158 /* the following are write 1 to clear bits */ 159 #define RDC_STAT_WR1C (RDC_STAT_RBREMPTY | \ 160 RDC_STAT_RCR_SHDW_FULL | \ 161 RDC_STAT_RBR_PRE_EMPTY | \ 162 RDC_STAT_RBR_PRE_PAR | \ 163 RDC_STAT_RCR_SHA_PAR | \ 164 RDC_STAT_RCR_TO | \ 165 RDC_STAT_RCR_THRES | \ 166 RDC_STAT_RBR_CPL | \ 167 RDC_STAT_PEU_ERR) 168 169 typedef union _rcr_entry_t { 170 uint64_t value; 171 struct { 172 #if defined(_BIG_ENDIAN) 173 uint32_t multi:1; 174 uint32_t pkt_type:2; 175 uint32_t reserved:3; 176 uint32_t error:4; 177 uint32_t l2_len:14; 178 uint32_t pktbufsz:2; 179 uint32_t pkt_buf_addr:6; 180 uint32_t pkt_buf_addr_l:32; 181 #else 182 uint32_t pkt_buf_addr_l:32; 183 uint32_t pkt_buf_addr:6; 184 uint32_t pktbufsz:2; 185 uint32_t l2_len:14; 186 uint32_t error:4; 187 uint32_t reserved:3; 188 uint32_t pkt_type:2; 189 uint32_t multi:1; 190 #endif 191 } bits; 192 } rcr_entry_t, *p_rcr_entry_t; 193 194 #define RX_DMA_MAILBOX_BYTE_LENGTH 64 195 #define RX_DMA_MBOX_UNUSED_1 8 196 #define RX_DMA_MBOX_UNUSED_2 16 197 198 typedef struct _rxdma_mailbox_t { 199 rdc_stat_t rxdma_ctl_stat; /* 8 bytes */ 200 rdc_rbr_qlen_t rbr_stat; /* 8 bytes */ 201 rdc_rbr_head_t rbr_hdh; /* 8 bytes */ 202 uint8_t resv_1[RX_DMA_MBOX_UNUSED_1]; 203 rdc_rcr_tail_t rcrstat_c; /* 8 bytes */ 204 uint8_t resv_2[RX_DMA_MBOX_UNUSED_1]; 205 rdc_rcr_qlen_t rcrstat_a; /* 8 bytes */ 206 uint8_t resv_3[RX_DMA_MBOX_UNUSED_1]; 207 } rxdma_mailbox_t, *p_rxdma_mailbox_t; 208 209 /* 210 * hardware workarounds: kick 16 (was 8 before) 211 */ 212 #define HXGE_RXDMA_POST_BATCH 16 213 214 #define RXBUF_START_ADDR(a, index, bsize) ((a & (index * bsize)) 215 #define RXBUF_OFFSET_FROM_START(a, start) (start - a) 216 #define RXBUF_64B_ALIGNED 64 217 218 #define HXGE_RXBUF_EXTRA 34 219 220 /* 221 * Receive buffer thresholds and buffer types 222 */ 223 #define HXGE_RX_BCOPY_SCALE 8 /* use 1/8 as lowest granularity */ 224 225 typedef enum { 226 HXGE_RX_COPY_ALL = 0, /* do bcopy on every packet */ 227 HXGE_RX_COPY_1, /* bcopy on 1/8 of buffer posted */ 228 HXGE_RX_COPY_2, /* bcopy on 2/8 of buffer posted */ 229 HXGE_RX_COPY_3, /* bcopy on 3/8 of buffer posted */ 230 HXGE_RX_COPY_4, /* bcopy on 4/8 of buffer posted */ 231 HXGE_RX_COPY_5, /* bcopy on 5/8 of buffer posted */ 232 HXGE_RX_COPY_6, /* bcopy on 6/8 of buffer posted */ 233 HXGE_RX_COPY_7, /* bcopy on 7/8 of buffer posted */ 234 HXGE_RX_COPY_NONE /* don't do bcopy at all */ 235 } hxge_rxbuf_threshold_t; 236 237 typedef enum { 238 HXGE_RBR_TYPE0 = RCR_PKTBUFSZ_0, /* bcopy buffer size 0 (small) */ 239 HXGE_RBR_TYPE1 = RCR_PKTBUFSZ_1, /* bcopy buffer size 1 (medium) */ 240 HXGE_RBR_TYPE2 = RCR_PKTBUFSZ_2 /* bcopy buffer size 2 (large) */ 241 } hxge_rxbuf_type_t; 242 243 typedef struct _rdc_errlog { 244 rdc_pref_par_log_t pre_par; 245 rdc_pref_par_log_t sha_par; 246 uint8_t compl_err_type; 247 } rdc_errlog_t; 248 249 /* 250 * Receive Statistics. 251 */ 252 typedef struct _hxge_rx_ring_stats_t { 253 uint64_t ipackets; 254 uint64_t ibytes; 255 uint32_t ierrors; 256 uint32_t jumbo_pkts; 257 258 /* 259 * Error event stats. 260 */ 261 uint32_t rcr_unknown_err; 262 uint32_t ctrl_fifo_ecc_err; 263 uint32_t data_fifo_ecc_err; 264 uint32_t rbr_tmout; /* rbr_cpl_to */ 265 uint32_t peu_resp_err; /* peu_resp_err */ 266 uint32_t rcr_sha_par; /* rcr_shadow_par_err */ 267 uint32_t rbr_pre_par; /* rbr_prefetch_par_err */ 268 uint32_t rbr_pre_empty; /* rbr_pre_empty */ 269 uint32_t rcr_shadow_full; /* rcr_shadow_full */ 270 uint32_t rcrfull; /* rcr_full */ 271 uint32_t rbr_empty; /* rbr_empty */ 272 uint32_t rbrfull; /* rbr_full */ 273 uint32_t rcr_to; /* rcr_to */ 274 uint32_t rcr_thres; /* rcr_thres */ 275 rdc_errlog_t errlog; 276 } hxge_rx_ring_stats_t, *p_hxge_rx_ring_stats_t; 277 278 typedef struct _hxge_rdc_sys_stats { 279 uint32_t ctrl_fifo_sec; 280 uint32_t ctrl_fifo_ded; 281 uint32_t data_fifo_sec; 282 uint32_t data_fifo_ded; 283 } hxge_rdc_sys_stats_t, *p_hxge_rdc_sys_stats_t; 284 285 typedef struct _rx_msg_t { 286 hxge_os_dma_common_t buf_dma; 287 hxge_os_mutex_t lock; 288 struct _hxge_t *hxgep; 289 struct _rx_rbr_ring_t *rx_rbr_p; 290 boolean_t free; 291 uint32_t ref_cnt; 292 hxge_os_frtn_t freeb; 293 size_t block_size; 294 uint32_t block_index; 295 uint32_t pkt_buf_size; 296 uint32_t pkt_buf_size_code; 297 uint32_t cur_usage_cnt; 298 uint32_t max_usage_cnt; 299 uchar_t *buffer; 300 uint32_t pri; 301 uint32_t shifted_addr; 302 boolean_t use_buf_pool; 303 p_mblk_t rx_mblk_p; 304 boolean_t rx_use_bcopy; 305 } rx_msg_t, *p_rx_msg_t; 306 307 /* Receive Completion Ring */ 308 typedef struct _rx_rcr_ring_t { 309 hxge_os_dma_common_t rcr_desc; 310 struct _hxge_t *hxgep; 311 312 p_hxge_rx_ring_stats_t rdc_stats; /* pointer to real kstats */ 313 314 rdc_rcr_cfg_a_t rcr_cfga; 315 rdc_rcr_cfg_b_t rcr_cfgb; 316 317 hxge_os_mutex_t lock; 318 uint16_t index; 319 uint16_t rdc; 320 boolean_t full_hdr_flag; /* 1: 18 bytes header */ 321 uint16_t sw_priv_hdr_len; /* 0 - 192 bytes (SW) */ 322 uint32_t comp_size; /* # of RCR entries */ 323 uint64_t rcr_addr; 324 uint_t comp_wrap_mask; 325 uint_t comp_rd_index; 326 uint_t comp_wt_index; 327 328 p_rcr_entry_t rcr_desc_first_p; 329 p_rcr_entry_t rcr_desc_first_pp; 330 p_rcr_entry_t rcr_desc_last_p; 331 p_rcr_entry_t rcr_desc_last_pp; 332 333 p_rcr_entry_t rcr_desc_rd_head_p; /* software next read */ 334 p_rcr_entry_t rcr_desc_rd_head_pp; 335 336 struct _rx_rbr_ring_t *rx_rbr_p; 337 uint32_t intr_timeout; 338 uint32_t intr_threshold; 339 uint64_t max_receive_pkts; 340 mac_resource_handle_t rcr_mac_handle; 341 uint32_t rcvd_pkt_bytes; /* Received bytes of a packet */ 342 } rx_rcr_ring_t, *p_rx_rcr_ring_t; 343 344 345 /* Buffer index information */ 346 typedef struct _rxbuf_index_info_t { 347 uint32_t buf_index; 348 uint32_t start_index; 349 uint32_t buf_size; 350 uint64_t dvma_addr; 351 uint64_t kaddr; 352 } rxbuf_index_info_t, *p_rxbuf_index_info_t; 353 354 /* Buffer index information */ 355 356 typedef struct _rxring_info_t { 357 uint32_t hint[3]; 358 uint32_t block_size_mask; 359 uint16_t max_iterations; 360 rxbuf_index_info_t buffer[HXGE_DMA_BLOCK]; 361 } rxring_info_t, *p_rxring_info_t; 362 363 364 typedef enum { 365 RBR_POSTING = 1, /* We may post rx buffers. */ 366 RBR_UNMAPPING, /* We are in the process of unmapping. */ 367 RBR_UNMAPPED /* The ring is unmapped. */ 368 } rbr_state_t; 369 370 371 /* Receive Buffer Block Ring */ 372 typedef struct _rx_rbr_ring_t { 373 hxge_os_dma_common_t rbr_desc; 374 p_rx_msg_t *rx_msg_ring; 375 p_hxge_dma_common_t *dma_bufp; 376 rdc_rbr_cfg_a_t rbr_cfga; 377 rdc_rbr_cfg_b_t rbr_cfgb; 378 rdc_rbr_kick_t rbr_kick; 379 rdc_page_handle_t page_hdl; 380 381 hxge_os_mutex_t lock; 382 hxge_os_mutex_t post_lock; 383 uint16_t index; 384 struct _hxge_t *hxgep; 385 uint16_t rdc; 386 uint_t rbr_max_size; 387 uint64_t rbr_addr; 388 uint_t rbr_wrap_mask; 389 uint_t rbb_max; 390 uint_t block_size; 391 uint_t num_blocks; 392 uint_t tnblocks; 393 uint_t pkt_buf_size0; 394 uint_t pkt_buf_size0_bytes; 395 uint_t hpi_pkt_buf_size0; 396 uint_t pkt_buf_size1; 397 uint_t pkt_buf_size1_bytes; 398 uint_t hpi_pkt_buf_size1; 399 uint_t pkt_buf_size2; 400 uint_t pkt_buf_size2_bytes; 401 uint_t hpi_pkt_buf_size2; 402 403 uint64_t rbr_head_pp; 404 uint64_t rbr_tail_pp; 405 uint32_t *rbr_desc_vp; 406 407 p_rx_rcr_ring_t rx_rcr_p; 408 409 rdc_rbr_head_t rbr_head; 410 uint_t rbr_wr_index; 411 uint_t rbr_rd_index; 412 uint_t rbr_hw_head_index; 413 uint64_t rbr_hw_head_ptr; 414 415 rxring_info_t *ring_info; 416 uint_t rbr_consumed; 417 uint_t rbr_threshold_hi; 418 uint_t rbr_threshold_lo; 419 hxge_rxbuf_type_t rbr_bufsize_type; 420 boolean_t rbr_use_bcopy; 421 422 /* 423 * <rbr_ref_cnt> is a count of those receive buffers which 424 * have been loaned to the kernel. We will not free this 425 * ring until the reference count reaches zero (0). 426 */ 427 uint32_t rbr_ref_cnt; 428 rbr_state_t rbr_state; /* POSTING, etc */ 429 430 int pages_to_post; 431 int pages_to_post_threshold; 432 int pages_to_skip; 433 } rx_rbr_ring_t, *p_rx_rbr_ring_t; 434 435 /* Receive Mailbox */ 436 typedef struct _rx_mbox_t { 437 hxge_os_dma_common_t rx_mbox; 438 rdc_rx_cfg1_t rx_cfg1; 439 rdc_rx_cfg2_t rx_cfg2; 440 uint64_t mbox_addr; 441 boolean_t cfg_set; 442 443 hxge_os_mutex_t lock; 444 uint16_t index; 445 struct _hxge_t *hxgep; 446 uint16_t rdc; 447 } rx_mbox_t, *p_rx_mbox_t; 448 449 typedef struct _rx_rbr_rings_t { 450 p_rx_rbr_ring_t *rbr_rings; 451 uint32_t ndmas; 452 boolean_t rxbuf_allocated; 453 } rx_rbr_rings_t, *p_rx_rbr_rings_t; 454 455 typedef struct _rx_rcr_rings_t { 456 p_rx_rcr_ring_t *rcr_rings; 457 uint32_t ndmas; 458 boolean_t cntl_buf_allocated; 459 } rx_rcr_rings_t, *p_rx_rcr_rings_t; 460 461 typedef struct _rx_mbox_areas_t { 462 p_rx_mbox_t *rxmbox_areas; 463 uint32_t ndmas; 464 boolean_t mbox_allocated; 465 } rx_mbox_areas_t, *p_rx_mbox_areas_t; 466 467 /* 468 * Receive DMA Prototypes. 469 */ 470 hxge_status_t hxge_init_rxdma_channels(p_hxge_t hxgep); 471 void hxge_uninit_rxdma_channels(p_hxge_t hxgep); 472 hxge_status_t hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, 473 uint16_t channel, rdc_stat_t *cs_p); 474 hxge_status_t hxge_enable_rxdma_channel(p_hxge_t hxgep, 475 uint16_t channel, p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, 476 p_rx_mbox_t mbox_p); 477 hxge_status_t hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable); 478 int hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel); 479 hxge_status_t hxge_rxdma_handle_sys_errors(p_hxge_t hxgep); 480 481 482 #ifdef __cplusplus 483 } 484 #endif 485 486 #endif /* _SYS_HXGE_HXGE_RXDMA_H */ 487