1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 28 lb_property_t lb_normal = {normal, "normal", hxge_lb_normal}; 29 lb_property_t lb_mac10g = {internal, "mac10g", hxge_lb_mac10g}; 30 31 uint32_t hxge_lb_dbg = 1; 32 33 extern uint32_t hxge_jumbo_frame_size; 34 35 static void hxge_rtrace_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 36 37 void 38 hxge_global_reset(p_hxge_t hxgep) 39 { 40 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_global_reset")); 41 42 (void) hxge_intr_hw_disable(hxgep); 43 44 if (hxgep->suspended) 45 (void) hxge_link_init(hxgep); 46 47 (void) hxge_vmac_init(hxgep); 48 49 (void) hxge_intr_hw_enable(hxgep); 50 51 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_global_reset")); 52 } 53 54 55 void 56 hxge_hw_id_init(p_hxge_t hxgep) 57 { 58 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_hw_id_init")); 59 60 /* 61 * Initialize the frame size to either standard "1500 + 38" or 62 * jumbo. The user may tune the frame size through the "mtu" parameter 63 * using "dladm set-linkprop" 64 */ 65 hxgep->vmac.minframesize = MIN_FRAME_SIZE; 66 hxgep->vmac.maxframesize = HXGE_DEFAULT_MTU + MTU_TO_FRAME_SIZE; 67 if (hxgep->param_arr[param_accept_jumbo].value) 68 hxgep->vmac.maxframesize = (uint16_t)hxge_jumbo_frame_size; 69 70 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_hw_id_init: maxframesize %d", 71 hxgep->vmac.maxframesize)); 72 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_hw_id_init")); 73 } 74 75 void 76 hxge_hw_init_niu_common(p_hxge_t hxgep) 77 { 78 p_hxge_hw_list_t hw_p; 79 80 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_hw_init_niu_common")); 81 82 if ((hw_p = hxgep->hxge_hw_p) == NULL) { 83 return; 84 } 85 86 MUTEX_ENTER(&hw_p->hxge_cfg_lock); 87 if (hw_p->flags & COMMON_INIT_DONE) { 88 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "hxge_hw_init_niu_common" 89 " already done for dip $%p exiting", hw_p->parent_devp)); 90 MUTEX_EXIT(&hw_p->hxge_cfg_lock); 91 return; 92 } 93 94 hw_p->flags = COMMON_INIT_START; 95 HXGE_DEBUG_MSG((hxgep, MOD_CTL, 96 "hxge_hw_init_niu_common Started for device id %x", 97 hw_p->parent_devp)); 98 99 (void) hxge_pfc_hw_reset(hxgep); 100 hw_p->flags = COMMON_INIT_DONE; 101 MUTEX_EXIT(&hw_p->hxge_cfg_lock); 102 103 HXGE_DEBUG_MSG((hxgep, MOD_CTL, 104 "hxge_hw_init_niu_common Done for device id %x", 105 hw_p->parent_devp)); 106 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_hw_init_niu_common")); 107 } 108 109 uint_t 110 hxge_intr(caddr_t arg1, caddr_t arg2) 111 { 112 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 113 p_hxge_t hxgep = (p_hxge_t)arg2; 114 uint_t serviced = DDI_INTR_UNCLAIMED; 115 uint8_t ldv; 116 hpi_handle_t handle; 117 p_hxge_ldgv_t ldgvp; 118 p_hxge_ldg_t ldgp, t_ldgp; 119 p_hxge_ldv_t t_ldvp; 120 uint32_t vector0 = 0, vector1 = 0; 121 int i, j, nldvs, nintrs = 1; 122 hpi_status_t rs = HPI_SUCCESS; 123 124 /* 125 * DDI interface returns second arg as NULL 126 */ 127 if ((arg2 == NULL) || ((void *) ldvp->hxgep != arg2)) { 128 hxgep = ldvp->hxgep; 129 } 130 131 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr")); 132 133 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 134 HXGE_ERROR_MSG((hxgep, INT_CTL, 135 "<== hxge_intr: not initialized 0x%x", serviced)); 136 return (serviced); 137 } 138 139 ldgvp = hxgep->ldgvp; 140 141 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr: ldgvp $%p", ldgvp)); 142 143 if (ldvp == NULL && ldgvp) { 144 t_ldvp = ldvp = ldgvp->ldvp; 145 } 146 147 if (ldvp) { 148 ldgp = t_ldgp = ldvp->ldgp; 149 } 150 151 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr: " 152 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 153 154 if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 155 HXGE_ERROR_MSG((hxgep, INT_CTL, "==> hxge_intr: " 156 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 157 HXGE_ERROR_MSG((hxgep, INT_CTL, "<== hxge_intr: not ready")); 158 return (DDI_INTR_UNCLAIMED); 159 } 160 161 /* 162 * This interrupt handler will have to go through 163 * all the logical devices to find out which 164 * logical device interrupts us and then call 165 * its handler to process the events. 166 */ 167 handle = HXGE_DEV_HPI_HANDLE(hxgep); 168 t_ldgp = ldgp; 169 t_ldvp = ldgp->ldvp; 170 171 nldvs = ldgp->nldvs; 172 173 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr: #ldvs %d #intrs %d", 174 nldvs, ldgvp->ldg_intrs)); 175 176 serviced = DDI_INTR_CLAIMED; 177 for (i = 0; i < nintrs; i++, t_ldgp++) { 178 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr(%d): #ldvs %d " 179 " #intrs %d", i, nldvs, nintrs)); 180 181 /* Get this group's flag bits. */ 182 t_ldgp->interrupted = B_FALSE; 183 rs = hpi_ldsv_ldfs_get(handle, t_ldgp->ldg, &vector0, &vector1); 184 if (rs) { 185 continue; 186 } 187 188 if (!vector0 && !vector1) { 189 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr: " 190 "no interrupts on group %d", t_ldgp->ldg)); 191 continue; 192 } 193 194 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr: " 195 "vector0 0x%llx vector1 0x%llx", vector0, vector1)); 196 197 t_ldgp->interrupted = B_TRUE; 198 nldvs = t_ldgp->nldvs; 199 200 for (j = 0; j < nldvs; j++, t_ldvp++) { 201 /* 202 * Call device's handler if flag bits are on. 203 */ 204 ldv = t_ldvp->ldv; 205 if ((LDV_ON(ldv, vector0) | (LDV_ON(ldv, vector1)))) { 206 HXGE_DEBUG_MSG((hxgep, INT_CTL, 207 "==> hxge_intr: calling device %d" 208 " #ldvs %d #intrs %d", j, nldvs, nintrs)); 209 (void) (t_ldvp->ldv_intr_handler)( 210 (caddr_t)t_ldvp, arg2); 211 } 212 } 213 } 214 215 t_ldgp = ldgp; 216 for (i = 0; i < nintrs; i++, t_ldgp++) { 217 /* rearm group interrupts */ 218 if (t_ldgp->interrupted) { 219 HXGE_DEBUG_MSG((hxgep, INT_CTL, 220 "==> hxge_intr: arm group %d", t_ldgp->ldg)); 221 (void) hpi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 222 t_ldgp->arm, t_ldgp->ldg_timer); 223 } 224 } 225 226 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr: serviced 0x%x", 227 serviced)); 228 return (serviced); 229 } 230 231 hxge_status_t 232 hxge_peu_handle_sys_errors(p_hxge_t hxgep) 233 { 234 hpi_handle_t handle; 235 p_hxge_peu_sys_stats_t statsp; 236 peu_intr_stat_t stat; 237 238 handle = hxgep->hpi_handle; 239 statsp = (p_hxge_peu_sys_stats_t)&hxgep->statsp->peu_sys_stats; 240 241 HXGE_REG_RD32(handle, PEU_INTR_STAT, &stat.value); 242 243 /* 244 * The PCIE errors are unrecoverrable and cannot be cleared. 245 * The only thing we can do here is to mask them off to prevent 246 * continued interrupts. 247 */ 248 HXGE_REG_WR32(handle, PEU_INTR_MASK, 0xffffffff); 249 250 if (stat.bits.spc_acc_err) { 251 statsp->spc_acc_err++; 252 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 253 "==> hxge_peu_handle_sys_errors: spc_acc_err")); 254 } 255 256 if (stat.bits.tdc_pioacc_err) { 257 statsp->tdc_pioacc_err++; 258 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 259 "==> hxge_peu_handle_sys_errors: tdc_pioacc_err")); 260 } 261 262 if (stat.bits.rdc_pioacc_err) { 263 statsp->rdc_pioacc_err++; 264 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 265 "==> hxge_peu_handle_sys_errors: rdc_pioacc_err")); 266 } 267 268 if (stat.bits.pfc_pioacc_err) { 269 statsp->pfc_pioacc_err++; 270 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 271 "==> hxge_peu_handle_sys_errors: pfc_pioacc_err")); 272 } 273 274 if (stat.bits.vmac_pioacc_err) { 275 statsp->vmac_pioacc_err++; 276 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 277 "==> hxge_peu_handle_sys_errors: vmac_pioacc_err")); 278 } 279 280 if (stat.bits.cpl_hdrq_parerr) { 281 statsp->cpl_hdrq_parerr++; 282 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 283 "==> hxge_peu_handle_sys_errors: cpl_hdrq_parerr")); 284 } 285 286 if (stat.bits.cpl_dataq_parerr) { 287 statsp->cpl_dataq_parerr++; 288 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 289 "==> hxge_peu_handle_sys_errors: cpl_dataq_parerr")); 290 } 291 292 if (stat.bits.retryram_xdlh_parerr) { 293 statsp->retryram_xdlh_parerr++; 294 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 295 "==> hxge_peu_handle_sys_errors: retryram_xdlh_parerr")); 296 } 297 298 if (stat.bits.retrysotram_xdlh_parerr) { 299 statsp->retrysotram_xdlh_parerr++; 300 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 301 "==> hxge_peu_handle_sys_errors: retrysotram_xdlh_parerr")); 302 } 303 304 if (stat.bits.p_hdrq_parerr) { 305 statsp->p_hdrq_parerr++; 306 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 307 "==> hxge_peu_handle_sys_errors: p_hdrq_parerr")); 308 } 309 310 if (stat.bits.p_dataq_parerr) { 311 statsp->p_dataq_parerr++; 312 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 313 "==> hxge_peu_handle_sys_errors: p_dataq_parerr")); 314 } 315 316 if (stat.bits.np_hdrq_parerr) { 317 statsp->np_hdrq_parerr++; 318 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 319 "==> hxge_peu_handle_sys_errors: np_hdrq_parerr")); 320 } 321 322 if (stat.bits.np_dataq_parerr) { 323 statsp->np_dataq_parerr++; 324 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 325 "==> hxge_peu_handle_sys_errors: np_dataq_parerr")); 326 } 327 328 if (stat.bits.eic_msix_parerr) { 329 statsp->eic_msix_parerr++; 330 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 331 "==> hxge_peu_handle_sys_errors: eic_msix_parerr")); 332 } 333 334 if (stat.bits.hcr_parerr) { 335 statsp->hcr_parerr++; 336 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 337 "==> hxge_peu_handle_sys_errors: hcr_parerr")); 338 } 339 340 return (HXGE_OK); 341 } 342 343 /*ARGSUSED*/ 344 uint_t 345 hxge_syserr_intr(caddr_t arg1, caddr_t arg2) 346 { 347 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 348 p_hxge_t hxgep = (p_hxge_t)arg2; 349 p_hxge_ldg_t ldgp = NULL; 350 hpi_handle_t handle; 351 dev_err_stat_t estat; 352 uint_t serviced = DDI_INTR_UNCLAIMED; 353 354 if ((arg1 == NULL) && (arg2 == NULL)) { 355 return (serviced); 356 } 357 358 if ((arg2 == NULL) || 359 ((ldvp != NULL) && ((void *)ldvp->hxgep != arg2))) { 360 if (ldvp != NULL) { 361 hxgep = ldvp->hxgep; 362 } 363 } 364 365 HXGE_DEBUG_MSG((hxgep, SYSERR_CTL, 366 "==> hxge_syserr_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 367 368 if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 369 ldgp = ldvp->ldgp; 370 if (ldgp == NULL) { 371 HXGE_ERROR_MSG((hxgep, SYSERR_CTL, 372 "<== hxge_syserrintr(no logical group): " 373 "arg2 $%p arg1 $%p", hxgep, ldvp)); 374 return (DDI_INTR_UNCLAIMED); 375 } 376 /* 377 * Get the logical device state if the function uses interrupt. 378 */ 379 } 380 381 /* This interrupt handler is for system error interrupts. */ 382 handle = HXGE_DEV_HPI_HANDLE(hxgep); 383 estat.value = 0; 384 (void) hpi_fzc_sys_err_stat_get(handle, &estat); 385 HXGE_DEBUG_MSG((hxgep, SYSERR_CTL, 386 "==> hxge_syserr_intr: device error 0x%016llx", estat.value)); 387 388 if (estat.bits.tdc_err0 || estat.bits.tdc_err1) { 389 /* TDMC */ 390 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 391 "==> hxge_syserr_intr: device error - TDMC")); 392 (void) hxge_txdma_handle_sys_errors(hxgep); 393 } else if (estat.bits.rdc_err0 || estat.bits.rdc_err1) { 394 /* RDMC */ 395 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 396 "==> hxge_syserr_intr: device error - RDMC")); 397 (void) hxge_rxdma_handle_sys_errors(hxgep); 398 } else if (estat.bits.vnm_pio_err1 || estat.bits.peu_err1) { 399 /* PCI-E */ 400 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 401 "==> hxge_syserr_intr: device error - PCI-E")); 402 403 /* kstats are updated here */ 404 (void) hxge_peu_handle_sys_errors(hxgep); 405 406 if (estat.bits.peu_err1) 407 HXGE_FM_REPORT_ERROR(hxgep, NULL, 408 HXGE_FM_EREPORT_PEU_ERR); 409 410 if (estat.bits.vnm_pio_err1) 411 HXGE_FM_REPORT_ERROR(hxgep, NULL, 412 HXGE_FM_EREPORT_PEU_VNM_PIO_ERR); 413 } else if (estat.value != 0) { 414 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 415 "==> hxge_syserr_intr: device error - unknown")); 416 } 417 418 serviced = DDI_INTR_CLAIMED; 419 420 if ((ldgp != NULL) && (ldvp != NULL) && 421 (ldgp->nldvs == 1) && !ldvp->use_timer) { 422 (void) hpi_intr_ldg_mgmt_set(handle, ldgp->ldg, 423 B_TRUE, ldgp->ldg_timer); 424 } 425 426 HXGE_DEBUG_MSG((hxgep, SYSERR_CTL, "<== hxge_syserr_intr")); 427 return (serviced); 428 } 429 430 void 431 hxge_intr_hw_enable(p_hxge_t hxgep) 432 { 433 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr_hw_enable")); 434 435 (void) hxge_intr_mask_mgmt_set(hxgep, B_TRUE); 436 437 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr_hw_enable")); 438 } 439 440 void 441 hxge_intr_hw_disable(p_hxge_t hxgep) 442 { 443 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr_hw_disable")); 444 445 (void) hxge_intr_mask_mgmt_set(hxgep, B_FALSE); 446 447 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr_hw_disable")); 448 } 449 450 void 451 hxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 452 { 453 p_hxge_t hxgep = (p_hxge_t)arg; 454 455 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_hw_blank")); 456 457 /* 458 * Replace current ticks and counts for later 459 * processing by the receive packet interrupt routines. 460 */ 461 hxgep->intr_timeout = (uint16_t)ticks; 462 hxgep->intr_threshold = (uint16_t)count; 463 464 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_hw_blank")); 465 } 466 467 void 468 hxge_hw_stop(p_hxge_t hxgep) 469 { 470 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_hw_stop")); 471 472 (void) hxge_tx_vmac_disable(hxgep); 473 (void) hxge_rx_vmac_disable(hxgep); 474 (void) hxge_txdma_hw_mode(hxgep, HXGE_DMA_STOP); 475 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 476 477 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_hw_stop")); 478 } 479 480 void 481 hxge_hw_ioctl(p_hxge_t hxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 482 { 483 int cmd; 484 485 HXGE_DEBUG_MSG((hxgep, IOC_CTL, "==> hxge_hw_ioctl")); 486 487 if (hxgep == NULL) { 488 miocnak(wq, mp, 0, EINVAL); 489 return; 490 } 491 492 iocp->ioc_error = 0; 493 cmd = iocp->ioc_cmd; 494 495 switch (cmd) { 496 default: 497 miocnak(wq, mp, 0, EINVAL); 498 return; 499 500 case HXGE_GET64: 501 hxge_get64(hxgep, mp->b_cont); 502 miocack(wq, mp, sizeof (uint32_t), 0); 503 break; 504 505 case HXGE_PUT64: 506 hxge_put64(hxgep, mp->b_cont); 507 miocack(wq, mp, 0, 0); 508 break; 509 510 case HXGE_PUT_TCAM: 511 hxge_put_tcam(hxgep, mp->b_cont); 512 miocack(wq, mp, 0, 0); 513 break; 514 515 case HXGE_GET_TCAM: 516 hxge_get_tcam(hxgep, mp->b_cont); 517 miocack(wq, mp, 0, 0); 518 break; 519 520 case HXGE_RTRACE: 521 hxge_rtrace_ioctl(hxgep, wq, mp, iocp); 522 break; 523 } 524 } 525 526 /* 527 * 10G is the only loopback mode for Hydra. 528 */ 529 void 530 hxge_loopback_ioctl(p_hxge_t hxgep, queue_t *wq, mblk_t *mp, 531 struct iocblk *iocp) 532 { 533 p_lb_property_t lb_props; 534 size_t size; 535 int i; 536 537 if (mp->b_cont == NULL) { 538 miocnak(wq, mp, 0, EINVAL); 539 } 540 541 switch (iocp->ioc_cmd) { 542 case LB_GET_MODE: 543 HXGE_DEBUG_MSG((hxgep, IOC_CTL, "HXGE_GET_LB_MODE command")); 544 if (hxgep != NULL) { 545 *(lb_info_sz_t *)mp->b_cont->b_rptr = 546 hxgep->statsp->port_stats.lb_mode; 547 miocack(wq, mp, sizeof (hxge_lb_t), 0); 548 } else 549 miocnak(wq, mp, 0, EINVAL); 550 break; 551 552 case LB_SET_MODE: 553 HXGE_DEBUG_MSG((hxgep, IOC_CTL, "HXGE_SET_LB_MODE command")); 554 if (iocp->ioc_count != sizeof (uint32_t)) { 555 miocack(wq, mp, 0, 0); 556 break; 557 } 558 if ((hxgep != NULL) && hxge_set_lb(hxgep, wq, mp->b_cont)) { 559 miocack(wq, mp, 0, 0); 560 } else { 561 miocnak(wq, mp, 0, EPROTO); 562 } 563 break; 564 565 case LB_GET_INFO_SIZE: 566 HXGE_DEBUG_MSG((hxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 567 if (hxgep != NULL) { 568 size = sizeof (lb_normal) + sizeof (lb_mac10g); 569 570 *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 571 572 HXGE_DEBUG_MSG((hxgep, IOC_CTL, 573 "HXGE_GET_LB_INFO command: size %d", size)); 574 miocack(wq, mp, sizeof (lb_info_sz_t), 0); 575 } else 576 miocnak(wq, mp, 0, EINVAL); 577 break; 578 579 case LB_GET_INFO: 580 HXGE_DEBUG_MSG((hxgep, IOC_CTL, "HXGE_GET_LB_INFO command")); 581 if (hxgep != NULL) { 582 size = sizeof (lb_normal) + sizeof (lb_mac10g); 583 HXGE_DEBUG_MSG((hxgep, IOC_CTL, 584 "HXGE_GET_LB_INFO command: size %d", size)); 585 if (size == iocp->ioc_count) { 586 i = 0; 587 lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 588 lb_props[i++] = lb_normal; 589 lb_props[i++] = lb_mac10g; 590 591 miocack(wq, mp, size, 0); 592 } else 593 miocnak(wq, mp, 0, EINVAL); 594 } else { 595 miocnak(wq, mp, 0, EINVAL); 596 cmn_err(CE_NOTE, "hxge_hw_ioctl: invalid command 0x%x", 597 iocp->ioc_cmd); 598 } 599 600 break; 601 } 602 } 603 604 /*ARGSUSED*/ 605 boolean_t 606 hxge_set_lb(p_hxge_t hxgep, queue_t *wq, p_mblk_t mp) 607 { 608 boolean_t status = B_TRUE; 609 uint32_t lb_mode; 610 lb_property_t *lb_info; 611 612 HXGE_DEBUG_MSG((hxgep, IOC_CTL, "<== hxge_set_lb")); 613 lb_mode = hxgep->statsp->port_stats.lb_mode; 614 if (lb_mode == *(uint32_t *)mp->b_rptr) { 615 cmn_err(CE_NOTE, 616 "hxge%d: Loopback mode already set (lb_mode %d).\n", 617 hxgep->instance, lb_mode); 618 status = B_FALSE; 619 goto hxge_set_lb_exit; 620 } 621 622 lb_mode = *(uint32_t *)mp->b_rptr; 623 lb_info = NULL; 624 625 /* 10G is the only loopback mode for Hydra */ 626 if (lb_mode == lb_normal.value) 627 lb_info = &lb_normal; 628 else if (lb_mode == lb_mac10g.value) 629 lb_info = &lb_mac10g; 630 else { 631 cmn_err(CE_NOTE, 632 "hxge%d: Loopback mode not supported(mode %d).\n", 633 hxgep->instance, lb_mode); 634 status = B_FALSE; 635 goto hxge_set_lb_exit; 636 } 637 638 if (lb_mode == hxge_lb_normal) { 639 if (hxge_lb_dbg) { 640 cmn_err(CE_NOTE, 641 "!hxge%d: Returning to normal operation", 642 hxgep->instance); 643 } 644 645 hxgep->statsp->port_stats.lb_mode = hxge_lb_normal; 646 hxge_global_reset(hxgep); 647 648 goto hxge_set_lb_exit; 649 } 650 651 hxgep->statsp->port_stats.lb_mode = lb_mode; 652 653 if (hxge_lb_dbg) 654 cmn_err(CE_NOTE, "!hxge%d: Adapter now in %s loopback mode", 655 hxgep->instance, lb_info->key); 656 657 if (lb_info->lb_type == internal) { 658 if ((hxgep->statsp->port_stats.lb_mode == hxge_lb_mac10g)) 659 hxgep->statsp->mac_stats.link_speed = 10000; 660 else { 661 cmn_err(CE_NOTE, 662 "hxge%d: Loopback mode not supported(mode %d).\n", 663 hxgep->instance, lb_mode); 664 status = B_FALSE; 665 goto hxge_set_lb_exit; 666 } 667 hxgep->statsp->mac_stats.link_duplex = 2; 668 hxgep->statsp->mac_stats.link_up = 1; 669 } 670 671 hxge_global_reset(hxgep); 672 673 hxge_set_lb_exit: 674 HXGE_DEBUG_MSG((hxgep, DDI_CTL, 675 "<== hxge_set_lb status = 0x%08x", status)); 676 677 return (status); 678 } 679 680 void 681 hxge_check_hw_state(p_hxge_t hxgep) 682 { 683 p_hxge_ldgv_t ldgvp; 684 p_hxge_ldv_t t_ldvp; 685 686 HXGE_DEBUG_MSG((hxgep, SYSERR_CTL, "==> hxge_check_hw_state")); 687 688 MUTEX_ENTER(hxgep->genlock); 689 690 hxgep->hxge_timerid = 0; 691 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 692 goto hxge_check_hw_state_exit; 693 } 694 695 hxge_check_tx_hang(hxgep); 696 697 ldgvp = hxgep->ldgvp; 698 if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 699 HXGE_ERROR_MSG((hxgep, SYSERR_CTL, "<== hxge_check_hw_state: " 700 "NULL ldgvp (interrupt not ready).")); 701 goto hxge_check_hw_state_exit; 702 } 703 704 t_ldvp = ldgvp->ldvp_syserr; 705 if (!t_ldvp->use_timer) { 706 HXGE_DEBUG_MSG((hxgep, SYSERR_CTL, "<== hxge_check_hw_state: " 707 "ldgvp $%p t_ldvp $%p use_timer flag %d", 708 ldgvp, t_ldvp, t_ldvp->use_timer)); 709 goto hxge_check_hw_state_exit; 710 } 711 712 if (fm_check_acc_handle(hxgep->dev_regs->hxge_regh) != DDI_FM_OK) { 713 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 714 "Bad register acc handle")); 715 } 716 717 (void) hxge_syserr_intr((caddr_t)t_ldvp, (caddr_t)hxgep); 718 719 hxgep->hxge_timerid = hxge_start_timer(hxgep, hxge_check_hw_state, 720 HXGE_CHECK_TIMER); 721 722 hxge_check_hw_state_exit: 723 MUTEX_EXIT(hxgep->genlock); 724 725 HXGE_DEBUG_MSG((hxgep, SYSERR_CTL, "<== hxge_check_hw_state")); 726 } 727 728 /*ARGSUSED*/ 729 static void 730 hxge_rtrace_ioctl(p_hxge_t hxgep, queue_t *wq, mblk_t *mp, 731 struct iocblk *iocp) 732 { 733 ssize_t size; 734 rtrace_t *rtp; 735 mblk_t *nmp; 736 uint32_t i, j; 737 uint32_t start_blk; 738 uint32_t base_entry; 739 uint32_t num_entries; 740 741 HXGE_DEBUG_MSG((hxgep, STR_CTL, "==> hxge_rtrace_ioctl")); 742 743 size = 1024; 744 if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 745 HXGE_DEBUG_MSG((hxgep, STR_CTL, 746 "malformed M_IOCTL MBLKL = %d size = %d", 747 MBLKL(mp->b_cont), size)); 748 miocnak(wq, mp, 0, EINVAL); 749 return; 750 } 751 752 nmp = mp->b_cont; 753 rtp = (rtrace_t *)nmp->b_rptr; 754 start_blk = rtp->next_idx; 755 num_entries = rtp->last_idx; 756 base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 757 758 HXGE_DEBUG_MSG((hxgep, STR_CTL, "start_blk = %d\n", start_blk)); 759 HXGE_DEBUG_MSG((hxgep, STR_CTL, "num_entries = %d\n", num_entries)); 760 HXGE_DEBUG_MSG((hxgep, STR_CTL, "base_entry = %d\n", base_entry)); 761 762 rtp->next_idx = hpi_rtracebuf.next_idx; 763 rtp->last_idx = hpi_rtracebuf.last_idx; 764 rtp->wrapped = hpi_rtracebuf.wrapped; 765 for (i = 0, j = base_entry; i < num_entries; i++, j++) { 766 rtp->buf[i].ctl_addr = hpi_rtracebuf.buf[j].ctl_addr; 767 rtp->buf[i].val_l32 = hpi_rtracebuf.buf[j].val_l32; 768 rtp->buf[i].val_h32 = hpi_rtracebuf.buf[j].val_h32; 769 } 770 771 nmp->b_wptr = nmp->b_rptr + size; 772 HXGE_DEBUG_MSG((hxgep, STR_CTL, "<== hxge_rtrace_ioctl")); 773 miocack(wq, mp, (int)size, 0); 774 } 775