1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_H 27 #define _SYS_HXGE_HXGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <hxge_vmac.h> 34 #include <hxge_pfc.h> 35 #include <hxge_classify.h> 36 37 /* 38 * HXGE diagnostics IOCTLS. 39 */ 40 #define HXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 41 42 #define HXGE_GET_TX_RING_SZ (HXGE_IOC|1) 43 #define HXGE_GET_TX_DESC (HXGE_IOC|2) 44 #define HXGE_GLOBAL_RESET (HXGE_IOC|3) 45 #define HXGE_TX_SIDE_RESET (HXGE_IOC|4) 46 #define HXGE_RX_SIDE_RESET (HXGE_IOC|5) 47 #define HXGE_RESET_MAC (HXGE_IOC|6) 48 #define HXGE_RTRACE (HXGE_IOC|7) 49 #define HXGE_GET_TCAM (HXGE_IOC|8) 50 #define HXGE_PUT_TCAM (HXGE_IOC|9) 51 52 #define HXGE_OK 0 53 #define HXGE_ERROR 0x40000000 54 #define HXGE_DDI_FAILED 0x20000000 55 56 /* 57 * Definitions for module_info. 58 */ 59 #define HXGE_DRIVER_NAME "hxge" /* module name */ 60 #define HXGE_CHECK_TIMER (5000) 61 62 typedef enum { 63 param_instance, 64 65 param_accept_jumbo, 66 param_rxdma_rbr_size, 67 param_rxdma_rcr_size, 68 param_rxdma_intr_time, 69 param_rxdma_intr_pkts, 70 param_vlan_ids, 71 param_implicit_vlan_id, 72 param_tcam_enable, 73 74 param_hash_init_value, 75 param_class_cfg_ether_usr1, 76 param_class_cfg_ether_usr2, 77 param_class_opt_ipv4_tcp, 78 param_class_opt_ipv4_udp, 79 param_class_opt_ipv4_ah, 80 param_class_opt_ipv4_sctp, 81 param_class_opt_ipv6_tcp, 82 param_class_opt_ipv6_udp, 83 param_class_opt_ipv6_ah, 84 param_class_opt_ipv6_sctp, 85 param_hxge_debug_flag, 86 param_hpi_debug_flag, 87 param_dump_ptrs, 88 param_end 89 } hxge_param_index_t; 90 91 92 #define HXGE_PARAM_READ 0x00000001ULL 93 #define HXGE_PARAM_WRITE 0x00000002ULL 94 #define HXGE_PARAM_SHARED 0x00000004ULL 95 #define HXGE_PARAM_PRIV 0x00000008ULL 96 #define HXGE_PARAM_RW HXGE_PARAM_READ | HXGE_PARAM_WRITE 97 #define HXGE_PARAM_RWS HXGE_PARAM_RW | HXGE_PARAM_SHARED 98 #define HXGE_PARAM_RWP HXGE_PARAM_RW | HXGE_PARAM_PRIV 99 100 #define HXGE_PARAM_RXDMA 0x00000010ULL 101 #define HXGE_PARAM_TXDMA 0x00000020ULL 102 #define HXGE_PARAM_MAC 0x00000040ULL 103 104 #define HXGE_PARAM_CMPLX 0x00010000ULL 105 #define HXGE_PARAM_NDD_WR_OK 0x00020000ULL 106 #define HXGE_PARAM_INIT_ONLY 0x00040000ULL 107 #define HXGE_PARAM_INIT_CONFIG 0x00080000ULL 108 109 #define HXGE_PARAM_READ_PROP 0x00100000ULL 110 #define HXGE_PARAM_PROP_ARR32 0x00200000ULL 111 #define HXGE_PARAM_PROP_ARR64 0x00400000ULL 112 #define HXGE_PARAM_PROP_STR 0x00800000ULL 113 114 #define HXGE_PARAM_DONT_SHOW 0x80000000ULL 115 116 #define HXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 117 #define HXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 118 #define HXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 119 #define HXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 120 121 typedef struct _hxge_param_t { 122 int (*getf)(); 123 int (*setf)(); /* null for read only */ 124 uint64_t type; /* R/W/ Common/Port/ .... */ 125 uint64_t minimum; 126 uint64_t maximum; 127 uint64_t value; /* for array params, pointer to value array */ 128 uint64_t old_value; /* for array params, pointer to old_value array */ 129 char *fcode_name; 130 char *name; 131 } hxge_param_t, *p_hxge_param_t; 132 133 134 typedef enum { 135 hxge_lb_normal, 136 hxge_lb_mac10g 137 } hxge_lb_t; 138 139 enum hxge_mac_state { 140 HXGE_MAC_STOPPED = 0, 141 HXGE_MAC_STARTED 142 }; 143 144 typedef struct _filter_t { 145 uint32_t all_phys_cnt; 146 uint32_t all_multicast_cnt; 147 uint32_t all_sap_cnt; 148 } filter_t, *p_filter_t; 149 150 typedef struct _hxge_port_stats_t { 151 hxge_lb_t lb_mode; 152 uint32_t poll_mode; 153 } hxge_port_stats_t, *p_hxge_port_stats_t; 154 155 156 typedef struct _hxge_peu_sys_stats { 157 uint32_t spc_acc_err; 158 uint32_t tdc_pioacc_err; 159 uint32_t rdc_pioacc_err; 160 uint32_t pfc_pioacc_err; 161 uint32_t vmac_pioacc_err; 162 uint32_t cpl_hdrq_parerr; 163 uint32_t cpl_dataq_parerr; 164 uint32_t retryram_xdlh_parerr; 165 uint32_t retrysotram_xdlh_parerr; 166 uint32_t p_hdrq_parerr; 167 uint32_t p_dataq_parerr; 168 uint32_t np_hdrq_parerr; 169 uint32_t np_dataq_parerr; 170 uint32_t eic_msix_parerr; 171 uint32_t hcr_parerr; 172 } hxge_peu_sys_stats_t, *p_hxge_peu_sys_stats_t; 173 174 175 typedef struct _hxge_stats_t { 176 /* 177 * Overall structure size 178 */ 179 size_t stats_size; 180 181 kstat_t *ksp; 182 kstat_t *rdc_ksp[HXGE_MAX_RDCS]; 183 kstat_t *tdc_ksp[HXGE_MAX_TDCS]; 184 kstat_t *rdc_sys_ksp; 185 kstat_t *tdc_sys_ksp; 186 kstat_t *pfc_ksp; 187 kstat_t *vmac_ksp; 188 kstat_t *port_ksp; 189 kstat_t *mmac_ksp; 190 kstat_t *peu_sys_ksp; 191 192 hxge_mac_stats_t mac_stats; 193 hxge_vmac_stats_t vmac_stats; /* VMAC Statistics */ 194 195 hxge_rx_ring_stats_t rdc_stats[HXGE_MAX_RDCS]; /* per rdc stats */ 196 hxge_rdc_sys_stats_t rdc_sys_stats; /* RDC system stats */ 197 198 hxge_tx_ring_stats_t tdc_stats[HXGE_MAX_TDCS]; /* per tdc stats */ 199 hxge_tdc_sys_stats_t tdc_sys_stats; /* TDC system stats */ 200 201 hxge_pfc_stats_t pfc_stats; /* pfc stats */ 202 hxge_port_stats_t port_stats; /* port stats */ 203 204 hxge_peu_sys_stats_t peu_sys_stats; /* PEU system stats */ 205 } hxge_stats_t, *p_hxge_stats_t; 206 207 typedef struct _hxge_intr_t { 208 boolean_t intr_registered; /* interrupts are registered */ 209 boolean_t intr_enabled; /* interrupts are enabled */ 210 boolean_t niu_msi_enable; /* debug or configurable? */ 211 uint8_t nldevs; /* # of logical devices */ 212 int intr_types; /* interrupt types supported */ 213 int intr_type; /* interrupt type to add */ 214 int msi_intx_cnt; /* # msi/intx ints returned */ 215 int intr_added; /* # ints actually needed */ 216 int intr_cap; /* interrupt capabilities */ 217 size_t intr_size; /* size of array to allocate */ 218 ddi_intr_handle_t *htable; /* For array of interrupts */ 219 /* Add interrupt number for each interrupt vector */ 220 int pri; 221 } hxge_intr_t, *p_hxge_intr_t; 222 223 typedef struct _hxge_ldgv_t { 224 uint8_t ndma_ldvs; 225 uint8_t nldvs; 226 uint8_t start_ldg; 227 uint8_t maxldgs; 228 uint8_t maxldvs; 229 uint8_t ldg_intrs; 230 uint32_t tmres; 231 p_hxge_ldg_t ldgp; 232 p_hxge_ldv_t ldvp; 233 p_hxge_ldv_t ldvp_syserr; 234 } hxge_ldgv_t, *p_hxge_ldgv_t; 235 236 typedef struct _hxge_timeout { 237 timeout_id_t id; 238 clock_t ticks; 239 kmutex_t lock; 240 uint32_t link_status; 241 boolean_t report_link_status; 242 } hxge_timeout; 243 244 typedef struct _hxge_addr { 245 boolean_t set; 246 boolean_t primary; 247 uint8_t addr[ETHERADDRL]; 248 } hxge_addr_t; 249 250 #define HXGE_MAX_MAC_ADDRS 16 251 252 typedef struct _hxge_mmac { 253 uint8_t total; 254 uint8_t available; 255 hxge_addr_t addrs[HXGE_MAX_MAC_ADDRS]; 256 } hxge_mmac_t; 257 258 /* 259 * Ring Group Strucuture. 260 */ 261 #define HXGE_MAX_RX_GROUPS 1 262 263 typedef struct _hxge_rx_ring_group_t { 264 mac_ring_type_t type; 265 mac_group_handle_t ghandle; 266 struct _hxge_t *hxgep; 267 int index; 268 boolean_t started; 269 } hxge_ring_group_t; 270 271 /* 272 * Ring Handle 273 */ 274 typedef struct _hxge_ring_handle_t { 275 struct _hxge_t *hxgep; 276 int index; /* port-wise */ 277 mac_ring_handle_t ring_handle; 278 boolean_t started; 279 } hxge_ring_handle_t; 280 281 typedef hxge_ring_handle_t *p_hxge_ring_handle_t; 282 283 /* 284 * Hydra Device instance state information. 285 * Each instance is dynamically allocated on first attach. 286 */ 287 struct _hxge_t { 288 dev_info_t *dip; /* device instance */ 289 dev_info_t *p_dip; /* Parent's device instance */ 290 int instance; /* instance number */ 291 uint32_t drv_state; /* driver state bit flags */ 292 uint64_t hxge_debug_level; /* driver state bit flags */ 293 kmutex_t genlock[1]; 294 enum hxge_mac_state hxge_mac_state; 295 296 p_dev_regs_t dev_regs; 297 hpi_handle_t hpi_handle; 298 hpi_handle_t hpi_pci_handle; 299 hpi_handle_t hpi_reg_handle; 300 hpi_handle_t hpi_msi_handle; 301 302 hxge_vmac_t vmac; 303 hxge_classify_t classifier; 304 305 mac_handle_t mach; /* mac module handle */ 306 307 p_hxge_stats_t statsp; 308 uint32_t param_count; 309 p_hxge_param_t param_arr; 310 hxge_hw_list_t *hxge_hw_p; /* pointer to per Hydra */ 311 uint8_t nrdc; 312 uint8_t rdc[HXGE_MAX_RDCS]; 313 boolean_t rdc_first_intr[HXGE_MAX_RDCS]; 314 uint8_t ntdc; 315 uint8_t tdc[HXGE_MAX_TDCS]; 316 317 hxge_ring_handle_t tx_ring_handles[HXGE_MAX_TDCS]; 318 hxge_ring_handle_t rx_ring_handles[HXGE_MAX_RDCS]; 319 hxge_ring_group_t rx_groups[HXGE_MAX_RX_GROUPS]; 320 321 hxge_intr_t hxge_intr_type; 322 hxge_dma_pt_cfg_t pt_config; 323 hxge_class_pt_cfg_t class_config; 324 325 /* Logical device and group data structures. */ 326 p_hxge_ldgv_t ldgvp; 327 328 caddr_t param_list; /* Parameter list */ 329 330 ether_addr_st factaddr; /* factory mac address */ 331 ether_addr_st ouraddr; /* individual address */ 332 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 333 hxge_mmac_t mmac; 334 335 ddi_iblock_cookie_t interrupt_cookie; 336 337 /* 338 * Blocks of memory may be pre-allocated by the 339 * partition manager or the driver. They may include 340 * blocks for configuration and buffers. The idea is 341 * to preallocate big blocks of contiguous areas in 342 * system memory (i.e. with IOMMU). These blocks then 343 * will be broken up to a fixed number of blocks with 344 * each block having the same block size (4K, 8K, 16K or 345 * 32K) in the case of buffer blocks. For systems that 346 * do not support DVMA, more than one big block will be 347 * allocated. 348 */ 349 uint32_t rx_default_block_size; 350 hxge_rx_block_size_t rx_bksize_code; 351 352 p_hxge_dma_pool_t rx_buf_pool_p; 353 p_hxge_dma_pool_t rx_rbr_cntl_pool_p; 354 p_hxge_dma_pool_t rx_rcr_cntl_pool_p; 355 p_hxge_dma_pool_t rx_mbox_cntl_pool_p; 356 357 p_hxge_dma_pool_t tx_buf_pool_p; 358 p_hxge_dma_pool_t tx_cntl_pool_p; 359 360 /* Receive buffer block ring and completion ring. */ 361 p_rx_rbr_rings_t rx_rbr_rings; 362 p_rx_rcr_rings_t rx_rcr_rings; 363 p_rx_mbox_areas_t rx_mbox_areas_p; 364 365 uint32_t start_rdc; 366 uint32_t max_rdcs; 367 368 /* Transmit descriptors rings */ 369 p_tx_rings_t tx_rings; 370 p_tx_mbox_areas_t tx_mbox_areas_p; 371 372 uint32_t start_tdc; 373 uint32_t max_tdcs; 374 uint32_t tdc_mask; 375 376 ddi_dma_handle_t dmasparehandle; 377 378 ulong_t sys_page_sz; 379 ulong_t sys_page_mask; 380 int suspended; 381 382 filter_t filter; /* Current instance filter */ 383 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 384 krwlock_t filter_lock; /* Lock to protect filters. */ 385 386 ulong_t sys_burst_sz; 387 timeout_id_t hxge_timerid; 388 uint8_t msg_min; 389 390 uint16_t intr_timeout; 391 uint16_t intr_threshold; 392 393 rtrace_t rtrace; 394 int fm_capabilities; /* FMA capabilities */ 395 396 uint32_t hxge_port_rbr_size; 397 uint32_t hxge_port_rcr_size; 398 uint32_t hxge_port_tx_ring_size; 399 400 kmutex_t pio_lock; 401 hxge_timeout timeout; 402 403 int msix_count; 404 int msix_index; 405 uint32_t msix_table[32][3]; 406 uint32_t msix_table_check[1][3]; 407 }; 408 409 /* 410 * Driver state flags. 411 */ 412 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 413 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 414 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 415 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 416 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 417 418 typedef struct _hxge_port_kstat_t { 419 /* 420 * Transciever state informations. 421 */ 422 kstat_named_t cap_autoneg; 423 kstat_named_t cap_10gfdx; 424 425 /* 426 * Link partner capabilities. 427 */ 428 kstat_named_t lp_cap_autoneg; 429 kstat_named_t lp_cap_10gfdx; 430 431 /* 432 * Shared link setup. 433 */ 434 kstat_named_t link_speed; 435 kstat_named_t link_duplex; 436 kstat_named_t link_up; 437 438 /* 439 * Lets the user know the MTU currently in use by 440 * the physical MAC port. 441 */ 442 kstat_named_t lb_mode; 443 444 kstat_named_t tx_max_pend; 445 kstat_named_t rx_jumbo_pkts; 446 447 /* 448 * Misc MAC statistics. 449 */ 450 kstat_named_t ifspeed; 451 kstat_named_t promisc; 452 } hxge_port_kstat_t, *p_hxge_port_kstat_t; 453 454 typedef struct _hxge_rdc_kstat { 455 /* 456 * Receive DMA channel statistics. 457 * This structure needs to be consistent with hxge_rdc_stat_index_t 458 * in hxge_kstat.c 459 */ 460 kstat_named_t ipackets; 461 kstat_named_t rbytes; 462 kstat_named_t errors; 463 kstat_named_t jumbo_pkts; 464 465 kstat_named_t rcr_unknown_err; 466 kstat_named_t rcr_sha_par_err; 467 kstat_named_t rbr_pre_par_err; 468 kstat_named_t rbr_pre_emty; 469 470 kstat_named_t rcr_shadow_full; 471 kstat_named_t rbr_tmout; 472 kstat_named_t peu_resp_err; 473 474 kstat_named_t ctrl_fifo_ecc_err; 475 kstat_named_t data_fifo_ecc_err; 476 477 kstat_named_t rcrfull; 478 kstat_named_t rbr_empty; 479 kstat_named_t rbr_empty_fail; 480 kstat_named_t rbr_empty_restore; 481 kstat_named_t rbrfull; 482 kstat_named_t rcr_invalids; /* Account for invalid RCR entries. */ 483 484 kstat_named_t rcr_to; 485 kstat_named_t rcr_thresh; 486 kstat_named_t pkt_drop; 487 } hxge_rdc_kstat_t, *p_hxge_rdc_kstat_t; 488 489 typedef struct _hxge_rdc_sys_kstat { 490 /* 491 * Receive DMA system statistics. 492 * This structure needs to be consistent with hxge_rdc_sys_stat_idx_t 493 * in hxge_kstat.c 494 */ 495 kstat_named_t ctrl_fifo_sec; 496 kstat_named_t ctrl_fifo_ded; 497 kstat_named_t data_fifo_sec; 498 kstat_named_t data_fifo_ded; 499 } hxge_rdc_sys_kstat_t, *p_hxge_rdc_sys_kstat_t; 500 501 typedef struct _hxge_tdc_kstat { 502 /* 503 * Transmit DMA channel statistics. 504 * This structure needs to be consistent with hxge_tdc_stats_index_t 505 * in hxge_kstat.c 506 */ 507 kstat_named_t opackets; 508 kstat_named_t obytes; 509 kstat_named_t obytes_with_pad; 510 kstat_named_t oerrors; 511 kstat_named_t tx_inits; 512 kstat_named_t tx_no_buf; 513 514 kstat_named_t peu_resp_err; 515 kstat_named_t pkt_size_err; 516 kstat_named_t tx_rng_oflow; 517 kstat_named_t pkt_size_hdr_err; 518 kstat_named_t runt_pkt_drop_err; 519 kstat_named_t pref_par_err; 520 kstat_named_t tdr_pref_cpl_to; 521 kstat_named_t pkt_cpl_to; 522 kstat_named_t invalid_sop; 523 kstat_named_t unexpected_sop; 524 525 kstat_named_t count_hdr_size_err; 526 kstat_named_t count_runt; 527 kstat_named_t count_abort; 528 529 kstat_named_t tx_starts; 530 kstat_named_t tx_no_desc; 531 kstat_named_t tx_dma_bind_fail; 532 kstat_named_t tx_hdr_pkts; 533 kstat_named_t tx_ddi_pkts; 534 kstat_named_t tx_jumbo_pkts; 535 kstat_named_t tx_max_pend; 536 kstat_named_t tx_marks; 537 } hxge_tdc_kstat_t, *p_hxge_tdc_kstat_t; 538 539 typedef struct _hxge_tdc_sys_kstat { 540 /* 541 * Transmit DMA system statistics. 542 * This structure needs to be consistent with hxge_tdc_sys_stat_idx_t 543 * in hxge_kstat.c 544 */ 545 kstat_named_t reord_tbl_par_err; 546 kstat_named_t reord_buf_ded_err; 547 kstat_named_t reord_buf_sec_err; 548 } hxge_tdc_sys_kstat_t, *p_hxge_tdc_sys_kstat_t; 549 550 typedef struct _hxge_vmac_kstat { 551 /* 552 * VMAC statistics. 553 * This structure needs to be consistent with hxge_vmac_stat_index_t 554 * in hxge_kstat.c 555 */ 556 kstat_named_t tx_frame_cnt; 557 kstat_named_t tx_byte_cnt; 558 559 kstat_named_t rx_frame_cnt; 560 kstat_named_t rx_byte_cnt; 561 kstat_named_t rx_drop_frame_cnt; 562 kstat_named_t rx_drop_byte_cnt; 563 kstat_named_t rx_crc_cnt; 564 kstat_named_t rx_pause_cnt; 565 kstat_named_t rx_bcast_fr_cnt; 566 kstat_named_t rx_mcast_fr_cnt; 567 } hxge_vmac_kstat_t, *p_hxge_vmac_kstat_t; 568 569 typedef struct _hxge_pfc_kstat { 570 /* 571 * This structure needs to be consistent with hxge_pfc_stat_index_t 572 * in hxge_kstat.c 573 */ 574 kstat_named_t pfc_pkt_drop; 575 kstat_named_t pfc_tcam_parity_err; 576 kstat_named_t pfc_vlan_parity_err; 577 kstat_named_t pfc_bad_cs_count; 578 kstat_named_t pfc_drop_count; 579 kstat_named_t pfc_tcp_ctrl_drop; 580 kstat_named_t pfc_l2_addr_drop; 581 kstat_named_t pfc_class_code_drop; 582 kstat_named_t pfc_tcam_drop; 583 kstat_named_t pfc_vlan_drop; 584 } hxge_pfc_kstat_t, *p_hxge_pfc_kstat_t; 585 586 typedef struct _hxge_mmac_kstat { 587 /* 588 * This structure needs to be consistent with hxge_mmac_stat_index_t 589 * in hxge_kstat.c 590 */ 591 kstat_named_t mmac_max_addr_cnt; 592 kstat_named_t mmac_avail_addr_cnt; 593 kstat_named_t mmac_addr1; 594 kstat_named_t mmac_addr2; 595 kstat_named_t mmac_addr3; 596 kstat_named_t mmac_addr4; 597 kstat_named_t mmac_addr5; 598 kstat_named_t mmac_addr6; 599 kstat_named_t mmac_addr7; 600 kstat_named_t mmac_addr8; 601 kstat_named_t mmac_addr9; 602 kstat_named_t mmac_addr10; 603 kstat_named_t mmac_addr11; 604 kstat_named_t mmac_addr12; 605 kstat_named_t mmac_addr13; 606 kstat_named_t mmac_addr14; 607 kstat_named_t mmac_addr15; 608 kstat_named_t mmac_addr16; 609 } hxge_mmac_kstat_t, *p_hxge_mmac_kstat_t; 610 611 typedef struct _hxge_peu_sys_kstat { 612 /* 613 * This structure needs to be consistent with hxge_peu_sys_stat_idx_t 614 * in hxge_kstat.c 615 */ 616 kstat_named_t spc_acc_err; 617 kstat_named_t tdc_pioacc_err; 618 kstat_named_t rdc_pioacc_err; 619 kstat_named_t pfc_pioacc_err; 620 kstat_named_t vmac_pioacc_err; 621 kstat_named_t cpl_hdrq_parerr; 622 kstat_named_t cpl_dataq_parerr; 623 kstat_named_t retryram_xdlh_parerr; 624 kstat_named_t retrysotram_xdlh_parerr; 625 kstat_named_t p_hdrq_parerr; 626 kstat_named_t p_dataq_parerr; 627 kstat_named_t np_hdrq_parerr; 628 kstat_named_t np_dataq_parerr; 629 kstat_named_t eic_msix_parerr; 630 kstat_named_t hcr_parerr; 631 } hxge_peu_sys_kstat_t, *p_hxge_peu_sys_kstat_t; 632 633 /* 634 * Prototype definitions. 635 */ 636 hxge_status_t hxge_init(p_hxge_t); 637 void hxge_uninit(p_hxge_t); 638 639 typedef void (*fptrv_t)(); 640 timeout_id_t hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec); 641 void hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid); 642 643 #ifdef __cplusplus 644 } 645 #endif 646 647 #endif /* _SYS_HXGE_HXGE_H */ 648