1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <hpi_vir.h> 29 #include <hxge_defs.h> 30 31 /* 32 * Set up a logical group number that a logical device belongs to. 33 */ 34 hpi_status_t 35 hpi_fzc_ldg_num_set(hpi_handle_t handle, uint8_t ld, uint8_t ldg) 36 { 37 ld_grp_ctrl_t gnum; 38 39 if (!LD_VALID(ld)) { 40 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 41 " hpi_fzc_ldg_num_set ld <0x%x>", ld)); 42 return (HPI_FAILURE | HPI_VIR_LD_INVALID(ld)); 43 } 44 45 if (!LDG_VALID(ldg)) { 46 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 47 " hpi_fzc_ldg_num_set ldg <0x%x>", ldg)); 48 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ld)); 49 } 50 51 gnum.value = 0; 52 gnum.bits.num = ldg; 53 54 HXGE_REG_WR32(handle, LD_GRP_CTRL + LD_NUM_OFFSET(ld), gnum.value); 55 56 return (HPI_SUCCESS); 57 } 58 59 /* 60 * Get device state vectors. 61 */ 62 hpi_status_t 63 hpi_ldsv_ldfs_get(hpi_handle_t handle, uint8_t ldg, uint32_t *vector0_p, 64 uint32_t *vector1_p) 65 { 66 int status; 67 68 if ((status = hpi_ldsv_get(handle, ldg, VECTOR0, vector0_p))) { 69 return (status); 70 } 71 if ((status = hpi_ldsv_get(handle, ldg, VECTOR1, vector1_p))) { 72 return (status); 73 } 74 75 return (HPI_SUCCESS); 76 } 77 78 /* 79 * Get device state vectors. 80 */ 81 hpi_status_t 82 hpi_ldsv_get(hpi_handle_t handle, uint8_t ldg, ldsv_type_t vector, 83 uint32_t *ldf_p) 84 { 85 uint32_t offset; 86 87 if (!LDG_VALID(ldg)) { 88 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 89 " hpi_ldsv_get Invalid Input ldg <0x%x>", ldg)); 90 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ldg)); 91 } 92 93 switch (vector) { 94 case VECTOR0: 95 offset = LDSV0 + LDSV_OFFSET(ldg); 96 break; 97 98 case VECTOR1: 99 offset = LDSV1 + LDSV_OFFSET(ldg); 100 break; 101 102 default: 103 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 104 " hpi_ldsv_get Invalid Input: ldsv type <0x%x>", vector)); 105 return (HPI_FAILURE | HPI_VIR_LDSV_INVALID(vector)); 106 } 107 108 HXGE_REG_RD32(handle, offset, ldf_p); 109 110 return (HPI_SUCCESS); 111 } 112 113 /* 114 * Set the mask bits for both ldf0 and ldf1. 115 */ 116 hpi_status_t 117 hpi_intr_mask_set(hpi_handle_t handle, uint8_t ld, uint8_t ldf_mask) 118 { 119 uint32_t offset; 120 121 if (!LD_VALID(ld)) { 122 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 123 " hpi_intr_mask_set ld", ld)); 124 return (HPI_FAILURE | HPI_VIR_LD_INVALID(ld)); 125 } 126 127 ldf_mask &= LD_IM_MASK; 128 offset = LDSV_OFFSET_MASK(ld); 129 130 HPI_DEBUG_MSG((handle.function, HPI_VIR_CTL, 131 "hpi_intr_mask_set: ld %d offset 0x%0x mask 0x%x", 132 ld, offset, ldf_mask)); 133 134 HXGE_REG_WR32(handle, offset, (uint32_t)ldf_mask); 135 136 return (HPI_SUCCESS); 137 } 138 139 /* 140 * Set interrupt timer and arm bit. 141 */ 142 hpi_status_t 143 hpi_intr_ldg_mgmt_set(hpi_handle_t handle, uint8_t ldg, boolean_t arm, 144 uint8_t timer) 145 { 146 ld_intr_mgmt_t mgm; 147 148 if (!LDG_VALID(ldg)) { 149 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 150 " hpi_intr_ldg_mgmt_set Invalid Input: ldg <0x%x>", ldg)); 151 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ldg)); 152 } 153 154 if (!LD_INTTIMER_VALID(timer)) { 155 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 156 " hpi_intr_ldg_mgmt_set Invalid Input" 157 " timer <0x%x>", timer)); 158 return (HPI_FAILURE | HPI_VIR_INTM_TM_INVALID(ldg)); 159 } 160 161 if (arm) { 162 mgm.bits.arm = 1; 163 } else { 164 HXGE_REG_RD32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), 165 &mgm.value); 166 } 167 168 mgm.bits.timer = timer; 169 HXGE_REG_WR32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), mgm.value); 170 171 HPI_DEBUG_MSG((handle.function, HPI_VIR_CTL, 172 " hpi_intr_ldg_mgmt_set: ldg %d reg offset 0x%x", 173 ldg, LD_INTR_MGMT + LDSV_OFFSET(ldg))); 174 175 return (HPI_SUCCESS); 176 } 177 178 /* 179 * Set the timer resolution. 180 */ 181 hpi_status_t 182 hpi_fzc_ldg_timer_res_set(hpi_handle_t handle, uint32_t res) 183 { 184 ld_intr_tim_res_t tm; 185 186 if (res > LDGTITMRES_RES_MASK) { 187 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 188 " hpi_fzc_ldg_timer_res_set Invalid Input: res <0x%x>", 189 res)); 190 return (HPI_FAILURE | HPI_VIR_TM_RES_INVALID); 191 } 192 193 tm.value = 0; 194 tm.bits.res = res; 195 196 HXGE_REG_WR32(handle, LD_INTR_TIM_RES, tm.value); 197 198 return (HPI_SUCCESS); 199 } 200 201 /* 202 * Set the system interrupt data. 203 */ 204 hpi_status_t 205 hpi_fzc_sid_set(hpi_handle_t handle, fzc_sid_t sid) 206 { 207 sid_t sd; 208 209 if (!LDG_VALID(sid.ldg)) { 210 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 211 " hpi_fzc_sid_set Invalid Input: ldg <0x%x>", sid.ldg)); 212 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(sid.ldg)); 213 } 214 215 if (!SID_VECTOR_VALID(sid.vector)) { 216 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 217 " hpi_fzc_sid_set Invalid Input: vector <0x%x>", 218 sid.vector)); 219 220 return (HPI_FAILURE | HPI_VIR_SID_VEC_INVALID(sid.vector)); 221 } 222 223 sd.value = 0; 224 sd.bits.data = sid.vector; 225 HXGE_REG_WR32(handle, SID + LDG_SID_OFFSET(sid.ldg), sd.value); 226 227 return (HPI_SUCCESS); 228 } 229 230 /* 231 * Mask/Unmask the device error mask bits. 232 */ 233 hpi_status_t 234 hpi_fzc_sys_err_mask_set(hpi_handle_t handle, boolean_t mask) 235 { 236 dev_err_mask_t dev_mask; 237 238 dev_mask.value = 0; 239 if (mask) { 240 dev_mask.bits.tdc_mask0 = 1; 241 dev_mask.bits.rdc_mask0 = 1; 242 dev_mask.bits.vnm_pio_mask1 = 1; 243 dev_mask.bits.tdc_mask1 = 1; 244 dev_mask.bits.rdc_mask1 = 1; 245 dev_mask.bits.peu_mask1 = 1; 246 } 247 248 HXGE_REG_WR32(handle, DEV_ERR_MASK, dev_mask.value); 249 return (HPI_SUCCESS); 250 } 251 252 /* 253 * Get the system error stats. 254 */ 255 hpi_status_t 256 hpi_fzc_sys_err_stat_get(hpi_handle_t handle, dev_err_stat_t *statp) 257 { 258 HXGE_REG_RD32(handle, DEV_ERR_STAT, &statp->value); 259 return (HPI_SUCCESS); 260 } 261