1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * ********************************************************************** 37 * Module Name: * 38 * e1000g_sw.h * 39 * * 40 * Abstract: * 41 * This header file contains Software-related data structures * 42 * definitions. * 43 * * 44 * ********************************************************************** 45 */ 46 47 #include <sys/types.h> 48 #include <sys/conf.h> 49 #include <sys/debug.h> 50 #include <sys/stropts.h> 51 #include <sys/stream.h> 52 #include <sys/strsun.h> 53 #include <sys/strlog.h> 54 #include <sys/kmem.h> 55 #include <sys/stat.h> 56 #include <sys/kstat.h> 57 #include <sys/modctl.h> 58 #include <sys/errno.h> 59 #include <sys/mac.h> 60 #include <sys/mac_ether.h> 61 #include <sys/vlan.h> 62 #include <sys/ddi.h> 63 #include <sys/sunddi.h> 64 #include <sys/disp.h> 65 #include <sys/pci.h> 66 #include <sys/sdt.h> 67 #include <sys/ethernet.h> 68 #include <sys/pattr.h> 69 #include <sys/strsubr.h> 70 #include <sys/netlb.h> 71 #include <inet/common.h> 72 #include <inet/ip.h> 73 #include <inet/mi.h> 74 #include <inet/nd.h> 75 #include <sys/ddifm.h> 76 #include <sys/fm/protocol.h> 77 #include <sys/fm/util.h> 78 #include <sys/fm/io/ddi.h> 79 #include "e1000_api.h" 80 81 82 #define JUMBO_FRAG_LENGTH 4096 83 84 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 85 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 86 #define MAX_NUM_MULTICAST_ADDRESSES 256 87 88 #define MAX_TX_DESC_PER_PACKET 16 89 90 /* 91 * constants used in setting flow control thresholds 92 */ 93 #define E1000_PBA_MASK 0xffff 94 #define E1000_PBA_SHIFT 10 95 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 96 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 97 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 98 99 #define MAX_NUM_TX_DESCRIPTOR 4096 100 #define MAX_NUM_RX_DESCRIPTOR 4096 101 #define MAX_NUM_RX_FREELIST 4096 102 #define MAX_NUM_TX_FREELIST 4096 103 #define MAX_RX_LIMIT_ON_INTR 4096 104 #define MAX_RX_INTR_DELAY 65535 105 #define MAX_RX_INTR_ABS_DELAY 65535 106 #define MAX_TX_INTR_DELAY 65535 107 #define MAX_TX_INTR_ABS_DELAY 65535 108 #define MAX_INTR_THROTTLING 65535 109 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 110 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 111 #define MAX_TX_RECYCLE_THRESHOLD MAX_NUM_TX_DESCRIPTOR 112 #define MAX_TX_RECYCLE_NUM MAX_NUM_TX_DESCRIPTOR 113 114 #define MIN_NUM_TX_DESCRIPTOR 80 115 #define MIN_NUM_RX_DESCRIPTOR 80 116 #define MIN_NUM_RX_FREELIST 64 117 #define MIN_NUM_TX_FREELIST 80 118 #define MIN_RX_LIMIT_ON_INTR 16 119 #define MIN_RX_INTR_DELAY 0 120 #define MIN_RX_INTR_ABS_DELAY 0 121 #define MIN_TX_INTR_DELAY 0 122 #define MIN_TX_INTR_ABS_DELAY 0 123 #define MIN_INTR_THROTTLING 0 124 #define MIN_RX_BCOPY_THRESHOLD 0 125 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 126 #define MIN_TX_RECYCLE_THRESHOLD 0 127 #define MIN_TX_RECYCLE_NUM MAX_TX_DESC_PER_PACKET 128 129 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 130 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 131 #define DEFAULT_NUM_RX_FREELIST 4096 132 #define DEFAULT_NUM_TX_FREELIST 2304 133 #define DEFAULT_RX_LIMIT_ON_INTR 128 134 135 #ifdef __sparc 136 #define MAX_INTR_PER_SEC 7100 137 #define MIN_INTR_PER_SEC 3000 138 #define DEFAULT_INTR_PACKET_LOW 5 139 #define DEFAULT_INTR_PACKET_HIGH 128 140 #define DEFAULT_TX_RECYCLE_THRESHOLD 512 141 #else 142 #define MAX_INTR_PER_SEC 15000 143 #define MIN_INTR_PER_SEC 4000 144 #define DEFAULT_INTR_PACKET_LOW 10 145 #define DEFAULT_INTR_PACKET_HIGH 48 146 #define DEFAULT_TX_RECYCLE_THRESHOLD DEFAULT_TX_NO_RESOURCE 147 #endif 148 149 #define DEFAULT_RX_INTR_DELAY 0 150 #define DEFAULT_RX_INTR_ABS_DELAY 64 151 #define DEFAULT_TX_INTR_DELAY 64 152 #define DEFAULT_TX_INTR_ABS_DELAY 64 153 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 154 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 155 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 156 157 #define DEFAULT_RX_BCOPY_THRESHOLD 128 158 #define DEFAULT_TX_BCOPY_THRESHOLD 512 159 #define DEFAULT_TX_RECYCLE_NUM 64 160 #define DEFAULT_TX_UPDATE_THRESHOLD 256 161 #define DEFAULT_TX_NO_RESOURCE 6 162 163 #define DEFAULT_TX_INTR_ENABLE 1 164 #define DEFAULT_FLOW_CONTROL 3 165 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 166 /* which is normally 0x040 */ 167 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 168 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 169 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 170 171 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 172 173 /* 174 * The size of the receive/transmite buffers 175 */ 176 #define E1000_RX_BUFFER_SIZE_2K (2048) 177 #define E1000_RX_BUFFER_SIZE_4K (4096) 178 #define E1000_RX_BUFFER_SIZE_8K (8192) 179 #define E1000_RX_BUFFER_SIZE_16K (16384) 180 181 #define E1000_TX_BUFFER_SIZE_2K (2048) 182 #define E1000_TX_BUFFER_SIZE_4K (4096) 183 #define E1000_TX_BUFFER_SIZE_8K (8192) 184 #define E1000_TX_BUFFER_SIZE_16K (16384) 185 186 #define FORCE_BCOPY_EXCEED_FRAGS 0x1 187 #define FORCE_BCOPY_UNDER_SIZE 0x2 188 189 #define E1000G_RX_SW_FREE 0x0 190 #define E1000G_RX_SW_SENDUP 0x1 191 #define E1000G_RX_SW_STOP 0x2 192 #define E1000G_RX_SW_DETACH 0x3 193 194 /* 195 * definitions for smartspeed workaround 196 */ 197 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 198 /* or 30 seconds */ 199 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 200 /* or 6 seconds */ 201 202 /* 203 * Definitions for module_info. 204 */ 205 #define WSNAME "e1000g" /* module name */ 206 207 /* 208 * Defined for IP header alignment. We also need to preserve space for 209 * VLAN tag (4 bytes) 210 */ 211 #define E1000G_IPALIGNROOM 6 212 #define E1000G_IPALIGNPRESERVEROOM 64 213 214 /* 215 * bit flags for 'attach_progress' which is a member variable in struct e1000g 216 */ 217 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 218 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 219 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 220 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 221 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 222 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 223 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 224 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 225 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 226 #define ATTACH_PROGRESS_NDD 0x0200 /* NDD initialized */ 227 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 228 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 229 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 230 231 /* 232 * Speed and Duplex Settings 233 */ 234 #define GDIAG_10_HALF 1 235 #define GDIAG_10_FULL 2 236 #define GDIAG_100_HALF 3 237 #define GDIAG_100_FULL 4 238 #define GDIAG_1000_FULL 6 239 #define GDIAG_ANY 7 240 241 /* 242 * Coexist Workaround RP: 07/04/03 243 * 82544 Workaround : Co-existence 244 */ 245 #define MAX_TX_BUF_SIZE (8 * 1024) 246 247 #define ROUNDOFF 0x1000 248 249 /* 250 * Defines for Jumbo Frame 251 */ 252 #define FRAME_SIZE_UPTO_2K 2048 253 #define FRAME_SIZE_UPTO_4K 4096 254 #define FRAME_SIZE_UPTO_8K 8192 255 #define FRAME_SIZE_UPTO_16K 16384 256 #define FRAME_SIZE_UPTO_9K 9234 257 258 #define MAXIMUM_MTU 9000 259 #define DEFAULT_MTU ETHERMTU 260 261 #define DEFAULT_FRAME_SIZE \ 262 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 263 #define MAXIMUM_FRAME_SIZE \ 264 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 265 266 /* Defines for Tx stall check */ 267 #define E1000G_STALL_WATCHDOG_COUNT 8 268 269 #define MAX_TX_LINK_DOWN_TIMEOUT 8 270 271 /* Defines for DVMA */ 272 #ifdef __sparc 273 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 274 #endif 275 276 /* 277 * Loopback definitions 278 */ 279 #define E1000G_LB_NONE 0 280 #define E1000G_LB_EXTERNAL_1000 1 281 #define E1000G_LB_EXTERNAL_100 2 282 #define E1000G_LB_EXTERNAL_10 3 283 #define E1000G_LB_INTERNAL_PHY 4 284 285 /* 286 * Private dip list definitions 287 */ 288 #define E1000G_PRIV_DEVI_ATTACH 0x0 289 #define E1000G_PRIV_DEVI_DETACH 0x1 290 291 /* 292 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 293 */ 294 #define QUEUE_INIT_LIST(_LH) \ 295 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 296 297 /* 298 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 299 */ 300 #define IS_QUEUE_EMPTY(_LH) \ 301 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 302 303 /* 304 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 305 * not remove the head from the queue. 306 */ 307 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 308 309 /* 310 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 311 */ 312 #define QUEUE_REMOVE_HEAD(_LH) \ 313 { \ 314 PSINGLE_LIST_LINK ListElem; \ 315 if (ListElem = (_LH)->Flink) \ 316 { \ 317 if (!((_LH)->Flink = ListElem->Flink)) \ 318 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 319 } \ 320 } 321 322 /* 323 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 324 * and return it (this differs from QUEUE_REMOVE_HEAD only in 325 * the 1st line). 326 */ 327 #define QUEUE_POP_HEAD(_LH) \ 328 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 329 { \ 330 PSINGLE_LIST_LINK ListElem; \ 331 ListElem = (_LH)->Flink; \ 332 if (ListElem) \ 333 { \ 334 (_LH)->Flink = ListElem->Flink; \ 335 if (!(_LH)->Flink) \ 336 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 337 } \ 338 } 339 340 /* 341 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 342 * remove the tail from the queue. 343 */ 344 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 345 346 /* 347 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 348 */ 349 #define QUEUE_PUSH_TAIL(_LH, _E) \ 350 if ((_LH)->Blink) \ 351 { \ 352 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 353 (PSINGLE_LIST_LINK)(_E); \ 354 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 355 } else { \ 356 (_LH)->Flink = \ 357 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 358 } \ 359 (_E)->Flink = (PSINGLE_LIST_LINK)0; 360 361 /* 362 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 363 */ 364 #define QUEUE_PUSH_HEAD(_LH, _E) \ 365 if (!((_E)->Flink = (_LH)->Flink)) \ 366 { \ 367 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 368 } \ 369 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 370 371 /* 372 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 373 * current element. 374 */ 375 #define QUEUE_GET_NEXT(_LH, _E) \ 376 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 377 (0) : ((_E)->Flink)) 378 379 /* 380 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 381 */ 382 #define QUEUE_APPEND(_LH1, _LH2) \ 383 if ((_LH2)->Flink) { \ 384 if ((_LH1)->Flink) { \ 385 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 386 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 387 } else { \ 388 (_LH1)->Flink = \ 389 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 390 } \ 391 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 392 } 393 394 /* 395 * Property lookups 396 */ 397 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 398 DDI_PROP_DONTPASS, (n)) 399 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 400 DDI_PROP_DONTPASS, (n), -1) 401 402 /* 403 * Shorthand for the NDD parameters 404 */ 405 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].ndp_val 406 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].ndp_val 407 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].ndp_val 408 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].ndp_val 409 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].ndp_val 410 #define param_100t4_cap nd_params[PARAM_100T4_CAP].ndp_val 411 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].ndp_val 412 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].ndp_val 413 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].ndp_val 414 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].ndp_val 415 416 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 417 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 418 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 419 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 420 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 421 #define param_adv_100t4 nd_params[PARAM_ADV_100T4_CAP].ndp_val 422 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 423 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 424 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 425 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 426 427 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 428 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 429 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 430 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 431 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 432 #define param_lp_100t4 nd_params[PARAM_LP_100T4_CAP].ndp_val 433 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 434 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 435 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 436 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 437 438 #ifdef E1000G_DEBUG 439 /* 440 * E1000G-specific ioctls ... 441 */ 442 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 443 + 'K') << 4) + 'G') << 4) 444 445 /* 446 * These diagnostic IOCTLS are enabled only in DEBUG drivers 447 */ 448 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 449 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 450 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 451 452 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 453 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 454 455 typedef struct { 456 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 457 uint64_t pp_acc_space; /* See #defines below */ 458 uint64_t pp_acc_offset; /* See regs definition */ 459 uint64_t pp_acc_data; /* output for peek */ 460 /* input for poke */ 461 } e1000g_peekpoke_t; 462 #endif /* E1000G_DEBUG */ 463 464 /* 465 * (Internal) return values from ioctl subroutines 466 */ 467 enum ioc_reply { 468 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 469 IOC_DONE, /* OK, reply sent */ 470 IOC_ACK, /* OK, just send ACK */ 471 IOC_REPLY /* OK, just send reply */ 472 }; 473 474 /* 475 * Named Data (ND) Parameter Management Structure 476 */ 477 typedef struct { 478 uint32_t ndp_info; 479 uint32_t ndp_min; 480 uint32_t ndp_max; 481 uint32_t ndp_val; 482 struct e1000g *ndp_instance; 483 char *ndp_name; 484 } nd_param_t; 485 486 /* 487 * NDD parameter indexes, divided into: 488 * 489 * read-only parameters describing the hardware's capabilities 490 * read-write parameters controlling the advertised capabilities 491 * read-only parameters describing the partner's capabilities 492 * read-write parameters controlling the force speed and duplex 493 * read-only parameters describing the link state 494 * read-only parameters describing the driver properties 495 * read-write parameters controlling the driver properties 496 */ 497 enum { 498 PARAM_AUTONEG_CAP, 499 PARAM_PAUSE_CAP, 500 PARAM_ASYM_PAUSE_CAP, 501 PARAM_1000FDX_CAP, 502 PARAM_1000HDX_CAP, 503 PARAM_100T4_CAP, 504 PARAM_100FDX_CAP, 505 PARAM_100HDX_CAP, 506 PARAM_10FDX_CAP, 507 PARAM_10HDX_CAP, 508 509 PARAM_ADV_AUTONEG_CAP, 510 PARAM_ADV_PAUSE_CAP, 511 PARAM_ADV_ASYM_PAUSE_CAP, 512 PARAM_ADV_1000FDX_CAP, 513 PARAM_ADV_1000HDX_CAP, 514 PARAM_ADV_100T4_CAP, 515 PARAM_ADV_100FDX_CAP, 516 PARAM_ADV_100HDX_CAP, 517 PARAM_ADV_10FDX_CAP, 518 PARAM_ADV_10HDX_CAP, 519 520 PARAM_LP_AUTONEG_CAP, 521 PARAM_LP_PAUSE_CAP, 522 PARAM_LP_ASYM_PAUSE_CAP, 523 PARAM_LP_1000FDX_CAP, 524 PARAM_LP_1000HDX_CAP, 525 PARAM_LP_100T4_CAP, 526 PARAM_LP_100FDX_CAP, 527 PARAM_LP_100HDX_CAP, 528 PARAM_LP_10FDX_CAP, 529 PARAM_LP_10HDX_CAP, 530 531 PARAM_LINK_STATUS, 532 PARAM_LINK_SPEED, 533 PARAM_LINK_DUPLEX, 534 PARAM_LINK_AUTONEG, 535 536 PARAM_MAX_FRAME_SIZE, 537 PARAM_LOOP_MODE, 538 PARAM_INTR_TYPE, 539 540 PARAM_TX_BCOPY_THRESHOLD, 541 PARAM_TX_INTR_ENABLE, 542 PARAM_TX_TIDV, 543 PARAM_TX_TADV, 544 PARAM_RX_BCOPY_THRESHOLD, 545 PARAM_RX_PKT_ON_INTR, 546 PARAM_RX_RDTR, 547 PARAM_RX_RADV, 548 549 PARAM_COUNT 550 }; 551 552 /* 553 * The entry of the private dip list 554 */ 555 typedef struct _private_devi_list { 556 dev_info_t *priv_dip; 557 uint16_t flag; 558 struct _private_devi_list *next; 559 } private_devi_list_t; 560 561 /* 562 * A structure that points to the next entry in the queue. 563 */ 564 typedef struct _SINGLE_LIST_LINK { 565 struct _SINGLE_LIST_LINK *Flink; 566 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 567 568 /* 569 * A "ListHead" structure that points to the head and tail of a queue 570 */ 571 typedef struct _LIST_DESCRIBER { 572 struct _SINGLE_LIST_LINK *volatile Flink; 573 struct _SINGLE_LIST_LINK *volatile Blink; 574 } LIST_DESCRIBER, *PLIST_DESCRIBER; 575 576 /* 577 * Address-Length pair structure that stores descriptor info 578 */ 579 typedef struct _sw_desc { 580 uint64_t address; 581 uint32_t length; 582 } sw_desc_t, *p_sw_desc_t; 583 584 typedef struct _desc_array { 585 sw_desc_t descriptor[4]; 586 uint32_t elements; 587 } desc_array_t, *p_desc_array_t; 588 589 typedef enum { 590 USE_NONE, 591 USE_BCOPY, 592 USE_DVMA, 593 USE_DMA 594 } dma_type_t; 595 596 typedef enum { 597 E1000G_STOP, 598 E1000G_START, 599 E1000G_ERROR 600 } chip_state_t; 601 602 typedef struct _dma_buffer { 603 caddr_t address; 604 uint64_t dma_address; 605 ddi_acc_handle_t acc_handle; 606 ddi_dma_handle_t dma_handle; 607 size_t size; 608 size_t len; 609 } dma_buffer_t, *p_dma_buffer_t; 610 611 /* 612 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 613 * structure stores the additional information that is 614 * associated with every packet to be transmitted. It stores the 615 * message block pointer and the TBD addresses associated with 616 * the m_blk and also the link to the next tcb in the chain 617 */ 618 typedef struct _tx_sw_packet { 619 /* Link to the next tx_sw_packet in the list */ 620 SINGLE_LIST_LINK Link; 621 mblk_t *mp; 622 uint32_t num_desc; 623 uint32_t num_mblk_frag; 624 dma_type_t dma_type; 625 dma_type_t data_transfer_type; 626 ddi_dma_handle_t tx_dma_handle; 627 dma_buffer_t tx_buf[1]; 628 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 629 } tx_sw_packet_t, *p_tx_sw_packet_t; 630 631 /* 632 * This structure is similar to the rx_sw_packet structure used 633 * for Ndis. This structure stores information about the 2k 634 * aligned receive buffer into which the FX1000 DMA's frames. 635 * This structure is maintained as a linked list of many 636 * receiver buffer pointers. 637 */ 638 typedef struct _rx_sw_packet { 639 /* Link to the next rx_sw_packet_t in the list */ 640 SINGLE_LIST_LINK Link; 641 struct _rx_sw_packet *next; 642 uint16_t flag; 643 mblk_t *mp; 644 caddr_t rx_ring; 645 dma_type_t dma_type; 646 frtn_t free_rtn; 647 dma_buffer_t rx_buf[1]; 648 } rx_sw_packet_t, *p_rx_sw_packet_t; 649 650 typedef struct _mblk_list { 651 mblk_t *head; 652 mblk_t *tail; 653 } mblk_list_t, *p_mblk_list_t; 654 655 typedef struct _cksum_data { 656 uint32_t ether_header_size; 657 uint32_t cksum_flags; 658 uint32_t cksum_start; 659 uint32_t cksum_stuff; 660 } cksum_data_t; 661 662 typedef union _e1000g_ether_addr { 663 struct { 664 uint32_t high; 665 uint32_t low; 666 } reg; 667 struct { 668 uint8_t set; 669 uint8_t redundant; 670 uint8_t addr[ETHERADDRL]; 671 } mac; 672 } e1000g_ether_addr_t; 673 674 typedef struct _e1000g_stat { 675 676 kstat_named_t link_speed; /* Link Speed */ 677 kstat_named_t reset_count; /* Reset Count */ 678 679 kstat_named_t rx_error; /* Rx Error in Packet */ 680 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 681 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 682 683 kstat_named_t tx_no_desc; /* Tx No Desc */ 684 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 685 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 686 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 687 kstat_named_t tx_reschedule; /* Tx Reschedule */ 688 689 #ifdef E1000G_DEBUG 690 kstat_named_t rx_none; /* Rx No Incoming Data */ 691 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 692 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 693 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 694 695 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 696 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 697 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 698 kstat_named_t tx_recycle; /* Tx Recycle */ 699 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 700 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 701 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 702 kstat_named_t tx_copy; /* Tx Send Copy */ 703 kstat_named_t tx_bind; /* Tx Send Bind */ 704 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 705 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 706 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 707 #endif 708 709 kstat_named_t Crcerrs; /* CRC Error Count */ 710 kstat_named_t Symerrs; /* Symbol Error Count */ 711 kstat_named_t Mpc; /* Missed Packet Count */ 712 kstat_named_t Scc; /* Single Collision Count */ 713 kstat_named_t Ecol; /* Excessive Collision Count */ 714 kstat_named_t Mcc; /* Multiple Collision Count */ 715 kstat_named_t Latecol; /* Late Collision Count */ 716 kstat_named_t Colc; /* Collision Count */ 717 kstat_named_t Dc; /* Defer Count */ 718 kstat_named_t Sec; /* Sequence Error Count */ 719 kstat_named_t Rlec; /* Receive Length Error Count */ 720 kstat_named_t Xonrxc; /* XON Received Count */ 721 kstat_named_t Xontxc; /* XON Xmitted Count */ 722 kstat_named_t Xoffrxc; /* XOFF Received Count */ 723 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 724 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 725 #ifdef E1000G_DEBUG 726 kstat_named_t Prc64; /* Packets Received - 64b */ 727 kstat_named_t Prc127; /* Packets Received - 65-127b */ 728 kstat_named_t Prc255; /* Packets Received - 127-255b */ 729 kstat_named_t Prc511; /* Packets Received - 256-511b */ 730 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 731 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 732 #endif 733 kstat_named_t Gprc; /* Good Packets Received Count */ 734 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 735 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 736 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 737 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 738 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 739 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 740 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 741 kstat_named_t Rnbc; /* Receive No Buffers Count */ 742 kstat_named_t Ruc; /* Receive Undersize Count */ 743 kstat_named_t Rfc; /* Receive Frag Count */ 744 kstat_named_t Roc; /* Receive Oversize Count */ 745 kstat_named_t Rjc; /* Receive Jabber Count */ 746 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 747 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 748 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 749 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 750 kstat_named_t Tpr; /* Total Packets Received */ 751 kstat_named_t Tpt; /* Total Packets Xmitted */ 752 #ifdef E1000G_DEBUG 753 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 754 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 755 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 756 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 757 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 758 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 759 #endif 760 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 761 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 762 kstat_named_t Algnerrc; /* Alignment Error count */ 763 kstat_named_t Tuc; /* Transmit Underrun count */ 764 kstat_named_t Rxerrc; /* Rx Error Count */ 765 kstat_named_t Tncrs; /* Transmit with no CRS */ 766 kstat_named_t Cexterr; /* Carrier Extension Error count */ 767 kstat_named_t Rutec; /* Receive DMA too Early count */ 768 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 769 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 770 } e1000g_stat_t, *p_e1000g_stat_t; 771 772 typedef struct _e1000g_tx_ring { 773 kmutex_t tx_lock; 774 kmutex_t freelist_lock; 775 kmutex_t usedlist_lock; 776 /* 777 * Descriptor queue definitions 778 */ 779 ddi_dma_handle_t tbd_dma_handle; 780 ddi_acc_handle_t tbd_acc_handle; 781 struct e1000_tx_desc *tbd_area; 782 uint64_t tbd_dma_addr; 783 struct e1000_tx_desc *tbd_first; 784 struct e1000_tx_desc *tbd_last; 785 struct e1000_tx_desc *tbd_oldest; 786 struct e1000_tx_desc *tbd_next; 787 uint32_t tbd_avail; 788 /* 789 * Software packet structures definitions 790 */ 791 p_tx_sw_packet_t packet_area; 792 LIST_DESCRIBER used_list; 793 LIST_DESCRIBER free_list; 794 /* 795 * TCP/UDP checksum offload 796 */ 797 cksum_data_t cksum_data; 798 /* 799 * Timer definitions for 82547 800 */ 801 timeout_id_t timer_id_82547; 802 boolean_t timer_enable_82547; 803 /* 804 * reschedule when tx resource is available 805 */ 806 boolean_t resched_needed; 807 uint32_t frags_limit; 808 uint32_t stall_watchdog; 809 uint32_t recycle_fail; 810 mblk_list_t mblks; 811 /* 812 * Statistics 813 */ 814 uint32_t stat_no_swpkt; 815 uint32_t stat_no_desc; 816 uint32_t stat_send_fail; 817 uint32_t stat_reschedule; 818 uint32_t stat_over_size; 819 #ifdef E1000G_DEBUG 820 uint32_t stat_under_size; 821 uint32_t stat_exceed_frags; 822 uint32_t stat_empty_frags; 823 uint32_t stat_recycle; 824 uint32_t stat_recycle_intr; 825 uint32_t stat_recycle_retry; 826 uint32_t stat_recycle_none; 827 uint32_t stat_copy; 828 uint32_t stat_bind; 829 uint32_t stat_multi_copy; 830 uint32_t stat_multi_cookie; 831 uint32_t stat_lack_desc; 832 #endif 833 /* 834 * Pointer to the adapter 835 */ 836 struct e1000g *adapter; 837 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 838 839 typedef struct _e1000g_rx_ring { 840 kmutex_t rx_lock; 841 kmutex_t freelist_lock; 842 /* 843 * Descriptor queue definitions 844 */ 845 ddi_dma_handle_t rbd_dma_handle; 846 ddi_acc_handle_t rbd_acc_handle; 847 struct e1000_rx_desc *rbd_area; 848 uint64_t rbd_dma_addr; 849 struct e1000_rx_desc *rbd_first; 850 struct e1000_rx_desc *rbd_last; 851 struct e1000_rx_desc *rbd_next; 852 /* 853 * Software packet structures definitions 854 */ 855 p_rx_sw_packet_t packet_area; 856 LIST_DESCRIBER recv_list; 857 LIST_DESCRIBER free_list; 858 859 p_rx_sw_packet_t pending_list; 860 uint32_t pending_count; 861 uint32_t avail_freepkt; 862 uint32_t rx_mblk_len; 863 mblk_t *rx_mblk; 864 mblk_t *rx_mblk_tail; 865 /* 866 * Statistics 867 */ 868 uint32_t stat_error; 869 uint32_t stat_esballoc_fail; 870 uint32_t stat_allocb_fail; 871 uint32_t stat_exceed_pkt; 872 #ifdef E1000G_DEBUG 873 uint32_t stat_none; 874 uint32_t stat_multi_desc; 875 uint32_t stat_no_freepkt; 876 #endif 877 /* 878 * Pointer to the adapter 879 */ 880 struct e1000g *adapter; 881 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 882 883 typedef struct e1000g { 884 int instance; 885 dev_info_t *dip; 886 dev_info_t *priv_dip; 887 mac_handle_t mh; 888 mac_resource_handle_t mrh; 889 struct e1000_hw shared; 890 struct e1000g_osdep osdep; 891 892 chip_state_t chip_state; 893 boolean_t e1000g_promisc; 894 boolean_t strip_crc; 895 boolean_t rx_buffer_setup; 896 link_state_t link_state; 897 uint32_t link_speed; 898 uint32_t link_duplex; 899 uint32_t master_latency_timer; 900 uint32_t smartspeed; /* smartspeed w/a counter */ 901 uint32_t init_count; 902 uint32_t reset_count; 903 uint32_t attach_progress; /* attach tracking */ 904 uint32_t loopback_mode; 905 906 uint32_t tx_desc_num; 907 uint32_t tx_freelist_num; 908 uint32_t rx_desc_num; 909 uint32_t rx_freelist_num; 910 uint32_t tx_buffer_size; 911 uint32_t rx_buffer_size; 912 913 uint32_t tx_link_down_timeout; 914 uint32_t tx_bcopy_thresh; 915 uint32_t rx_limit_onintr; 916 uint32_t rx_bcopy_thresh; 917 #ifndef NO_82542_SUPPORT 918 uint32_t rx_buf_align; 919 #endif 920 921 boolean_t intr_adaptive; 922 boolean_t tx_intr_enable; 923 uint32_t tx_recycle_thresh; 924 uint32_t tx_recycle_num; 925 uint32_t tx_intr_delay; 926 uint32_t tx_intr_abs_delay; 927 uint32_t rx_intr_delay; 928 uint32_t rx_intr_abs_delay; 929 uint32_t intr_throttling_rate; 930 931 uint32_t default_mtu; 932 933 boolean_t watchdog_timer_enabled; 934 boolean_t watchdog_timer_started; 935 timeout_id_t watchdog_tid; 936 boolean_t link_complete; 937 timeout_id_t link_tid; 938 939 e1000g_rx_ring_t rx_ring[1]; 940 e1000g_tx_ring_t tx_ring[1]; 941 942 /* 943 * Rx and Tx packet count for interrupt adaptive setting 944 */ 945 uint32_t rx_pkt_cnt; 946 uint32_t tx_pkt_cnt; 947 948 /* 949 * The watchdog_lock must be held when updateing the 950 * timeout fields in struct e1000g, that is, 951 * watchdog_tid, watchdog_timer_started. 952 */ 953 kmutex_t watchdog_lock; 954 /* 955 * The link_lock protects the link fields in struct e1000g, 956 * such as link_state, link_speed, link_duplex, link_complete, and 957 * link_tid. 958 */ 959 kmutex_t link_lock; 960 /* 961 * The chip_lock assures that the Rx/Tx process must be 962 * stopped while other functions change the hardware 963 * configuration of e1000g card, such as e1000g_reset(), 964 * e1000g_reset_hw() etc are executed. 965 */ 966 krwlock_t chip_lock; 967 968 boolean_t unicst_init; 969 uint32_t unicst_avail; 970 uint32_t unicst_total; 971 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 972 973 uint32_t mcast_count; 974 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 975 976 #ifdef __sparc 977 ulong_t sys_page_sz; 978 uint_t dvma_page_num; 979 #endif 980 981 boolean_t msi_enabled; 982 boolean_t tx_hcksum_enabled; 983 int intr_type; 984 int intr_cnt; 985 int intr_cap; 986 size_t intr_size; 987 uint_t intr_pri; 988 ddi_intr_handle_t *htable; 989 990 int tx_softint_pri; 991 ddi_softint_handle_t tx_softint_handle; 992 993 kstat_t *e1000g_ksp; 994 995 /* 996 * NDD parameters 997 */ 998 caddr_t nd_data; 999 nd_param_t nd_params[PARAM_COUNT]; 1000 1001 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 1002 uint16_t phy_status; /* contents of PHY_STATUS */ 1003 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 1004 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 1005 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 1006 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 1007 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 1008 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 1009 1010 /* 1011 * FMA capabilities 1012 */ 1013 int fm_capabilities; 1014 1015 uint32_t param_en_1000fdx:1, 1016 param_en_1000hdx:1, 1017 param_en_100fdx:1, 1018 param_en_100hdx:1, 1019 param_en_10fdx:1, 1020 param_en_10hdx:1, 1021 param_pad_to_32:26; 1022 } e1000g_t; 1023 1024 1025 /* 1026 * Function prototypes 1027 */ 1028 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1029 void e1000g_release_dma_resources(struct e1000g *Adapter); 1030 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 1031 void e1000g_tx_setup(struct e1000g *Adapter); 1032 void e1000g_rx_setup(struct e1000g *Adapter); 1033 void e1000g_setup_multicast(struct e1000g *Adapter); 1034 boolean_t e1000g_reset(struct e1000g *Adapter); 1035 1036 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1037 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1038 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1039 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1040 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1041 mblk_t *e1000g_receive(struct e1000g *Adapter); 1042 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1043 1044 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1045 int e1000g_init_stats(struct e1000g *Adapter); 1046 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1047 uint32_t frame_len, uint8_t *mac_addr); 1048 enum ioc_reply e1000g_nd_ioctl(struct e1000g *Adapter, 1049 queue_t *wq, mblk_t *mp, struct iocblk *iocp); 1050 void e1000g_nd_cleanup(struct e1000g *Adapter); 1051 int e1000g_nd_init(struct e1000g *Adapter); 1052 1053 void e1000g_clear_interrupt(struct e1000g *Adapter); 1054 void e1000g_mask_interrupt(struct e1000g *Adapter); 1055 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1056 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1057 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1058 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1059 void e1000_enable_pciex_master(struct e1000_hw *hw); 1060 void e1000g_get_driver_control(struct e1000_hw *hw); 1061 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1062 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1063 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1064 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1065 1066 int e1000g_reset_link(struct e1000g *Adapter); 1067 1068 #pragma inline(e1000_rar_set) 1069 1070 /* 1071 * Global variables 1072 */ 1073 extern boolean_t e1000g_force_detach; 1074 extern uint32_t e1000g_mblks_pending; 1075 extern krwlock_t e1000g_rx_detach_lock; 1076 extern private_devi_list_t *e1000g_private_devi_list; 1077 1078 #ifdef __cplusplus 1079 } 1080 #endif 1081 1082 #endif /* _E1000G_SW_H */ 1083