1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 /* Driver states */ 81 #define E1000G_UNKNOWN 0x00 82 #define E1000G_INITIALIZED 0x01 83 #define E1000G_STARTED 0x02 84 #define E1000G_SUSPENDED 0x04 85 #define E1000G_ERROR 0x80 86 87 #define JUMBO_FRAG_LENGTH 4096 88 89 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 90 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 91 #define MAX_NUM_MULTICAST_ADDRESSES 256 92 93 /* 94 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 95 * + one for cross page split 96 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 97 * two for the workaround of the 82546 chip 98 */ 99 #define MAX_COOKIES 18 100 #define MAX_TX_DESC_PER_PACKET 21 101 102 /* 103 * constants used in setting flow control thresholds 104 */ 105 #define E1000_PBA_10K 0x000A 106 #define E1000_PBA_MASK 0xffff 107 #define E1000_PBA_SHIFT 10 108 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 109 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 110 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 111 112 #define MAX_NUM_TX_DESCRIPTOR 4096 113 #define MAX_NUM_RX_DESCRIPTOR 4096 114 #define MAX_NUM_RX_FREELIST 4096 115 #define MAX_NUM_TX_FREELIST 4096 116 #define MAX_RX_LIMIT_ON_INTR 4096 117 #define MAX_RX_INTR_DELAY 65535 118 #define MAX_RX_INTR_ABS_DELAY 65535 119 #define MAX_TX_INTR_DELAY 65535 120 #define MAX_TX_INTR_ABS_DELAY 65535 121 #define MAX_INTR_THROTTLING 65535 122 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 123 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 124 125 #define MIN_NUM_TX_DESCRIPTOR 80 126 #define MIN_NUM_RX_DESCRIPTOR 80 127 #define MIN_NUM_RX_FREELIST 64 128 #define MIN_NUM_TX_FREELIST 80 129 #define MIN_RX_LIMIT_ON_INTR 16 130 #define MIN_RX_INTR_DELAY 0 131 #define MIN_RX_INTR_ABS_DELAY 0 132 #define MIN_TX_INTR_DELAY 0 133 #define MIN_TX_INTR_ABS_DELAY 0 134 #define MIN_INTR_THROTTLING 0 135 #define MIN_RX_BCOPY_THRESHOLD 0 136 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 137 138 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 139 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 140 #define DEFAULT_NUM_RX_FREELIST 4096 141 #define DEFAULT_NUM_TX_FREELIST 2304 142 #define DEFAULT_RX_LIMIT_ON_INTR 128 143 144 #ifdef __sparc 145 #define MAX_INTR_PER_SEC 7100 146 #define MIN_INTR_PER_SEC 3000 147 #define DEFAULT_INTR_PACKET_LOW 5 148 #define DEFAULT_INTR_PACKET_HIGH 128 149 #else 150 #define MAX_INTR_PER_SEC 15000 151 #define MIN_INTR_PER_SEC 4000 152 #define DEFAULT_INTR_PACKET_LOW 10 153 #define DEFAULT_INTR_PACKET_HIGH 48 154 #endif 155 156 #define DEFAULT_RX_INTR_DELAY 0 157 #define DEFAULT_RX_INTR_ABS_DELAY 64 158 #define DEFAULT_TX_INTR_DELAY 64 159 #define DEFAULT_TX_INTR_ABS_DELAY 64 160 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 161 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 162 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 163 164 #define DEFAULT_RX_BCOPY_THRESHOLD 128 165 #define DEFAULT_TX_BCOPY_THRESHOLD 512 166 #define DEFAULT_TX_UPDATE_THRESHOLD 256 167 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 168 169 #define DEFAULT_TX_INTR_ENABLE 1 170 #define DEFAULT_FLOW_CONTROL 3 171 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 172 /* which is normally 0x040 */ 173 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 174 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 175 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 176 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 177 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 178 179 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 180 #define RX_DRAIN_TIME (200) /* # milliseconds recv drain */ 181 182 #define TX_STALL_TIME_2S (200) /* in unit of tick */ 183 #define TX_STALL_TIME_8S (800) /* in unit of tick */ 184 185 /* 186 * The size of the receive/transmite buffers 187 */ 188 #define E1000_RX_BUFFER_SIZE_2K (2048) 189 #define E1000_RX_BUFFER_SIZE_4K (4096) 190 #define E1000_RX_BUFFER_SIZE_8K (8192) 191 #define E1000_RX_BUFFER_SIZE_16K (16384) 192 193 #define E1000_TX_BUFFER_SIZE_2K (2048) 194 #define E1000_TX_BUFFER_SIZE_4K (4096) 195 #define E1000_TX_BUFFER_SIZE_8K (8192) 196 #define E1000_TX_BUFFER_SIZE_16K (16384) 197 198 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 199 200 #define E1000G_RX_NORMAL 0x0 201 #define E1000G_RX_STOPPED 0x1 202 203 #define E1000G_CHAIN_NO_LIMIT 0 204 205 /* 206 * definitions for smartspeed workaround 207 */ 208 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 209 /* or 30 seconds */ 210 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 211 /* or 6 seconds */ 212 213 /* 214 * Definitions for module_info. 215 */ 216 #define WSNAME "e1000g" /* module name */ 217 218 /* 219 * Defined for IP header alignment. We also need to preserve space for 220 * VLAN tag (4 bytes) 221 */ 222 #define E1000G_IPALIGNROOM 6 223 #define E1000G_IPALIGNPRESERVEROOM 64 224 225 /* 226 * bit flags for 'attach_progress' which is a member variable in struct e1000g 227 */ 228 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 229 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 230 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 231 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 232 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 233 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 234 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 235 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 236 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 237 /* 0200 used to be PROGRESS_NDD. Now unused */ 238 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 239 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 240 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 241 242 /* 243 * Speed and Duplex Settings 244 */ 245 #define GDIAG_10_HALF 1 246 #define GDIAG_10_FULL 2 247 #define GDIAG_100_HALF 3 248 #define GDIAG_100_FULL 4 249 #define GDIAG_1000_FULL 6 250 #define GDIAG_ANY 7 251 252 /* 253 * Coexist Workaround RP: 07/04/03 254 * 82544 Workaround : Co-existence 255 */ 256 #define MAX_TX_BUF_SIZE (8 * 1024) 257 258 /* 259 * Defines for Jumbo Frame 260 */ 261 #define FRAME_SIZE_UPTO_2K 2048 262 #define FRAME_SIZE_UPTO_4K 4096 263 #define FRAME_SIZE_UPTO_8K 8192 264 #define FRAME_SIZE_UPTO_16K 16384 265 #define FRAME_SIZE_UPTO_9K 9234 266 267 #define MAXIMUM_MTU 9000 268 #define DEFAULT_MTU ETHERMTU 269 270 #define DEFAULT_FRAME_SIZE \ 271 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 272 #define MAXIMUM_FRAME_SIZE \ 273 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 274 275 #define E1000_LSO_MAXLEN 65535 276 277 /* Defines for Tx stall check */ 278 #define E1000G_STALL_WATCHDOG_COUNT 8 279 280 #define MAX_TX_LINK_DOWN_TIMEOUT 8 281 282 /* Defines for DVMA */ 283 #ifdef __sparc 284 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 285 #endif 286 287 /* 288 * Loopback definitions 289 */ 290 #define E1000G_LB_NONE 0 291 #define E1000G_LB_EXTERNAL_1000 1 292 #define E1000G_LB_EXTERNAL_100 2 293 #define E1000G_LB_EXTERNAL_10 3 294 #define E1000G_LB_INTERNAL_PHY 4 295 296 /* 297 * Private dip list definitions 298 */ 299 #define E1000G_PRIV_DEVI_ATTACH 0x0 300 #define E1000G_PRIV_DEVI_DETACH 0x1 301 302 /* 303 * Tx descriptor LENGTH field mask 304 */ 305 #define E1000G_TBD_LENGTH_MASK 0x000fffff 306 307 #define E1000G_IS_VLAN_PACKET(ptr) \ 308 ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \ 309 htons(ETHERTYPE_VLAN)) 310 311 /* 312 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 313 */ 314 #define QUEUE_INIT_LIST(_LH) \ 315 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 316 317 /* 318 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 319 */ 320 #define IS_QUEUE_EMPTY(_LH) \ 321 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 322 323 /* 324 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 325 * not remove the head from the queue. 326 */ 327 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 328 329 /* 330 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 331 */ 332 #define QUEUE_REMOVE_HEAD(_LH) \ 333 { \ 334 PSINGLE_LIST_LINK ListElem; \ 335 if (ListElem = (_LH)->Flink) \ 336 { \ 337 if (!((_LH)->Flink = ListElem->Flink)) \ 338 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 339 } \ 340 } 341 342 /* 343 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 344 * and return it (this differs from QUEUE_REMOVE_HEAD only in 345 * the 1st line). 346 */ 347 #define QUEUE_POP_HEAD(_LH) \ 348 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 349 { \ 350 PSINGLE_LIST_LINK ListElem; \ 351 ListElem = (_LH)->Flink; \ 352 if (ListElem) \ 353 { \ 354 (_LH)->Flink = ListElem->Flink; \ 355 if (!(_LH)->Flink) \ 356 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 357 } \ 358 } 359 360 /* 361 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 362 * remove the tail from the queue. 363 */ 364 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 365 366 /* 367 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 368 */ 369 #define QUEUE_PUSH_TAIL(_LH, _E) \ 370 if ((_LH)->Blink) \ 371 { \ 372 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 373 (PSINGLE_LIST_LINK)(_E); \ 374 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 375 } else { \ 376 (_LH)->Flink = \ 377 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 378 } \ 379 (_E)->Flink = (PSINGLE_LIST_LINK)0; 380 381 /* 382 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 383 */ 384 #define QUEUE_PUSH_HEAD(_LH, _E) \ 385 if (!((_E)->Flink = (_LH)->Flink)) \ 386 { \ 387 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 388 } \ 389 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 390 391 /* 392 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 393 * current element. 394 */ 395 #define QUEUE_GET_NEXT(_LH, _E) \ 396 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 397 (0) : ((_E)->Flink)) 398 399 /* 400 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 401 */ 402 #define QUEUE_APPEND(_LH1, _LH2) \ 403 if ((_LH2)->Flink) { \ 404 if ((_LH1)->Flink) { \ 405 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 406 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 407 } else { \ 408 (_LH1)->Flink = \ 409 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 410 } \ 411 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 412 } 413 414 415 #define QUEUE_SWITCH(_LH1, _LH2) \ 416 if ((_LH2)->Flink) { \ 417 (_LH1)->Flink = (_LH2)->Flink; \ 418 (_LH1)->Blink = (_LH2)->Blink; \ 419 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 420 } 421 422 /* 423 * Property lookups 424 */ 425 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 426 DDI_PROP_DONTPASS, (n)) 427 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 428 DDI_PROP_DONTPASS, (n), -1) 429 430 #ifdef E1000G_DEBUG 431 /* 432 * E1000G-specific ioctls ... 433 */ 434 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 435 + 'K') << 4) + 'G') << 4) 436 437 /* 438 * These diagnostic IOCTLS are enabled only in DEBUG drivers 439 */ 440 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 441 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 442 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 443 444 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 445 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 446 447 typedef struct { 448 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 449 uint64_t pp_acc_space; /* See #defines below */ 450 uint64_t pp_acc_offset; /* See regs definition */ 451 uint64_t pp_acc_data; /* output for peek */ 452 /* input for poke */ 453 } e1000g_peekpoke_t; 454 #endif /* E1000G_DEBUG */ 455 456 /* 457 * (Internal) return values from ioctl subroutines 458 */ 459 enum ioc_reply { 460 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 461 IOC_DONE, /* OK, reply sent */ 462 IOC_ACK, /* OK, just send ACK */ 463 IOC_REPLY /* OK, just send reply */ 464 }; 465 466 /* 467 * Named Data (ND) Parameter Management Structure 468 */ 469 typedef struct { 470 uint32_t ndp_info; 471 uint32_t ndp_min; 472 uint32_t ndp_max; 473 uint32_t ndp_val; 474 struct e1000g *ndp_instance; 475 char *ndp_name; 476 } nd_param_t; 477 478 /* 479 * The entry of the private dip list 480 */ 481 typedef struct _private_devi_list { 482 dev_info_t *priv_dip; 483 uint32_t flag; 484 uint32_t pending_rx_count; 485 struct _private_devi_list *prev; 486 struct _private_devi_list *next; 487 } private_devi_list_t; 488 489 /* 490 * A structure that points to the next entry in the queue. 491 */ 492 typedef struct _SINGLE_LIST_LINK { 493 struct _SINGLE_LIST_LINK *Flink; 494 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 495 496 /* 497 * A "ListHead" structure that points to the head and tail of a queue 498 */ 499 typedef struct _LIST_DESCRIBER { 500 struct _SINGLE_LIST_LINK *volatile Flink; 501 struct _SINGLE_LIST_LINK *volatile Blink; 502 } LIST_DESCRIBER, *PLIST_DESCRIBER; 503 504 /* 505 * Address-Length pair structure that stores descriptor info 506 */ 507 typedef struct _sw_desc { 508 uint64_t address; 509 uint32_t length; 510 } sw_desc_t, *p_sw_desc_t; 511 512 typedef struct _desc_array { 513 sw_desc_t descriptor[4]; 514 uint32_t elements; 515 } desc_array_t, *p_desc_array_t; 516 517 typedef enum { 518 USE_NONE, 519 USE_BCOPY, 520 USE_DVMA, 521 USE_DMA 522 } dma_type_t; 523 524 typedef struct _dma_buffer { 525 caddr_t address; 526 uint64_t dma_address; 527 ddi_acc_handle_t acc_handle; 528 ddi_dma_handle_t dma_handle; 529 size_t size; 530 size_t len; 531 } dma_buffer_t, *p_dma_buffer_t; 532 533 /* 534 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 535 * structure stores the additional information that is 536 * associated with every packet to be transmitted. It stores the 537 * message block pointer and the TBD addresses associated with 538 * the m_blk and also the link to the next tcb in the chain 539 */ 540 typedef struct _tx_sw_packet { 541 /* Link to the next tx_sw_packet in the list */ 542 SINGLE_LIST_LINK Link; 543 mblk_t *mp; 544 uint32_t num_desc; 545 uint32_t num_mblk_frag; 546 dma_type_t dma_type; 547 dma_type_t data_transfer_type; 548 ddi_dma_handle_t tx_dma_handle; 549 dma_buffer_t tx_buf[1]; 550 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 551 int64_t tickstamp; 552 } tx_sw_packet_t, *p_tx_sw_packet_t; 553 554 /* 555 * This structure is similar to the rx_sw_packet structure used 556 * for Ndis. This structure stores information about the 2k 557 * aligned receive buffer into which the FX1000 DMA's frames. 558 * This structure is maintained as a linked list of many 559 * receiver buffer pointers. 560 */ 561 typedef struct _rx_sw_packet { 562 /* Link to the next rx_sw_packet_t in the list */ 563 SINGLE_LIST_LINK Link; 564 struct _rx_sw_packet *next; 565 uint32_t ref_cnt; 566 mblk_t *mp; 567 caddr_t rx_data; 568 dma_type_t dma_type; 569 frtn_t free_rtn; 570 dma_buffer_t rx_buf[1]; 571 } rx_sw_packet_t, *p_rx_sw_packet_t; 572 573 typedef struct _mblk_list { 574 mblk_t *head; 575 mblk_t *tail; 576 } mblk_list_t, *p_mblk_list_t; 577 578 typedef struct _context_data { 579 uint32_t ether_header_size; 580 uint32_t cksum_flags; 581 uint32_t cksum_start; 582 uint32_t cksum_stuff; 583 uint16_t mss; 584 uint8_t hdr_len; 585 uint32_t pay_len; 586 boolean_t lso_flag; 587 } context_data_t; 588 589 typedef union _e1000g_ether_addr { 590 struct { 591 uint32_t high; 592 uint32_t low; 593 } reg; 594 struct { 595 uint8_t set; 596 uint8_t redundant; 597 uint8_t addr[ETHERADDRL]; 598 } mac; 599 } e1000g_ether_addr_t; 600 601 typedef struct _e1000g_stat { 602 603 kstat_named_t link_speed; /* Link Speed */ 604 kstat_named_t reset_count; /* Reset Count */ 605 606 kstat_named_t rx_error; /* Rx Error in Packet */ 607 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 608 kstat_named_t rx_size_error; /* Rx Size Error */ 609 610 kstat_named_t tx_no_desc; /* Tx No Desc */ 611 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 612 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 613 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 614 kstat_named_t tx_reschedule; /* Tx Reschedule */ 615 616 #ifdef E1000G_DEBUG 617 kstat_named_t rx_none; /* Rx No Incoming Data */ 618 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 619 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 620 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 621 622 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 623 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 624 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 625 kstat_named_t tx_recycle; /* Tx Recycle */ 626 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 627 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 628 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 629 kstat_named_t tx_copy; /* Tx Send Copy */ 630 kstat_named_t tx_bind; /* Tx Send Bind */ 631 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 632 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 633 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 634 #endif 635 636 kstat_named_t Crcerrs; /* CRC Error Count */ 637 kstat_named_t Symerrs; /* Symbol Error Count */ 638 kstat_named_t Mpc; /* Missed Packet Count */ 639 kstat_named_t Scc; /* Single Collision Count */ 640 kstat_named_t Ecol; /* Excessive Collision Count */ 641 kstat_named_t Mcc; /* Multiple Collision Count */ 642 kstat_named_t Latecol; /* Late Collision Count */ 643 kstat_named_t Colc; /* Collision Count */ 644 kstat_named_t Dc; /* Defer Count */ 645 kstat_named_t Sec; /* Sequence Error Count */ 646 kstat_named_t Rlec; /* Receive Length Error Count */ 647 kstat_named_t Xonrxc; /* XON Received Count */ 648 kstat_named_t Xontxc; /* XON Xmitted Count */ 649 kstat_named_t Xoffrxc; /* XOFF Received Count */ 650 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 651 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 652 #ifdef E1000G_DEBUG 653 kstat_named_t Prc64; /* Packets Received - 64b */ 654 kstat_named_t Prc127; /* Packets Received - 65-127b */ 655 kstat_named_t Prc255; /* Packets Received - 127-255b */ 656 kstat_named_t Prc511; /* Packets Received - 256-511b */ 657 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 658 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 659 #endif 660 kstat_named_t Gprc; /* Good Packets Received Count */ 661 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 662 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 663 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 664 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 665 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 666 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 667 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 668 kstat_named_t Rnbc; /* Receive No Buffers Count */ 669 kstat_named_t Ruc; /* Receive Undersize Count */ 670 kstat_named_t Rfc; /* Receive Frag Count */ 671 kstat_named_t Roc; /* Receive Oversize Count */ 672 kstat_named_t Rjc; /* Receive Jabber Count */ 673 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 674 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 675 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 676 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 677 kstat_named_t Tpr; /* Total Packets Received */ 678 kstat_named_t Tpt; /* Total Packets Xmitted */ 679 #ifdef E1000G_DEBUG 680 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 681 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 682 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 683 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 684 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 685 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 686 #endif 687 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 688 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 689 kstat_named_t Algnerrc; /* Alignment Error count */ 690 kstat_named_t Tuc; /* Transmit Underrun count */ 691 kstat_named_t Rxerrc; /* Rx Error Count */ 692 kstat_named_t Tncrs; /* Transmit with no CRS */ 693 kstat_named_t Cexterr; /* Carrier Extension Error count */ 694 kstat_named_t Rutec; /* Receive DMA too Early count */ 695 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 696 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 697 } e1000g_stat_t, *p_e1000g_stat_t; 698 699 typedef struct _e1000g_tx_ring { 700 kmutex_t tx_lock; 701 kmutex_t freelist_lock; 702 kmutex_t usedlist_lock; 703 /* 704 * Descriptor queue definitions 705 */ 706 ddi_dma_handle_t tbd_dma_handle; 707 ddi_acc_handle_t tbd_acc_handle; 708 struct e1000_tx_desc *tbd_area; 709 uint64_t tbd_dma_addr; 710 struct e1000_tx_desc *tbd_first; 711 struct e1000_tx_desc *tbd_last; 712 struct e1000_tx_desc *tbd_oldest; 713 struct e1000_tx_desc *tbd_next; 714 uint32_t tbd_avail; 715 /* 716 * Software packet structures definitions 717 */ 718 p_tx_sw_packet_t packet_area; 719 LIST_DESCRIBER used_list; 720 LIST_DESCRIBER free_list; 721 /* 722 * TCP/UDP Context Data Information 723 */ 724 context_data_t pre_context; 725 /* 726 * Timer definitions for 82547 727 */ 728 timeout_id_t timer_id_82547; 729 boolean_t timer_enable_82547; 730 /* 731 * reschedule when tx resource is available 732 */ 733 boolean_t resched_needed; 734 clock_t resched_timestamp; 735 mblk_list_t mblks; 736 /* 737 * Statistics 738 */ 739 uint32_t stat_no_swpkt; 740 uint32_t stat_no_desc; 741 uint32_t stat_send_fail; 742 uint32_t stat_reschedule; 743 uint32_t stat_timer_reschedule; 744 uint32_t stat_over_size; 745 #ifdef E1000G_DEBUG 746 uint32_t stat_under_size; 747 uint32_t stat_exceed_frags; 748 uint32_t stat_empty_frags; 749 uint32_t stat_recycle; 750 uint32_t stat_recycle_intr; 751 uint32_t stat_recycle_retry; 752 uint32_t stat_recycle_none; 753 uint32_t stat_copy; 754 uint32_t stat_bind; 755 uint32_t stat_multi_copy; 756 uint32_t stat_multi_cookie; 757 uint32_t stat_lack_desc; 758 uint32_t stat_lso_header_fail; 759 #endif 760 /* 761 * Pointer to the adapter 762 */ 763 struct e1000g *adapter; 764 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 765 766 typedef struct _e1000g_rx_data { 767 kmutex_t freelist_lock; 768 kmutex_t recycle_lock; 769 /* 770 * Descriptor queue definitions 771 */ 772 ddi_dma_handle_t rbd_dma_handle; 773 ddi_acc_handle_t rbd_acc_handle; 774 struct e1000_rx_desc *rbd_area; 775 uint64_t rbd_dma_addr; 776 struct e1000_rx_desc *rbd_first; 777 struct e1000_rx_desc *rbd_last; 778 struct e1000_rx_desc *rbd_next; 779 /* 780 * Software packet structures definitions 781 */ 782 p_rx_sw_packet_t packet_area; 783 LIST_DESCRIBER recv_list; 784 LIST_DESCRIBER free_list; 785 LIST_DESCRIBER recycle_list; 786 uint32_t flag; 787 788 uint32_t pending_count; 789 uint32_t avail_freepkt; 790 uint32_t recycle_freepkt; 791 uint32_t rx_mblk_len; 792 mblk_t *rx_mblk; 793 mblk_t *rx_mblk_tail; 794 795 private_devi_list_t *priv_devi_node; 796 struct _e1000g_rx_ring *rx_ring; 797 } e1000g_rx_data_t; 798 799 typedef struct _e1000g_rx_ring { 800 e1000g_rx_data_t *rx_data; 801 802 kmutex_t rx_lock; 803 804 mac_ring_handle_t mrh; 805 mac_ring_handle_t mrh_init; 806 uint64_t ring_gen_num; 807 boolean_t poll_flag; 808 809 /* 810 * Statistics 811 */ 812 uint32_t stat_error; 813 uint32_t stat_allocb_fail; 814 uint32_t stat_exceed_pkt; 815 uint32_t stat_size_error; 816 #ifdef E1000G_DEBUG 817 uint32_t stat_none; 818 uint32_t stat_multi_desc; 819 uint32_t stat_no_freepkt; 820 #endif 821 /* 822 * Pointer to the adapter 823 */ 824 struct e1000g *adapter; 825 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 826 827 typedef struct e1000g { 828 int instance; 829 dev_info_t *dip; 830 dev_info_t *priv_dip; 831 private_devi_list_t *priv_devi_node; 832 mac_handle_t mh; 833 mac_resource_handle_t mrh; 834 struct e1000_hw shared; 835 struct e1000g_osdep osdep; 836 837 uint32_t e1000g_state; 838 boolean_t e1000g_promisc; 839 boolean_t strip_crc; 840 boolean_t rx_buffer_setup; 841 boolean_t esb2_workaround; 842 link_state_t link_state; 843 uint32_t link_speed; 844 uint32_t link_duplex; 845 uint32_t master_latency_timer; 846 uint32_t smartspeed; /* smartspeed w/a counter */ 847 uint32_t init_count; 848 uint32_t reset_count; 849 boolean_t reset_flag; 850 uint32_t stall_threshold; 851 boolean_t stall_flag; 852 uint32_t attach_progress; /* attach tracking */ 853 uint32_t loopback_mode; 854 uint32_t pending_rx_count; 855 856 uint32_t tx_desc_num; 857 uint32_t tx_freelist_num; 858 uint32_t rx_desc_num; 859 uint32_t rx_freelist_num; 860 uint32_t tx_buffer_size; 861 uint32_t rx_buffer_size; 862 863 uint32_t tx_link_down_timeout; 864 uint32_t tx_bcopy_thresh; 865 uint32_t rx_limit_onintr; 866 uint32_t rx_bcopy_thresh; 867 uint32_t rx_buf_align; 868 uint32_t desc_align; 869 870 boolean_t intr_adaptive; 871 boolean_t tx_intr_enable; 872 uint32_t tx_intr_delay; 873 uint32_t tx_intr_abs_delay; 874 uint32_t rx_intr_delay; 875 uint32_t rx_intr_abs_delay; 876 uint32_t intr_throttling_rate; 877 878 uint32_t default_mtu; 879 uint32_t max_frame_size; 880 uint32_t min_frame_size; 881 882 boolean_t watchdog_timer_enabled; 883 boolean_t watchdog_timer_started; 884 timeout_id_t watchdog_tid; 885 boolean_t link_complete; 886 timeout_id_t link_tid; 887 888 e1000g_rx_ring_t rx_ring[1]; 889 e1000g_tx_ring_t tx_ring[1]; 890 mac_group_handle_t rx_group; 891 892 /* 893 * Rx and Tx packet count for interrupt adaptive setting 894 */ 895 uint32_t rx_pkt_cnt; 896 uint32_t tx_pkt_cnt; 897 898 /* 899 * The watchdog_lock must be held when updateing the 900 * timeout fields in struct e1000g, that is, 901 * watchdog_tid, watchdog_timer_started. 902 */ 903 kmutex_t watchdog_lock; 904 /* 905 * The link_lock protects the link fields in struct e1000g, 906 * such as link_state, link_speed, link_duplex, link_complete, and 907 * link_tid. 908 */ 909 kmutex_t link_lock; 910 /* 911 * The chip_lock assures that the Rx/Tx process must be 912 * stopped while other functions change the hardware 913 * configuration of e1000g card, such as e1000g_reset(), 914 * e1000g_reset_hw() etc are executed. 915 */ 916 krwlock_t chip_lock; 917 918 boolean_t unicst_init; 919 uint32_t unicst_avail; 920 uint32_t unicst_total; 921 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 922 923 uint32_t mcast_count; 924 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 925 926 ulong_t sys_page_sz; 927 #ifdef __sparc 928 uint_t dvma_page_num; 929 #endif 930 931 boolean_t msi_enable; 932 boolean_t tx_hcksum_enable; 933 boolean_t lso_enable; 934 boolean_t lso_premature_issue; 935 boolean_t mem_workaround_82546; 936 int intr_type; 937 int intr_cnt; 938 int intr_cap; 939 size_t intr_size; 940 uint_t intr_pri; 941 ddi_intr_handle_t *htable; 942 943 int tx_softint_pri; 944 ddi_softint_handle_t tx_softint_handle; 945 946 kstat_t *e1000g_ksp; 947 948 boolean_t poll_mode; 949 950 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 951 uint16_t phy_status; /* contents of PHY_STATUS */ 952 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 953 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 954 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 955 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 956 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 957 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 958 959 /* 960 * FMA capabilities 961 */ 962 int fm_capabilities; 963 964 uint32_t param_en_1000fdx:1, 965 param_en_1000hdx:1, 966 param_en_100fdx:1, 967 param_en_100hdx:1, 968 param_en_10fdx:1, 969 param_en_10hdx:1, 970 param_autoneg_cap:1, 971 param_pause_cap:1, 972 param_asym_pause_cap:1, 973 param_1000fdx_cap:1, 974 param_1000hdx_cap:1, 975 param_100t4_cap:1, 976 param_100fdx_cap:1, 977 param_100hdx_cap:1, 978 param_10fdx_cap:1, 979 param_10hdx_cap:1, 980 param_adv_autoneg:1, 981 param_adv_pause:1, 982 param_adv_asym_pause:1, 983 param_adv_1000fdx:1, 984 param_adv_1000hdx:1, 985 param_adv_100t4:1, 986 param_adv_100fdx:1, 987 param_adv_100hdx:1, 988 param_adv_10fdx:1, 989 param_adv_10hdx:1, 990 param_lp_autoneg:1, 991 param_lp_pause:1, 992 param_lp_asym_pause:1, 993 param_lp_1000fdx:1, 994 param_lp_1000hdx:1, 995 param_lp_100t4:1; 996 997 uint32_t param_lp_100fdx:1, 998 param_lp_100hdx:1, 999 param_lp_10fdx:1, 1000 param_lp_10hdx:1, 1001 param_pad_to_32:28; 1002 1003 } e1000g_t; 1004 1005 1006 /* 1007 * Function prototypes 1008 */ 1009 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node); 1010 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data); 1011 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data); 1012 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1013 void e1000g_release_dma_resources(struct e1000g *Adapter); 1014 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release); 1015 void e1000g_tx_setup(struct e1000g *Adapter); 1016 void e1000g_rx_setup(struct e1000g *Adapter); 1017 void e1000g_setup_multicast(struct e1000g *Adapter); 1018 1019 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1020 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1021 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1022 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1023 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1024 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1025 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1026 1027 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1028 int e1000g_init_stats(struct e1000g *Adapter); 1029 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1030 uint32_t frame_len, uint8_t *mac_addr); 1031 1032 void e1000g_clear_interrupt(struct e1000g *Adapter); 1033 void e1000g_mask_interrupt(struct e1000g *Adapter); 1034 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1035 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1036 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1037 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1038 void e1000_enable_pciex_master(struct e1000_hw *hw); 1039 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1040 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1041 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1042 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1043 int e1000g_reset_link(struct e1000g *Adapter); 1044 1045 /* 1046 * Global variables 1047 */ 1048 extern boolean_t e1000g_force_detach; 1049 extern uint32_t e1000g_mblks_pending; 1050 extern kmutex_t e1000g_rx_detach_lock; 1051 extern private_devi_list_t *e1000g_private_devi_list; 1052 extern int e1000g_poll_mode; 1053 1054 #ifdef __cplusplus 1055 } 1056 #endif 1057 1058 #endif /* _E1000G_SW_H */ 1059