1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 #define JUMBO_FRAG_LENGTH 4096 81 82 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 83 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 84 #define MAX_NUM_MULTICAST_ADDRESSES 256 85 86 /* 87 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 88 * + one for cross page split 89 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 90 * two for the workaround of the 82546 chip 91 */ 92 #define MAX_COOKIES 18 93 #define MAX_TX_DESC_PER_PACKET 21 94 95 /* 96 * constants used in setting flow control thresholds 97 */ 98 #define E1000_PBA_10K 0x000A 99 #define E1000_PBA_MASK 0xffff 100 #define E1000_PBA_SHIFT 10 101 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 102 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 103 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 104 105 #define MAX_NUM_TX_DESCRIPTOR 4096 106 #define MAX_NUM_RX_DESCRIPTOR 4096 107 #define MAX_NUM_RX_FREELIST 4096 108 #define MAX_NUM_TX_FREELIST 4096 109 #define MAX_RX_LIMIT_ON_INTR 4096 110 #define MAX_RX_INTR_DELAY 65535 111 #define MAX_RX_INTR_ABS_DELAY 65535 112 #define MAX_TX_INTR_DELAY 65535 113 #define MAX_TX_INTR_ABS_DELAY 65535 114 #define MAX_INTR_THROTTLING 65535 115 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 116 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 117 118 #define MIN_NUM_TX_DESCRIPTOR 80 119 #define MIN_NUM_RX_DESCRIPTOR 80 120 #define MIN_NUM_RX_FREELIST 64 121 #define MIN_NUM_TX_FREELIST 80 122 #define MIN_RX_LIMIT_ON_INTR 16 123 #define MIN_RX_INTR_DELAY 0 124 #define MIN_RX_INTR_ABS_DELAY 0 125 #define MIN_TX_INTR_DELAY 0 126 #define MIN_TX_INTR_ABS_DELAY 0 127 #define MIN_INTR_THROTTLING 0 128 #define MIN_RX_BCOPY_THRESHOLD 0 129 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 130 131 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 132 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 133 #define DEFAULT_NUM_RX_FREELIST 4096 134 #define DEFAULT_NUM_TX_FREELIST 2304 135 #define DEFAULT_RX_LIMIT_ON_INTR 128 136 137 #ifdef __sparc 138 #define MAX_INTR_PER_SEC 7100 139 #define MIN_INTR_PER_SEC 3000 140 #define DEFAULT_INTR_PACKET_LOW 5 141 #define DEFAULT_INTR_PACKET_HIGH 128 142 #else 143 #define MAX_INTR_PER_SEC 15000 144 #define MIN_INTR_PER_SEC 4000 145 #define DEFAULT_INTR_PACKET_LOW 10 146 #define DEFAULT_INTR_PACKET_HIGH 48 147 #endif 148 149 #define DEFAULT_RX_INTR_DELAY 0 150 #define DEFAULT_RX_INTR_ABS_DELAY 64 151 #define DEFAULT_TX_INTR_DELAY 64 152 #define DEFAULT_TX_INTR_ABS_DELAY 64 153 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 154 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 155 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 156 157 #define DEFAULT_RX_BCOPY_THRESHOLD 128 158 #define DEFAULT_TX_BCOPY_THRESHOLD 512 159 #define DEFAULT_TX_UPDATE_THRESHOLD 256 160 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 161 162 #define DEFAULT_TX_INTR_ENABLE 1 163 #define DEFAULT_FLOW_CONTROL 3 164 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 165 /* which is normally 0x040 */ 166 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 167 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 168 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 169 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 170 171 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 172 173 /* 174 * The size of the receive/transmite buffers 175 */ 176 #define E1000_RX_BUFFER_SIZE_2K (2048) 177 #define E1000_RX_BUFFER_SIZE_4K (4096) 178 #define E1000_RX_BUFFER_SIZE_8K (8192) 179 #define E1000_RX_BUFFER_SIZE_16K (16384) 180 181 #define E1000_TX_BUFFER_SIZE_2K (2048) 182 #define E1000_TX_BUFFER_SIZE_4K (4096) 183 #define E1000_TX_BUFFER_SIZE_8K (8192) 184 #define E1000_TX_BUFFER_SIZE_16K (16384) 185 186 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 187 188 #define E1000G_RX_SW_FREE 0x0 189 #define E1000G_RX_SW_SENDUP 0x1 190 #define E1000G_RX_SW_STOP 0x2 191 #define E1000G_RX_SW_DETACH 0x3 192 193 /* 194 * definitions for smartspeed workaround 195 */ 196 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 197 /* or 30 seconds */ 198 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 199 /* or 6 seconds */ 200 201 /* 202 * Definitions for module_info. 203 */ 204 #define WSNAME "e1000g" /* module name */ 205 206 /* 207 * Defined for IP header alignment. We also need to preserve space for 208 * VLAN tag (4 bytes) 209 */ 210 #define E1000G_IPALIGNROOM 6 211 #define E1000G_IPALIGNPRESERVEROOM 64 212 213 /* 214 * bit flags for 'attach_progress' which is a member variable in struct e1000g 215 */ 216 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 217 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 218 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 219 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 220 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 221 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 222 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 223 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 224 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 225 /* 0200 used to be PROGRESS_NDD. Now unused */ 226 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 227 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 228 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 229 230 /* 231 * Speed and Duplex Settings 232 */ 233 #define GDIAG_10_HALF 1 234 #define GDIAG_10_FULL 2 235 #define GDIAG_100_HALF 3 236 #define GDIAG_100_FULL 4 237 #define GDIAG_1000_FULL 6 238 #define GDIAG_ANY 7 239 240 /* 241 * Coexist Workaround RP: 07/04/03 242 * 82544 Workaround : Co-existence 243 */ 244 #define MAX_TX_BUF_SIZE (8 * 1024) 245 246 /* 247 * Defines for Jumbo Frame 248 */ 249 #define FRAME_SIZE_UPTO_2K 2048 250 #define FRAME_SIZE_UPTO_4K 4096 251 #define FRAME_SIZE_UPTO_8K 8192 252 #define FRAME_SIZE_UPTO_16K 16384 253 #define FRAME_SIZE_UPTO_9K 9234 254 255 #define MAXIMUM_MTU 9000 256 #define DEFAULT_MTU ETHERMTU 257 258 #define DEFAULT_FRAME_SIZE \ 259 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 260 #define MAXIMUM_FRAME_SIZE \ 261 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 262 263 #define E1000_LSO_MAXLEN 65535 264 265 /* Defines for Tx stall check */ 266 #define E1000G_STALL_WATCHDOG_COUNT 8 267 268 #define MAX_TX_LINK_DOWN_TIMEOUT 8 269 270 /* Defines for DVMA */ 271 #ifdef __sparc 272 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 273 #endif 274 275 /* 276 * Loopback definitions 277 */ 278 #define E1000G_LB_NONE 0 279 #define E1000G_LB_EXTERNAL_1000 1 280 #define E1000G_LB_EXTERNAL_100 2 281 #define E1000G_LB_EXTERNAL_10 3 282 #define E1000G_LB_INTERNAL_PHY 4 283 284 /* 285 * Private dip list definitions 286 */ 287 #define E1000G_PRIV_DEVI_ATTACH 0x0 288 #define E1000G_PRIV_DEVI_DETACH 0x1 289 290 /* 291 * Tx descriptor LENGTH field mask 292 */ 293 #define E1000G_TBD_LENGTH_MASK 0x000fffff 294 295 /* 296 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 297 */ 298 #define QUEUE_INIT_LIST(_LH) \ 299 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 300 301 /* 302 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 303 */ 304 #define IS_QUEUE_EMPTY(_LH) \ 305 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 306 307 /* 308 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 309 * not remove the head from the queue. 310 */ 311 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 312 313 /* 314 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 315 */ 316 #define QUEUE_REMOVE_HEAD(_LH) \ 317 { \ 318 PSINGLE_LIST_LINK ListElem; \ 319 if (ListElem = (_LH)->Flink) \ 320 { \ 321 if (!((_LH)->Flink = ListElem->Flink)) \ 322 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 323 } \ 324 } 325 326 /* 327 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 328 * and return it (this differs from QUEUE_REMOVE_HEAD only in 329 * the 1st line). 330 */ 331 #define QUEUE_POP_HEAD(_LH) \ 332 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 333 { \ 334 PSINGLE_LIST_LINK ListElem; \ 335 ListElem = (_LH)->Flink; \ 336 if (ListElem) \ 337 { \ 338 (_LH)->Flink = ListElem->Flink; \ 339 if (!(_LH)->Flink) \ 340 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 341 } \ 342 } 343 344 /* 345 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 346 * remove the tail from the queue. 347 */ 348 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 349 350 /* 351 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 352 */ 353 #define QUEUE_PUSH_TAIL(_LH, _E) \ 354 if ((_LH)->Blink) \ 355 { \ 356 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 357 (PSINGLE_LIST_LINK)(_E); \ 358 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 359 } else { \ 360 (_LH)->Flink = \ 361 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 362 } \ 363 (_E)->Flink = (PSINGLE_LIST_LINK)0; 364 365 /* 366 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 367 */ 368 #define QUEUE_PUSH_HEAD(_LH, _E) \ 369 if (!((_E)->Flink = (_LH)->Flink)) \ 370 { \ 371 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 372 } \ 373 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 374 375 /* 376 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 377 * current element. 378 */ 379 #define QUEUE_GET_NEXT(_LH, _E) \ 380 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 381 (0) : ((_E)->Flink)) 382 383 /* 384 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 385 */ 386 #define QUEUE_APPEND(_LH1, _LH2) \ 387 if ((_LH2)->Flink) { \ 388 if ((_LH1)->Flink) { \ 389 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 390 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 391 } else { \ 392 (_LH1)->Flink = \ 393 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 394 } \ 395 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 396 } 397 398 399 #define QUEUE_SWITCH(_LH1, _LH2) \ 400 if ((_LH2)->Flink) { \ 401 (_LH1)->Flink = (_LH2)->Flink; \ 402 (_LH1)->Blink = (_LH2)->Blink; \ 403 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 404 } 405 406 /* 407 * Property lookups 408 */ 409 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 410 DDI_PROP_DONTPASS, (n)) 411 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 412 DDI_PROP_DONTPASS, (n), -1) 413 414 #ifdef E1000G_DEBUG 415 /* 416 * E1000G-specific ioctls ... 417 */ 418 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 419 + 'K') << 4) + 'G') << 4) 420 421 /* 422 * These diagnostic IOCTLS are enabled only in DEBUG drivers 423 */ 424 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 425 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 426 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 427 428 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 429 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 430 431 typedef struct { 432 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 433 uint64_t pp_acc_space; /* See #defines below */ 434 uint64_t pp_acc_offset; /* See regs definition */ 435 uint64_t pp_acc_data; /* output for peek */ 436 /* input for poke */ 437 } e1000g_peekpoke_t; 438 #endif /* E1000G_DEBUG */ 439 440 /* 441 * (Internal) return values from ioctl subroutines 442 */ 443 enum ioc_reply { 444 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 445 IOC_DONE, /* OK, reply sent */ 446 IOC_ACK, /* OK, just send ACK */ 447 IOC_REPLY /* OK, just send reply */ 448 }; 449 450 /* 451 * Named Data (ND) Parameter Management Structure 452 */ 453 typedef struct { 454 uint32_t ndp_info; 455 uint32_t ndp_min; 456 uint32_t ndp_max; 457 uint32_t ndp_val; 458 struct e1000g *ndp_instance; 459 char *ndp_name; 460 } nd_param_t; 461 462 /* 463 * The entry of the private dip list 464 */ 465 typedef struct _private_devi_list { 466 dev_info_t *priv_dip; 467 uint16_t flag; 468 struct _private_devi_list *next; 469 } private_devi_list_t; 470 471 /* 472 * A structure that points to the next entry in the queue. 473 */ 474 typedef struct _SINGLE_LIST_LINK { 475 struct _SINGLE_LIST_LINK *Flink; 476 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 477 478 /* 479 * A "ListHead" structure that points to the head and tail of a queue 480 */ 481 typedef struct _LIST_DESCRIBER { 482 struct _SINGLE_LIST_LINK *volatile Flink; 483 struct _SINGLE_LIST_LINK *volatile Blink; 484 } LIST_DESCRIBER, *PLIST_DESCRIBER; 485 486 /* 487 * Address-Length pair structure that stores descriptor info 488 */ 489 typedef struct _sw_desc { 490 uint64_t address; 491 uint32_t length; 492 } sw_desc_t, *p_sw_desc_t; 493 494 typedef struct _desc_array { 495 sw_desc_t descriptor[4]; 496 uint32_t elements; 497 } desc_array_t, *p_desc_array_t; 498 499 typedef enum { 500 USE_NONE, 501 USE_BCOPY, 502 USE_DVMA, 503 USE_DMA 504 } dma_type_t; 505 506 typedef enum { 507 E1000G_STOP, 508 E1000G_START, 509 E1000G_ERROR 510 } chip_state_t; 511 512 typedef struct _dma_buffer { 513 caddr_t address; 514 uint64_t dma_address; 515 ddi_acc_handle_t acc_handle; 516 ddi_dma_handle_t dma_handle; 517 size_t size; 518 size_t len; 519 } dma_buffer_t, *p_dma_buffer_t; 520 521 /* 522 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 523 * structure stores the additional information that is 524 * associated with every packet to be transmitted. It stores the 525 * message block pointer and the TBD addresses associated with 526 * the m_blk and also the link to the next tcb in the chain 527 */ 528 typedef struct _tx_sw_packet { 529 /* Link to the next tx_sw_packet in the list */ 530 SINGLE_LIST_LINK Link; 531 mblk_t *mp; 532 uint32_t num_desc; 533 uint32_t num_mblk_frag; 534 dma_type_t dma_type; 535 dma_type_t data_transfer_type; 536 ddi_dma_handle_t tx_dma_handle; 537 dma_buffer_t tx_buf[1]; 538 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 539 } tx_sw_packet_t, *p_tx_sw_packet_t; 540 541 /* 542 * This structure is similar to the rx_sw_packet structure used 543 * for Ndis. This structure stores information about the 2k 544 * aligned receive buffer into which the FX1000 DMA's frames. 545 * This structure is maintained as a linked list of many 546 * receiver buffer pointers. 547 */ 548 typedef struct _rx_sw_packet { 549 /* Link to the next rx_sw_packet_t in the list */ 550 SINGLE_LIST_LINK Link; 551 struct _rx_sw_packet *next; 552 uint16_t flag; 553 mblk_t *mp; 554 caddr_t rx_ring; 555 dma_type_t dma_type; 556 frtn_t free_rtn; 557 dma_buffer_t rx_buf[1]; 558 } rx_sw_packet_t, *p_rx_sw_packet_t; 559 560 typedef struct _mblk_list { 561 mblk_t *head; 562 mblk_t *tail; 563 } mblk_list_t, *p_mblk_list_t; 564 565 typedef struct _context_data { 566 uint32_t ether_header_size; 567 uint32_t cksum_flags; 568 uint32_t cksum_start; 569 uint32_t cksum_stuff; 570 uint16_t mss; 571 uint8_t hdr_len; 572 uint32_t pay_len; 573 boolean_t lso_flag; 574 } context_data_t; 575 576 typedef union _e1000g_ether_addr { 577 struct { 578 uint32_t high; 579 uint32_t low; 580 } reg; 581 struct { 582 uint8_t set; 583 uint8_t redundant; 584 uint8_t addr[ETHERADDRL]; 585 } mac; 586 } e1000g_ether_addr_t; 587 588 typedef struct _e1000g_stat { 589 590 kstat_named_t link_speed; /* Link Speed */ 591 kstat_named_t reset_count; /* Reset Count */ 592 593 kstat_named_t rx_error; /* Rx Error in Packet */ 594 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 595 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 596 597 kstat_named_t tx_no_desc; /* Tx No Desc */ 598 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 599 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 600 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 601 kstat_named_t tx_reschedule; /* Tx Reschedule */ 602 603 #ifdef E1000G_DEBUG 604 kstat_named_t rx_none; /* Rx No Incoming Data */ 605 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 606 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 607 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 608 609 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 610 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 611 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 612 kstat_named_t tx_recycle; /* Tx Recycle */ 613 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 614 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 615 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 616 kstat_named_t tx_copy; /* Tx Send Copy */ 617 kstat_named_t tx_bind; /* Tx Send Bind */ 618 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 619 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 620 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 621 #endif 622 623 kstat_named_t Crcerrs; /* CRC Error Count */ 624 kstat_named_t Symerrs; /* Symbol Error Count */ 625 kstat_named_t Mpc; /* Missed Packet Count */ 626 kstat_named_t Scc; /* Single Collision Count */ 627 kstat_named_t Ecol; /* Excessive Collision Count */ 628 kstat_named_t Mcc; /* Multiple Collision Count */ 629 kstat_named_t Latecol; /* Late Collision Count */ 630 kstat_named_t Colc; /* Collision Count */ 631 kstat_named_t Dc; /* Defer Count */ 632 kstat_named_t Sec; /* Sequence Error Count */ 633 kstat_named_t Rlec; /* Receive Length Error Count */ 634 kstat_named_t Xonrxc; /* XON Received Count */ 635 kstat_named_t Xontxc; /* XON Xmitted Count */ 636 kstat_named_t Xoffrxc; /* XOFF Received Count */ 637 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 638 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 639 #ifdef E1000G_DEBUG 640 kstat_named_t Prc64; /* Packets Received - 64b */ 641 kstat_named_t Prc127; /* Packets Received - 65-127b */ 642 kstat_named_t Prc255; /* Packets Received - 127-255b */ 643 kstat_named_t Prc511; /* Packets Received - 256-511b */ 644 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 645 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 646 #endif 647 kstat_named_t Gprc; /* Good Packets Received Count */ 648 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 649 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 650 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 651 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 652 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 653 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 654 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 655 kstat_named_t Rnbc; /* Receive No Buffers Count */ 656 kstat_named_t Ruc; /* Receive Undersize Count */ 657 kstat_named_t Rfc; /* Receive Frag Count */ 658 kstat_named_t Roc; /* Receive Oversize Count */ 659 kstat_named_t Rjc; /* Receive Jabber Count */ 660 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 661 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 662 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 663 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 664 kstat_named_t Tpr; /* Total Packets Received */ 665 kstat_named_t Tpt; /* Total Packets Xmitted */ 666 #ifdef E1000G_DEBUG 667 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 668 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 669 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 670 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 671 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 672 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 673 #endif 674 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 675 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 676 kstat_named_t Algnerrc; /* Alignment Error count */ 677 kstat_named_t Tuc; /* Transmit Underrun count */ 678 kstat_named_t Rxerrc; /* Rx Error Count */ 679 kstat_named_t Tncrs; /* Transmit with no CRS */ 680 kstat_named_t Cexterr; /* Carrier Extension Error count */ 681 kstat_named_t Rutec; /* Receive DMA too Early count */ 682 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 683 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 684 } e1000g_stat_t, *p_e1000g_stat_t; 685 686 typedef struct _e1000g_tx_ring { 687 kmutex_t tx_lock; 688 kmutex_t freelist_lock; 689 kmutex_t usedlist_lock; 690 /* 691 * Descriptor queue definitions 692 */ 693 ddi_dma_handle_t tbd_dma_handle; 694 ddi_acc_handle_t tbd_acc_handle; 695 struct e1000_tx_desc *tbd_area; 696 uint64_t tbd_dma_addr; 697 struct e1000_tx_desc *tbd_first; 698 struct e1000_tx_desc *tbd_last; 699 struct e1000_tx_desc *tbd_oldest; 700 struct e1000_tx_desc *tbd_next; 701 uint32_t tbd_avail; 702 /* 703 * Software packet structures definitions 704 */ 705 p_tx_sw_packet_t packet_area; 706 LIST_DESCRIBER used_list; 707 LIST_DESCRIBER free_list; 708 /* 709 * TCP/UDP Context Data Information 710 */ 711 context_data_t pre_context; 712 /* 713 * Timer definitions for 82547 714 */ 715 timeout_id_t timer_id_82547; 716 boolean_t timer_enable_82547; 717 /* 718 * reschedule when tx resource is available 719 */ 720 boolean_t resched_needed; 721 clock_t resched_timestamp; 722 uint32_t stall_watchdog; 723 uint32_t recycle_fail; 724 mblk_list_t mblks; 725 /* 726 * Statistics 727 */ 728 uint32_t stat_no_swpkt; 729 uint32_t stat_no_desc; 730 uint32_t stat_send_fail; 731 uint32_t stat_reschedule; 732 uint32_t stat_timer_reschedule; 733 uint32_t stat_over_size; 734 #ifdef E1000G_DEBUG 735 uint32_t stat_under_size; 736 uint32_t stat_exceed_frags; 737 uint32_t stat_empty_frags; 738 uint32_t stat_recycle; 739 uint32_t stat_recycle_intr; 740 uint32_t stat_recycle_retry; 741 uint32_t stat_recycle_none; 742 uint32_t stat_copy; 743 uint32_t stat_bind; 744 uint32_t stat_multi_copy; 745 uint32_t stat_multi_cookie; 746 uint32_t stat_lack_desc; 747 uint32_t stat_lso_header_fail; 748 #endif 749 /* 750 * Pointer to the adapter 751 */ 752 struct e1000g *adapter; 753 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 754 755 typedef struct _e1000g_rx_ring { 756 kmutex_t rx_lock; 757 kmutex_t freelist_lock; 758 kmutex_t recycle_lock; 759 /* 760 * Descriptor queue definitions 761 */ 762 ddi_dma_handle_t rbd_dma_handle; 763 ddi_acc_handle_t rbd_acc_handle; 764 struct e1000_rx_desc *rbd_area; 765 uint64_t rbd_dma_addr; 766 struct e1000_rx_desc *rbd_first; 767 struct e1000_rx_desc *rbd_last; 768 struct e1000_rx_desc *rbd_next; 769 /* 770 * Software packet structures definitions 771 */ 772 p_rx_sw_packet_t packet_area; 773 LIST_DESCRIBER recv_list; 774 LIST_DESCRIBER free_list; 775 LIST_DESCRIBER recycle_list; 776 777 p_rx_sw_packet_t pending_list; 778 uint32_t pending_count; 779 uint32_t avail_freepkt; 780 uint32_t recycle_freepkt; 781 uint32_t rx_mblk_len; 782 mblk_t *rx_mblk; 783 mblk_t *rx_mblk_tail; 784 mac_ring_handle_t mrh; 785 mac_ring_handle_t mrh_init; 786 uint64_t ring_gen_num; 787 mblk_t *poll_list_head; 788 mblk_t *poll_list_tail; 789 uint_t poll_list_sz; 790 boolean_t poll_flag; 791 792 /* 793 * Statistics 794 */ 795 uint32_t stat_error; 796 uint32_t stat_esballoc_fail; 797 uint32_t stat_allocb_fail; 798 uint32_t stat_exceed_pkt; 799 #ifdef E1000G_DEBUG 800 uint32_t stat_none; 801 uint32_t stat_multi_desc; 802 uint32_t stat_no_freepkt; 803 #endif 804 /* 805 * Pointer to the adapter 806 */ 807 struct e1000g *adapter; 808 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 809 810 typedef struct e1000g { 811 int instance; 812 dev_info_t *dip; 813 dev_info_t *priv_dip; 814 mac_handle_t mh; 815 mac_resource_handle_t mrh; 816 struct e1000_hw shared; 817 struct e1000g_osdep osdep; 818 819 chip_state_t chip_state; 820 boolean_t e1000g_promisc; 821 boolean_t strip_crc; 822 boolean_t rx_buffer_setup; 823 boolean_t esb2_workaround; 824 link_state_t link_state; 825 uint32_t link_speed; 826 uint32_t link_duplex; 827 uint32_t master_latency_timer; 828 uint32_t smartspeed; /* smartspeed w/a counter */ 829 uint32_t init_count; 830 uint32_t reset_count; 831 uint32_t attach_progress; /* attach tracking */ 832 uint32_t loopback_mode; 833 834 uint32_t tx_desc_num; 835 uint32_t tx_freelist_num; 836 uint32_t rx_desc_num; 837 uint32_t rx_freelist_num; 838 uint32_t tx_buffer_size; 839 uint32_t rx_buffer_size; 840 841 uint32_t tx_link_down_timeout; 842 uint32_t tx_bcopy_thresh; 843 uint32_t rx_limit_onintr; 844 uint32_t rx_bcopy_thresh; 845 uint32_t rx_buf_align; 846 uint32_t desc_align; 847 848 boolean_t intr_adaptive; 849 boolean_t tx_intr_enable; 850 uint32_t tx_intr_delay; 851 uint32_t tx_intr_abs_delay; 852 uint32_t rx_intr_delay; 853 uint32_t rx_intr_abs_delay; 854 uint32_t intr_throttling_rate; 855 856 uint32_t default_mtu; 857 uint32_t max_frame_size; 858 uint32_t min_frame_size; 859 860 boolean_t watchdog_timer_enabled; 861 boolean_t watchdog_timer_started; 862 timeout_id_t watchdog_tid; 863 boolean_t link_complete; 864 timeout_id_t link_tid; 865 866 e1000g_rx_ring_t rx_ring[1]; 867 e1000g_tx_ring_t tx_ring[1]; 868 mac_group_handle_t rx_group; 869 870 kmutex_t gen_lock; /* General lock for the whole struct e1000g */ 871 872 /* 873 * Rx and Tx packet count for interrupt adaptive setting 874 */ 875 uint32_t rx_pkt_cnt; 876 uint32_t tx_pkt_cnt; 877 878 /* 879 * The watchdog_lock must be held when updateing the 880 * timeout fields in struct e1000g, that is, 881 * watchdog_tid, watchdog_timer_started. 882 */ 883 kmutex_t watchdog_lock; 884 /* 885 * The link_lock protects the link fields in struct e1000g, 886 * such as link_state, link_speed, link_duplex, link_complete, and 887 * link_tid. 888 */ 889 kmutex_t link_lock; 890 /* 891 * The chip_lock assures that the Rx/Tx process must be 892 * stopped while other functions change the hardware 893 * configuration of e1000g card, such as e1000g_reset(), 894 * e1000g_reset_hw() etc are executed. 895 */ 896 krwlock_t chip_lock; 897 898 boolean_t unicst_init; 899 uint32_t unicst_avail; 900 uint32_t unicst_total; 901 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 902 903 uint32_t mcast_count; 904 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 905 906 ulong_t sys_page_sz; 907 #ifdef __sparc 908 uint_t dvma_page_num; 909 #endif 910 911 boolean_t msi_enable; 912 boolean_t tx_hcksum_enable; 913 boolean_t lso_enable; 914 boolean_t lso_premature_issue; 915 int intr_type; 916 int intr_cnt; 917 int intr_cap; 918 size_t intr_size; 919 uint_t intr_pri; 920 ddi_intr_handle_t *htable; 921 922 int tx_softint_pri; 923 ddi_softint_handle_t tx_softint_handle; 924 925 kstat_t *e1000g_ksp; 926 927 boolean_t poll_mode; 928 929 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 930 uint16_t phy_status; /* contents of PHY_STATUS */ 931 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 932 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 933 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 934 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 935 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 936 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 937 938 /* 939 * FMA capabilities 940 */ 941 int fm_capabilities; 942 943 uint32_t param_en_1000fdx:1, 944 param_en_1000hdx:1, 945 param_en_100fdx:1, 946 param_en_100hdx:1, 947 param_en_10fdx:1, 948 param_en_10hdx:1, 949 param_autoneg_cap:1, 950 param_pause_cap:1, 951 param_asym_pause_cap:1, 952 param_1000fdx_cap:1, 953 param_1000hdx_cap:1, 954 param_100t4_cap:1, 955 param_100fdx_cap:1, 956 param_100hdx_cap:1, 957 param_10fdx_cap:1, 958 param_10hdx_cap:1, 959 param_adv_autoneg:1, 960 param_adv_pause:1, 961 param_adv_asym_pause:1, 962 param_adv_1000fdx:1, 963 param_adv_1000hdx:1, 964 param_adv_100t4:1, 965 param_adv_100fdx:1, 966 param_adv_100hdx:1, 967 param_adv_10fdx:1, 968 param_adv_10hdx:1, 969 param_lp_autoneg:1, 970 param_lp_pause:1, 971 param_lp_asym_pause:1, 972 param_lp_1000fdx:1, 973 param_lp_1000hdx:1, 974 param_lp_100t4:1; 975 976 uint32_t param_lp_100fdx:1, 977 param_lp_100hdx:1, 978 param_lp_10fdx:1, 979 param_lp_10hdx:1, 980 param_pad_to_32:28; 981 982 } e1000g_t; 983 984 985 /* 986 * Function prototypes 987 */ 988 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 989 void e1000g_release_dma_resources(struct e1000g *Adapter); 990 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 991 void e1000g_tx_setup(struct e1000g *Adapter); 992 void e1000g_rx_setup(struct e1000g *Adapter); 993 void e1000g_setup_multicast(struct e1000g *Adapter); 994 995 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 996 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 997 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 998 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 999 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1000 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t *sz); 1001 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1002 1003 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1004 int e1000g_init_stats(struct e1000g *Adapter); 1005 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1006 uint32_t frame_len, uint8_t *mac_addr); 1007 1008 void e1000g_clear_interrupt(struct e1000g *Adapter); 1009 void e1000g_mask_interrupt(struct e1000g *Adapter); 1010 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1011 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1012 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1013 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1014 void e1000_enable_pciex_master(struct e1000_hw *hw); 1015 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1016 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1017 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1018 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1019 int e1000g_reset_link(struct e1000g *Adapter); 1020 1021 /* 1022 * Global variables 1023 */ 1024 extern boolean_t e1000g_force_detach; 1025 extern uint32_t e1000g_mblks_pending; 1026 extern krwlock_t e1000g_rx_detach_lock; 1027 extern private_devi_list_t *e1000g_private_devi_list; 1028 extern int e1000g_poll_mode; 1029 1030 #ifdef __cplusplus 1031 } 1032 #endif 1033 1034 #endif /* _E1000G_SW_H */ 1035