1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: e1000g_stat.c * 30 * * 31 * Abstract: Functions for processing statistics * 32 * * 33 * ********************************************************************** 34 */ 35 #include "e1000g_sw.h" 36 #include "e1000g_debug.h" 37 38 static int e1000g_update_stats(kstat_t *ksp, int rw); 39 static uint32_t e1000g_read_phy_stat(struct e1000_hw *hw, int reg); 40 41 /* 42 * e1000_tbi_adjust_stats 43 * 44 * Adjusts statistic counters when a frame is accepted 45 * under the TBI workaround. This function has been 46 * adapted for Solaris from shared code. 47 */ 48 void 49 e1000_tbi_adjust_stats(struct e1000g *Adapter, 50 uint32_t frame_len, uint8_t *mac_addr) 51 { 52 uint32_t carry_bit; 53 p_e1000g_stat_t e1000g_ksp; 54 55 e1000g_ksp = (p_e1000g_stat_t)Adapter->e1000g_ksp->ks_data; 56 57 /* First adjust the frame length */ 58 frame_len--; 59 60 /* 61 * We need to adjust the statistics counters, since the hardware 62 * counters overcount this packet as a CRC error and undercount 63 * the packet as a good packet 64 */ 65 /* This packet should not be counted as a CRC error */ 66 e1000g_ksp->Crcerrs.value.ul--; 67 /* This packet does count as a Good Packet Received */ 68 e1000g_ksp->Gprc.value.ul++; 69 70 /* 71 * Adjust the Good Octets received counters 72 */ 73 carry_bit = 0x80000000 & e1000g_ksp->Gorl.value.ul; 74 e1000g_ksp->Gorl.value.ul += frame_len; 75 /* 76 * If the high bit of Gorcl (the low 32 bits of the Good Octets 77 * Received Count) was one before the addition, 78 * AND it is zero after, then we lost the carry out, 79 * need to add one to Gorch (Good Octets Received Count High). 80 * This could be simplified if all environments supported 81 * 64-bit integers. 82 */ 83 if (carry_bit && ((e1000g_ksp->Gorl.value.ul & 0x80000000) == 0)) { 84 e1000g_ksp->Gorh.value.ul++; 85 } 86 /* 87 * Is this a broadcast or multicast? Check broadcast first, 88 * since the test for a multicast frame will test positive on 89 * a broadcast frame. 90 */ 91 if ((mac_addr[0] == (uint8_t)0xff) && 92 (mac_addr[1] == (uint8_t)0xff)) { 93 /* 94 * Broadcast packet 95 */ 96 e1000g_ksp->Bprc.value.ul++; 97 } else if (*mac_addr & 0x01) { 98 /* 99 * Multicast packet 100 */ 101 e1000g_ksp->Mprc.value.ul++; 102 } 103 104 if (frame_len == Adapter->max_frame_size) { 105 /* 106 * In this case, the hardware has overcounted the number of 107 * oversize frames. 108 */ 109 if (e1000g_ksp->Roc.value.ul > 0) 110 e1000g_ksp->Roc.value.ul--; 111 } 112 113 #ifdef E1000G_DEBUG 114 /* 115 * Adjust the bin counters when the extra byte put the frame in the 116 * wrong bin. Remember that the frame_len was adjusted above. 117 */ 118 if (frame_len == 64) { 119 e1000g_ksp->Prc64.value.ul++; 120 e1000g_ksp->Prc127.value.ul--; 121 } else if (frame_len == 127) { 122 e1000g_ksp->Prc127.value.ul++; 123 e1000g_ksp->Prc255.value.ul--; 124 } else if (frame_len == 255) { 125 e1000g_ksp->Prc255.value.ul++; 126 e1000g_ksp->Prc511.value.ul--; 127 } else if (frame_len == 511) { 128 e1000g_ksp->Prc511.value.ul++; 129 e1000g_ksp->Prc1023.value.ul--; 130 } else if (frame_len == 1023) { 131 e1000g_ksp->Prc1023.value.ul++; 132 e1000g_ksp->Prc1522.value.ul--; 133 } else if (frame_len == 1522) { 134 e1000g_ksp->Prc1522.value.ul++; 135 } 136 #endif 137 } 138 139 140 /* 141 * e1000g_update_stats - update driver private kstat counters 142 * 143 * This routine will dump and reset the e1000's internal 144 * statistics counters. The current stats dump values will 145 * be sent to the kernel status area. 146 */ 147 static int 148 e1000g_update_stats(kstat_t *ksp, int rw) 149 { 150 struct e1000g *Adapter; 151 struct e1000_hw *hw; 152 p_e1000g_stat_t e1000g_ksp; 153 e1000g_tx_ring_t *tx_ring; 154 e1000g_rx_ring_t *rx_ring; 155 e1000g_rx_data_t *rx_data; 156 uint64_t val; 157 uint32_t low_val, high_val; 158 159 if (rw == KSTAT_WRITE) 160 return (EACCES); 161 162 Adapter = (struct e1000g *)ksp->ks_private; 163 ASSERT(Adapter != NULL); 164 e1000g_ksp = (p_e1000g_stat_t)ksp->ks_data; 165 ASSERT(e1000g_ksp != NULL); 166 hw = &Adapter->shared; 167 168 tx_ring = Adapter->tx_ring; 169 rx_ring = Adapter->rx_ring; 170 rx_data = rx_ring->rx_data; 171 172 rw_enter(&Adapter->chip_lock, RW_WRITER); 173 174 e1000g_ksp->link_speed.value.ul = Adapter->link_speed; 175 e1000g_ksp->reset_count.value.ul = Adapter->reset_count; 176 177 e1000g_ksp->rx_error.value.ul = rx_ring->stat_error; 178 e1000g_ksp->rx_allocb_fail.value.ul = rx_ring->stat_allocb_fail; 179 e1000g_ksp->rx_size_error.value.ul = rx_ring->stat_size_error; 180 181 e1000g_ksp->tx_no_swpkt.value.ul = tx_ring->stat_no_swpkt; 182 e1000g_ksp->tx_no_desc.value.ul = tx_ring->stat_no_desc; 183 e1000g_ksp->tx_send_fail.value.ul = tx_ring->stat_send_fail; 184 e1000g_ksp->tx_reschedule.value.ul = tx_ring->stat_reschedule; 185 e1000g_ksp->tx_over_size.value.ul = tx_ring->stat_over_size; 186 187 #ifdef E1000G_DEBUG 188 e1000g_ksp->rx_none.value.ul = rx_ring->stat_none; 189 e1000g_ksp->rx_multi_desc.value.ul = rx_ring->stat_multi_desc; 190 e1000g_ksp->rx_no_freepkt.value.ul = rx_ring->stat_no_freepkt; 191 if (rx_data != NULL) 192 e1000g_ksp->rx_avail_freepkt.value.ul = rx_data->avail_freepkt; 193 194 e1000g_ksp->tx_under_size.value.ul = tx_ring->stat_under_size; 195 e1000g_ksp->tx_exceed_frags.value.ul = tx_ring->stat_exceed_frags; 196 e1000g_ksp->tx_empty_frags.value.ul = tx_ring->stat_empty_frags; 197 e1000g_ksp->tx_recycle.value.ul = tx_ring->stat_recycle; 198 e1000g_ksp->tx_recycle_intr.value.ul = tx_ring->stat_recycle_intr; 199 e1000g_ksp->tx_recycle_retry.value.ul = tx_ring->stat_recycle_retry; 200 e1000g_ksp->tx_recycle_none.value.ul = tx_ring->stat_recycle_none; 201 e1000g_ksp->tx_copy.value.ul = tx_ring->stat_copy; 202 e1000g_ksp->tx_bind.value.ul = tx_ring->stat_bind; 203 e1000g_ksp->tx_multi_copy.value.ul = tx_ring->stat_multi_copy; 204 e1000g_ksp->tx_multi_cookie.value.ul = tx_ring->stat_multi_cookie; 205 e1000g_ksp->tx_lack_desc.value.ul = tx_ring->stat_lack_desc; 206 #endif 207 208 /* 209 * Standard Stats 210 */ 211 e1000g_ksp->Mpc.value.ul += E1000_READ_REG(hw, E1000_MPC); 212 e1000g_ksp->Rlec.value.ul += E1000_READ_REG(hw, E1000_RLEC); 213 e1000g_ksp->Xonrxc.value.ul += E1000_READ_REG(hw, E1000_XONRXC); 214 e1000g_ksp->Xontxc.value.ul += E1000_READ_REG(hw, E1000_XONTXC); 215 e1000g_ksp->Xoffrxc.value.ul += E1000_READ_REG(hw, E1000_XOFFRXC); 216 e1000g_ksp->Xofftxc.value.ul += E1000_READ_REG(hw, E1000_XOFFTXC); 217 e1000g_ksp->Fcruc.value.ul += E1000_READ_REG(hw, E1000_FCRUC); 218 219 if ((hw->mac.type != e1000_ich8lan) && 220 (hw->mac.type != e1000_ich9lan) && 221 (hw->mac.type != e1000_ich10lan) && 222 (hw->mac.type != e1000_pchlan)) { 223 e1000g_ksp->Symerrs.value.ul += 224 E1000_READ_REG(hw, E1000_SYMERRS); 225 #ifdef E1000G_DEBUG 226 e1000g_ksp->Prc64.value.ul += 227 E1000_READ_REG(hw, E1000_PRC64); 228 e1000g_ksp->Prc127.value.ul += 229 E1000_READ_REG(hw, E1000_PRC127); 230 e1000g_ksp->Prc255.value.ul += 231 E1000_READ_REG(hw, E1000_PRC255); 232 e1000g_ksp->Prc511.value.ul += 233 E1000_READ_REG(hw, E1000_PRC511); 234 e1000g_ksp->Prc1023.value.ul += 235 E1000_READ_REG(hw, E1000_PRC1023); 236 e1000g_ksp->Prc1522.value.ul += 237 E1000_READ_REG(hw, E1000_PRC1522); 238 239 e1000g_ksp->Ptc64.value.ul += 240 E1000_READ_REG(hw, E1000_PTC64); 241 e1000g_ksp->Ptc127.value.ul += 242 E1000_READ_REG(hw, E1000_PTC127); 243 e1000g_ksp->Ptc255.value.ul += 244 E1000_READ_REG(hw, E1000_PTC255); 245 e1000g_ksp->Ptc511.value.ul += 246 E1000_READ_REG(hw, E1000_PTC511); 247 e1000g_ksp->Ptc1023.value.ul += 248 E1000_READ_REG(hw, E1000_PTC1023); 249 e1000g_ksp->Ptc1522.value.ul += 250 E1000_READ_REG(hw, E1000_PTC1522); 251 #endif 252 } 253 254 e1000g_ksp->Gprc.value.ul += E1000_READ_REG(hw, E1000_GPRC); 255 e1000g_ksp->Gptc.value.ul += E1000_READ_REG(hw, E1000_GPTC); 256 e1000g_ksp->Ruc.value.ul += E1000_READ_REG(hw, E1000_RUC); 257 e1000g_ksp->Rfc.value.ul += E1000_READ_REG(hw, E1000_RFC); 258 e1000g_ksp->Roc.value.ul += E1000_READ_REG(hw, E1000_ROC); 259 e1000g_ksp->Rjc.value.ul += E1000_READ_REG(hw, E1000_RJC); 260 e1000g_ksp->Tpr.value.ul += E1000_READ_REG(hw, E1000_TPR); 261 e1000g_ksp->Tncrs.value.ul += e1000g_read_phy_stat(hw, E1000_TNCRS); 262 e1000g_ksp->Tsctc.value.ul += E1000_READ_REG(hw, E1000_TSCTC); 263 e1000g_ksp->Tsctfc.value.ul += E1000_READ_REG(hw, E1000_TSCTFC); 264 265 /* 266 * Adaptive Calculations 267 */ 268 hw->mac.tx_packet_delta = E1000_READ_REG(hw, E1000_TPT); 269 e1000g_ksp->Tpt.value.ul += hw->mac.tx_packet_delta; 270 271 /* 272 * The 64-bit register will reset whenever the upper 273 * 32 bits are read. So we need to read the lower 274 * 32 bits first, then read the upper 32 bits. 275 */ 276 low_val = E1000_READ_REG(hw, E1000_GORCL); 277 high_val = E1000_READ_REG(hw, E1000_GORCH); 278 val = (uint64_t)e1000g_ksp->Gorh.value.ul << 32 | 279 (uint64_t)e1000g_ksp->Gorl.value.ul; 280 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 281 e1000g_ksp->Gorl.value.ul = (uint32_t)val; 282 e1000g_ksp->Gorh.value.ul = (uint32_t)(val >> 32); 283 284 low_val = E1000_READ_REG(hw, E1000_GOTCL); 285 high_val = E1000_READ_REG(hw, E1000_GOTCH); 286 val = (uint64_t)e1000g_ksp->Goth.value.ul << 32 | 287 (uint64_t)e1000g_ksp->Gotl.value.ul; 288 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 289 e1000g_ksp->Gotl.value.ul = (uint32_t)val; 290 e1000g_ksp->Goth.value.ul = (uint32_t)(val >> 32); 291 292 low_val = E1000_READ_REG(hw, E1000_TORL); 293 high_val = E1000_READ_REG(hw, E1000_TORH); 294 val = (uint64_t)e1000g_ksp->Torh.value.ul << 32 | 295 (uint64_t)e1000g_ksp->Torl.value.ul; 296 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 297 e1000g_ksp->Torl.value.ul = (uint32_t)val; 298 e1000g_ksp->Torh.value.ul = (uint32_t)(val >> 32); 299 300 low_val = E1000_READ_REG(hw, E1000_TOTL); 301 high_val = E1000_READ_REG(hw, E1000_TOTH); 302 val = (uint64_t)e1000g_ksp->Toth.value.ul << 32 | 303 (uint64_t)e1000g_ksp->Totl.value.ul; 304 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 305 e1000g_ksp->Totl.value.ul = (uint32_t)val; 306 e1000g_ksp->Toth.value.ul = (uint32_t)(val >> 32); 307 308 rw_exit(&Adapter->chip_lock); 309 310 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 311 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_UNAFFECTED); 312 return (EIO); 313 } 314 315 return (0); 316 } 317 318 int 319 e1000g_m_stat(void *arg, uint_t stat, uint64_t *val) 320 { 321 struct e1000g *Adapter = (struct e1000g *)arg; 322 struct e1000_hw *hw = &Adapter->shared; 323 p_e1000g_stat_t e1000g_ksp; 324 uint32_t low_val, high_val; 325 326 e1000g_ksp = (p_e1000g_stat_t)Adapter->e1000g_ksp->ks_data; 327 328 rw_enter(&Adapter->chip_lock, RW_READER); 329 330 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 331 rw_exit(&Adapter->chip_lock); 332 return (ECANCELED); 333 } 334 335 switch (stat) { 336 case MAC_STAT_IFSPEED: 337 *val = Adapter->link_speed * 1000000ull; 338 break; 339 340 case MAC_STAT_MULTIRCV: 341 e1000g_ksp->Mprc.value.ul += 342 E1000_READ_REG(hw, E1000_MPRC); 343 *val = e1000g_ksp->Mprc.value.ul; 344 break; 345 346 case MAC_STAT_BRDCSTRCV: 347 e1000g_ksp->Bprc.value.ul += 348 E1000_READ_REG(hw, E1000_BPRC); 349 *val = e1000g_ksp->Bprc.value.ul; 350 break; 351 352 case MAC_STAT_MULTIXMT: 353 e1000g_ksp->Mptc.value.ul += 354 E1000_READ_REG(hw, E1000_MPTC); 355 *val = e1000g_ksp->Mptc.value.ul; 356 break; 357 358 case MAC_STAT_BRDCSTXMT: 359 e1000g_ksp->Bptc.value.ul += 360 E1000_READ_REG(hw, E1000_BPTC); 361 *val = e1000g_ksp->Bptc.value.ul; 362 break; 363 364 case MAC_STAT_NORCVBUF: 365 e1000g_ksp->Rnbc.value.ul += 366 E1000_READ_REG(hw, E1000_RNBC); 367 *val = e1000g_ksp->Rnbc.value.ul; 368 break; 369 370 case MAC_STAT_IERRORS: 371 e1000g_ksp->Rxerrc.value.ul += 372 E1000_READ_REG(hw, E1000_RXERRC); 373 e1000g_ksp->Algnerrc.value.ul += 374 E1000_READ_REG(hw, E1000_ALGNERRC); 375 e1000g_ksp->Rlec.value.ul += 376 E1000_READ_REG(hw, E1000_RLEC); 377 e1000g_ksp->Crcerrs.value.ul += 378 E1000_READ_REG(hw, E1000_CRCERRS); 379 e1000g_ksp->Cexterr.value.ul += 380 E1000_READ_REG(hw, E1000_CEXTERR); 381 *val = e1000g_ksp->Rxerrc.value.ul + 382 e1000g_ksp->Algnerrc.value.ul + 383 e1000g_ksp->Rlec.value.ul + 384 e1000g_ksp->Crcerrs.value.ul + 385 e1000g_ksp->Cexterr.value.ul; 386 break; 387 388 case MAC_STAT_NOXMTBUF: 389 *val = Adapter->tx_ring->stat_no_desc; 390 break; 391 392 case MAC_STAT_OERRORS: 393 e1000g_ksp->Ecol.value.ul += 394 e1000g_read_phy_stat(hw, E1000_ECOL); 395 *val = e1000g_ksp->Ecol.value.ul; 396 break; 397 398 case MAC_STAT_COLLISIONS: 399 e1000g_ksp->Colc.value.ul += 400 e1000g_read_phy_stat(hw, E1000_COLC); 401 *val = e1000g_ksp->Colc.value.ul; 402 break; 403 404 case MAC_STAT_RBYTES: 405 /* 406 * The 64-bit register will reset whenever the upper 407 * 32 bits are read. So we need to read the lower 408 * 32 bits first, then read the upper 32 bits. 409 */ 410 low_val = E1000_READ_REG(hw, E1000_TORL); 411 high_val = E1000_READ_REG(hw, E1000_TORH); 412 *val = (uint64_t)e1000g_ksp->Torh.value.ul << 32 | 413 (uint64_t)e1000g_ksp->Torl.value.ul; 414 *val += (uint64_t)high_val << 32 | (uint64_t)low_val; 415 416 e1000g_ksp->Torl.value.ul = (uint32_t)*val; 417 e1000g_ksp->Torh.value.ul = (uint32_t)(*val >> 32); 418 break; 419 420 case MAC_STAT_IPACKETS: 421 e1000g_ksp->Tpr.value.ul += 422 E1000_READ_REG(hw, E1000_TPR); 423 *val = e1000g_ksp->Tpr.value.ul; 424 break; 425 426 case MAC_STAT_OBYTES: 427 /* 428 * The 64-bit register will reset whenever the upper 429 * 32 bits are read. So we need to read the lower 430 * 32 bits first, then read the upper 32 bits. 431 */ 432 low_val = E1000_READ_REG(hw, E1000_TOTL); 433 high_val = E1000_READ_REG(hw, E1000_TOTH); 434 *val = (uint64_t)e1000g_ksp->Toth.value.ul << 32 | 435 (uint64_t)e1000g_ksp->Totl.value.ul; 436 *val += (uint64_t)high_val << 32 | (uint64_t)low_val; 437 438 e1000g_ksp->Totl.value.ul = (uint32_t)*val; 439 e1000g_ksp->Toth.value.ul = (uint32_t)(*val >> 32); 440 break; 441 442 case MAC_STAT_OPACKETS: 443 e1000g_ksp->Tpt.value.ul += 444 E1000_READ_REG(hw, E1000_TPT); 445 *val = e1000g_ksp->Tpt.value.ul; 446 break; 447 448 case ETHER_STAT_ALIGN_ERRORS: 449 e1000g_ksp->Algnerrc.value.ul += 450 E1000_READ_REG(hw, E1000_ALGNERRC); 451 *val = e1000g_ksp->Algnerrc.value.ul; 452 break; 453 454 case ETHER_STAT_FCS_ERRORS: 455 e1000g_ksp->Crcerrs.value.ul += 456 E1000_READ_REG(hw, E1000_CRCERRS); 457 *val = e1000g_ksp->Crcerrs.value.ul; 458 break; 459 460 case ETHER_STAT_SQE_ERRORS: 461 e1000g_ksp->Sec.value.ul += 462 E1000_READ_REG(hw, E1000_SEC); 463 *val = e1000g_ksp->Sec.value.ul; 464 break; 465 466 case ETHER_STAT_CARRIER_ERRORS: 467 e1000g_ksp->Cexterr.value.ul += 468 E1000_READ_REG(hw, E1000_CEXTERR); 469 *val = e1000g_ksp->Cexterr.value.ul; 470 break; 471 472 case ETHER_STAT_EX_COLLISIONS: 473 e1000g_ksp->Ecol.value.ul += 474 e1000g_read_phy_stat(hw, E1000_ECOL); 475 *val = e1000g_ksp->Ecol.value.ul; 476 break; 477 478 case ETHER_STAT_TX_LATE_COLLISIONS: 479 e1000g_ksp->Latecol.value.ul += 480 e1000g_read_phy_stat(hw, E1000_LATECOL); 481 *val = e1000g_ksp->Latecol.value.ul; 482 break; 483 484 case ETHER_STAT_DEFER_XMTS: 485 e1000g_ksp->Dc.value.ul += 486 e1000g_read_phy_stat(hw, E1000_DC); 487 *val = e1000g_ksp->Dc.value.ul; 488 break; 489 490 case ETHER_STAT_FIRST_COLLISIONS: 491 e1000g_ksp->Scc.value.ul += 492 e1000g_read_phy_stat(hw, E1000_SCC); 493 *val = e1000g_ksp->Scc.value.ul; 494 break; 495 496 case ETHER_STAT_MULTI_COLLISIONS: 497 e1000g_ksp->Mcc.value.ul += 498 e1000g_read_phy_stat(hw, E1000_MCC); 499 *val = e1000g_ksp->Mcc.value.ul; 500 break; 501 502 case ETHER_STAT_MACRCV_ERRORS: 503 e1000g_ksp->Rxerrc.value.ul += 504 E1000_READ_REG(hw, E1000_RXERRC); 505 *val = e1000g_ksp->Rxerrc.value.ul; 506 break; 507 508 case ETHER_STAT_MACXMT_ERRORS: 509 e1000g_ksp->Ecol.value.ul += 510 e1000g_read_phy_stat(hw, E1000_ECOL); 511 *val = e1000g_ksp->Ecol.value.ul; 512 break; 513 514 case ETHER_STAT_TOOLONG_ERRORS: 515 e1000g_ksp->Roc.value.ul += 516 E1000_READ_REG(hw, E1000_ROC); 517 *val = e1000g_ksp->Roc.value.ul; 518 break; 519 520 case ETHER_STAT_XCVR_ADDR: 521 /* The Internal PHY's MDI address for each MAC is 1 */ 522 *val = 1; 523 break; 524 525 case ETHER_STAT_XCVR_ID: 526 *val = hw->phy.id | hw->phy.revision; 527 break; 528 529 case ETHER_STAT_XCVR_INUSE: 530 switch (Adapter->link_speed) { 531 case SPEED_1000: 532 *val = 533 (hw->phy.media_type == e1000_media_type_copper) ? 534 XCVR_1000T : XCVR_1000X; 535 break; 536 case SPEED_100: 537 *val = 538 (hw->phy.media_type == e1000_media_type_copper) ? 539 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 540 XCVR_100T4 : XCVR_100T2 : XCVR_100X; 541 break; 542 case SPEED_10: 543 *val = XCVR_10; 544 break; 545 default: 546 *val = XCVR_NONE; 547 break; 548 } 549 break; 550 551 case ETHER_STAT_CAP_1000FDX: 552 *val = Adapter->param_1000fdx_cap; 553 break; 554 555 case ETHER_STAT_CAP_1000HDX: 556 *val = Adapter->param_1000hdx_cap; 557 break; 558 559 case ETHER_STAT_CAP_100FDX: 560 *val = Adapter->param_100fdx_cap; 561 break; 562 563 case ETHER_STAT_CAP_100HDX: 564 *val = Adapter->param_100hdx_cap; 565 break; 566 567 case ETHER_STAT_CAP_10FDX: 568 *val = Adapter->param_10fdx_cap; 569 break; 570 571 case ETHER_STAT_CAP_10HDX: 572 *val = Adapter->param_10hdx_cap; 573 break; 574 575 case ETHER_STAT_CAP_ASMPAUSE: 576 *val = Adapter->param_asym_pause_cap; 577 break; 578 579 case ETHER_STAT_CAP_PAUSE: 580 *val = Adapter->param_pause_cap; 581 break; 582 583 case ETHER_STAT_CAP_AUTONEG: 584 *val = Adapter->param_autoneg_cap; 585 break; 586 587 case ETHER_STAT_ADV_CAP_1000FDX: 588 *val = Adapter->param_adv_1000fdx; 589 break; 590 591 case ETHER_STAT_ADV_CAP_1000HDX: 592 *val = Adapter->param_adv_1000hdx; 593 break; 594 595 case ETHER_STAT_ADV_CAP_100FDX: 596 *val = Adapter->param_adv_100fdx; 597 break; 598 599 case ETHER_STAT_ADV_CAP_100HDX: 600 *val = Adapter->param_adv_100hdx; 601 break; 602 603 case ETHER_STAT_ADV_CAP_10FDX: 604 *val = Adapter->param_adv_10fdx; 605 break; 606 607 case ETHER_STAT_ADV_CAP_10HDX: 608 *val = Adapter->param_adv_10hdx; 609 break; 610 611 case ETHER_STAT_ADV_CAP_ASMPAUSE: 612 *val = Adapter->param_adv_asym_pause; 613 break; 614 615 case ETHER_STAT_ADV_CAP_PAUSE: 616 *val = Adapter->param_adv_pause; 617 break; 618 619 case ETHER_STAT_ADV_CAP_AUTONEG: 620 *val = hw->mac.autoneg; 621 break; 622 623 case ETHER_STAT_LP_CAP_1000FDX: 624 *val = Adapter->param_lp_1000fdx; 625 break; 626 627 case ETHER_STAT_LP_CAP_1000HDX: 628 *val = Adapter->param_lp_1000hdx; 629 break; 630 631 case ETHER_STAT_LP_CAP_100FDX: 632 *val = Adapter->param_lp_100fdx; 633 break; 634 635 case ETHER_STAT_LP_CAP_100HDX: 636 *val = Adapter->param_lp_100hdx; 637 break; 638 639 case ETHER_STAT_LP_CAP_10FDX: 640 *val = Adapter->param_lp_10fdx; 641 break; 642 643 case ETHER_STAT_LP_CAP_10HDX: 644 *val = Adapter->param_lp_10hdx; 645 break; 646 647 case ETHER_STAT_LP_CAP_ASMPAUSE: 648 *val = Adapter->param_lp_asym_pause; 649 break; 650 651 case ETHER_STAT_LP_CAP_PAUSE: 652 *val = Adapter->param_lp_pause; 653 break; 654 655 case ETHER_STAT_LP_CAP_AUTONEG: 656 *val = Adapter->param_lp_autoneg; 657 break; 658 659 case ETHER_STAT_LINK_ASMPAUSE: 660 *val = Adapter->param_asym_pause_cap; 661 break; 662 663 case ETHER_STAT_LINK_PAUSE: 664 *val = Adapter->param_pause_cap; 665 break; 666 667 case ETHER_STAT_LINK_AUTONEG: 668 *val = hw->mac.autoneg; 669 break; 670 671 case ETHER_STAT_LINK_DUPLEX: 672 *val = (Adapter->link_duplex == FULL_DUPLEX) ? 673 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 674 break; 675 676 case ETHER_STAT_CAP_100T4: 677 *val = Adapter->param_100t4_cap; 678 break; 679 680 case ETHER_STAT_ADV_CAP_100T4: 681 *val = Adapter->param_adv_100t4; 682 break; 683 684 case ETHER_STAT_LP_CAP_100T4: 685 *val = Adapter->param_lp_100t4; 686 break; 687 688 default: 689 rw_exit(&Adapter->chip_lock); 690 return (ENOTSUP); 691 } 692 693 rw_exit(&Adapter->chip_lock); 694 695 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 696 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_UNAFFECTED); 697 return (EIO); 698 } 699 700 return (0); 701 } 702 703 /* 704 * e1000g_init_stats - initialize kstat data structures 705 * 706 * This routine will create and initialize the driver private 707 * statistics counters. 708 */ 709 int 710 e1000g_init_stats(struct e1000g *Adapter) 711 { 712 kstat_t *ksp; 713 p_e1000g_stat_t e1000g_ksp; 714 715 /* 716 * Create and init kstat 717 */ 718 ksp = kstat_create(WSNAME, ddi_get_instance(Adapter->dip), 719 "statistics", "net", KSTAT_TYPE_NAMED, 720 sizeof (e1000g_stat_t) / sizeof (kstat_named_t), 0); 721 722 if (ksp == NULL) { 723 e1000g_log(Adapter, CE_WARN, 724 "Could not create kernel statistics\n"); 725 return (DDI_FAILURE); 726 } 727 728 Adapter->e1000g_ksp = ksp; /* Fill in the Adapters ksp */ 729 730 e1000g_ksp = (p_e1000g_stat_t)ksp->ks_data; 731 732 /* 733 * Initialize all the statistics 734 */ 735 kstat_named_init(&e1000g_ksp->link_speed, "link_speed", 736 KSTAT_DATA_ULONG); 737 kstat_named_init(&e1000g_ksp->reset_count, "Reset Count", 738 KSTAT_DATA_ULONG); 739 740 kstat_named_init(&e1000g_ksp->rx_error, "Rx Error", 741 KSTAT_DATA_ULONG); 742 kstat_named_init(&e1000g_ksp->rx_allocb_fail, "Rx Allocb Failure", 743 KSTAT_DATA_ULONG); 744 kstat_named_init(&e1000g_ksp->rx_size_error, "Rx Size Error", 745 KSTAT_DATA_ULONG); 746 747 kstat_named_init(&e1000g_ksp->tx_no_desc, "Tx No Desc", 748 KSTAT_DATA_ULONG); 749 kstat_named_init(&e1000g_ksp->tx_no_swpkt, "Tx No Buffer", 750 KSTAT_DATA_ULONG); 751 kstat_named_init(&e1000g_ksp->tx_send_fail, "Tx Send Failure", 752 KSTAT_DATA_ULONG); 753 kstat_named_init(&e1000g_ksp->tx_over_size, "Tx Pkt Over Size", 754 KSTAT_DATA_ULONG); 755 kstat_named_init(&e1000g_ksp->tx_reschedule, "Tx Reschedule", 756 KSTAT_DATA_ULONG); 757 758 kstat_named_init(&e1000g_ksp->Mpc, "Recv_Missed_Packets", 759 KSTAT_DATA_ULONG); 760 kstat_named_init(&e1000g_ksp->Symerrs, "Recv_Symbol_Errors", 761 KSTAT_DATA_ULONG); 762 kstat_named_init(&e1000g_ksp->Rlec, "Recv_Length_Errors", 763 KSTAT_DATA_ULONG); 764 kstat_named_init(&e1000g_ksp->Xonrxc, "XONs_Recvd", 765 KSTAT_DATA_ULONG); 766 kstat_named_init(&e1000g_ksp->Xontxc, "XONs_Xmitd", 767 KSTAT_DATA_ULONG); 768 kstat_named_init(&e1000g_ksp->Xoffrxc, "XOFFs_Recvd", 769 KSTAT_DATA_ULONG); 770 kstat_named_init(&e1000g_ksp->Xofftxc, "XOFFs_Xmitd", 771 KSTAT_DATA_ULONG); 772 kstat_named_init(&e1000g_ksp->Fcruc, "Recv_Unsupport_FC_Pkts", 773 KSTAT_DATA_ULONG); 774 #ifdef E1000G_DEBUG 775 kstat_named_init(&e1000g_ksp->Prc64, "Pkts_Recvd_( 64b)", 776 KSTAT_DATA_ULONG); 777 kstat_named_init(&e1000g_ksp->Prc127, "Pkts_Recvd_( 65- 127b)", 778 KSTAT_DATA_ULONG); 779 kstat_named_init(&e1000g_ksp->Prc255, "Pkts_Recvd_( 127- 255b)", 780 KSTAT_DATA_ULONG); 781 kstat_named_init(&e1000g_ksp->Prc511, "Pkts_Recvd_( 256- 511b)", 782 KSTAT_DATA_ULONG); 783 kstat_named_init(&e1000g_ksp->Prc1023, "Pkts_Recvd_( 511-1023b)", 784 KSTAT_DATA_ULONG); 785 kstat_named_init(&e1000g_ksp->Prc1522, "Pkts_Recvd_(1024-1522b)", 786 KSTAT_DATA_ULONG); 787 #endif 788 kstat_named_init(&e1000g_ksp->Gprc, "Good_Pkts_Recvd", 789 KSTAT_DATA_ULONG); 790 kstat_named_init(&e1000g_ksp->Gptc, "Good_Pkts_Xmitd", 791 KSTAT_DATA_ULONG); 792 kstat_named_init(&e1000g_ksp->Gorl, "Good_Octets_Recvd_Lo", 793 KSTAT_DATA_ULONG); 794 kstat_named_init(&e1000g_ksp->Gorh, "Good_Octets_Recvd_Hi", 795 KSTAT_DATA_ULONG); 796 kstat_named_init(&e1000g_ksp->Gotl, "Good_Octets_Xmitd_Lo", 797 KSTAT_DATA_ULONG); 798 kstat_named_init(&e1000g_ksp->Goth, "Good_Octets_Xmitd_Hi", 799 KSTAT_DATA_ULONG); 800 kstat_named_init(&e1000g_ksp->Ruc, "Recv_Undersize", 801 KSTAT_DATA_ULONG); 802 kstat_named_init(&e1000g_ksp->Rfc, "Recv_Frag", 803 KSTAT_DATA_ULONG); 804 kstat_named_init(&e1000g_ksp->Roc, "Recv_Oversize", 805 KSTAT_DATA_ULONG); 806 kstat_named_init(&e1000g_ksp->Rjc, "Recv_Jabber", 807 KSTAT_DATA_ULONG); 808 kstat_named_init(&e1000g_ksp->Torl, "Total_Octets_Recvd_Lo", 809 KSTAT_DATA_ULONG); 810 kstat_named_init(&e1000g_ksp->Torh, "Total_Octets_Recvd_Hi", 811 KSTAT_DATA_ULONG); 812 kstat_named_init(&e1000g_ksp->Totl, "Total_Octets_Xmitd_Lo", 813 KSTAT_DATA_ULONG); 814 kstat_named_init(&e1000g_ksp->Toth, "Total_Octets_Xmitd_Hi", 815 KSTAT_DATA_ULONG); 816 kstat_named_init(&e1000g_ksp->Tpr, "Total_Packets_Recvd", 817 KSTAT_DATA_ULONG); 818 kstat_named_init(&e1000g_ksp->Tpt, "Total_Packets_Xmitd", 819 KSTAT_DATA_ULONG); 820 #ifdef E1000G_DEBUG 821 kstat_named_init(&e1000g_ksp->Ptc64, "Pkts_Xmitd_( 64b)", 822 KSTAT_DATA_ULONG); 823 kstat_named_init(&e1000g_ksp->Ptc127, "Pkts_Xmitd_( 65- 127b)", 824 KSTAT_DATA_ULONG); 825 kstat_named_init(&e1000g_ksp->Ptc255, "Pkts_Xmitd_( 128- 255b)", 826 KSTAT_DATA_ULONG); 827 kstat_named_init(&e1000g_ksp->Ptc511, "Pkts_Xmitd_( 255- 511b)", 828 KSTAT_DATA_ULONG); 829 kstat_named_init(&e1000g_ksp->Ptc1023, "Pkts_Xmitd_( 512-1023b)", 830 KSTAT_DATA_ULONG); 831 kstat_named_init(&e1000g_ksp->Ptc1522, "Pkts_Xmitd_(1024-1522b)", 832 KSTAT_DATA_ULONG); 833 #endif 834 kstat_named_init(&e1000g_ksp->Tncrs, "Xmit_with_No_CRS", 835 KSTAT_DATA_ULONG); 836 kstat_named_init(&e1000g_ksp->Tsctc, "Xmit_TCP_Seg_Contexts", 837 KSTAT_DATA_ULONG); 838 kstat_named_init(&e1000g_ksp->Tsctfc, "Xmit_TCP_Seg_Contexts_Fail", 839 KSTAT_DATA_ULONG); 840 841 #ifdef E1000G_DEBUG 842 kstat_named_init(&e1000g_ksp->rx_none, "Rx No Data", 843 KSTAT_DATA_ULONG); 844 kstat_named_init(&e1000g_ksp->rx_multi_desc, "Rx Span Multi Desc", 845 KSTAT_DATA_ULONG); 846 kstat_named_init(&e1000g_ksp->rx_no_freepkt, "Rx Freelist Empty", 847 KSTAT_DATA_ULONG); 848 kstat_named_init(&e1000g_ksp->rx_avail_freepkt, "Rx Freelist Avail", 849 KSTAT_DATA_ULONG); 850 851 kstat_named_init(&e1000g_ksp->tx_under_size, "Tx Pkt Under Size", 852 KSTAT_DATA_ULONG); 853 kstat_named_init(&e1000g_ksp->tx_exceed_frags, "Tx Exceed Max Frags", 854 KSTAT_DATA_ULONG); 855 kstat_named_init(&e1000g_ksp->tx_empty_frags, "Tx Empty Frags", 856 KSTAT_DATA_ULONG); 857 kstat_named_init(&e1000g_ksp->tx_recycle, "Tx Recycle", 858 KSTAT_DATA_ULONG); 859 kstat_named_init(&e1000g_ksp->tx_recycle_intr, "Tx Recycle Intr", 860 KSTAT_DATA_ULONG); 861 kstat_named_init(&e1000g_ksp->tx_recycle_retry, "Tx Recycle Retry", 862 KSTAT_DATA_ULONG); 863 kstat_named_init(&e1000g_ksp->tx_recycle_none, "Tx Recycled None", 864 KSTAT_DATA_ULONG); 865 kstat_named_init(&e1000g_ksp->tx_copy, "Tx Send Copy", 866 KSTAT_DATA_ULONG); 867 kstat_named_init(&e1000g_ksp->tx_bind, "Tx Send Bind", 868 KSTAT_DATA_ULONG); 869 kstat_named_init(&e1000g_ksp->tx_multi_copy, "Tx Copy Multi Frags", 870 KSTAT_DATA_ULONG); 871 kstat_named_init(&e1000g_ksp->tx_multi_cookie, "Tx Bind Multi Cookies", 872 KSTAT_DATA_ULONG); 873 kstat_named_init(&e1000g_ksp->tx_lack_desc, "Tx Desc Insufficient", 874 KSTAT_DATA_ULONG); 875 #endif 876 877 /* 878 * Function to provide kernel stat update on demand 879 */ 880 ksp->ks_update = e1000g_update_stats; 881 882 /* 883 * Pointer into provider's raw statistics 884 */ 885 ksp->ks_private = (void *)Adapter; 886 887 /* 888 * Add kstat to systems kstat chain 889 */ 890 kstat_install(ksp); 891 892 return (DDI_SUCCESS); 893 } 894 895 /* 896 * e1000g_read_phy_stat - read certain PHY statistics 897 * 898 * Certain statistics are read from MAC registers on some silicon types 899 * but are read from the PHY on other silicon types. This routine 900 * handles that difference as needed. 901 */ 902 static uint32_t 903 e1000g_read_phy_stat(struct e1000_hw *hw, int reg) 904 { 905 uint16_t phy_low, phy_high; 906 uint32_t val; 907 908 /* get statistic from PHY in these cases */ 909 if ((hw->phy.type == e1000_phy_82578) || 910 (hw->phy.type == e1000_phy_82577)) { 911 912 switch (reg) { 913 case E1000_SCC: 914 (void) e1000_read_phy_reg(hw, HV_SCC_UPPER, &phy_high); 915 (void) e1000_read_phy_reg(hw, HV_SCC_LOWER, &phy_low); 916 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 917 break; 918 919 case E1000_MCC: 920 (void) e1000_read_phy_reg(hw, HV_MCC_UPPER, &phy_high); 921 (void) e1000_read_phy_reg(hw, HV_MCC_LOWER, &phy_low); 922 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 923 break; 924 925 case E1000_ECOL: 926 (void) e1000_read_phy_reg(hw, HV_ECOL_UPPER, &phy_high); 927 (void) e1000_read_phy_reg(hw, HV_ECOL_LOWER, &phy_low); 928 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 929 break; 930 931 case E1000_COLC: 932 (void) e1000_read_phy_reg(hw, HV_COLC_UPPER, &phy_high); 933 (void) e1000_read_phy_reg(hw, HV_COLC_LOWER, &phy_low); 934 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 935 break; 936 937 case E1000_LATECOL: 938 (void) e1000_read_phy_reg(hw, HV_LATECOL_UPPER, 939 &phy_high); 940 (void) e1000_read_phy_reg(hw, HV_LATECOL_LOWER, 941 &phy_low); 942 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 943 break; 944 945 case E1000_DC: 946 (void) e1000_read_phy_reg(hw, HV_DC_UPPER, &phy_high); 947 (void) e1000_read_phy_reg(hw, HV_DC_LOWER, &phy_low); 948 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 949 break; 950 951 case E1000_TNCRS: 952 (void) e1000_read_phy_reg(hw, HV_TNCRS_UPPER, 953 &phy_high); 954 (void) e1000_read_phy_reg(hw, HV_TNCRS_LOWER, 955 &phy_low); 956 val = ((uint32_t)phy_high << 16) | (uint32_t)phy_low; 957 break; 958 959 default: 960 break; 961 } 962 963 /* get statistic from MAC otherwise */ 964 } else { 965 val = E1000_READ_REG(hw, reg); 966 } 967 968 return (val); 969 } 970