1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: e1000g_stat.c * 32 * * 33 * Abstract: Functions for processing statistics * 34 * * 35 * ********************************************************************** 36 */ 37 #include "e1000g_sw.h" 38 #include "e1000g_debug.h" 39 40 static int e1000g_update_stats(kstat_t *ksp, int rw); 41 42 /* 43 * e1000_tbi_adjust_stats 44 * 45 * Adjusts statistic counters when a frame is accepted 46 * under the TBI workaround. This function has been 47 * adapted for Solaris from shared code. 48 */ 49 void 50 e1000_tbi_adjust_stats(struct e1000g *Adapter, 51 uint32_t frame_len, uint8_t *mac_addr) 52 { 53 struct e1000_hw *hw = &Adapter->shared; 54 uint32_t carry_bit; 55 p_e1000g_stat_t e1000g_ksp; 56 57 e1000g_ksp = (p_e1000g_stat_t)Adapter->e1000g_ksp->ks_data; 58 59 /* First adjust the frame length */ 60 frame_len--; 61 62 /* 63 * We need to adjust the statistics counters, since the hardware 64 * counters overcount this packet as a CRC error and undercount 65 * the packet as a good packet 66 */ 67 /* This packet should not be counted as a CRC error */ 68 e1000g_ksp->Crcerrs.value.ul--; 69 /* This packet does count as a Good Packet Received */ 70 e1000g_ksp->Gprc.value.ul++; 71 72 /* 73 * Adjust the Good Octets received counters 74 */ 75 carry_bit = 0x80000000 & e1000g_ksp->Gorl.value.ul; 76 e1000g_ksp->Gorl.value.ul += frame_len; 77 /* 78 * If the high bit of Gorcl (the low 32 bits of the Good Octets 79 * Received Count) was one before the addition, 80 * AND it is zero after, then we lost the carry out, 81 * need to add one to Gorch (Good Octets Received Count High). 82 * This could be simplified if all environments supported 83 * 64-bit integers. 84 */ 85 if (carry_bit && ((e1000g_ksp->Gorl.value.ul & 0x80000000) == 0)) { 86 e1000g_ksp->Gorh.value.ul++; 87 } 88 /* 89 * Is this a broadcast or multicast? Check broadcast first, 90 * since the test for a multicast frame will test positive on 91 * a broadcast frame. 92 */ 93 if ((mac_addr[0] == (uint8_t)0xff) && 94 (mac_addr[1] == (uint8_t)0xff)) { 95 /* 96 * Broadcast packet 97 */ 98 e1000g_ksp->Bprc.value.ul++; 99 } else if (*mac_addr & 0x01) { 100 /* 101 * Multicast packet 102 */ 103 e1000g_ksp->Mprc.value.ul++; 104 } 105 106 if (frame_len == hw->mac.max_frame_size) { 107 /* 108 * In this case, the hardware has overcounted the number of 109 * oversize frames. 110 */ 111 if (e1000g_ksp->Roc.value.ul > 0) 112 e1000g_ksp->Roc.value.ul--; 113 } 114 115 /* 116 * Adjust the bin counters when the extra byte put the frame in the 117 * wrong bin. Remember that the frame_len was adjusted above. 118 */ 119 if (frame_len == 64) { 120 e1000g_ksp->Prc64.value.ul++; 121 e1000g_ksp->Prc127.value.ul--; 122 } else if (frame_len == 127) { 123 e1000g_ksp->Prc127.value.ul++; 124 e1000g_ksp->Prc255.value.ul--; 125 } else if (frame_len == 255) { 126 e1000g_ksp->Prc255.value.ul++; 127 e1000g_ksp->Prc511.value.ul--; 128 } else if (frame_len == 511) { 129 e1000g_ksp->Prc511.value.ul++; 130 e1000g_ksp->Prc1023.value.ul--; 131 } else if (frame_len == 1023) { 132 e1000g_ksp->Prc1023.value.ul++; 133 e1000g_ksp->Prc1522.value.ul--; 134 } else if (frame_len == 1522) { 135 e1000g_ksp->Prc1522.value.ul++; 136 } 137 } 138 139 140 /* 141 * e1000g_update_stats - update driver private kstat counters 142 * 143 * This routine will dump and reset the e1000's internal 144 * statistics counters. The current stats dump values will 145 * be sent to the kernel status area. 146 */ 147 static int 148 e1000g_update_stats(kstat_t *ksp, int rw) 149 { 150 struct e1000g *Adapter; 151 struct e1000_hw *hw; 152 p_e1000g_stat_t e1000g_ksp; 153 e1000g_tx_ring_t *tx_ring; 154 e1000g_rx_ring_t *rx_ring; 155 uint64_t val; 156 uint32_t low_val, high_val; 157 158 if (rw == KSTAT_WRITE) 159 return (EACCES); 160 161 Adapter = (struct e1000g *)ksp->ks_private; 162 ASSERT(Adapter != NULL); 163 e1000g_ksp = (p_e1000g_stat_t)ksp->ks_data; 164 ASSERT(e1000g_ksp != NULL); 165 hw = &Adapter->shared; 166 167 tx_ring = Adapter->tx_ring; 168 rx_ring = Adapter->rx_ring; 169 170 rw_enter(&Adapter->chip_lock, RW_WRITER); 171 172 e1000g_ksp->link_speed.value.ul = Adapter->link_speed; 173 e1000g_ksp->reset_count.value.ul = Adapter->reset_count; 174 175 e1000g_ksp->rx_error.value.ul = rx_ring->stat_error; 176 e1000g_ksp->rx_esballoc_fail.value.ul = rx_ring->stat_esballoc_fail; 177 e1000g_ksp->rx_allocb_fail.value.ul = rx_ring->stat_allocb_fail; 178 e1000g_ksp->rx_exceed_pkt.value.ul = rx_ring->stat_exceed_pkt; 179 180 e1000g_ksp->tx_no_swpkt.value.ul = tx_ring->stat_no_swpkt; 181 e1000g_ksp->tx_no_desc.value.ul = tx_ring->stat_no_desc; 182 e1000g_ksp->tx_send_fail.value.ul = tx_ring->stat_send_fail; 183 e1000g_ksp->tx_reschedule.value.ul = tx_ring->stat_reschedule; 184 e1000g_ksp->tx_over_size.value.ul = tx_ring->stat_over_size; 185 186 #ifdef E1000G_DEBUG 187 e1000g_ksp->rx_none.value.ul = rx_ring->stat_none; 188 e1000g_ksp->rx_multi_desc.value.ul = rx_ring->stat_multi_desc; 189 e1000g_ksp->rx_no_freepkt.value.ul = rx_ring->stat_no_freepkt; 190 e1000g_ksp->rx_avail_freepkt.value.ul = rx_ring->avail_freepkt; 191 192 e1000g_ksp->tx_under_size.value.ul = tx_ring->stat_under_size; 193 e1000g_ksp->tx_exceed_frags.value.ul = tx_ring->stat_exceed_frags; 194 e1000g_ksp->tx_empty_frags.value.ul = tx_ring->stat_empty_frags; 195 e1000g_ksp->tx_recycle.value.ul = tx_ring->stat_recycle; 196 e1000g_ksp->tx_recycle_intr.value.ul = tx_ring->stat_recycle_intr; 197 e1000g_ksp->tx_recycle_retry.value.ul = tx_ring->stat_recycle_retry; 198 e1000g_ksp->tx_recycle_none.value.ul = tx_ring->stat_recycle_none; 199 e1000g_ksp->tx_copy.value.ul = tx_ring->stat_copy; 200 e1000g_ksp->tx_bind.value.ul = tx_ring->stat_bind; 201 e1000g_ksp->tx_multi_copy.value.ul = tx_ring->stat_multi_copy; 202 e1000g_ksp->tx_multi_cookie.value.ul = tx_ring->stat_multi_cookie; 203 e1000g_ksp->tx_lack_desc.value.ul = tx_ring->stat_lack_desc; 204 #endif 205 206 /* 207 * Standard Stats 208 */ 209 e1000g_ksp->Mpc.value.ul += E1000_READ_REG(hw, E1000_MPC); 210 e1000g_ksp->Rlec.value.ul += E1000_READ_REG(hw, E1000_RLEC); 211 e1000g_ksp->Xonrxc.value.ul += E1000_READ_REG(hw, E1000_XONRXC); 212 e1000g_ksp->Xontxc.value.ul += E1000_READ_REG(hw, E1000_XONTXC); 213 e1000g_ksp->Xoffrxc.value.ul += E1000_READ_REG(hw, E1000_XOFFRXC); 214 e1000g_ksp->Xofftxc.value.ul += E1000_READ_REG(hw, E1000_XOFFTXC); 215 e1000g_ksp->Fcruc.value.ul += E1000_READ_REG(hw, E1000_FCRUC); 216 217 if ((hw->mac.type != e1000_ich8lan) && 218 (hw->mac.type != e1000_ich9lan)) { 219 e1000g_ksp->Symerrs.value.ul += 220 E1000_READ_REG(hw, E1000_SYMERRS); 221 222 e1000g_ksp->Prc64.value.ul += 223 E1000_READ_REG(hw, E1000_PRC64); 224 e1000g_ksp->Prc127.value.ul += 225 E1000_READ_REG(hw, E1000_PRC127); 226 e1000g_ksp->Prc255.value.ul += 227 E1000_READ_REG(hw, E1000_PRC255); 228 e1000g_ksp->Prc511.value.ul += 229 E1000_READ_REG(hw, E1000_PRC511); 230 e1000g_ksp->Prc1023.value.ul += 231 E1000_READ_REG(hw, E1000_PRC1023); 232 e1000g_ksp->Prc1522.value.ul += 233 E1000_READ_REG(hw, E1000_PRC1522); 234 235 e1000g_ksp->Ptc64.value.ul += 236 E1000_READ_REG(hw, E1000_PTC64); 237 e1000g_ksp->Ptc127.value.ul += 238 E1000_READ_REG(hw, E1000_PTC127); 239 e1000g_ksp->Ptc255.value.ul += 240 E1000_READ_REG(hw, E1000_PTC255); 241 e1000g_ksp->Ptc511.value.ul += 242 E1000_READ_REG(hw, E1000_PTC511); 243 e1000g_ksp->Ptc1023.value.ul += 244 E1000_READ_REG(hw, E1000_PTC1023); 245 e1000g_ksp->Ptc1522.value.ul += 246 E1000_READ_REG(hw, E1000_PTC1522); 247 } 248 249 e1000g_ksp->Gprc.value.ul += E1000_READ_REG(hw, E1000_GPRC); 250 e1000g_ksp->Gptc.value.ul += E1000_READ_REG(hw, E1000_GPTC); 251 e1000g_ksp->Ruc.value.ul += E1000_READ_REG(hw, E1000_RUC); 252 e1000g_ksp->Rfc.value.ul += E1000_READ_REG(hw, E1000_RFC); 253 e1000g_ksp->Roc.value.ul += E1000_READ_REG(hw, E1000_ROC); 254 e1000g_ksp->Rjc.value.ul += E1000_READ_REG(hw, E1000_RJC); 255 e1000g_ksp->Tpr.value.ul += E1000_READ_REG(hw, E1000_TPR); 256 e1000g_ksp->Tncrs.value.ul += E1000_READ_REG(hw, E1000_TNCRS); 257 e1000g_ksp->Tsctc.value.ul += E1000_READ_REG(hw, E1000_TSCTC); 258 e1000g_ksp->Tsctfc.value.ul += E1000_READ_REG(hw, E1000_TSCTFC); 259 260 /* 261 * Adaptive Calculations 262 */ 263 hw->mac.tx_packet_delta = E1000_READ_REG(hw, E1000_TPT); 264 e1000g_ksp->Tpt.value.ul += hw->mac.tx_packet_delta; 265 266 /* 267 * The 64-bit register will reset whenever the upper 268 * 32 bits are read. So we need to read the lower 269 * 32 bits first, then read the upper 32 bits. 270 */ 271 low_val = E1000_READ_REG(hw, E1000_GORCL); 272 high_val = E1000_READ_REG(hw, E1000_GORCH); 273 val = (uint64_t)e1000g_ksp->Gorh.value.ul << 32 | 274 (uint64_t)e1000g_ksp->Gorl.value.ul; 275 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 276 e1000g_ksp->Gorl.value.ul = (uint32_t)val; 277 e1000g_ksp->Gorh.value.ul = (uint32_t)(val >> 32); 278 279 low_val = E1000_READ_REG(hw, E1000_GOTCL); 280 high_val = E1000_READ_REG(hw, E1000_GOTCH); 281 val = (uint64_t)e1000g_ksp->Goth.value.ul << 32 | 282 (uint64_t)e1000g_ksp->Gotl.value.ul; 283 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 284 e1000g_ksp->Gotl.value.ul = (uint32_t)val; 285 e1000g_ksp->Goth.value.ul = (uint32_t)(val >> 32); 286 287 low_val = E1000_READ_REG(hw, E1000_TORL); 288 high_val = E1000_READ_REG(hw, E1000_TORH); 289 val = (uint64_t)e1000g_ksp->Torh.value.ul << 32 | 290 (uint64_t)e1000g_ksp->Torl.value.ul; 291 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 292 e1000g_ksp->Torl.value.ul = (uint32_t)val; 293 e1000g_ksp->Torh.value.ul = (uint32_t)(val >> 32); 294 295 low_val = E1000_READ_REG(hw, E1000_TOTL); 296 high_val = E1000_READ_REG(hw, E1000_TOTH); 297 val = (uint64_t)e1000g_ksp->Toth.value.ul << 32 | 298 (uint64_t)e1000g_ksp->Totl.value.ul; 299 val += (uint64_t)high_val << 32 | (uint64_t)low_val; 300 e1000g_ksp->Totl.value.ul = (uint32_t)val; 301 e1000g_ksp->Toth.value.ul = (uint32_t)(val >> 32); 302 303 rw_exit(&Adapter->chip_lock); 304 305 return (0); 306 } 307 308 int 309 e1000g_m_stat(void *arg, uint_t stat, uint64_t *val) 310 { 311 struct e1000g *Adapter = (struct e1000g *)arg; 312 struct e1000_hw *hw = &Adapter->shared; 313 p_e1000g_stat_t e1000g_ksp; 314 uint32_t low_val, high_val; 315 uint16_t phy_reg, phy_reg_2; 316 317 e1000g_ksp = (p_e1000g_stat_t)Adapter->e1000g_ksp->ks_data; 318 319 rw_enter(&Adapter->chip_lock, RW_WRITER); 320 321 switch (stat) { 322 case MAC_STAT_IFSPEED: 323 *val = Adapter->link_speed * 1000000ull; 324 break; 325 326 case MAC_STAT_MULTIRCV: 327 e1000g_ksp->Mprc.value.ul += 328 E1000_READ_REG(hw, E1000_MPRC); 329 *val = e1000g_ksp->Mprc.value.ul; 330 break; 331 332 case MAC_STAT_BRDCSTRCV: 333 e1000g_ksp->Bprc.value.ul += 334 E1000_READ_REG(hw, E1000_BPRC); 335 *val = e1000g_ksp->Bprc.value.ul; 336 break; 337 338 case MAC_STAT_MULTIXMT: 339 e1000g_ksp->Mptc.value.ul += 340 E1000_READ_REG(hw, E1000_MPTC); 341 *val = e1000g_ksp->Mptc.value.ul; 342 break; 343 344 case MAC_STAT_BRDCSTXMT: 345 e1000g_ksp->Bptc.value.ul += 346 E1000_READ_REG(hw, E1000_BPTC); 347 *val = e1000g_ksp->Bptc.value.ul; 348 break; 349 350 case MAC_STAT_NORCVBUF: 351 e1000g_ksp->Rnbc.value.ul += 352 E1000_READ_REG(hw, E1000_RNBC); 353 *val = e1000g_ksp->Rnbc.value.ul; 354 break; 355 356 case MAC_STAT_IERRORS: 357 e1000g_ksp->Rxerrc.value.ul += 358 E1000_READ_REG(hw, E1000_RXERRC); 359 e1000g_ksp->Algnerrc.value.ul += 360 E1000_READ_REG(hw, E1000_ALGNERRC); 361 e1000g_ksp->Rlec.value.ul += 362 E1000_READ_REG(hw, E1000_RLEC); 363 e1000g_ksp->Crcerrs.value.ul += 364 E1000_READ_REG(hw, E1000_CRCERRS); 365 e1000g_ksp->Cexterr.value.ul += 366 E1000_READ_REG(hw, E1000_CEXTERR); 367 *val = e1000g_ksp->Rxerrc.value.ul + 368 e1000g_ksp->Algnerrc.value.ul + 369 e1000g_ksp->Rlec.value.ul + 370 e1000g_ksp->Crcerrs.value.ul + 371 e1000g_ksp->Cexterr.value.ul; 372 break; 373 374 case MAC_STAT_NOXMTBUF: 375 *val = Adapter->tx_ring->stat_no_desc; 376 break; 377 378 case MAC_STAT_OERRORS: 379 e1000g_ksp->Ecol.value.ul += 380 E1000_READ_REG(hw, E1000_ECOL); 381 *val = e1000g_ksp->Ecol.value.ul; 382 break; 383 384 case MAC_STAT_COLLISIONS: 385 e1000g_ksp->Colc.value.ul += 386 E1000_READ_REG(hw, E1000_COLC); 387 *val = e1000g_ksp->Colc.value.ul; 388 break; 389 390 case MAC_STAT_RBYTES: 391 /* 392 * The 64-bit register will reset whenever the upper 393 * 32 bits are read. So we need to read the lower 394 * 32 bits first, then read the upper 32 bits. 395 */ 396 low_val = E1000_READ_REG(hw, E1000_TORL); 397 high_val = E1000_READ_REG(hw, E1000_TORH); 398 *val = (uint64_t)e1000g_ksp->Torh.value.ul << 32 | 399 (uint64_t)e1000g_ksp->Torl.value.ul; 400 *val += (uint64_t)high_val << 32 | (uint64_t)low_val; 401 402 e1000g_ksp->Torl.value.ul = (uint32_t)*val; 403 e1000g_ksp->Torh.value.ul = (uint32_t)(*val >> 32); 404 break; 405 406 case MAC_STAT_IPACKETS: 407 e1000g_ksp->Tpr.value.ul += 408 E1000_READ_REG(hw, E1000_TPR); 409 *val = e1000g_ksp->Tpr.value.ul; 410 break; 411 412 case MAC_STAT_OBYTES: 413 /* 414 * The 64-bit register will reset whenever the upper 415 * 32 bits are read. So we need to read the lower 416 * 32 bits first, then read the upper 32 bits. 417 */ 418 low_val = E1000_READ_REG(hw, E1000_TOTL); 419 high_val = E1000_READ_REG(hw, E1000_TOTH); 420 *val = (uint64_t)e1000g_ksp->Toth.value.ul << 32 | 421 (uint64_t)e1000g_ksp->Totl.value.ul; 422 *val += (uint64_t)high_val << 32 | (uint64_t)low_val; 423 424 e1000g_ksp->Totl.value.ul = (uint32_t)*val; 425 e1000g_ksp->Toth.value.ul = (uint32_t)(*val >> 32); 426 break; 427 428 case MAC_STAT_OPACKETS: 429 e1000g_ksp->Tpt.value.ul += 430 E1000_READ_REG(hw, E1000_TPT); 431 *val = e1000g_ksp->Tpt.value.ul; 432 break; 433 434 case ETHER_STAT_ALIGN_ERRORS: 435 e1000g_ksp->Algnerrc.value.ul += 436 E1000_READ_REG(hw, E1000_ALGNERRC); 437 *val = e1000g_ksp->Algnerrc.value.ul; 438 break; 439 440 case ETHER_STAT_FCS_ERRORS: 441 e1000g_ksp->Crcerrs.value.ul += 442 E1000_READ_REG(hw, E1000_CRCERRS); 443 *val = e1000g_ksp->Crcerrs.value.ul; 444 break; 445 446 case ETHER_STAT_SQE_ERRORS: 447 e1000g_ksp->Sec.value.ul += 448 E1000_READ_REG(hw, E1000_SEC); 449 *val = e1000g_ksp->Sec.value.ul; 450 break; 451 452 case ETHER_STAT_CARRIER_ERRORS: 453 e1000g_ksp->Cexterr.value.ul += 454 E1000_READ_REG(hw, E1000_CEXTERR); 455 *val = e1000g_ksp->Cexterr.value.ul; 456 break; 457 458 case ETHER_STAT_EX_COLLISIONS: 459 e1000g_ksp->Ecol.value.ul += 460 E1000_READ_REG(hw, E1000_ECOL); 461 *val = e1000g_ksp->Ecol.value.ul; 462 break; 463 464 case ETHER_STAT_TX_LATE_COLLISIONS: 465 e1000g_ksp->Latecol.value.ul += 466 E1000_READ_REG(hw, E1000_LATECOL); 467 *val = e1000g_ksp->Latecol.value.ul; 468 break; 469 470 case ETHER_STAT_DEFER_XMTS: 471 e1000g_ksp->Dc.value.ul += 472 E1000_READ_REG(hw, E1000_DC); 473 *val = e1000g_ksp->Dc.value.ul; 474 break; 475 476 case ETHER_STAT_FIRST_COLLISIONS: 477 e1000g_ksp->Scc.value.ul += 478 E1000_READ_REG(hw, E1000_SCC); 479 *val = e1000g_ksp->Scc.value.ul; 480 break; 481 482 case ETHER_STAT_MULTI_COLLISIONS: 483 e1000g_ksp->Mcc.value.ul += 484 E1000_READ_REG(hw, E1000_MCC); 485 *val = e1000g_ksp->Mcc.value.ul; 486 break; 487 488 case ETHER_STAT_MACRCV_ERRORS: 489 e1000g_ksp->Rxerrc.value.ul += 490 E1000_READ_REG(hw, E1000_RXERRC); 491 *val = e1000g_ksp->Rxerrc.value.ul; 492 break; 493 494 case ETHER_STAT_MACXMT_ERRORS: 495 e1000g_ksp->Ecol.value.ul += 496 E1000_READ_REG(hw, E1000_ECOL); 497 *val = e1000g_ksp->Ecol.value.ul; 498 break; 499 500 case ETHER_STAT_TOOLONG_ERRORS: 501 e1000g_ksp->Roc.value.ul += 502 E1000_READ_REG(hw, E1000_ROC); 503 *val = e1000g_ksp->Roc.value.ul; 504 break; 505 506 case ETHER_STAT_XCVR_ADDR: 507 /* The Internal PHY's MDI address for each MAC is 1 */ 508 *val = 1; 509 break; 510 511 case ETHER_STAT_XCVR_ID: 512 e1000_read_phy_reg(hw, PHY_ID1, &phy_reg); 513 e1000_read_phy_reg(hw, PHY_ID2, &phy_reg_2); 514 *val = (uint32_t)((phy_reg << 16) | phy_reg_2); 515 break; 516 517 case ETHER_STAT_XCVR_INUSE: 518 e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); 519 switch (Adapter->link_speed) { 520 case SPEED_1000: 521 *val = 522 (hw->media_type == e1000_media_type_copper) ? 523 XCVR_1000T : XCVR_1000X; 524 break; 525 case SPEED_100: 526 *val = 527 (hw->media_type == e1000_media_type_copper) ? 528 (phy_reg & MII_SR_100T4_CAPS) ? 529 XCVR_100T4 : XCVR_100T2 : XCVR_100X; 530 break; 531 case SPEED_10: 532 *val = XCVR_10; 533 break; 534 default: 535 *val = XCVR_NONE; 536 break; 537 } 538 break; 539 540 case ETHER_STAT_CAP_1000FDX: 541 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_reg); 542 *val = ((phy_reg & IEEE_ESR_1000T_FD_CAPS) || 543 (phy_reg & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 544 break; 545 546 case ETHER_STAT_CAP_1000HDX: 547 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_reg); 548 *val = ((phy_reg & IEEE_ESR_1000T_HD_CAPS) || 549 (phy_reg & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 550 break; 551 552 case ETHER_STAT_CAP_100FDX: 553 e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); 554 *val = ((phy_reg & MII_SR_100X_FD_CAPS) || 555 (phy_reg & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 556 break; 557 558 case ETHER_STAT_CAP_100HDX: 559 e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); 560 *val = ((phy_reg & MII_SR_100X_HD_CAPS) || 561 (phy_reg & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 562 break; 563 564 case ETHER_STAT_CAP_10FDX: 565 e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); 566 *val = (phy_reg & MII_SR_10T_FD_CAPS) ? 1 : 0; 567 break; 568 569 case ETHER_STAT_CAP_10HDX: 570 e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); 571 *val = (phy_reg & MII_SR_10T_HD_CAPS) ? 1 : 0; 572 break; 573 574 case ETHER_STAT_CAP_ASMPAUSE: 575 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 576 *val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; 577 break; 578 579 case ETHER_STAT_CAP_PAUSE: 580 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 581 *val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; 582 break; 583 584 case ETHER_STAT_CAP_AUTONEG: 585 e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg); 586 *val = (phy_reg & MII_SR_AUTONEG_CAPS) ? 1 : 0; 587 break; 588 589 case ETHER_STAT_ADV_CAP_1000FDX: 590 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_reg); 591 *val = (phy_reg & CR_1000T_FD_CAPS) ? 1 : 0; 592 break; 593 594 case ETHER_STAT_ADV_CAP_1000HDX: 595 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_reg); 596 *val = (phy_reg & CR_1000T_HD_CAPS) ? 1 : 0; 597 break; 598 599 case ETHER_STAT_ADV_CAP_100FDX: 600 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 601 *val = (phy_reg & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 602 break; 603 604 case ETHER_STAT_ADV_CAP_100HDX: 605 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 606 *val = (phy_reg & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 607 break; 608 609 case ETHER_STAT_ADV_CAP_10FDX: 610 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 611 *val = (phy_reg & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 612 break; 613 614 case ETHER_STAT_ADV_CAP_10HDX: 615 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 616 *val = (phy_reg & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 617 break; 618 619 case ETHER_STAT_ADV_CAP_ASMPAUSE: 620 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 621 *val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; 622 break; 623 624 case ETHER_STAT_ADV_CAP_PAUSE: 625 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 626 *val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; 627 break; 628 629 case ETHER_STAT_ADV_CAP_AUTONEG: 630 *val = hw->mac.autoneg; 631 break; 632 633 case ETHER_STAT_LP_CAP_1000FDX: 634 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_reg); 635 *val = (phy_reg & SR_1000T_LP_FD_CAPS) ? 1 : 0; 636 break; 637 638 case ETHER_STAT_LP_CAP_1000HDX: 639 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_reg); 640 *val = (phy_reg & SR_1000T_LP_HD_CAPS) ? 1 : 0; 641 break; 642 643 case ETHER_STAT_LP_CAP_100FDX: 644 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); 645 *val = (phy_reg & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 646 break; 647 648 case ETHER_STAT_LP_CAP_100HDX: 649 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); 650 *val = (phy_reg & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 651 break; 652 653 case ETHER_STAT_LP_CAP_10FDX: 654 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); 655 *val = (phy_reg & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 656 break; 657 658 case ETHER_STAT_LP_CAP_10HDX: 659 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); 660 *val = (phy_reg & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 661 break; 662 663 case ETHER_STAT_LP_CAP_ASMPAUSE: 664 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); 665 *val = (phy_reg & NWAY_LPAR_ASM_DIR) ? 1 : 0; 666 break; 667 668 case ETHER_STAT_LP_CAP_PAUSE: 669 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_reg); 670 *val = (phy_reg & NWAY_LPAR_PAUSE) ? 1 : 0; 671 break; 672 673 case ETHER_STAT_LP_CAP_AUTONEG: 674 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_reg); 675 *val = (phy_reg & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 676 break; 677 678 case ETHER_STAT_LINK_ASMPAUSE: 679 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 680 *val = (phy_reg & NWAY_AR_ASM_DIR) ? 1 : 0; 681 break; 682 683 case ETHER_STAT_LINK_PAUSE: 684 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_reg); 685 *val = (phy_reg & NWAY_AR_PAUSE) ? 1 : 0; 686 break; 687 688 case ETHER_STAT_LINK_AUTONEG: 689 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 690 *val = (phy_reg & MII_CR_AUTO_NEG_EN) ? 1 : 0; 691 break; 692 693 case ETHER_STAT_LINK_DUPLEX: 694 *val = (Adapter->link_duplex == FULL_DUPLEX) ? 695 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 696 break; 697 698 default: 699 rw_exit(&Adapter->chip_lock); 700 return (ENOTSUP); 701 } 702 703 rw_exit(&Adapter->chip_lock); 704 705 return (0); 706 } 707 708 /* 709 * e1000g_init_stats - initialize kstat data structures 710 * 711 * This routine will create and initialize the driver private 712 * statistics counters. 713 */ 714 int 715 e1000g_init_stats(struct e1000g *Adapter) 716 { 717 kstat_t *ksp; 718 p_e1000g_stat_t e1000g_ksp; 719 720 /* 721 * Create and init kstat 722 */ 723 ksp = kstat_create(WSNAME, ddi_get_instance(Adapter->dip), 724 "statistics", "net", KSTAT_TYPE_NAMED, 725 sizeof (e1000g_stat_t) / sizeof (kstat_named_t), 0); 726 727 if (ksp == NULL) { 728 e1000g_log(Adapter, CE_WARN, 729 "Could not create kernel statistics\n"); 730 return (DDI_FAILURE); 731 } 732 733 Adapter->e1000g_ksp = ksp; /* Fill in the Adapters ksp */ 734 735 e1000g_ksp = (p_e1000g_stat_t)ksp->ks_data; 736 737 /* 738 * Initialize all the statistics 739 */ 740 kstat_named_init(&e1000g_ksp->link_speed, "link_speed", 741 KSTAT_DATA_ULONG); 742 kstat_named_init(&e1000g_ksp->reset_count, "Reset Count", 743 KSTAT_DATA_ULONG); 744 745 kstat_named_init(&e1000g_ksp->rx_error, "Rx Error", 746 KSTAT_DATA_ULONG); 747 kstat_named_init(&e1000g_ksp->rx_esballoc_fail, "Rx Desballoc Failure", 748 KSTAT_DATA_ULONG); 749 kstat_named_init(&e1000g_ksp->rx_exceed_pkt, "Rx Exceed Max Pkt Count", 750 KSTAT_DATA_ULONG); 751 kstat_named_init(&e1000g_ksp->rx_allocb_fail, "Rx Allocb Failure", 752 KSTAT_DATA_ULONG); 753 754 kstat_named_init(&e1000g_ksp->tx_no_desc, "Tx No Desc", 755 KSTAT_DATA_ULONG); 756 kstat_named_init(&e1000g_ksp->tx_no_swpkt, "Tx No Buffer", 757 KSTAT_DATA_ULONG); 758 kstat_named_init(&e1000g_ksp->tx_send_fail, "Tx Send Failure", 759 KSTAT_DATA_ULONG); 760 kstat_named_init(&e1000g_ksp->tx_over_size, "Tx Pkt Over Size", 761 KSTAT_DATA_ULONG); 762 kstat_named_init(&e1000g_ksp->tx_reschedule, "Tx Reschedule", 763 KSTAT_DATA_ULONG); 764 765 kstat_named_init(&e1000g_ksp->Mpc, "Recv_Missed_Packets", 766 KSTAT_DATA_ULONG); 767 kstat_named_init(&e1000g_ksp->Symerrs, "Recv_Symbol_Errors", 768 KSTAT_DATA_ULONG); 769 kstat_named_init(&e1000g_ksp->Rlec, "Recv_Length_Errors", 770 KSTAT_DATA_ULONG); 771 kstat_named_init(&e1000g_ksp->Xonrxc, "XONs_Recvd", 772 KSTAT_DATA_ULONG); 773 kstat_named_init(&e1000g_ksp->Xontxc, "XONs_Xmitd", 774 KSTAT_DATA_ULONG); 775 kstat_named_init(&e1000g_ksp->Xoffrxc, "XOFFs_Recvd", 776 KSTAT_DATA_ULONG); 777 kstat_named_init(&e1000g_ksp->Xofftxc, "XOFFs_Xmitd", 778 KSTAT_DATA_ULONG); 779 kstat_named_init(&e1000g_ksp->Fcruc, "Recv_Unsupport_FC_Pkts", 780 KSTAT_DATA_ULONG); 781 kstat_named_init(&e1000g_ksp->Prc64, "Pkts_Recvd_( 64b)", 782 KSTAT_DATA_ULONG); 783 kstat_named_init(&e1000g_ksp->Prc127, "Pkts_Recvd_( 65- 127b)", 784 KSTAT_DATA_ULONG); 785 kstat_named_init(&e1000g_ksp->Prc255, "Pkts_Recvd_( 127- 255b)", 786 KSTAT_DATA_ULONG); 787 kstat_named_init(&e1000g_ksp->Prc511, "Pkts_Recvd_( 256- 511b)", 788 KSTAT_DATA_ULONG); 789 kstat_named_init(&e1000g_ksp->Prc1023, "Pkts_Recvd_( 511-1023b)", 790 KSTAT_DATA_ULONG); 791 kstat_named_init(&e1000g_ksp->Prc1522, "Pkts_Recvd_(1024-1522b)", 792 KSTAT_DATA_ULONG); 793 kstat_named_init(&e1000g_ksp->Gprc, "Good_Pkts_Recvd", 794 KSTAT_DATA_ULONG); 795 kstat_named_init(&e1000g_ksp->Gptc, "Good_Pkts_Xmitd", 796 KSTAT_DATA_ULONG); 797 kstat_named_init(&e1000g_ksp->Gorl, "Good_Octets_Recvd_Lo", 798 KSTAT_DATA_ULONG); 799 kstat_named_init(&e1000g_ksp->Gorh, "Good_Octets_Recvd_Hi", 800 KSTAT_DATA_ULONG); 801 kstat_named_init(&e1000g_ksp->Gotl, "Good_Octets_Xmitd_Lo", 802 KSTAT_DATA_ULONG); 803 kstat_named_init(&e1000g_ksp->Goth, "Good_Octets_Xmitd_Hi", 804 KSTAT_DATA_ULONG); 805 kstat_named_init(&e1000g_ksp->Ruc, "Recv_Undersize", 806 KSTAT_DATA_ULONG); 807 kstat_named_init(&e1000g_ksp->Rfc, "Recv_Frag", 808 KSTAT_DATA_ULONG); 809 kstat_named_init(&e1000g_ksp->Roc, "Recv_Oversize", 810 KSTAT_DATA_ULONG); 811 kstat_named_init(&e1000g_ksp->Rjc, "Recv_Jabber", 812 KSTAT_DATA_ULONG); 813 kstat_named_init(&e1000g_ksp->Torl, "Total_Octets_Recvd_Lo", 814 KSTAT_DATA_ULONG); 815 kstat_named_init(&e1000g_ksp->Torh, "Total_Octets_Recvd_Hi", 816 KSTAT_DATA_ULONG); 817 kstat_named_init(&e1000g_ksp->Totl, "Total_Octets_Xmitd_Lo", 818 KSTAT_DATA_ULONG); 819 kstat_named_init(&e1000g_ksp->Toth, "Total_Octets_Xmitd_Hi", 820 KSTAT_DATA_ULONG); 821 kstat_named_init(&e1000g_ksp->Tpr, "Total_Packets_Recvd", 822 KSTAT_DATA_ULONG); 823 kstat_named_init(&e1000g_ksp->Tpt, "Total_Packets_Xmitd", 824 KSTAT_DATA_ULONG); 825 kstat_named_init(&e1000g_ksp->Ptc64, "Pkts_Xmitd_( 64b)", 826 KSTAT_DATA_ULONG); 827 kstat_named_init(&e1000g_ksp->Ptc127, "Pkts_Xmitd_( 65- 127b)", 828 KSTAT_DATA_ULONG); 829 kstat_named_init(&e1000g_ksp->Ptc255, "Pkts_Xmitd_( 128- 255b)", 830 KSTAT_DATA_ULONG); 831 kstat_named_init(&e1000g_ksp->Ptc511, "Pkts_Xmitd_( 255- 511b)", 832 KSTAT_DATA_ULONG); 833 kstat_named_init(&e1000g_ksp->Ptc1023, "Pkts_Xmitd_( 512-1023b)", 834 KSTAT_DATA_ULONG); 835 kstat_named_init(&e1000g_ksp->Ptc1522, "Pkts_Xmitd_(1024-1522b)", 836 KSTAT_DATA_ULONG); 837 kstat_named_init(&e1000g_ksp->Tncrs, "Xmit_with_No_CRS", 838 KSTAT_DATA_ULONG); 839 kstat_named_init(&e1000g_ksp->Tsctc, "Xmit_TCP_Seg_Contexts", 840 KSTAT_DATA_ULONG); 841 kstat_named_init(&e1000g_ksp->Tsctfc, "Xmit_TCP_Seg_Contexts_Fail", 842 KSTAT_DATA_ULONG); 843 844 #ifdef E1000G_DEBUG 845 kstat_named_init(&e1000g_ksp->rx_none, "Rx No Data", 846 KSTAT_DATA_ULONG); 847 kstat_named_init(&e1000g_ksp->rx_multi_desc, "Rx Span Multi Desc", 848 KSTAT_DATA_ULONG); 849 kstat_named_init(&e1000g_ksp->rx_no_freepkt, "Rx Freelist Empty", 850 KSTAT_DATA_ULONG); 851 kstat_named_init(&e1000g_ksp->rx_avail_freepkt, "Rx Freelist Avail", 852 KSTAT_DATA_ULONG); 853 854 kstat_named_init(&e1000g_ksp->tx_under_size, "Tx Pkt Under Size", 855 KSTAT_DATA_ULONG); 856 kstat_named_init(&e1000g_ksp->tx_exceed_frags, "Tx Exceed Max Frags", 857 KSTAT_DATA_ULONG); 858 kstat_named_init(&e1000g_ksp->tx_empty_frags, "Tx Empty Frags", 859 KSTAT_DATA_ULONG); 860 kstat_named_init(&e1000g_ksp->tx_recycle, "Tx Recycle", 861 KSTAT_DATA_ULONG); 862 kstat_named_init(&e1000g_ksp->tx_recycle_intr, "Tx Recycle Intr", 863 KSTAT_DATA_ULONG); 864 kstat_named_init(&e1000g_ksp->tx_recycle_retry, "Tx Recycle Retry", 865 KSTAT_DATA_ULONG); 866 kstat_named_init(&e1000g_ksp->tx_recycle_none, "Tx Recycled None", 867 KSTAT_DATA_ULONG); 868 kstat_named_init(&e1000g_ksp->tx_copy, "Tx Send Copy", 869 KSTAT_DATA_ULONG); 870 kstat_named_init(&e1000g_ksp->tx_bind, "Tx Send Bind", 871 KSTAT_DATA_ULONG); 872 kstat_named_init(&e1000g_ksp->tx_multi_copy, "Tx Copy Multi Frags", 873 KSTAT_DATA_ULONG); 874 kstat_named_init(&e1000g_ksp->tx_multi_cookie, "Tx Bind Multi Cookies", 875 KSTAT_DATA_ULONG); 876 kstat_named_init(&e1000g_ksp->tx_lack_desc, "Tx Desc Insufficient", 877 KSTAT_DATA_ULONG); 878 #endif 879 880 /* 881 * Function to provide kernel stat update on demand 882 */ 883 ksp->ks_update = e1000g_update_stats; 884 885 /* 886 * Pointer into provider's raw statistics 887 */ 888 ksp->ks_private = (void *)Adapter; 889 890 /* 891 * Add kstat to systems kstat chain 892 */ 893 kstat_install(ksp); 894 895 return (DDI_SUCCESS); 896 } 897