1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.2"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 96 /* 97 * Local routines 98 */ 99 static boolean_t e1000g_reset_adapter(struct e1000g *); 100 static void e1000g_tx_clean(struct e1000g *); 101 static void e1000g_rx_clean(struct e1000g *); 102 static void e1000g_link_timer(void *); 103 static void e1000g_local_timer(void *); 104 static boolean_t e1000g_link_check(struct e1000g *); 105 static boolean_t e1000g_stall_check(struct e1000g *); 106 static void e1000g_smartspeed(struct e1000g *); 107 static void e1000g_get_conf(struct e1000g *); 108 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 109 static void enable_watchdog_timer(struct e1000g *); 110 static void disable_watchdog_timer(struct e1000g *); 111 static void start_watchdog_timer(struct e1000g *); 112 static void restart_watchdog_timer(struct e1000g *); 113 static void stop_watchdog_timer(struct e1000g *); 114 static void stop_link_timer(struct e1000g *); 115 static void stop_82547_timer(e1000g_tx_ring_t *); 116 static void e1000g_force_speed_duplex(struct e1000g *); 117 static void e1000g_get_max_frame_size(struct e1000g *); 118 static boolean_t is_valid_mac_addr(uint8_t *); 119 static void e1000g_unattach(dev_info_t *, struct e1000g *); 120 #ifdef E1000G_DEBUG 121 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 122 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 123 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 125 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 126 struct iocblk *, mblk_t *); 127 #endif 128 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 129 struct iocblk *, mblk_t *); 130 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 131 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 132 static void e1000g_set_internal_loopback(struct e1000g *); 133 static void e1000g_set_external_loopback_1000(struct e1000g *); 134 static void e1000g_set_external_loopback_100(struct e1000g *); 135 static void e1000g_set_external_loopback_10(struct e1000g *); 136 static int e1000g_add_intrs(struct e1000g *); 137 static int e1000g_intr_add(struct e1000g *, int); 138 static int e1000g_rem_intrs(struct e1000g *); 139 static int e1000g_enable_intrs(struct e1000g *); 140 static int e1000g_disable_intrs(struct e1000g *); 141 static boolean_t e1000g_link_up(struct e1000g *); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *); 144 #endif 145 static void e1000g_get_phy_state(struct e1000g *); 146 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 147 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 148 const void *impl_data); 149 static void e1000g_fm_init(struct e1000g *Adapter); 150 static void e1000g_fm_fini(struct e1000g *Adapter); 151 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 152 static void e1000g_param_sync(struct e1000g *); 153 static void e1000g_get_driver_control(struct e1000_hw *); 154 static void e1000g_release_driver_control(struct e1000_hw *); 155 static void e1000g_restore_promisc(struct e1000g *Adapter); 156 157 mac_priv_prop_t e1000g_priv_props[] = { 158 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 159 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 160 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 161 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 162 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 164 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 167 {"_intr_adaptive", MAC_PROP_PERM_RW}, 168 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 169 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 170 }; 171 #define E1000G_MAX_PRIV_PROPS \ 172 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 173 174 175 static struct cb_ops cb_ws_ops = { 176 nulldev, /* cb_open */ 177 nulldev, /* cb_close */ 178 nodev, /* cb_strategy */ 179 nodev, /* cb_print */ 180 nodev, /* cb_dump */ 181 nodev, /* cb_read */ 182 nodev, /* cb_write */ 183 nodev, /* cb_ioctl */ 184 nodev, /* cb_devmap */ 185 nodev, /* cb_mmap */ 186 nodev, /* cb_segmap */ 187 nochpoll, /* cb_chpoll */ 188 ddi_prop_op, /* cb_prop_op */ 189 NULL, /* cb_stream */ 190 D_MP | D_HOTPLUG, /* cb_flag */ 191 CB_REV, /* cb_rev */ 192 nodev, /* cb_aread */ 193 nodev /* cb_awrite */ 194 }; 195 196 static struct dev_ops ws_ops = { 197 DEVO_REV, /* devo_rev */ 198 0, /* devo_refcnt */ 199 NULL, /* devo_getinfo */ 200 nulldev, /* devo_identify */ 201 nulldev, /* devo_probe */ 202 e1000g_attach, /* devo_attach */ 203 e1000g_detach, /* devo_detach */ 204 nodev, /* devo_reset */ 205 &cb_ws_ops, /* devo_cb_ops */ 206 NULL, /* devo_bus_ops */ 207 ddi_power, /* devo_power */ 208 e1000g_quiesce /* devo_quiesce */ 209 }; 210 211 static struct modldrv modldrv = { 212 &mod_driverops, /* Type of module. This one is a driver */ 213 ident, /* Discription string */ 214 &ws_ops, /* driver ops */ 215 }; 216 217 static struct modlinkage modlinkage = { 218 MODREV_1, &modldrv, NULL 219 }; 220 221 /* Access attributes for register mapping */ 222 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 223 DDI_DEVICE_ATTR_V0, 224 DDI_STRUCTURE_LE_ACC, 225 DDI_STRICTORDER_ACC, 226 DDI_FLAGERR_ACC 227 }; 228 229 #define E1000G_M_CALLBACK_FLAGS \ 230 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 231 232 static mac_callbacks_t e1000g_m_callbacks = { 233 E1000G_M_CALLBACK_FLAGS, 234 e1000g_m_stat, 235 e1000g_m_start, 236 e1000g_m_stop, 237 e1000g_m_promisc, 238 e1000g_m_multicst, 239 NULL, 240 e1000g_m_tx, 241 e1000g_m_ioctl, 242 e1000g_m_getcapab, 243 NULL, 244 NULL, 245 e1000g_m_setprop, 246 e1000g_m_getprop 247 }; 248 249 /* 250 * Global variables 251 */ 252 uint32_t e1000g_mblks_pending = 0; 253 /* 254 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 255 * Here we maintain a private dev_info list if e1000g_force_detach is 256 * enabled. If we force the driver to detach while there are still some 257 * rx buffers retained in the upper layer, we have to keep a copy of the 258 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 259 * structure will be freed after the driver is detached. However when we 260 * finally free those rx buffers released by the upper layer, we need to 261 * refer to the dev_info to free the dma buffers. So we save a copy of 262 * the dev_info for this purpose. On x86 platform, we assume this copy 263 * of dev_info is always valid, but on SPARC platform, it could be invalid 264 * after the system board level DR operation. For this reason, the global 265 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 266 */ 267 #ifdef __sparc 268 boolean_t e1000g_force_detach = B_FALSE; 269 #else 270 boolean_t e1000g_force_detach = B_TRUE; 271 #endif 272 private_devi_list_t *e1000g_private_devi_list = NULL; 273 274 /* 275 * The rwlock is defined to protect the whole processing of rx recycling 276 * and the rx packets release in detach processing to make them mutually 277 * exclusive. 278 * The rx recycling processes different rx packets in different threads, 279 * so it will be protected with RW_READER and it won't block any other rx 280 * recycling threads. 281 * While the detach processing will be protected with RW_WRITER to make 282 * it mutually exclusive with the rx recycling. 283 */ 284 krwlock_t e1000g_rx_detach_lock; 285 /* 286 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 287 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 288 * If there are many e1000g instances, the system may run out of DVMA 289 * resources during the initialization of the instances, then the flag will 290 * be changed to "USE_DMA". Because different e1000g instances are initialized 291 * in parallel, we need to use this lock to protect the flag. 292 */ 293 krwlock_t e1000g_dma_type_lock; 294 295 /* 296 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 297 * Based on the information from Intel, the 82546 chipset has some hardware 298 * problem. When one port is being reset and the other port is trying to 299 * access the eeprom, it could cause system hang or panic. To workaround this 300 * hardware problem, we use a global mutex to prevent such operations from 301 * happening simultaneously on different instances. This workaround is applied 302 * to all the devices supported by this driver. 303 */ 304 kmutex_t e1000g_nvm_lock; 305 306 /* 307 * Loadable module configuration entry points for the driver 308 */ 309 310 /* 311 * _init - module initialization 312 */ 313 int 314 _init(void) 315 { 316 int status; 317 318 mac_init_ops(&ws_ops, WSNAME); 319 status = mod_install(&modlinkage); 320 if (status != DDI_SUCCESS) 321 mac_fini_ops(&ws_ops); 322 else { 323 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 324 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 325 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 326 } 327 328 return (status); 329 } 330 331 /* 332 * _fini - module finalization 333 */ 334 int 335 _fini(void) 336 { 337 int status; 338 339 rw_enter(&e1000g_rx_detach_lock, RW_READER); 340 if (e1000g_mblks_pending != 0) { 341 rw_exit(&e1000g_rx_detach_lock); 342 return (EBUSY); 343 } 344 rw_exit(&e1000g_rx_detach_lock); 345 346 status = mod_remove(&modlinkage); 347 if (status == DDI_SUCCESS) { 348 mac_fini_ops(&ws_ops); 349 350 if (e1000g_force_detach) { 351 private_devi_list_t *devi_node; 352 353 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 354 while (e1000g_private_devi_list != NULL) { 355 devi_node = e1000g_private_devi_list; 356 e1000g_private_devi_list = 357 e1000g_private_devi_list->next; 358 359 kmem_free(devi_node->priv_dip, 360 sizeof (struct dev_info)); 361 kmem_free(devi_node, 362 sizeof (private_devi_list_t)); 363 } 364 rw_exit(&e1000g_rx_detach_lock); 365 } 366 367 rw_destroy(&e1000g_rx_detach_lock); 368 rw_destroy(&e1000g_dma_type_lock); 369 mutex_destroy(&e1000g_nvm_lock); 370 } 371 372 return (status); 373 } 374 375 /* 376 * _info - module information 377 */ 378 int 379 _info(struct modinfo *modinfop) 380 { 381 return (mod_info(&modlinkage, modinfop)); 382 } 383 384 /* 385 * e1000g_attach - driver attach 386 * 387 * This function is the device-specific initialization entry 388 * point. This entry point is required and must be written. 389 * The DDI_ATTACH command must be provided in the attach entry 390 * point. When attach() is called with cmd set to DDI_ATTACH, 391 * all normal kernel services (such as kmem_alloc(9F)) are 392 * available for use by the driver. 393 * 394 * The attach() function will be called once for each instance 395 * of the device on the system with cmd set to DDI_ATTACH. 396 * Until attach() succeeds, the only driver entry points which 397 * may be called are open(9E) and getinfo(9E). 398 */ 399 static int 400 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 401 { 402 struct e1000g *Adapter; 403 struct e1000_hw *hw; 404 struct e1000g_osdep *osdep; 405 int instance; 406 407 switch (cmd) { 408 default: 409 e1000g_log(NULL, CE_WARN, 410 "Unsupported command send to e1000g_attach... "); 411 return (DDI_FAILURE); 412 413 case DDI_RESUME: 414 return (e1000g_resume(devinfo)); 415 416 case DDI_ATTACH: 417 break; 418 } 419 420 /* 421 * get device instance number 422 */ 423 instance = ddi_get_instance(devinfo); 424 425 /* 426 * Allocate soft data structure 427 */ 428 Adapter = 429 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 430 431 Adapter->dip = devinfo; 432 Adapter->instance = instance; 433 Adapter->tx_ring->adapter = Adapter; 434 Adapter->rx_ring->adapter = Adapter; 435 436 hw = &Adapter->shared; 437 osdep = &Adapter->osdep; 438 hw->back = osdep; 439 osdep->adapter = Adapter; 440 441 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 442 443 /* 444 * Initialize for fma support 445 */ 446 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 447 0, 0x0f, 448 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 449 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 450 e1000g_fm_init(Adapter); 451 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 452 453 /* 454 * PCI Configure 455 */ 456 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 457 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 458 goto attach_fail; 459 } 460 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 461 462 /* 463 * Setup hardware 464 */ 465 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 466 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 467 goto attach_fail; 468 } 469 470 /* 471 * Map in the device registers. 472 */ 473 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 474 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 475 goto attach_fail; 476 } 477 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 478 479 /* 480 * Initialize driver parameters 481 */ 482 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 483 goto attach_fail; 484 } 485 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 486 487 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 488 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 489 goto attach_fail; 490 } 491 492 /* 493 * Initialize interrupts 494 */ 495 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 496 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 497 goto attach_fail; 498 } 499 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 500 501 /* 502 * Initialize mutex's for this device. 503 * Do this before enabling the interrupt handler and 504 * register the softint to avoid the condition where 505 * interrupt handler can try using uninitialized mutex 506 */ 507 e1000g_init_locks(Adapter); 508 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 509 510 /* 511 * Initialize Driver Counters 512 */ 513 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 514 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 515 goto attach_fail; 516 } 517 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 518 519 /* 520 * Initialize chip hardware and software structures 521 */ 522 rw_enter(&Adapter->chip_lock, RW_WRITER); 523 if (e1000g_init(Adapter) != DDI_SUCCESS) { 524 rw_exit(&Adapter->chip_lock); 525 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 526 goto attach_fail; 527 } 528 rw_exit(&Adapter->chip_lock); 529 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 530 531 /* 532 * Register the driver to the MAC 533 */ 534 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 535 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 536 goto attach_fail; 537 } 538 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 539 540 /* 541 * Now that mutex locks are initialized, and the chip is also 542 * initialized, enable interrupts. 543 */ 544 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 545 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 546 goto attach_fail; 547 } 548 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 549 550 /* 551 * If e1000g_force_detach is enabled, in global private dip list, 552 * we will create a new entry, which maintains the priv_dip for DR 553 * supports after driver detached. 554 */ 555 if (e1000g_force_detach) { 556 private_devi_list_t *devi_node; 557 558 Adapter->priv_dip = 559 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 560 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 561 sizeof (struct dev_info)); 562 563 devi_node = 564 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 565 566 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 567 devi_node->priv_dip = Adapter->priv_dip; 568 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 569 devi_node->next = e1000g_private_devi_list; 570 e1000g_private_devi_list = devi_node; 571 rw_exit(&e1000g_rx_detach_lock); 572 } 573 574 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 575 Adapter->e1000g_state = E1000G_INITIALIZED; 576 577 return (DDI_SUCCESS); 578 579 attach_fail: 580 e1000g_unattach(devinfo, Adapter); 581 return (DDI_FAILURE); 582 } 583 584 static int 585 e1000g_register_mac(struct e1000g *Adapter) 586 { 587 struct e1000_hw *hw = &Adapter->shared; 588 mac_register_t *mac; 589 int err; 590 591 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 592 return (DDI_FAILURE); 593 594 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 595 mac->m_driver = Adapter; 596 mac->m_dip = Adapter->dip; 597 mac->m_src_addr = hw->mac.addr; 598 mac->m_callbacks = &e1000g_m_callbacks; 599 mac->m_min_sdu = 0; 600 mac->m_max_sdu = Adapter->default_mtu; 601 mac->m_margin = VLAN_TAGSZ; 602 mac->m_priv_props = e1000g_priv_props; 603 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 604 mac->m_v12n = MAC_VIRT_LEVEL1; 605 606 err = mac_register(mac, &Adapter->mh); 607 mac_free(mac); 608 609 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 610 } 611 612 static int 613 e1000g_identify_hardware(struct e1000g *Adapter) 614 { 615 struct e1000_hw *hw = &Adapter->shared; 616 struct e1000g_osdep *osdep = &Adapter->osdep; 617 618 /* Get the device id */ 619 hw->vendor_id = 620 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 621 hw->device_id = 622 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 623 hw->revision_id = 624 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 625 hw->subsystem_device_id = 626 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 627 hw->subsystem_vendor_id = 628 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 629 630 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 631 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 632 "MAC type could not be set properly."); 633 return (DDI_FAILURE); 634 } 635 636 return (DDI_SUCCESS); 637 } 638 639 static int 640 e1000g_regs_map(struct e1000g *Adapter) 641 { 642 dev_info_t *devinfo = Adapter->dip; 643 struct e1000_hw *hw = &Adapter->shared; 644 struct e1000g_osdep *osdep = &Adapter->osdep; 645 off_t mem_size; 646 647 /* Get size of adapter register memory */ 648 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 649 DDI_SUCCESS) { 650 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 651 "ddi_dev_regsize for registers failed"); 652 return (DDI_FAILURE); 653 } 654 655 /* Map adapter register memory */ 656 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 657 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 658 &osdep->reg_handle)) != DDI_SUCCESS) { 659 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 660 "ddi_regs_map_setup for registers failed"); 661 goto regs_map_fail; 662 } 663 664 /* ICH needs to map flash memory */ 665 if (hw->mac.type == e1000_ich8lan || 666 hw->mac.type == e1000_ich9lan || 667 hw->mac.type == e1000_ich10lan) { 668 /* get flash size */ 669 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 670 &mem_size) != DDI_SUCCESS) { 671 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 672 "ddi_dev_regsize for ICH flash failed"); 673 goto regs_map_fail; 674 } 675 676 /* map flash in */ 677 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 678 (caddr_t *)&hw->flash_address, 0, 679 mem_size, &e1000g_regs_acc_attr, 680 &osdep->ich_flash_handle) != DDI_SUCCESS) { 681 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 682 "ddi_regs_map_setup for ICH flash failed"); 683 goto regs_map_fail; 684 } 685 } 686 687 return (DDI_SUCCESS); 688 689 regs_map_fail: 690 if (osdep->reg_handle != NULL) 691 ddi_regs_map_free(&osdep->reg_handle); 692 693 return (DDI_FAILURE); 694 } 695 696 static int 697 e1000g_set_driver_params(struct e1000g *Adapter) 698 { 699 struct e1000_hw *hw; 700 uint32_t mem_bar, io_bar, bar64; 701 702 hw = &Adapter->shared; 703 704 /* Set MAC type and initialize hardware functions */ 705 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 706 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 707 "Could not setup hardware functions"); 708 return (DDI_FAILURE); 709 } 710 711 /* Get bus information */ 712 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 713 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 714 "Could not get bus information"); 715 return (DDI_FAILURE); 716 } 717 718 /* get mem_base addr */ 719 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 720 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 721 722 /* get io_base addr */ 723 if (hw->mac.type >= e1000_82544) { 724 if (bar64) { 725 /* IO BAR is different for 64 bit BAR mode */ 726 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 727 PCI_CONF_BASE4); 728 } else { 729 /* normal 32-bit BAR mode */ 730 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 731 PCI_CONF_BASE2); 732 } 733 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 734 } else { 735 /* no I/O access for adapters prior to 82544 */ 736 hw->io_base = 0x0; 737 } 738 739 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 740 741 hw->mac.autoneg_failed = B_TRUE; 742 743 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 744 hw->phy.autoneg_wait_to_complete = B_FALSE; 745 746 /* Adaptive IFS related changes */ 747 hw->mac.adaptive_ifs = B_TRUE; 748 749 /* Enable phy init script for IGP phy of 82541/82547 */ 750 if ((hw->mac.type == e1000_82547) || 751 (hw->mac.type == e1000_82541) || 752 (hw->mac.type == e1000_82547_rev_2) || 753 (hw->mac.type == e1000_82541_rev_2)) 754 e1000_init_script_state_82541(hw, B_TRUE); 755 756 /* Enable the TTL workaround for 82541/82547 */ 757 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 758 759 #ifdef __sparc 760 Adapter->strip_crc = B_TRUE; 761 #else 762 Adapter->strip_crc = B_FALSE; 763 #endif 764 765 /* Get conf file properties */ 766 e1000g_get_conf(Adapter); 767 768 /* Get speed/duplex settings in conf file */ 769 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 770 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 771 e1000g_force_speed_duplex(Adapter); 772 773 /* Get Jumbo Frames settings in conf file */ 774 e1000g_get_max_frame_size(Adapter); 775 776 /* Set Rx/Tx buffer size */ 777 e1000g_set_bufsize(Adapter); 778 779 /* Master Latency Timer */ 780 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 781 782 /* copper options */ 783 if (hw->phy.media_type == e1000_media_type_copper) { 784 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 785 hw->phy.disable_polarity_correction = B_FALSE; 786 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 787 } 788 789 /* The initial link state should be "unknown" */ 790 Adapter->link_state = LINK_STATE_UNKNOWN; 791 792 /* Initialize rx parameters */ 793 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 794 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 795 796 /* Initialize tx parameters */ 797 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 798 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 799 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 800 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 801 802 /* Initialize rx parameters */ 803 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 804 805 return (DDI_SUCCESS); 806 } 807 808 static void 809 e1000g_set_bufsize(struct e1000g *Adapter) 810 { 811 struct e1000_mac_info *mac = &Adapter->shared.mac; 812 uint64_t rx_size; 813 uint64_t tx_size; 814 815 dev_info_t *devinfo = Adapter->dip; 816 #ifdef __sparc 817 ulong_t iommu_pagesize; 818 #endif 819 /* Get the system page size */ 820 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 821 822 #ifdef __sparc 823 iommu_pagesize = dvma_pagesize(devinfo); 824 if (iommu_pagesize != 0) { 825 if (Adapter->sys_page_sz == iommu_pagesize) { 826 if (iommu_pagesize > 0x4000) 827 Adapter->sys_page_sz = 0x4000; 828 } else { 829 if (Adapter->sys_page_sz > iommu_pagesize) 830 Adapter->sys_page_sz = iommu_pagesize; 831 } 832 } 833 if (Adapter->lso_enable) { 834 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 835 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 836 } else { 837 Adapter->dvma_page_num = Adapter->max_frame_size / 838 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 839 } 840 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 841 #endif 842 843 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 844 845 if (Adapter->mem_workaround_82546 && 846 ((mac->type == e1000_82545) || 847 (mac->type == e1000_82546) || 848 (mac->type == e1000_82546_rev_3))) { 849 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 850 } else { 851 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 852 if ((rx_size > FRAME_SIZE_UPTO_2K) && 853 (rx_size <= FRAME_SIZE_UPTO_4K)) 854 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 855 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 856 (rx_size <= FRAME_SIZE_UPTO_8K)) 857 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 858 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 859 (rx_size <= FRAME_SIZE_UPTO_16K)) 860 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 861 else 862 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 863 } 864 865 tx_size = Adapter->max_frame_size; 866 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 867 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 868 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 869 (tx_size <= FRAME_SIZE_UPTO_8K)) 870 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 871 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 872 (tx_size <= FRAME_SIZE_UPTO_16K)) 873 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 874 else 875 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 876 877 /* 878 * For Wiseman adapters we have an requirement of having receive 879 * buffers aligned at 256 byte boundary. Since Livengood does not 880 * require this and forcing it for all hardwares will have 881 * performance implications, I am making it applicable only for 882 * Wiseman and for Jumbo frames enabled mode as rest of the time, 883 * it is okay to have normal frames...but it does involve a 884 * potential risk where we may loose data if buffer is not 885 * aligned...so all wiseman boards to have 256 byte aligned 886 * buffers 887 */ 888 if (mac->type < e1000_82543) 889 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 890 else 891 Adapter->rx_buf_align = 1; 892 } 893 894 /* 895 * e1000g_detach - driver detach 896 * 897 * The detach() function is the complement of the attach routine. 898 * If cmd is set to DDI_DETACH, detach() is used to remove the 899 * state associated with a given instance of a device node 900 * prior to the removal of that instance from the system. 901 * 902 * The detach() function will be called once for each instance 903 * of the device for which there has been a successful attach() 904 * once there are no longer any opens on the device. 905 * 906 * Interrupts routine are disabled, All memory allocated by this 907 * driver are freed. 908 */ 909 static int 910 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 911 { 912 struct e1000g *Adapter; 913 boolean_t rx_drain; 914 915 switch (cmd) { 916 default: 917 return (DDI_FAILURE); 918 919 case DDI_SUSPEND: 920 return (e1000g_suspend(devinfo)); 921 922 case DDI_DETACH: 923 break; 924 } 925 926 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 927 if (Adapter == NULL) 928 return (DDI_FAILURE); 929 930 rx_drain = e1000g_rx_drain(Adapter); 931 if (!rx_drain && !e1000g_force_detach) 932 return (DDI_FAILURE); 933 934 if (mac_unregister(Adapter->mh) != 0) { 935 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 936 return (DDI_FAILURE); 937 } 938 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 939 940 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 941 942 /* 943 * If e1000g_force_detach is enabled, driver detach is safe. 944 * We will let e1000g_free_priv_devi_node routine determine 945 * whether we need to free the priv_dip entry for current 946 * driver instance. 947 */ 948 if (e1000g_force_detach) { 949 e1000g_free_priv_devi_node(Adapter, rx_drain); 950 } 951 952 e1000g_unattach(devinfo, Adapter); 953 954 return (DDI_SUCCESS); 955 } 956 957 /* 958 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 959 * 960 * If free_flag is true, that indicates the upper layer is not holding 961 * the rx buffers, we could free the priv_dip entry safely. 962 * 963 * Otherwise, we have to keep this entry even after driver detached, 964 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 965 * so that driver could free it while all of rx buffers are returned 966 * by upper layer later. 967 */ 968 static void 969 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 970 { 971 private_devi_list_t *devi_node, *devi_del; 972 973 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 974 ASSERT(e1000g_private_devi_list != NULL); 975 ASSERT(Adapter->priv_dip != NULL); 976 977 devi_node = e1000g_private_devi_list; 978 if (devi_node->priv_dip == Adapter->priv_dip) { 979 if (free_flag) { 980 e1000g_private_devi_list = 981 devi_node->next; 982 kmem_free(devi_node->priv_dip, 983 sizeof (struct dev_info)); 984 kmem_free(devi_node, 985 sizeof (private_devi_list_t)); 986 } else { 987 ASSERT(e1000g_mblks_pending != 0); 988 devi_node->flag = 989 E1000G_PRIV_DEVI_DETACH; 990 } 991 rw_exit(&e1000g_rx_detach_lock); 992 return; 993 } 994 995 devi_node = e1000g_private_devi_list; 996 while (devi_node->next != NULL) { 997 if (devi_node->next->priv_dip == Adapter->priv_dip) { 998 if (free_flag) { 999 devi_del = devi_node->next; 1000 devi_node->next = devi_del->next; 1001 kmem_free(devi_del->priv_dip, 1002 sizeof (struct dev_info)); 1003 kmem_free(devi_del, 1004 sizeof (private_devi_list_t)); 1005 } else { 1006 ASSERT(e1000g_mblks_pending != 0); 1007 devi_node->next->flag = 1008 E1000G_PRIV_DEVI_DETACH; 1009 } 1010 break; 1011 } 1012 devi_node = devi_node->next; 1013 } 1014 rw_exit(&e1000g_rx_detach_lock); 1015 } 1016 1017 static void 1018 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1019 { 1020 int result; 1021 1022 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1023 (void) e1000g_disable_intrs(Adapter); 1024 } 1025 1026 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1027 (void) mac_unregister(Adapter->mh); 1028 } 1029 1030 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1031 (void) e1000g_rem_intrs(Adapter); 1032 } 1033 1034 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1035 (void) ddi_prop_remove_all(devinfo); 1036 } 1037 1038 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1039 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1040 } 1041 1042 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1043 stop_link_timer(Adapter); 1044 1045 mutex_enter(&e1000g_nvm_lock); 1046 result = e1000_reset_hw(&Adapter->shared); 1047 mutex_exit(&e1000g_nvm_lock); 1048 1049 if (result != E1000_SUCCESS) { 1050 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1051 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1052 } 1053 } 1054 1055 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1056 if (Adapter->osdep.reg_handle != NULL) 1057 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1058 if (Adapter->osdep.ich_flash_handle != NULL) 1059 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1060 } 1061 1062 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1063 if (Adapter->osdep.cfg_handle != NULL) 1064 pci_config_teardown(&Adapter->osdep.cfg_handle); 1065 } 1066 1067 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1068 e1000g_destroy_locks(Adapter); 1069 } 1070 1071 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1072 e1000g_fm_fini(Adapter); 1073 } 1074 1075 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1076 1077 /* 1078 * Another hotplug spec requirement, 1079 * run ddi_set_driver_private(devinfo, null); 1080 */ 1081 ddi_set_driver_private(devinfo, NULL); 1082 } 1083 1084 static void 1085 e1000g_init_locks(struct e1000g *Adapter) 1086 { 1087 e1000g_tx_ring_t *tx_ring; 1088 e1000g_rx_ring_t *rx_ring; 1089 1090 rw_init(&Adapter->chip_lock, NULL, 1091 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1092 mutex_init(&Adapter->link_lock, NULL, 1093 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1094 mutex_init(&Adapter->watchdog_lock, NULL, 1095 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1096 1097 tx_ring = Adapter->tx_ring; 1098 1099 mutex_init(&tx_ring->tx_lock, NULL, 1100 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1101 mutex_init(&tx_ring->usedlist_lock, NULL, 1102 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1103 mutex_init(&tx_ring->freelist_lock, NULL, 1104 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1105 1106 rx_ring = Adapter->rx_ring; 1107 1108 mutex_init(&rx_ring->rx_lock, NULL, 1109 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1110 mutex_init(&rx_ring->freelist_lock, NULL, 1111 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1112 mutex_init(&rx_ring->recycle_lock, NULL, 1113 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1114 } 1115 1116 static void 1117 e1000g_destroy_locks(struct e1000g *Adapter) 1118 { 1119 e1000g_tx_ring_t *tx_ring; 1120 e1000g_rx_ring_t *rx_ring; 1121 1122 tx_ring = Adapter->tx_ring; 1123 mutex_destroy(&tx_ring->tx_lock); 1124 mutex_destroy(&tx_ring->usedlist_lock); 1125 mutex_destroy(&tx_ring->freelist_lock); 1126 1127 rx_ring = Adapter->rx_ring; 1128 mutex_destroy(&rx_ring->rx_lock); 1129 mutex_destroy(&rx_ring->freelist_lock); 1130 mutex_destroy(&rx_ring->recycle_lock); 1131 1132 mutex_destroy(&Adapter->link_lock); 1133 mutex_destroy(&Adapter->watchdog_lock); 1134 rw_destroy(&Adapter->chip_lock); 1135 } 1136 1137 static int 1138 e1000g_resume(dev_info_t *devinfo) 1139 { 1140 struct e1000g *Adapter; 1141 1142 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1143 if (Adapter == NULL) 1144 e1000g_log(Adapter, CE_PANIC, 1145 "Instance pointer is null\n"); 1146 1147 if (Adapter->dip != devinfo) 1148 e1000g_log(Adapter, CE_PANIC, 1149 "Devinfo is not the same as saved devinfo\n"); 1150 1151 rw_enter(&Adapter->chip_lock, RW_WRITER); 1152 1153 if (Adapter->e1000g_state & E1000G_STARTED) { 1154 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1155 rw_exit(&Adapter->chip_lock); 1156 /* 1157 * We note the failure, but return success, as the 1158 * system is still usable without this controller. 1159 */ 1160 e1000g_log(Adapter, CE_WARN, 1161 "e1000g_resume: failed to restart controller\n"); 1162 return (DDI_SUCCESS); 1163 } 1164 /* Enable and start the watchdog timer */ 1165 enable_watchdog_timer(Adapter); 1166 } 1167 1168 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1169 1170 rw_exit(&Adapter->chip_lock); 1171 1172 return (DDI_SUCCESS); 1173 } 1174 1175 static int 1176 e1000g_suspend(dev_info_t *devinfo) 1177 { 1178 struct e1000g *Adapter; 1179 1180 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1181 if (Adapter == NULL) 1182 return (DDI_FAILURE); 1183 1184 rw_enter(&Adapter->chip_lock, RW_WRITER); 1185 1186 Adapter->e1000g_state |= E1000G_SUSPENDED; 1187 1188 /* if the port isn't plumbed, we can simply return */ 1189 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1190 rw_exit(&Adapter->chip_lock); 1191 return (DDI_SUCCESS); 1192 } 1193 1194 e1000g_stop(Adapter, B_FALSE); 1195 1196 rw_exit(&Adapter->chip_lock); 1197 1198 /* Disable and stop all the timers */ 1199 disable_watchdog_timer(Adapter); 1200 stop_link_timer(Adapter); 1201 stop_82547_timer(Adapter->tx_ring); 1202 1203 return (DDI_SUCCESS); 1204 } 1205 1206 static int 1207 e1000g_init(struct e1000g *Adapter) 1208 { 1209 uint32_t pba; 1210 uint32_t high_water; 1211 struct e1000_hw *hw; 1212 clock_t link_timeout; 1213 int result; 1214 1215 hw = &Adapter->shared; 1216 1217 /* 1218 * reset to put the hardware in a known state 1219 * before we try to do anything with the eeprom 1220 */ 1221 mutex_enter(&e1000g_nvm_lock); 1222 result = e1000_reset_hw(hw); 1223 mutex_exit(&e1000g_nvm_lock); 1224 1225 if (result != E1000_SUCCESS) { 1226 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1227 goto init_fail; 1228 } 1229 1230 mutex_enter(&e1000g_nvm_lock); 1231 result = e1000_validate_nvm_checksum(hw); 1232 if (result < E1000_SUCCESS) { 1233 /* 1234 * Some PCI-E parts fail the first check due to 1235 * the link being in sleep state. Call it again, 1236 * if it fails a second time its a real issue. 1237 */ 1238 result = e1000_validate_nvm_checksum(hw); 1239 } 1240 mutex_exit(&e1000g_nvm_lock); 1241 1242 if (result < E1000_SUCCESS) { 1243 e1000g_log(Adapter, CE_WARN, 1244 "Invalid NVM checksum. Please contact " 1245 "the vendor to update the NVM."); 1246 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1247 goto init_fail; 1248 } 1249 1250 result = 0; 1251 #ifdef __sparc 1252 /* 1253 * First, we try to get the local ethernet address from OBP. If 1254 * failed, then we get it from the EEPROM of NIC card. 1255 */ 1256 result = e1000g_find_mac_address(Adapter); 1257 #endif 1258 /* Get the local ethernet address. */ 1259 if (!result) { 1260 mutex_enter(&e1000g_nvm_lock); 1261 result = e1000_read_mac_addr(hw); 1262 mutex_exit(&e1000g_nvm_lock); 1263 } 1264 1265 if (result < E1000_SUCCESS) { 1266 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1267 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1268 goto init_fail; 1269 } 1270 1271 /* check for valid mac address */ 1272 if (!is_valid_mac_addr(hw->mac.addr)) { 1273 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1274 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1275 goto init_fail; 1276 } 1277 1278 /* Set LAA state for 82571 chipset */ 1279 e1000_set_laa_state_82571(hw, B_TRUE); 1280 1281 /* Master Latency Timer implementation */ 1282 if (Adapter->master_latency_timer) { 1283 pci_config_put8(Adapter->osdep.cfg_handle, 1284 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1285 } 1286 1287 if (hw->mac.type < e1000_82547) { 1288 /* 1289 * Total FIFO is 64K 1290 */ 1291 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1292 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1293 else 1294 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1295 } else if ((hw->mac.type == e1000_82571) || 1296 (hw->mac.type == e1000_82572) || 1297 (hw->mac.type == e1000_80003es2lan)) { 1298 /* 1299 * Total FIFO is 48K 1300 */ 1301 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1302 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1303 else 1304 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1305 } else if (hw->mac.type == e1000_82573) { 1306 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1307 } else if (hw->mac.type == e1000_82574) { 1308 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1309 pba = E1000_READ_REG(hw, E1000_PBA); 1310 } else if (hw->mac.type == e1000_ich8lan) { 1311 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1312 } else if (hw->mac.type == e1000_ich9lan) { 1313 pba = E1000_PBA_10K; 1314 } else if (hw->mac.type == e1000_ich10lan) { 1315 pba = E1000_PBA_10K; 1316 } else { 1317 /* 1318 * Total FIFO is 40K 1319 */ 1320 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1321 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1322 else 1323 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1324 } 1325 E1000_WRITE_REG(hw, E1000_PBA, pba); 1326 1327 /* 1328 * These parameters set thresholds for the adapter's generation(Tx) 1329 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1330 * settings. Flow control is enabled or disabled in the configuration 1331 * file. 1332 * High-water mark is set down from the top of the rx fifo (not 1333 * sensitive to max_frame_size) and low-water is set just below 1334 * high-water mark. 1335 * The high water mark must be low enough to fit one full frame above 1336 * it in the rx FIFO. Should be the lower of: 1337 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1338 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1339 * Rx FIFO size minus one full frame. 1340 */ 1341 high_water = min(((pba << 10) * 9 / 10), 1342 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1343 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1344 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1345 ((pba << 10) - Adapter->max_frame_size))); 1346 1347 hw->fc.high_water = high_water & 0xFFF8; 1348 hw->fc.low_water = hw->fc.high_water - 8; 1349 1350 if (hw->mac.type == e1000_80003es2lan) 1351 hw->fc.pause_time = 0xFFFF; 1352 else 1353 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1354 hw->fc.send_xon = B_TRUE; 1355 1356 /* 1357 * Reset the adapter hardware the second time. 1358 */ 1359 mutex_enter(&e1000g_nvm_lock); 1360 result = e1000_reset_hw(hw); 1361 mutex_exit(&e1000g_nvm_lock); 1362 1363 if (result != E1000_SUCCESS) { 1364 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1365 goto init_fail; 1366 } 1367 1368 /* disable wakeup control by default */ 1369 if (hw->mac.type >= e1000_82544) 1370 E1000_WRITE_REG(hw, E1000_WUC, 0); 1371 1372 /* 1373 * MWI should be disabled on 82546. 1374 */ 1375 if (hw->mac.type == e1000_82546) 1376 e1000_pci_clear_mwi(hw); 1377 else 1378 e1000_pci_set_mwi(hw); 1379 1380 /* 1381 * Configure/Initialize hardware 1382 */ 1383 mutex_enter(&e1000g_nvm_lock); 1384 result = e1000_init_hw(hw); 1385 mutex_exit(&e1000g_nvm_lock); 1386 1387 if (result < E1000_SUCCESS) { 1388 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1389 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1390 goto init_fail; 1391 } 1392 1393 /* 1394 * Restore LED settings to the default from EEPROM 1395 * to meet the standard for Sun platforms. 1396 */ 1397 (void) e1000_cleanup_led(hw); 1398 1399 /* Disable Smart Power Down */ 1400 phy_spd_state(hw, B_FALSE); 1401 1402 /* Make sure driver has control */ 1403 e1000g_get_driver_control(hw); 1404 1405 /* 1406 * Initialize unicast addresses. 1407 */ 1408 e1000g_init_unicst(Adapter); 1409 1410 /* 1411 * Setup and initialize the mctable structures. After this routine 1412 * completes Multicast table will be set 1413 */ 1414 e1000g_setup_multicast(Adapter); 1415 msec_delay(5); 1416 1417 /* 1418 * Implement Adaptive IFS 1419 */ 1420 e1000_reset_adaptive(hw); 1421 1422 /* Setup Interrupt Throttling Register */ 1423 if (hw->mac.type >= e1000_82540) { 1424 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1425 } else 1426 Adapter->intr_adaptive = B_FALSE; 1427 1428 /* Start the timer for link setup */ 1429 if (hw->mac.autoneg) 1430 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1431 else 1432 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1433 1434 mutex_enter(&Adapter->link_lock); 1435 if (hw->phy.autoneg_wait_to_complete) { 1436 Adapter->link_complete = B_TRUE; 1437 } else { 1438 Adapter->link_complete = B_FALSE; 1439 Adapter->link_tid = timeout(e1000g_link_timer, 1440 (void *)Adapter, link_timeout); 1441 } 1442 mutex_exit(&Adapter->link_lock); 1443 1444 /* Enable PCI-Ex master */ 1445 if (hw->bus.type == e1000_bus_type_pci_express) { 1446 e1000_enable_pciex_master(hw); 1447 } 1448 1449 /* Save the state of the phy */ 1450 e1000g_get_phy_state(Adapter); 1451 1452 e1000g_param_sync(Adapter); 1453 1454 Adapter->init_count++; 1455 1456 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1457 goto init_fail; 1458 } 1459 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1460 goto init_fail; 1461 } 1462 1463 Adapter->poll_mode = e1000g_poll_mode; 1464 1465 return (DDI_SUCCESS); 1466 1467 init_fail: 1468 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1469 return (DDI_FAILURE); 1470 } 1471 1472 /* 1473 * Check if the link is up 1474 */ 1475 static boolean_t 1476 e1000g_link_up(struct e1000g *Adapter) 1477 { 1478 struct e1000_hw *hw; 1479 boolean_t link_up; 1480 1481 hw = &Adapter->shared; 1482 1483 (void) e1000_check_for_link(hw); 1484 1485 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1486 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1487 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1488 (hw->mac.serdes_has_link))) { 1489 link_up = B_TRUE; 1490 } else { 1491 link_up = B_FALSE; 1492 } 1493 1494 return (link_up); 1495 } 1496 1497 static void 1498 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1499 { 1500 struct iocblk *iocp; 1501 struct e1000g *e1000gp; 1502 enum ioc_reply status; 1503 1504 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1505 iocp->ioc_error = 0; 1506 e1000gp = (struct e1000g *)arg; 1507 1508 ASSERT(e1000gp); 1509 if (e1000gp == NULL) { 1510 miocnak(q, mp, 0, EINVAL); 1511 return; 1512 } 1513 1514 rw_enter(&e1000gp->chip_lock, RW_READER); 1515 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1516 rw_exit(&e1000gp->chip_lock); 1517 miocnak(q, mp, 0, EINVAL); 1518 return; 1519 } 1520 rw_exit(&e1000gp->chip_lock); 1521 1522 switch (iocp->ioc_cmd) { 1523 1524 case LB_GET_INFO_SIZE: 1525 case LB_GET_INFO: 1526 case LB_GET_MODE: 1527 case LB_SET_MODE: 1528 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1529 break; 1530 1531 1532 #ifdef E1000G_DEBUG 1533 case E1000G_IOC_REG_PEEK: 1534 case E1000G_IOC_REG_POKE: 1535 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1536 break; 1537 case E1000G_IOC_CHIP_RESET: 1538 e1000gp->reset_count++; 1539 if (e1000g_reset_adapter(e1000gp)) 1540 status = IOC_ACK; 1541 else 1542 status = IOC_INVAL; 1543 break; 1544 #endif 1545 default: 1546 status = IOC_INVAL; 1547 break; 1548 } 1549 1550 /* 1551 * Decide how to reply 1552 */ 1553 switch (status) { 1554 default: 1555 case IOC_INVAL: 1556 /* 1557 * Error, reply with a NAK and EINVAL or the specified error 1558 */ 1559 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1560 EINVAL : iocp->ioc_error); 1561 break; 1562 1563 case IOC_DONE: 1564 /* 1565 * OK, reply already sent 1566 */ 1567 break; 1568 1569 case IOC_ACK: 1570 /* 1571 * OK, reply with an ACK 1572 */ 1573 miocack(q, mp, 0, 0); 1574 break; 1575 1576 case IOC_REPLY: 1577 /* 1578 * OK, send prepared reply as ACK or NAK 1579 */ 1580 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1581 M_IOCACK : M_IOCNAK; 1582 qreply(q, mp); 1583 break; 1584 } 1585 } 1586 1587 /* 1588 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1589 * capable of supporting only one interrupt and we shouldn't disable 1590 * the physical interrupt. In this case we let the interrupt come and 1591 * we queue the packets in the rx ring itself in case we are in polling 1592 * mode (better latency but slightly lower performance and a very 1593 * high intrrupt count in mpstat which is harmless). 1594 * 1595 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1596 * which can be disabled in poll mode. This gives better overall 1597 * throughput (compared to the mode above), shows very low interrupt 1598 * count but has slightly higher latency since we pick the packets when 1599 * the poll thread does polling. 1600 * 1601 * Currently, this flag should be enabled only while doing performance 1602 * measurement or when it can be guaranteed that entire NIC going 1603 * in poll mode will not harm any traffic like cluster heartbeat etc. 1604 */ 1605 int e1000g_poll_mode = 0; 1606 1607 /* 1608 * Called from the upper layers when driver is in polling mode to 1609 * pick up any queued packets. Care should be taken to not block 1610 * this thread. 1611 */ 1612 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1613 { 1614 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1615 mblk_t *mp = NULL; 1616 mblk_t *tail; 1617 uint_t sz = 0; 1618 struct e1000g *adapter; 1619 1620 adapter = rx_ring->adapter; 1621 1622 rw_enter(&adapter->chip_lock, RW_READER); 1623 1624 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1625 rw_exit(&adapter->chip_lock); 1626 return (NULL); 1627 } 1628 1629 mutex_enter(&rx_ring->rx_lock); 1630 ASSERT(rx_ring->poll_flag); 1631 1632 /* 1633 * Get any packets that have arrived. Works only if we 1634 * actually disable the physical adapter/rx_ring interrupt. 1635 * (e1000g_poll_mode == 1). In case e1000g_poll_mode == 0, 1636 * packets will have already been added to the poll list 1637 * by the interrupt (see e1000g_intr_work()). 1638 */ 1639 if (adapter->poll_mode) { 1640 mp = e1000g_receive(rx_ring, &tail, &sz); 1641 if (mp != NULL) { 1642 if (rx_ring->poll_list_head == NULL) 1643 rx_ring->poll_list_head = mp; 1644 else 1645 rx_ring->poll_list_tail->b_next = mp; 1646 rx_ring->poll_list_tail = tail; 1647 rx_ring->poll_list_sz += sz; 1648 } 1649 } 1650 1651 mp = rx_ring->poll_list_head; 1652 if (mp == NULL) { 1653 mutex_exit(&rx_ring->rx_lock); 1654 rw_exit(&adapter->chip_lock); 1655 return (NULL); 1656 } 1657 1658 /* Check if we can sendup the entire chain */ 1659 if (bytes_to_pickup >= rx_ring->poll_list_sz) { 1660 mp = rx_ring->poll_list_head; 1661 rx_ring->poll_list_head = NULL; 1662 rx_ring->poll_list_tail = NULL; 1663 rx_ring->poll_list_sz = 0; 1664 mutex_exit(&rx_ring->rx_lock); 1665 rw_exit(&adapter->chip_lock); 1666 return (mp); 1667 } 1668 1669 /* 1670 * We need to find out how much chain we can send up. We 1671 * are guaranteed that atleast one packet will go up since 1672 * we already checked that. 1673 */ 1674 tail = mp; 1675 sz = 0; 1676 while (mp != NULL) { 1677 sz += MBLKL(mp); 1678 if (sz > bytes_to_pickup) { 1679 sz -= MBLKL(mp); 1680 break; 1681 } 1682 tail = mp; 1683 mp = mp->b_next; 1684 } 1685 1686 mp = rx_ring->poll_list_head; 1687 rx_ring->poll_list_head = tail->b_next; 1688 if (rx_ring->poll_list_head == NULL) 1689 rx_ring->poll_list_tail = NULL; 1690 rx_ring->poll_list_sz -= sz; 1691 tail->b_next = NULL; 1692 mutex_exit(&rx_ring->rx_lock); 1693 rw_exit(&adapter->chip_lock); 1694 return (mp); 1695 } 1696 1697 static int 1698 e1000g_m_start(void *arg) 1699 { 1700 struct e1000g *Adapter = (struct e1000g *)arg; 1701 1702 rw_enter(&Adapter->chip_lock, RW_WRITER); 1703 1704 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1705 rw_exit(&Adapter->chip_lock); 1706 return (ECANCELED); 1707 } 1708 1709 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1710 rw_exit(&Adapter->chip_lock); 1711 return (ENOTACTIVE); 1712 } 1713 1714 Adapter->e1000g_state |= E1000G_STARTED; 1715 1716 rw_exit(&Adapter->chip_lock); 1717 1718 /* Enable and start the watchdog timer */ 1719 enable_watchdog_timer(Adapter); 1720 1721 return (0); 1722 } 1723 1724 static int 1725 e1000g_start(struct e1000g *Adapter, boolean_t global) 1726 { 1727 if (global) { 1728 /* Allocate dma resources for descriptors and buffers */ 1729 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1730 e1000g_log(Adapter, CE_WARN, 1731 "Alloc DMA resources failed"); 1732 return (DDI_FAILURE); 1733 } 1734 Adapter->rx_buffer_setup = B_FALSE; 1735 } 1736 1737 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1738 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1739 e1000g_log(Adapter, CE_WARN, 1740 "Adapter initialization failed"); 1741 if (global) 1742 e1000g_release_dma_resources(Adapter); 1743 return (DDI_FAILURE); 1744 } 1745 } 1746 1747 /* Setup and initialize the transmit structures */ 1748 e1000g_tx_setup(Adapter); 1749 msec_delay(5); 1750 1751 /* Setup and initialize the receive structures */ 1752 e1000g_rx_setup(Adapter); 1753 msec_delay(5); 1754 1755 /* Restore the e1000g promiscuous mode */ 1756 e1000g_restore_promisc(Adapter); 1757 1758 e1000g_mask_interrupt(Adapter); 1759 1760 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1761 1762 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1763 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1764 return (DDI_FAILURE); 1765 } 1766 1767 return (DDI_SUCCESS); 1768 } 1769 1770 static void 1771 e1000g_m_stop(void *arg) 1772 { 1773 struct e1000g *Adapter = (struct e1000g *)arg; 1774 1775 /* Drain tx sessions */ 1776 (void) e1000g_tx_drain(Adapter); 1777 1778 rw_enter(&Adapter->chip_lock, RW_WRITER); 1779 1780 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1781 rw_exit(&Adapter->chip_lock); 1782 return; 1783 } 1784 Adapter->e1000g_state &= ~E1000G_STARTED; 1785 e1000g_stop(Adapter, B_TRUE); 1786 1787 rw_exit(&Adapter->chip_lock); 1788 1789 /* Disable and stop all the timers */ 1790 disable_watchdog_timer(Adapter); 1791 stop_link_timer(Adapter); 1792 stop_82547_timer(Adapter->tx_ring); 1793 } 1794 1795 static void 1796 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1797 { 1798 int result; 1799 1800 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1801 1802 /* Stop the chip and release pending resources */ 1803 1804 /* Tell firmware driver is no longer in control */ 1805 e1000g_release_driver_control(&Adapter->shared); 1806 1807 e1000g_clear_all_interrupts(Adapter); 1808 1809 mutex_enter(&e1000g_nvm_lock); 1810 result = e1000_reset_hw(&Adapter->shared); 1811 mutex_exit(&e1000g_nvm_lock); 1812 1813 if (result != E1000_SUCCESS) { 1814 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1815 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1816 } 1817 1818 /* Release resources still held by the TX descriptors */ 1819 e1000g_tx_clean(Adapter); 1820 1821 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1822 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1823 1824 /* Clean the pending rx jumbo packet fragment */ 1825 e1000g_rx_clean(Adapter); 1826 1827 if (global) 1828 e1000g_release_dma_resources(Adapter); 1829 } 1830 1831 static void 1832 e1000g_rx_clean(struct e1000g *Adapter) 1833 { 1834 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1835 1836 if (rx_ring->rx_mblk != NULL) { 1837 freemsg(rx_ring->rx_mblk); 1838 rx_ring->rx_mblk = NULL; 1839 rx_ring->rx_mblk_tail = NULL; 1840 rx_ring->rx_mblk_len = 0; 1841 } 1842 } 1843 1844 static void 1845 e1000g_tx_clean(struct e1000g *Adapter) 1846 { 1847 e1000g_tx_ring_t *tx_ring; 1848 p_tx_sw_packet_t packet; 1849 mblk_t *mp; 1850 mblk_t *nmp; 1851 uint32_t packet_count; 1852 1853 tx_ring = Adapter->tx_ring; 1854 1855 /* 1856 * Here we don't need to protect the lists using 1857 * the usedlist_lock and freelist_lock, for they 1858 * have been protected by the chip_lock. 1859 */ 1860 mp = NULL; 1861 nmp = NULL; 1862 packet_count = 0; 1863 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1864 while (packet != NULL) { 1865 if (packet->mp != NULL) { 1866 /* Assemble the message chain */ 1867 if (mp == NULL) { 1868 mp = packet->mp; 1869 nmp = packet->mp; 1870 } else { 1871 nmp->b_next = packet->mp; 1872 nmp = packet->mp; 1873 } 1874 /* Disconnect the message from the sw packet */ 1875 packet->mp = NULL; 1876 } 1877 1878 e1000g_free_tx_swpkt(packet); 1879 packet_count++; 1880 1881 packet = (p_tx_sw_packet_t) 1882 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1883 } 1884 1885 if (mp != NULL) 1886 freemsgchain(mp); 1887 1888 if (packet_count > 0) { 1889 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1890 QUEUE_INIT_LIST(&tx_ring->used_list); 1891 1892 /* Setup TX descriptor pointers */ 1893 tx_ring->tbd_next = tx_ring->tbd_first; 1894 tx_ring->tbd_oldest = tx_ring->tbd_first; 1895 1896 /* Setup our HW Tx Head & Tail descriptor pointers */ 1897 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1898 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1899 } 1900 } 1901 1902 static boolean_t 1903 e1000g_tx_drain(struct e1000g *Adapter) 1904 { 1905 int i; 1906 boolean_t done; 1907 e1000g_tx_ring_t *tx_ring; 1908 1909 tx_ring = Adapter->tx_ring; 1910 1911 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1912 for (i = 0; i < TX_DRAIN_TIME; i++) { 1913 mutex_enter(&tx_ring->usedlist_lock); 1914 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1915 mutex_exit(&tx_ring->usedlist_lock); 1916 1917 if (done) 1918 break; 1919 1920 msec_delay(1); 1921 } 1922 1923 return (done); 1924 } 1925 1926 static boolean_t 1927 e1000g_rx_drain(struct e1000g *Adapter) 1928 { 1929 e1000g_rx_ring_t *rx_ring; 1930 p_rx_sw_packet_t packet; 1931 boolean_t done; 1932 1933 rx_ring = Adapter->rx_ring; 1934 done = B_TRUE; 1935 1936 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1937 1938 while (rx_ring->pending_list != NULL) { 1939 packet = rx_ring->pending_list; 1940 rx_ring->pending_list = 1941 rx_ring->pending_list->next; 1942 1943 if (packet->flag == E1000G_RX_SW_STOP) { 1944 packet->flag = E1000G_RX_SW_DETACH; 1945 done = B_FALSE; 1946 } else { 1947 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1948 ASSERT(packet->mp == NULL); 1949 e1000g_free_rx_sw_packet(packet); 1950 } 1951 } 1952 1953 rw_exit(&e1000g_rx_detach_lock); 1954 1955 return (done); 1956 } 1957 1958 static boolean_t 1959 e1000g_reset_adapter(struct e1000g *Adapter) 1960 { 1961 /* Disable and stop all the timers */ 1962 disable_watchdog_timer(Adapter); 1963 stop_link_timer(Adapter); 1964 stop_82547_timer(Adapter->tx_ring); 1965 1966 rw_enter(&Adapter->chip_lock, RW_WRITER); 1967 1968 e1000g_stop(Adapter, B_FALSE); 1969 1970 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1971 rw_exit(&Adapter->chip_lock); 1972 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1973 return (B_FALSE); 1974 } 1975 1976 rw_exit(&Adapter->chip_lock); 1977 1978 /* Enable and start the watchdog timer */ 1979 enable_watchdog_timer(Adapter); 1980 1981 return (B_TRUE); 1982 } 1983 1984 boolean_t 1985 e1000g_global_reset(struct e1000g *Adapter) 1986 { 1987 /* Disable and stop all the timers */ 1988 disable_watchdog_timer(Adapter); 1989 stop_link_timer(Adapter); 1990 stop_82547_timer(Adapter->tx_ring); 1991 1992 rw_enter(&Adapter->chip_lock, RW_WRITER); 1993 1994 e1000g_stop(Adapter, B_TRUE); 1995 1996 Adapter->init_count = 0; 1997 1998 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1999 rw_exit(&Adapter->chip_lock); 2000 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2001 return (B_FALSE); 2002 } 2003 2004 rw_exit(&Adapter->chip_lock); 2005 2006 /* Enable and start the watchdog timer */ 2007 enable_watchdog_timer(Adapter); 2008 2009 return (B_TRUE); 2010 } 2011 2012 /* 2013 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2014 * 2015 * This interrupt service routine is for PCI-Express adapters. 2016 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2017 * bit is set. 2018 */ 2019 static uint_t 2020 e1000g_intr_pciexpress(caddr_t arg) 2021 { 2022 struct e1000g *Adapter; 2023 uint32_t icr; 2024 2025 Adapter = (struct e1000g *)(uintptr_t)arg; 2026 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2027 2028 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2029 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2030 2031 if (icr & E1000_ICR_INT_ASSERTED) { 2032 /* 2033 * E1000_ICR_INT_ASSERTED bit was set: 2034 * Read(Clear) the ICR, claim this interrupt, 2035 * look for work to do. 2036 */ 2037 e1000g_intr_work(Adapter, icr); 2038 return (DDI_INTR_CLAIMED); 2039 } else { 2040 /* 2041 * E1000_ICR_INT_ASSERTED bit was not set: 2042 * Don't claim this interrupt, return immediately. 2043 */ 2044 return (DDI_INTR_UNCLAIMED); 2045 } 2046 } 2047 2048 /* 2049 * e1000g_intr - ISR for PCI/PCI-X chipsets 2050 * 2051 * This interrupt service routine is for PCI/PCI-X adapters. 2052 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2053 * bit is set or not. 2054 */ 2055 static uint_t 2056 e1000g_intr(caddr_t arg) 2057 { 2058 struct e1000g *Adapter; 2059 uint32_t icr; 2060 2061 Adapter = (struct e1000g *)(uintptr_t)arg; 2062 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2063 2064 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2065 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2066 2067 if (icr) { 2068 /* 2069 * Any bit was set in ICR: 2070 * Read(Clear) the ICR, claim this interrupt, 2071 * look for work to do. 2072 */ 2073 e1000g_intr_work(Adapter, icr); 2074 return (DDI_INTR_CLAIMED); 2075 } else { 2076 /* 2077 * No bit was set in ICR: 2078 * Don't claim this interrupt, return immediately. 2079 */ 2080 return (DDI_INTR_UNCLAIMED); 2081 } 2082 } 2083 2084 /* 2085 * e1000g_intr_work - actual processing of ISR 2086 * 2087 * Read(clear) the ICR contents and call appropriate interrupt 2088 * processing routines. 2089 */ 2090 static void 2091 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2092 { 2093 struct e1000_hw *hw; 2094 hw = &Adapter->shared; 2095 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2096 2097 Adapter->rx_pkt_cnt = 0; 2098 Adapter->tx_pkt_cnt = 0; 2099 2100 rw_enter(&Adapter->chip_lock, RW_READER); 2101 2102 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2103 rw_exit(&Adapter->chip_lock); 2104 return; 2105 } 2106 /* 2107 * Here we need to check the "e1000g_state" flag within the chip_lock to 2108 * ensure the receive routine will not execute when the adapter is 2109 * being reset. 2110 */ 2111 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2112 rw_exit(&Adapter->chip_lock); 2113 return; 2114 } 2115 2116 if (icr & E1000_ICR_RXT0) { 2117 mblk_t *mp; 2118 uint_t sz = 0; 2119 mblk_t *tmp, *tail = NULL; 2120 e1000g_rx_ring_t *rx_ring; 2121 2122 rx_ring = Adapter->rx_ring; 2123 mutex_enter(&rx_ring->rx_lock); 2124 2125 /* 2126 * If the real interrupt for the Rx ring was 2127 * not disabled (e1000g_poll_mode == 0), then 2128 * we still pick up the packets and queue them 2129 * on Rx ring if we were in polling mode. this 2130 * enables the polling thread to pick up packets 2131 * really fast in polling mode and helps improve 2132 * latency. 2133 */ 2134 mp = e1000g_receive(rx_ring, &tail, &sz); 2135 rw_exit(&Adapter->chip_lock); 2136 2137 if (mp != NULL) { 2138 ASSERT(tail != NULL); 2139 if (!rx_ring->poll_flag) { 2140 /* 2141 * If not polling, see if something was 2142 * already queued. Take care not to 2143 * reorder packets. 2144 */ 2145 if (rx_ring->poll_list_head == NULL) { 2146 mutex_exit(&rx_ring->rx_lock); 2147 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2148 mp, rx_ring->ring_gen_num); 2149 } else { 2150 tmp = rx_ring->poll_list_head; 2151 rx_ring->poll_list_head = NULL; 2152 rx_ring->poll_list_tail->b_next = mp; 2153 rx_ring->poll_list_tail = NULL; 2154 rx_ring->poll_list_sz = 0; 2155 mutex_exit(&rx_ring->rx_lock); 2156 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2157 tmp, rx_ring->ring_gen_num); 2158 } 2159 } else { 2160 /* 2161 * We are in a polling mode. Put the 2162 * processed packets on the poll list. 2163 */ 2164 if (rx_ring->poll_list_head == NULL) 2165 rx_ring->poll_list_head = mp; 2166 else 2167 rx_ring->poll_list_tail->b_next = mp; 2168 rx_ring->poll_list_tail = tail; 2169 rx_ring->poll_list_sz += sz; 2170 mutex_exit(&rx_ring->rx_lock); 2171 } 2172 } else if (!rx_ring->poll_flag && 2173 rx_ring->poll_list_head != NULL) { 2174 /* 2175 * Nothing new has arrived (then why 2176 * was the interrupt raised??). Check 2177 * if something queued from the last 2178 * time. 2179 */ 2180 tmp = rx_ring->poll_list_head; 2181 rx_ring->poll_list_head = NULL; 2182 rx_ring->poll_list_tail = NULL; 2183 rx_ring->poll_list_sz = 0; 2184 mutex_exit(&rx_ring->rx_lock); 2185 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2186 tmp, rx_ring->ring_gen_num); 2187 } else { 2188 mutex_exit(&rx_ring->rx_lock); 2189 } 2190 } else 2191 rw_exit(&Adapter->chip_lock); 2192 2193 if (icr & E1000_ICR_TXDW) { 2194 if (!Adapter->tx_intr_enable) 2195 e1000g_clear_tx_interrupt(Adapter); 2196 2197 /* Recycle the tx descriptors */ 2198 rw_enter(&Adapter->chip_lock, RW_READER); 2199 (void) e1000g_recycle(tx_ring); 2200 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2201 rw_exit(&Adapter->chip_lock); 2202 2203 if (tx_ring->resched_needed && 2204 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2205 tx_ring->resched_needed = B_FALSE; 2206 mac_tx_update(Adapter->mh); 2207 E1000G_STAT(tx_ring->stat_reschedule); 2208 } 2209 } 2210 2211 /* 2212 * The Receive Sequence errors RXSEQ and the link status change LSC 2213 * are checked to detect that the cable has been pulled out. For 2214 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2215 * are an indication that cable is not connected. 2216 */ 2217 if ((icr & E1000_ICR_RXSEQ) || 2218 (icr & E1000_ICR_LSC) || 2219 (icr & E1000_ICR_GPI_EN1)) { 2220 boolean_t link_changed; 2221 timeout_id_t tid = 0; 2222 2223 stop_watchdog_timer(Adapter); 2224 2225 rw_enter(&Adapter->chip_lock, RW_WRITER); 2226 2227 /* 2228 * Because we got a link-status-change interrupt, force 2229 * e1000_check_for_link() to look at phy 2230 */ 2231 Adapter->shared.mac.get_link_status = B_TRUE; 2232 2233 /* e1000g_link_check takes care of link status change */ 2234 link_changed = e1000g_link_check(Adapter); 2235 2236 /* Get new phy state */ 2237 e1000g_get_phy_state(Adapter); 2238 2239 /* 2240 * If the link timer has not timed out, we'll not notify 2241 * the upper layer with any link state until the link is up. 2242 */ 2243 if (link_changed && !Adapter->link_complete) { 2244 if (Adapter->link_state == LINK_STATE_UP) { 2245 mutex_enter(&Adapter->link_lock); 2246 Adapter->link_complete = B_TRUE; 2247 tid = Adapter->link_tid; 2248 Adapter->link_tid = 0; 2249 mutex_exit(&Adapter->link_lock); 2250 } else { 2251 link_changed = B_FALSE; 2252 } 2253 } 2254 rw_exit(&Adapter->chip_lock); 2255 2256 if (link_changed) { 2257 if (tid != 0) 2258 (void) untimeout(tid); 2259 2260 /* 2261 * Workaround for esb2. Data stuck in fifo on a link 2262 * down event. Stop receiver here and reset in watchdog. 2263 */ 2264 if ((Adapter->link_state == LINK_STATE_DOWN) && 2265 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2266 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2267 E1000_WRITE_REG(hw, E1000_RCTL, 2268 rctl & ~E1000_RCTL_EN); 2269 e1000g_log(Adapter, CE_WARN, 2270 "ESB2 receiver disabled"); 2271 Adapter->esb2_workaround = B_TRUE; 2272 } 2273 2274 mac_link_update(Adapter->mh, Adapter->link_state); 2275 } 2276 2277 start_watchdog_timer(Adapter); 2278 } 2279 } 2280 2281 static void 2282 e1000g_init_unicst(struct e1000g *Adapter) 2283 { 2284 struct e1000_hw *hw; 2285 int slot; 2286 2287 hw = &Adapter->shared; 2288 2289 if (Adapter->init_count == 0) { 2290 /* Initialize the multiple unicast addresses */ 2291 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2292 2293 /* Workaround for an erratum of 82571 chipst */ 2294 if ((hw->mac.type == e1000_82571) && 2295 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2296 Adapter->unicst_total--; 2297 2298 Adapter->unicst_avail = Adapter->unicst_total; 2299 2300 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2301 /* Clear both the flag and MAC address */ 2302 Adapter->unicst_addr[slot].reg.high = 0; 2303 Adapter->unicst_addr[slot].reg.low = 0; 2304 } 2305 } else { 2306 /* Workaround for an erratum of 82571 chipst */ 2307 if ((hw->mac.type == e1000_82571) && 2308 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2309 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2310 2311 /* Re-configure the RAR registers */ 2312 for (slot = 0; slot < Adapter->unicst_total; slot++) 2313 if (Adapter->unicst_addr[slot].mac.set == 1) 2314 e1000_rar_set(hw, 2315 Adapter->unicst_addr[slot].mac.addr, slot); 2316 } 2317 2318 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2319 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2320 } 2321 2322 static int 2323 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2324 int slot) 2325 { 2326 struct e1000_hw *hw; 2327 2328 hw = &Adapter->shared; 2329 2330 /* 2331 * The first revision of Wiseman silicon (rev 2.0) has an errata 2332 * that requires the receiver to be in reset when any of the 2333 * receive address registers (RAR regs) are accessed. The first 2334 * rev of Wiseman silicon also requires MWI to be disabled when 2335 * a global reset or a receive reset is issued. So before we 2336 * initialize the RARs, we check the rev of the Wiseman controller 2337 * and work around any necessary HW errata. 2338 */ 2339 if ((hw->mac.type == e1000_82542) && 2340 (hw->revision_id == E1000_REVISION_2)) { 2341 e1000_pci_clear_mwi(hw); 2342 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2343 msec_delay(5); 2344 } 2345 if (mac_addr == NULL) { 2346 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2347 E1000_WRITE_FLUSH(hw); 2348 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2349 E1000_WRITE_FLUSH(hw); 2350 /* Clear both the flag and MAC address */ 2351 Adapter->unicst_addr[slot].reg.high = 0; 2352 Adapter->unicst_addr[slot].reg.low = 0; 2353 } else { 2354 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2355 ETHERADDRL); 2356 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2357 Adapter->unicst_addr[slot].mac.set = 1; 2358 } 2359 2360 /* Workaround for an erratum of 82571 chipst */ 2361 if (slot == 0) { 2362 if ((hw->mac.type == e1000_82571) && 2363 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2364 if (mac_addr == NULL) { 2365 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2366 slot << 1, 0); 2367 E1000_WRITE_FLUSH(hw); 2368 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2369 (slot << 1) + 1, 0); 2370 E1000_WRITE_FLUSH(hw); 2371 } else { 2372 e1000_rar_set(hw, (uint8_t *)mac_addr, 2373 LAST_RAR_ENTRY); 2374 } 2375 } 2376 2377 /* 2378 * If we are using Wiseman rev 2.0 silicon, we will have previously 2379 * put the receive in reset, and disabled MWI, to work around some 2380 * HW errata. Now we should take the receiver out of reset, and 2381 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2382 */ 2383 if ((hw->mac.type == e1000_82542) && 2384 (hw->revision_id == E1000_REVISION_2)) { 2385 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2386 msec_delay(1); 2387 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2388 e1000_pci_set_mwi(hw); 2389 e1000g_rx_setup(Adapter); 2390 } 2391 2392 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2393 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2394 return (EIO); 2395 } 2396 2397 return (0); 2398 } 2399 2400 static int 2401 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2402 { 2403 struct e1000_hw *hw = &Adapter->shared; 2404 int res = 0; 2405 2406 if ((multiaddr[0] & 01) == 0) { 2407 res = EINVAL; 2408 goto done; 2409 } 2410 2411 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2412 res = ENOENT; 2413 goto done; 2414 } 2415 2416 bcopy(multiaddr, 2417 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2418 Adapter->mcast_count++; 2419 2420 /* 2421 * Update the MC table in the hardware 2422 */ 2423 e1000g_clear_interrupt(Adapter); 2424 2425 e1000g_setup_multicast(Adapter); 2426 2427 if ((hw->mac.type == e1000_82542) && 2428 (hw->revision_id == E1000_REVISION_2)) 2429 e1000g_rx_setup(Adapter); 2430 2431 e1000g_mask_interrupt(Adapter); 2432 2433 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2434 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2435 res = EIO; 2436 } 2437 2438 done: 2439 return (res); 2440 } 2441 2442 static int 2443 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2444 { 2445 struct e1000_hw *hw = &Adapter->shared; 2446 unsigned i; 2447 2448 for (i = 0; i < Adapter->mcast_count; i++) { 2449 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2450 ETHERADDRL) == 0) { 2451 for (i++; i < Adapter->mcast_count; i++) { 2452 Adapter->mcast_table[i - 1] = 2453 Adapter->mcast_table[i]; 2454 } 2455 Adapter->mcast_count--; 2456 break; 2457 } 2458 } 2459 2460 /* 2461 * Update the MC table in the hardware 2462 */ 2463 e1000g_clear_interrupt(Adapter); 2464 2465 e1000g_setup_multicast(Adapter); 2466 2467 if ((hw->mac.type == e1000_82542) && 2468 (hw->revision_id == E1000_REVISION_2)) 2469 e1000g_rx_setup(Adapter); 2470 2471 e1000g_mask_interrupt(Adapter); 2472 2473 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2474 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2475 return (EIO); 2476 } 2477 2478 return (0); 2479 } 2480 2481 /* 2482 * e1000g_setup_multicast - setup multicast data structures 2483 * 2484 * This routine initializes all of the multicast related structures. 2485 */ 2486 void 2487 e1000g_setup_multicast(struct e1000g *Adapter) 2488 { 2489 uint8_t *mc_addr_list; 2490 uint32_t mc_addr_count; 2491 uint32_t rctl; 2492 struct e1000_hw *hw; 2493 2494 hw = &Adapter->shared; 2495 2496 /* 2497 * The e1000g has the ability to do perfect filtering of 16 2498 * addresses. The driver uses one of the e1000g's 16 receive 2499 * address registers for its node/network/mac/individual address. 2500 * So, we have room for up to 15 multicast addresses in the CAM, 2501 * additional MC addresses are handled by the MTA (Multicast Table 2502 * Array) 2503 */ 2504 2505 rctl = E1000_READ_REG(hw, E1000_RCTL); 2506 2507 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2508 2509 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2510 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2511 "Adapter requested more than %d MC Addresses.\n", 2512 MAX_NUM_MULTICAST_ADDRESSES); 2513 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2514 } else { 2515 /* 2516 * Set the number of MC addresses that we are being 2517 * requested to use 2518 */ 2519 mc_addr_count = Adapter->mcast_count; 2520 } 2521 /* 2522 * The Wiseman 2.0 silicon has an errata by which the receiver will 2523 * hang while writing to the receive address registers if the receiver 2524 * is not in reset before writing to the registers. Updating the RAR 2525 * is done during the setting up of the multicast table, hence the 2526 * receiver has to be put in reset before updating the multicast table 2527 * and then taken out of reset at the end 2528 */ 2529 /* 2530 * if WMI was enabled then dis able it before issueing the global 2531 * reset to the hardware. 2532 */ 2533 /* 2534 * Only required for WISEMAN_2_0 2535 */ 2536 if ((hw->mac.type == e1000_82542) && 2537 (hw->revision_id == E1000_REVISION_2)) { 2538 e1000_pci_clear_mwi(hw); 2539 /* 2540 * The e1000g must be in reset before changing any RA 2541 * registers. Reset receive unit. The chip will remain in 2542 * the reset state until software explicitly restarts it. 2543 */ 2544 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2545 /* Allow receiver time to go in to reset */ 2546 msec_delay(5); 2547 } 2548 2549 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2550 Adapter->unicst_total, hw->mac.rar_entry_count); 2551 2552 /* 2553 * Only for Wiseman_2_0 2554 * If MWI was enabled then re-enable it after issueing (as we 2555 * disabled it up there) the receive reset command. 2556 * Wainwright does not have a receive reset command and only thing 2557 * close to it is global reset which will require tx setup also 2558 */ 2559 if ((hw->mac.type == e1000_82542) && 2560 (hw->revision_id == E1000_REVISION_2)) { 2561 /* 2562 * if WMI was enabled then reenable it after issueing the 2563 * global or receive reset to the hardware. 2564 */ 2565 2566 /* 2567 * Take receiver out of reset 2568 * clear E1000_RCTL_RST bit (and all others) 2569 */ 2570 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2571 msec_delay(5); 2572 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2573 e1000_pci_set_mwi(hw); 2574 } 2575 2576 /* 2577 * Restore original value 2578 */ 2579 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2580 } 2581 2582 int 2583 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2584 { 2585 struct e1000g *Adapter = (struct e1000g *)arg; 2586 int result; 2587 2588 rw_enter(&Adapter->chip_lock, RW_WRITER); 2589 2590 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2591 result = ECANCELED; 2592 goto done; 2593 } 2594 2595 result = (add) ? multicst_add(Adapter, addr) 2596 : multicst_remove(Adapter, addr); 2597 2598 done: 2599 rw_exit(&Adapter->chip_lock); 2600 return (result); 2601 2602 } 2603 2604 int 2605 e1000g_m_promisc(void *arg, boolean_t on) 2606 { 2607 struct e1000g *Adapter = (struct e1000g *)arg; 2608 uint32_t rctl; 2609 2610 rw_enter(&Adapter->chip_lock, RW_WRITER); 2611 2612 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2613 rw_exit(&Adapter->chip_lock); 2614 return (ECANCELED); 2615 } 2616 2617 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2618 2619 if (on) 2620 rctl |= 2621 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2622 else 2623 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2624 2625 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2626 2627 Adapter->e1000g_promisc = on; 2628 2629 rw_exit(&Adapter->chip_lock); 2630 2631 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2632 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2633 return (EIO); 2634 } 2635 2636 return (0); 2637 } 2638 2639 /* 2640 * Entry points to enable and disable interrupts at the granularity of 2641 * a group. 2642 * Turns the poll_mode for the whole adapter on and off to enable or 2643 * override the ring level polling control over the hardware interrupts. 2644 */ 2645 static int 2646 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2647 { 2648 struct e1000g *adapter = (struct e1000g *)arg; 2649 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2650 2651 /* 2652 * Later interrupts at the granularity of the this ring will 2653 * invoke mac_rx() with NULL, indicating the need for another 2654 * software classification. 2655 * We have a single ring usable per adapter now, so we only need to 2656 * reset the rx handle for that one. 2657 * When more RX rings can be used, we should update each one of them. 2658 */ 2659 mutex_enter(&rx_ring->rx_lock); 2660 rx_ring->mrh = NULL; 2661 adapter->poll_mode = B_FALSE; 2662 mutex_exit(&rx_ring->rx_lock); 2663 return (0); 2664 } 2665 2666 static int 2667 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2668 { 2669 struct e1000g *adapter = (struct e1000g *)arg; 2670 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2671 2672 mutex_enter(&rx_ring->rx_lock); 2673 2674 /* 2675 * Later interrupts at the granularity of the this ring will 2676 * invoke mac_rx() with the handle for this ring; 2677 */ 2678 adapter->poll_mode = B_TRUE; 2679 rx_ring->mrh = rx_ring->mrh_init; 2680 mutex_exit(&rx_ring->rx_lock); 2681 return (0); 2682 } 2683 2684 /* 2685 * Entry points to enable and disable interrupts at the granularity of 2686 * a ring. 2687 * adapter poll_mode controls whether we actually proceed with hardware 2688 * interrupt toggling. 2689 */ 2690 static int 2691 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2692 { 2693 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2694 struct e1000g *adapter = rx_ring->adapter; 2695 struct e1000_hw *hw = &adapter->shared; 2696 uint32_t intr_mask; 2697 boolean_t poll_mode; 2698 2699 rw_enter(&adapter->chip_lock, RW_READER); 2700 2701 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2702 rw_exit(&adapter->chip_lock); 2703 return (0); 2704 } 2705 2706 mutex_enter(&rx_ring->rx_lock); 2707 rx_ring->poll_flag = 0; 2708 poll_mode = adapter->poll_mode; 2709 mutex_exit(&rx_ring->rx_lock); 2710 2711 if (poll_mode) { 2712 /* Rx interrupt enabling for MSI and legacy */ 2713 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2714 intr_mask |= E1000_IMS_RXT0; 2715 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2716 E1000_WRITE_FLUSH(hw); 2717 2718 /* Trigger a Rx interrupt to check Rx ring */ 2719 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2720 E1000_WRITE_FLUSH(hw); 2721 } 2722 2723 rw_exit(&adapter->chip_lock); 2724 return (0); 2725 } 2726 2727 static int 2728 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2729 { 2730 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2731 struct e1000g *adapter = rx_ring->adapter; 2732 struct e1000_hw *hw = &adapter->shared; 2733 boolean_t poll_mode; 2734 2735 rw_enter(&adapter->chip_lock, RW_READER); 2736 2737 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2738 rw_exit(&adapter->chip_lock); 2739 return (0); 2740 } 2741 2742 /* 2743 * Once the adapter can support per Rx ring interrupt, 2744 * we should disable the real interrupt instead of just setting 2745 * the flag. 2746 */ 2747 mutex_enter(&rx_ring->rx_lock); 2748 rx_ring->poll_flag = 1; 2749 poll_mode = adapter->poll_mode; 2750 mutex_exit(&rx_ring->rx_lock); 2751 2752 if (poll_mode) { 2753 /* Rx interrupt disabling for MSI and legacy */ 2754 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2755 E1000_WRITE_FLUSH(hw); 2756 } 2757 2758 rw_exit(&adapter->chip_lock); 2759 return (0); 2760 } 2761 2762 /* 2763 * e1000g_unicst_find - Find the slot for the specified unicast address 2764 */ 2765 static int 2766 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2767 { 2768 int slot; 2769 2770 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2771 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2772 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2773 mac_addr, ETHERADDRL) == 0)) 2774 return (slot); 2775 } 2776 2777 return (-1); 2778 } 2779 2780 /* 2781 * Entry points to add and remove a MAC address to a ring group. 2782 * The caller takes care of adding and removing the MAC addresses 2783 * to the filter via these two routines. 2784 */ 2785 2786 static int 2787 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2788 { 2789 struct e1000g *Adapter = (struct e1000g *)arg; 2790 int slot, err; 2791 2792 rw_enter(&Adapter->chip_lock, RW_WRITER); 2793 2794 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2795 rw_exit(&Adapter->chip_lock); 2796 return (ECANCELED); 2797 } 2798 2799 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2800 /* The same address is already in slot */ 2801 rw_exit(&Adapter->chip_lock); 2802 return (0); 2803 } 2804 2805 if (Adapter->unicst_avail == 0) { 2806 /* no slots available */ 2807 rw_exit(&Adapter->chip_lock); 2808 return (ENOSPC); 2809 } 2810 2811 /* Search for a free slot */ 2812 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2813 if (Adapter->unicst_addr[slot].mac.set == 0) 2814 break; 2815 } 2816 ASSERT(slot < Adapter->unicst_total); 2817 2818 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2819 if (err == 0) 2820 Adapter->unicst_avail--; 2821 2822 rw_exit(&Adapter->chip_lock); 2823 2824 return (err); 2825 } 2826 2827 static int 2828 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2829 { 2830 struct e1000g *Adapter = (struct e1000g *)arg; 2831 int slot, err; 2832 2833 rw_enter(&Adapter->chip_lock, RW_WRITER); 2834 2835 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2836 rw_exit(&Adapter->chip_lock); 2837 return (ECANCELED); 2838 } 2839 2840 slot = e1000g_unicst_find(Adapter, mac_addr); 2841 if (slot == -1) { 2842 rw_exit(&Adapter->chip_lock); 2843 return (EINVAL); 2844 } 2845 2846 ASSERT(Adapter->unicst_addr[slot].mac.set); 2847 2848 /* Clear this slot */ 2849 err = e1000g_unicst_set(Adapter, NULL, slot); 2850 if (err == 0) 2851 Adapter->unicst_avail++; 2852 2853 rw_exit(&Adapter->chip_lock); 2854 2855 return (err); 2856 } 2857 2858 static int 2859 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2860 { 2861 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2862 2863 mutex_enter(&rx_ring->rx_lock); 2864 rx_ring->ring_gen_num = mr_gen_num; 2865 mutex_exit(&rx_ring->rx_lock); 2866 return (0); 2867 } 2868 2869 /* 2870 * Callback funtion for MAC layer to register all rings. 2871 * 2872 * The hardware supports a single group with currently only one ring 2873 * available. 2874 * Though not offering virtualization ability per se, exposing the 2875 * group/ring still enables the polling and interrupt toggling. 2876 */ 2877 void 2878 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2879 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2880 { 2881 struct e1000g *Adapter = (struct e1000g *)arg; 2882 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2883 mac_intr_t *mintr; 2884 2885 /* 2886 * We advertised only RX group/rings, so the MAC framework shouldn't 2887 * ask for any thing else. 2888 */ 2889 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2890 2891 rx_ring->mrh = rx_ring->mrh_init = rh; 2892 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2893 infop->mri_start = e1000g_ring_start; 2894 infop->mri_stop = NULL; 2895 infop->mri_poll = e1000g_poll_ring; 2896 2897 /* Ring level interrupts */ 2898 mintr = &infop->mri_intr; 2899 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2900 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2901 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2902 } 2903 2904 static void 2905 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2906 mac_group_info_t *infop, mac_group_handle_t gh) 2907 { 2908 struct e1000g *Adapter = (struct e1000g *)arg; 2909 mac_intr_t *mintr; 2910 2911 /* 2912 * We advertised a single RX ring. Getting a request for anything else 2913 * signifies a bug in the MAC framework. 2914 */ 2915 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2916 2917 Adapter->rx_group = gh; 2918 2919 infop->mgi_driver = (mac_group_driver_t)Adapter; 2920 infop->mgi_start = NULL; 2921 infop->mgi_stop = NULL; 2922 infop->mgi_addmac = e1000g_addmac; 2923 infop->mgi_remmac = e1000g_remmac; 2924 infop->mgi_count = 1; 2925 2926 /* Group level interrupts */ 2927 mintr = &infop->mgi_intr; 2928 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2929 mintr->mi_enable = e1000g_rx_group_intr_enable; 2930 mintr->mi_disable = e1000g_rx_group_intr_disable; 2931 } 2932 2933 static boolean_t 2934 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2935 { 2936 struct e1000g *Adapter = (struct e1000g *)arg; 2937 2938 switch (cap) { 2939 case MAC_CAPAB_HCKSUM: { 2940 uint32_t *txflags = cap_data; 2941 2942 if (Adapter->tx_hcksum_enable) 2943 *txflags = HCKSUM_IPHDRCKSUM | 2944 HCKSUM_INET_PARTIAL; 2945 else 2946 return (B_FALSE); 2947 break; 2948 } 2949 2950 case MAC_CAPAB_LSO: { 2951 mac_capab_lso_t *cap_lso = cap_data; 2952 2953 if (Adapter->lso_enable) { 2954 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2955 cap_lso->lso_basic_tcp_ipv4.lso_max = 2956 E1000_LSO_MAXLEN; 2957 } else 2958 return (B_FALSE); 2959 break; 2960 } 2961 case MAC_CAPAB_RINGS: { 2962 mac_capab_rings_t *cap_rings = cap_data; 2963 2964 /* No TX rings exposed yet */ 2965 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2966 return (B_FALSE); 2967 2968 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2969 cap_rings->mr_rnum = 1; 2970 cap_rings->mr_gnum = 1; 2971 cap_rings->mr_rget = e1000g_fill_ring; 2972 cap_rings->mr_gget = e1000g_fill_group; 2973 break; 2974 } 2975 default: 2976 return (B_FALSE); 2977 } 2978 return (B_TRUE); 2979 } 2980 2981 static boolean_t 2982 e1000g_param_locked(mac_prop_id_t pr_num) 2983 { 2984 /* 2985 * All en_* parameters are locked (read-only) while 2986 * the device is in any sort of loopback mode ... 2987 */ 2988 switch (pr_num) { 2989 case MAC_PROP_EN_1000FDX_CAP: 2990 case MAC_PROP_EN_1000HDX_CAP: 2991 case MAC_PROP_EN_100FDX_CAP: 2992 case MAC_PROP_EN_100HDX_CAP: 2993 case MAC_PROP_EN_10FDX_CAP: 2994 case MAC_PROP_EN_10HDX_CAP: 2995 case MAC_PROP_AUTONEG: 2996 case MAC_PROP_FLOWCTRL: 2997 return (B_TRUE); 2998 } 2999 return (B_FALSE); 3000 } 3001 3002 /* 3003 * callback function for set/get of properties 3004 */ 3005 static int 3006 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3007 uint_t pr_valsize, const void *pr_val) 3008 { 3009 struct e1000g *Adapter = arg; 3010 struct e1000_mac_info *mac = &Adapter->shared.mac; 3011 struct e1000_phy_info *phy = &Adapter->shared.phy; 3012 struct e1000_fc_info *fc = &Adapter->shared.fc; 3013 int err = 0; 3014 link_flowctrl_t flowctrl; 3015 uint32_t cur_mtu, new_mtu; 3016 uint64_t tmp = 0; 3017 3018 rw_enter(&Adapter->chip_lock, RW_WRITER); 3019 3020 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3021 rw_exit(&Adapter->chip_lock); 3022 return (ECANCELED); 3023 } 3024 3025 if (Adapter->loopback_mode != E1000G_LB_NONE && 3026 e1000g_param_locked(pr_num)) { 3027 /* 3028 * All en_* parameters are locked (read-only) 3029 * while the device is in any sort of loopback mode. 3030 */ 3031 rw_exit(&Adapter->chip_lock); 3032 return (EBUSY); 3033 } 3034 3035 switch (pr_num) { 3036 case MAC_PROP_EN_1000FDX_CAP: 3037 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3038 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3039 goto reset; 3040 case MAC_PROP_EN_100FDX_CAP: 3041 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3042 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3043 goto reset; 3044 case MAC_PROP_EN_100HDX_CAP: 3045 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3046 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3047 goto reset; 3048 case MAC_PROP_EN_10FDX_CAP: 3049 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3050 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3051 goto reset; 3052 case MAC_PROP_EN_10HDX_CAP: 3053 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3054 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3055 goto reset; 3056 case MAC_PROP_AUTONEG: 3057 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3058 goto reset; 3059 case MAC_PROP_FLOWCTRL: 3060 fc->send_xon = B_TRUE; 3061 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3062 3063 switch (flowctrl) { 3064 default: 3065 err = EINVAL; 3066 break; 3067 case LINK_FLOWCTRL_NONE: 3068 fc->current_mode = e1000_fc_none; 3069 break; 3070 case LINK_FLOWCTRL_RX: 3071 fc->current_mode = e1000_fc_rx_pause; 3072 break; 3073 case LINK_FLOWCTRL_TX: 3074 fc->current_mode = e1000_fc_tx_pause; 3075 break; 3076 case LINK_FLOWCTRL_BI: 3077 fc->current_mode = e1000_fc_full; 3078 break; 3079 } 3080 reset: 3081 if (err == 0) { 3082 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3083 err = EINVAL; 3084 } 3085 break; 3086 case MAC_PROP_ADV_1000FDX_CAP: 3087 case MAC_PROP_ADV_1000HDX_CAP: 3088 case MAC_PROP_ADV_100FDX_CAP: 3089 case MAC_PROP_ADV_100HDX_CAP: 3090 case MAC_PROP_ADV_10FDX_CAP: 3091 case MAC_PROP_ADV_10HDX_CAP: 3092 case MAC_PROP_EN_1000HDX_CAP: 3093 case MAC_PROP_STATUS: 3094 case MAC_PROP_SPEED: 3095 case MAC_PROP_DUPLEX: 3096 err = ENOTSUP; /* read-only prop. Can't set this. */ 3097 break; 3098 case MAC_PROP_MTU: 3099 cur_mtu = Adapter->default_mtu; 3100 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3101 if (new_mtu == cur_mtu) { 3102 err = 0; 3103 break; 3104 } 3105 3106 tmp = new_mtu + sizeof (struct ether_vlan_header) + 3107 ETHERFCSL; 3108 if ((tmp < DEFAULT_FRAME_SIZE) || 3109 (tmp > MAXIMUM_FRAME_SIZE)) { 3110 err = EINVAL; 3111 break; 3112 } 3113 3114 /* ich8 does not support jumbo frames */ 3115 if ((mac->type == e1000_ich8lan) && 3116 (tmp > DEFAULT_FRAME_SIZE)) { 3117 err = EINVAL; 3118 break; 3119 } 3120 /* ich9 does not do jumbo frames on one phy type */ 3121 if ((mac->type == e1000_ich9lan) && 3122 (phy->type == e1000_phy_ife) && 3123 (tmp > DEFAULT_FRAME_SIZE)) { 3124 err = EINVAL; 3125 break; 3126 } 3127 if (Adapter->e1000g_state & E1000G_STARTED) { 3128 err = EBUSY; 3129 break; 3130 } 3131 3132 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3133 if (err == 0) { 3134 Adapter->max_frame_size = (uint32_t)tmp; 3135 Adapter->default_mtu = new_mtu; 3136 e1000g_set_bufsize(Adapter); 3137 } 3138 break; 3139 case MAC_PROP_PRIVATE: 3140 err = e1000g_set_priv_prop(Adapter, pr_name, 3141 pr_valsize, pr_val); 3142 break; 3143 default: 3144 err = ENOTSUP; 3145 break; 3146 } 3147 rw_exit(&Adapter->chip_lock); 3148 return (err); 3149 } 3150 3151 static int 3152 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3153 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3154 { 3155 struct e1000g *Adapter = arg; 3156 struct e1000_fc_info *fc = &Adapter->shared.fc; 3157 int err = 0; 3158 link_flowctrl_t flowctrl; 3159 uint64_t tmp = 0; 3160 3161 if (pr_valsize == 0) 3162 return (EINVAL); 3163 3164 *perm = MAC_PROP_PERM_RW; 3165 3166 bzero(pr_val, pr_valsize); 3167 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3168 return (e1000g_get_def_val(Adapter, pr_num, 3169 pr_valsize, pr_val)); 3170 } 3171 3172 switch (pr_num) { 3173 case MAC_PROP_DUPLEX: 3174 *perm = MAC_PROP_PERM_READ; 3175 if (pr_valsize >= sizeof (link_duplex_t)) { 3176 bcopy(&Adapter->link_duplex, pr_val, 3177 sizeof (link_duplex_t)); 3178 } else 3179 err = EINVAL; 3180 break; 3181 case MAC_PROP_SPEED: 3182 *perm = MAC_PROP_PERM_READ; 3183 if (pr_valsize >= sizeof (uint64_t)) { 3184 tmp = Adapter->link_speed * 1000000ull; 3185 bcopy(&tmp, pr_val, sizeof (tmp)); 3186 } else 3187 err = EINVAL; 3188 break; 3189 case MAC_PROP_AUTONEG: 3190 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3191 break; 3192 case MAC_PROP_FLOWCTRL: 3193 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3194 switch (fc->current_mode) { 3195 case e1000_fc_none: 3196 flowctrl = LINK_FLOWCTRL_NONE; 3197 break; 3198 case e1000_fc_rx_pause: 3199 flowctrl = LINK_FLOWCTRL_RX; 3200 break; 3201 case e1000_fc_tx_pause: 3202 flowctrl = LINK_FLOWCTRL_TX; 3203 break; 3204 case e1000_fc_full: 3205 flowctrl = LINK_FLOWCTRL_BI; 3206 break; 3207 } 3208 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3209 } else 3210 err = EINVAL; 3211 break; 3212 case MAC_PROP_ADV_1000FDX_CAP: 3213 *perm = MAC_PROP_PERM_READ; 3214 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3215 break; 3216 case MAC_PROP_EN_1000FDX_CAP: 3217 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3218 break; 3219 case MAC_PROP_ADV_1000HDX_CAP: 3220 *perm = MAC_PROP_PERM_READ; 3221 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3222 break; 3223 case MAC_PROP_EN_1000HDX_CAP: 3224 *perm = MAC_PROP_PERM_READ; 3225 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3226 break; 3227 case MAC_PROP_ADV_100FDX_CAP: 3228 *perm = MAC_PROP_PERM_READ; 3229 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3230 break; 3231 case MAC_PROP_EN_100FDX_CAP: 3232 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3233 break; 3234 case MAC_PROP_ADV_100HDX_CAP: 3235 *perm = MAC_PROP_PERM_READ; 3236 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3237 break; 3238 case MAC_PROP_EN_100HDX_CAP: 3239 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3240 break; 3241 case MAC_PROP_ADV_10FDX_CAP: 3242 *perm = MAC_PROP_PERM_READ; 3243 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3244 break; 3245 case MAC_PROP_EN_10FDX_CAP: 3246 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3247 break; 3248 case MAC_PROP_ADV_10HDX_CAP: 3249 *perm = MAC_PROP_PERM_READ; 3250 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3251 break; 3252 case MAC_PROP_EN_10HDX_CAP: 3253 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3254 break; 3255 case MAC_PROP_ADV_100T4_CAP: 3256 case MAC_PROP_EN_100T4_CAP: 3257 *perm = MAC_PROP_PERM_READ; 3258 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3259 break; 3260 case MAC_PROP_PRIVATE: 3261 err = e1000g_get_priv_prop(Adapter, pr_name, 3262 pr_flags, pr_valsize, pr_val, perm); 3263 break; 3264 default: 3265 err = ENOTSUP; 3266 break; 3267 } 3268 return (err); 3269 } 3270 3271 /* ARGSUSED2 */ 3272 static int 3273 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3274 uint_t pr_valsize, const void *pr_val) 3275 { 3276 int err = 0; 3277 long result; 3278 struct e1000_hw *hw = &Adapter->shared; 3279 3280 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3281 if (pr_val == NULL) { 3282 err = EINVAL; 3283 return (err); 3284 } 3285 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3286 if (result < MIN_TX_BCOPY_THRESHOLD || 3287 result > MAX_TX_BCOPY_THRESHOLD) 3288 err = EINVAL; 3289 else { 3290 Adapter->tx_bcopy_thresh = (uint32_t)result; 3291 } 3292 return (err); 3293 } 3294 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3295 if (pr_val == NULL) { 3296 err = EINVAL; 3297 return (err); 3298 } 3299 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3300 if (result < 0 || result > 1) 3301 err = EINVAL; 3302 else { 3303 Adapter->tx_intr_enable = (result == 1) ? 3304 B_TRUE: B_FALSE; 3305 if (Adapter->tx_intr_enable) 3306 e1000g_mask_tx_interrupt(Adapter); 3307 else 3308 e1000g_clear_tx_interrupt(Adapter); 3309 if (e1000g_check_acc_handle( 3310 Adapter->osdep.reg_handle) != DDI_FM_OK) 3311 ddi_fm_service_impact(Adapter->dip, 3312 DDI_SERVICE_DEGRADED); 3313 } 3314 return (err); 3315 } 3316 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3317 if (pr_val == NULL) { 3318 err = EINVAL; 3319 return (err); 3320 } 3321 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3322 if (result < MIN_TX_INTR_DELAY || 3323 result > MAX_TX_INTR_DELAY) 3324 err = EINVAL; 3325 else { 3326 Adapter->tx_intr_delay = (uint32_t)result; 3327 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3328 if (e1000g_check_acc_handle( 3329 Adapter->osdep.reg_handle) != DDI_FM_OK) 3330 ddi_fm_service_impact(Adapter->dip, 3331 DDI_SERVICE_DEGRADED); 3332 } 3333 return (err); 3334 } 3335 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3336 if (pr_val == NULL) { 3337 err = EINVAL; 3338 return (err); 3339 } 3340 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3341 if (result < MIN_TX_INTR_ABS_DELAY || 3342 result > MAX_TX_INTR_ABS_DELAY) 3343 err = EINVAL; 3344 else { 3345 Adapter->tx_intr_abs_delay = (uint32_t)result; 3346 E1000_WRITE_REG(hw, E1000_TADV, 3347 Adapter->tx_intr_abs_delay); 3348 if (e1000g_check_acc_handle( 3349 Adapter->osdep.reg_handle) != DDI_FM_OK) 3350 ddi_fm_service_impact(Adapter->dip, 3351 DDI_SERVICE_DEGRADED); 3352 } 3353 return (err); 3354 } 3355 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3356 if (pr_val == NULL) { 3357 err = EINVAL; 3358 return (err); 3359 } 3360 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3361 if (result < MIN_RX_BCOPY_THRESHOLD || 3362 result > MAX_RX_BCOPY_THRESHOLD) 3363 err = EINVAL; 3364 else 3365 Adapter->rx_bcopy_thresh = (uint32_t)result; 3366 return (err); 3367 } 3368 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3369 if (pr_val == NULL) { 3370 err = EINVAL; 3371 return (err); 3372 } 3373 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3374 if (result < MIN_RX_LIMIT_ON_INTR || 3375 result > MAX_RX_LIMIT_ON_INTR) 3376 err = EINVAL; 3377 else 3378 Adapter->rx_limit_onintr = (uint32_t)result; 3379 return (err); 3380 } 3381 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3382 if (pr_val == NULL) { 3383 err = EINVAL; 3384 return (err); 3385 } 3386 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3387 if (result < MIN_RX_INTR_DELAY || 3388 result > MAX_RX_INTR_DELAY) 3389 err = EINVAL; 3390 else { 3391 Adapter->rx_intr_delay = (uint32_t)result; 3392 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3393 if (e1000g_check_acc_handle( 3394 Adapter->osdep.reg_handle) != DDI_FM_OK) 3395 ddi_fm_service_impact(Adapter->dip, 3396 DDI_SERVICE_DEGRADED); 3397 } 3398 return (err); 3399 } 3400 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3401 if (pr_val == NULL) { 3402 err = EINVAL; 3403 return (err); 3404 } 3405 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3406 if (result < MIN_RX_INTR_ABS_DELAY || 3407 result > MAX_RX_INTR_ABS_DELAY) 3408 err = EINVAL; 3409 else { 3410 Adapter->rx_intr_abs_delay = (uint32_t)result; 3411 E1000_WRITE_REG(hw, E1000_RADV, 3412 Adapter->rx_intr_abs_delay); 3413 if (e1000g_check_acc_handle( 3414 Adapter->osdep.reg_handle) != DDI_FM_OK) 3415 ddi_fm_service_impact(Adapter->dip, 3416 DDI_SERVICE_DEGRADED); 3417 } 3418 return (err); 3419 } 3420 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3421 if (pr_val == NULL) { 3422 err = EINVAL; 3423 return (err); 3424 } 3425 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3426 if (result < MIN_INTR_THROTTLING || 3427 result > MAX_INTR_THROTTLING) 3428 err = EINVAL; 3429 else { 3430 if (hw->mac.type >= e1000_82540) { 3431 Adapter->intr_throttling_rate = 3432 (uint32_t)result; 3433 E1000_WRITE_REG(hw, E1000_ITR, 3434 Adapter->intr_throttling_rate); 3435 if (e1000g_check_acc_handle( 3436 Adapter->osdep.reg_handle) != DDI_FM_OK) 3437 ddi_fm_service_impact(Adapter->dip, 3438 DDI_SERVICE_DEGRADED); 3439 } else 3440 err = EINVAL; 3441 } 3442 return (err); 3443 } 3444 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3445 if (pr_val == NULL) { 3446 err = EINVAL; 3447 return (err); 3448 } 3449 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3450 if (result < 0 || result > 1) 3451 err = EINVAL; 3452 else { 3453 if (hw->mac.type >= e1000_82540) { 3454 Adapter->intr_adaptive = (result == 1) ? 3455 B_TRUE : B_FALSE; 3456 } else { 3457 err = EINVAL; 3458 } 3459 } 3460 return (err); 3461 } 3462 return (ENOTSUP); 3463 } 3464 3465 static int 3466 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3467 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3468 { 3469 int err = ENOTSUP; 3470 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3471 int value; 3472 3473 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3474 *perm = MAC_PROP_PERM_READ; 3475 if (is_default) 3476 goto done; 3477 value = Adapter->param_adv_pause; 3478 err = 0; 3479 goto done; 3480 } 3481 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3482 *perm = MAC_PROP_PERM_READ; 3483 if (is_default) 3484 goto done; 3485 value = Adapter->param_adv_asym_pause; 3486 err = 0; 3487 goto done; 3488 } 3489 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3490 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3491 Adapter->tx_bcopy_thresh); 3492 err = 0; 3493 goto done; 3494 } 3495 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3496 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3497 Adapter->tx_intr_enable); 3498 err = 0; 3499 goto done; 3500 } 3501 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3502 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3503 Adapter->tx_intr_delay); 3504 err = 0; 3505 goto done; 3506 } 3507 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3508 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3509 Adapter->tx_intr_abs_delay); 3510 err = 0; 3511 goto done; 3512 } 3513 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3514 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3515 Adapter->rx_bcopy_thresh); 3516 err = 0; 3517 goto done; 3518 } 3519 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3520 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3521 Adapter->rx_limit_onintr); 3522 err = 0; 3523 goto done; 3524 } 3525 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3526 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3527 Adapter->rx_intr_delay); 3528 err = 0; 3529 goto done; 3530 } 3531 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3532 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3533 Adapter->rx_intr_abs_delay); 3534 err = 0; 3535 goto done; 3536 } 3537 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3538 value = (is_default ? DEFAULT_INTR_THROTTLING : 3539 Adapter->intr_throttling_rate); 3540 err = 0; 3541 goto done; 3542 } 3543 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3544 value = (is_default ? 1 : Adapter->intr_adaptive); 3545 err = 0; 3546 goto done; 3547 } 3548 done: 3549 if (err == 0) { 3550 (void) snprintf(pr_val, pr_valsize, "%d", value); 3551 } 3552 return (err); 3553 } 3554 3555 /* 3556 * e1000g_get_conf - get configurations set in e1000g.conf 3557 * This routine gets user-configured values out of the configuration 3558 * file e1000g.conf. 3559 * 3560 * For each configurable value, there is a minimum, a maximum, and a 3561 * default. 3562 * If user does not configure a value, use the default. 3563 * If user configures below the minimum, use the minumum. 3564 * If user configures above the maximum, use the maxumum. 3565 */ 3566 static void 3567 e1000g_get_conf(struct e1000g *Adapter) 3568 { 3569 struct e1000_hw *hw = &Adapter->shared; 3570 boolean_t tbi_compatibility = B_FALSE; 3571 3572 /* 3573 * get each configurable property from e1000g.conf 3574 */ 3575 3576 /* 3577 * NumTxDescriptors 3578 */ 3579 Adapter->tx_desc_num = 3580 e1000g_get_prop(Adapter, "NumTxDescriptors", 3581 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3582 DEFAULT_NUM_TX_DESCRIPTOR); 3583 3584 /* 3585 * NumRxDescriptors 3586 */ 3587 Adapter->rx_desc_num = 3588 e1000g_get_prop(Adapter, "NumRxDescriptors", 3589 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3590 DEFAULT_NUM_RX_DESCRIPTOR); 3591 3592 /* 3593 * NumRxFreeList 3594 */ 3595 Adapter->rx_freelist_num = 3596 e1000g_get_prop(Adapter, "NumRxFreeList", 3597 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3598 DEFAULT_NUM_RX_FREELIST); 3599 3600 /* 3601 * NumTxPacketList 3602 */ 3603 Adapter->tx_freelist_num = 3604 e1000g_get_prop(Adapter, "NumTxPacketList", 3605 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3606 DEFAULT_NUM_TX_FREELIST); 3607 3608 /* 3609 * FlowControl 3610 */ 3611 hw->fc.send_xon = B_TRUE; 3612 hw->fc.current_mode = 3613 e1000g_get_prop(Adapter, "FlowControl", 3614 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3615 /* 4 is the setting that says "let the eeprom decide" */ 3616 if (hw->fc.current_mode == 4) 3617 hw->fc.current_mode = e1000_fc_default; 3618 3619 /* 3620 * Max Num Receive Packets on Interrupt 3621 */ 3622 Adapter->rx_limit_onintr = 3623 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3624 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3625 DEFAULT_RX_LIMIT_ON_INTR); 3626 3627 /* 3628 * PHY master slave setting 3629 */ 3630 hw->phy.ms_type = 3631 e1000g_get_prop(Adapter, "SetMasterSlave", 3632 e1000_ms_hw_default, e1000_ms_auto, 3633 e1000_ms_hw_default); 3634 3635 /* 3636 * Parameter which controls TBI mode workaround, which is only 3637 * needed on certain switches such as Cisco 6500/Foundry 3638 */ 3639 tbi_compatibility = 3640 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3641 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3642 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3643 3644 /* 3645 * MSI Enable 3646 */ 3647 Adapter->msi_enable = 3648 e1000g_get_prop(Adapter, "MSIEnable", 3649 0, 1, DEFAULT_MSI_ENABLE); 3650 3651 /* 3652 * Interrupt Throttling Rate 3653 */ 3654 Adapter->intr_throttling_rate = 3655 e1000g_get_prop(Adapter, "intr_throttling_rate", 3656 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3657 DEFAULT_INTR_THROTTLING); 3658 3659 /* 3660 * Adaptive Interrupt Blanking Enable/Disable 3661 * It is enabled by default 3662 */ 3663 Adapter->intr_adaptive = 3664 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3665 B_TRUE : B_FALSE; 3666 3667 /* 3668 * Hardware checksum enable/disable parameter 3669 */ 3670 Adapter->tx_hcksum_enable = 3671 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3672 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3673 /* 3674 * Checksum on/off selection via global parameters. 3675 * 3676 * If the chip is flagged as not capable of (correctly) 3677 * handling checksumming, we don't enable it on either 3678 * Rx or Tx side. Otherwise, we take this chip's settings 3679 * from the patchable global defaults. 3680 * 3681 * We advertise our capabilities only if TX offload is 3682 * enabled. On receive, the stack will accept checksummed 3683 * packets anyway, even if we haven't said we can deliver 3684 * them. 3685 */ 3686 switch (hw->mac.type) { 3687 case e1000_82540: 3688 case e1000_82544: 3689 case e1000_82545: 3690 case e1000_82545_rev_3: 3691 case e1000_82546: 3692 case e1000_82546_rev_3: 3693 case e1000_82571: 3694 case e1000_82572: 3695 case e1000_82573: 3696 case e1000_80003es2lan: 3697 break; 3698 /* 3699 * For the following Intel PRO/1000 chipsets, we have not 3700 * tested the hardware checksum offload capability, so we 3701 * disable the capability for them. 3702 * e1000_82542, 3703 * e1000_82543, 3704 * e1000_82541, 3705 * e1000_82541_rev_2, 3706 * e1000_82547, 3707 * e1000_82547_rev_2, 3708 */ 3709 default: 3710 Adapter->tx_hcksum_enable = B_FALSE; 3711 } 3712 3713 /* 3714 * Large Send Offloading(LSO) Enable/Disable 3715 * If the tx hardware checksum is not enabled, LSO should be 3716 * disabled. 3717 */ 3718 Adapter->lso_enable = 3719 e1000g_get_prop(Adapter, "lso_enable", 3720 0, 1, DEFAULT_LSO_ENABLE); 3721 3722 switch (hw->mac.type) { 3723 case e1000_82546: 3724 case e1000_82546_rev_3: 3725 if (Adapter->lso_enable) 3726 Adapter->lso_premature_issue = B_TRUE; 3727 /* FALLTHRU */ 3728 case e1000_82571: 3729 case e1000_82572: 3730 case e1000_82573: 3731 case e1000_80003es2lan: 3732 break; 3733 default: 3734 Adapter->lso_enable = B_FALSE; 3735 } 3736 3737 if (!Adapter->tx_hcksum_enable) { 3738 Adapter->lso_premature_issue = B_FALSE; 3739 Adapter->lso_enable = B_FALSE; 3740 } 3741 3742 /* 3743 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3744 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3745 * will not cross 64k boundary. 3746 */ 3747 Adapter->mem_workaround_82546 = 3748 e1000g_get_prop(Adapter, "mem_workaround_82546", 3749 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3750 } 3751 3752 /* 3753 * e1000g_get_prop - routine to read properties 3754 * 3755 * Get a user-configure property value out of the configuration 3756 * file e1000g.conf. 3757 * 3758 * Caller provides name of the property, a default value, a minimum 3759 * value, and a maximum value. 3760 * 3761 * Return configured value of the property, with default, minimum and 3762 * maximum properly applied. 3763 */ 3764 static int 3765 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3766 char *propname, /* name of the property */ 3767 int minval, /* minimum acceptable value */ 3768 int maxval, /* maximim acceptable value */ 3769 int defval) /* default value */ 3770 { 3771 int propval; /* value returned for requested property */ 3772 int *props; /* point to array of properties returned */ 3773 uint_t nprops; /* number of property value returned */ 3774 3775 /* 3776 * get the array of properties from the config file 3777 */ 3778 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3779 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3780 /* got some properties, test if we got enough */ 3781 if (Adapter->instance < nprops) { 3782 propval = props[Adapter->instance]; 3783 } else { 3784 /* not enough properties configured */ 3785 propval = defval; 3786 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3787 "Not Enough %s values found in e1000g.conf" 3788 " - set to %d\n", 3789 propname, propval); 3790 } 3791 3792 /* free memory allocated for properties */ 3793 ddi_prop_free(props); 3794 3795 } else { 3796 propval = defval; 3797 } 3798 3799 /* 3800 * enforce limits 3801 */ 3802 if (propval > maxval) { 3803 propval = maxval; 3804 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3805 "Too High %s value in e1000g.conf - set to %d\n", 3806 propname, propval); 3807 } 3808 3809 if (propval < minval) { 3810 propval = minval; 3811 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3812 "Too Low %s value in e1000g.conf - set to %d\n", 3813 propname, propval); 3814 } 3815 3816 return (propval); 3817 } 3818 3819 static boolean_t 3820 e1000g_link_check(struct e1000g *Adapter) 3821 { 3822 uint16_t speed, duplex, phydata; 3823 boolean_t link_changed = B_FALSE; 3824 struct e1000_hw *hw; 3825 uint32_t reg_tarc; 3826 3827 hw = &Adapter->shared; 3828 3829 if (e1000g_link_up(Adapter)) { 3830 /* 3831 * The Link is up, check whether it was marked as down earlier 3832 */ 3833 if (Adapter->link_state != LINK_STATE_UP) { 3834 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3835 Adapter->link_speed = speed; 3836 Adapter->link_duplex = duplex; 3837 Adapter->link_state = LINK_STATE_UP; 3838 link_changed = B_TRUE; 3839 3840 Adapter->tx_link_down_timeout = 0; 3841 3842 if ((hw->mac.type == e1000_82571) || 3843 (hw->mac.type == e1000_82572)) { 3844 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3845 if (speed == SPEED_1000) 3846 reg_tarc |= (1 << 21); 3847 else 3848 reg_tarc &= ~(1 << 21); 3849 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3850 } 3851 } 3852 Adapter->smartspeed = 0; 3853 } else { 3854 if (Adapter->link_state != LINK_STATE_DOWN) { 3855 Adapter->link_speed = 0; 3856 Adapter->link_duplex = 0; 3857 Adapter->link_state = LINK_STATE_DOWN; 3858 link_changed = B_TRUE; 3859 3860 /* 3861 * SmartSpeed workaround for Tabor/TanaX, When the 3862 * driver loses link disable auto master/slave 3863 * resolution. 3864 */ 3865 if (hw->phy.type == e1000_phy_igp) { 3866 (void) e1000_read_phy_reg(hw, 3867 PHY_1000T_CTRL, &phydata); 3868 phydata |= CR_1000T_MS_ENABLE; 3869 (void) e1000_write_phy_reg(hw, 3870 PHY_1000T_CTRL, phydata); 3871 } 3872 } else { 3873 e1000g_smartspeed(Adapter); 3874 } 3875 3876 if (Adapter->e1000g_state & E1000G_STARTED) { 3877 if (Adapter->tx_link_down_timeout < 3878 MAX_TX_LINK_DOWN_TIMEOUT) { 3879 Adapter->tx_link_down_timeout++; 3880 } else if (Adapter->tx_link_down_timeout == 3881 MAX_TX_LINK_DOWN_TIMEOUT) { 3882 e1000g_tx_clean(Adapter); 3883 Adapter->tx_link_down_timeout++; 3884 } 3885 } 3886 } 3887 3888 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3889 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3890 3891 return (link_changed); 3892 } 3893 3894 /* 3895 * e1000g_reset_link - Using the link properties to setup the link 3896 */ 3897 int 3898 e1000g_reset_link(struct e1000g *Adapter) 3899 { 3900 struct e1000_mac_info *mac; 3901 struct e1000_phy_info *phy; 3902 boolean_t invalid; 3903 3904 mac = &Adapter->shared.mac; 3905 phy = &Adapter->shared.phy; 3906 invalid = B_FALSE; 3907 3908 if (Adapter->param_adv_autoneg == 1) { 3909 mac->autoneg = B_TRUE; 3910 phy->autoneg_advertised = 0; 3911 3912 /* 3913 * 1000hdx is not supported for autonegotiation 3914 */ 3915 if (Adapter->param_adv_1000fdx == 1) 3916 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3917 3918 if (Adapter->param_adv_100fdx == 1) 3919 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3920 3921 if (Adapter->param_adv_100hdx == 1) 3922 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3923 3924 if (Adapter->param_adv_10fdx == 1) 3925 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3926 3927 if (Adapter->param_adv_10hdx == 1) 3928 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3929 3930 if (phy->autoneg_advertised == 0) 3931 invalid = B_TRUE; 3932 } else { 3933 mac->autoneg = B_FALSE; 3934 3935 /* 3936 * 1000fdx and 1000hdx are not supported for forced link 3937 */ 3938 if (Adapter->param_adv_100fdx == 1) 3939 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3940 else if (Adapter->param_adv_100hdx == 1) 3941 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3942 else if (Adapter->param_adv_10fdx == 1) 3943 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3944 else if (Adapter->param_adv_10hdx == 1) 3945 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3946 else 3947 invalid = B_TRUE; 3948 3949 } 3950 3951 if (invalid) { 3952 e1000g_log(Adapter, CE_WARN, 3953 "Invalid link sets. Setup link to" 3954 "support autonegotiation with all link capabilities."); 3955 mac->autoneg = B_TRUE; 3956 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3957 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3958 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3959 } 3960 3961 return (e1000_setup_link(&Adapter->shared)); 3962 } 3963 3964 static void 3965 e1000g_timer_tx_resched(struct e1000g *Adapter) 3966 { 3967 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 3968 3969 rw_enter(&Adapter->chip_lock, RW_READER); 3970 3971 if (tx_ring->resched_needed && 3972 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 3973 drv_usectohz(1000000)) && 3974 (Adapter->e1000g_state & E1000G_STARTED) && 3975 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 3976 tx_ring->resched_needed = B_FALSE; 3977 mac_tx_update(Adapter->mh); 3978 E1000G_STAT(tx_ring->stat_reschedule); 3979 E1000G_STAT(tx_ring->stat_timer_reschedule); 3980 } 3981 3982 rw_exit(&Adapter->chip_lock); 3983 } 3984 3985 static void 3986 e1000g_local_timer(void *ws) 3987 { 3988 struct e1000g *Adapter = (struct e1000g *)ws; 3989 struct e1000_hw *hw; 3990 e1000g_ether_addr_t ether_addr; 3991 boolean_t link_changed; 3992 3993 hw = &Adapter->shared; 3994 3995 if (Adapter->e1000g_state & E1000G_ERROR) { 3996 rw_enter(&Adapter->chip_lock, RW_WRITER); 3997 Adapter->e1000g_state &= ~E1000G_ERROR; 3998 rw_exit(&Adapter->chip_lock); 3999 4000 Adapter->reset_count++; 4001 if (e1000g_global_reset(Adapter)) { 4002 ddi_fm_service_impact(Adapter->dip, 4003 DDI_SERVICE_RESTORED); 4004 e1000g_timer_tx_resched(Adapter); 4005 } else 4006 ddi_fm_service_impact(Adapter->dip, 4007 DDI_SERVICE_LOST); 4008 return; 4009 } 4010 4011 if (e1000g_stall_check(Adapter)) { 4012 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4013 "Tx stall detected. Activate automatic recovery.\n"); 4014 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4015 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4016 Adapter->reset_count++; 4017 if (e1000g_reset_adapter(Adapter)) { 4018 ddi_fm_service_impact(Adapter->dip, 4019 DDI_SERVICE_RESTORED); 4020 e1000g_timer_tx_resched(Adapter); 4021 } 4022 return; 4023 } 4024 4025 link_changed = B_FALSE; 4026 rw_enter(&Adapter->chip_lock, RW_READER); 4027 if (Adapter->link_complete) 4028 link_changed = e1000g_link_check(Adapter); 4029 rw_exit(&Adapter->chip_lock); 4030 4031 if (link_changed) 4032 mac_link_update(Adapter->mh, Adapter->link_state); 4033 4034 /* 4035 * Workaround for esb2. Data stuck in fifo on a link 4036 * down event. Reset the adapter to recover it. 4037 */ 4038 if (Adapter->esb2_workaround) { 4039 Adapter->esb2_workaround = B_FALSE; 4040 (void) e1000g_reset_adapter(Adapter); 4041 return; 4042 } 4043 4044 /* 4045 * With 82571 controllers, any locally administered address will 4046 * be overwritten when there is a reset on the other port. 4047 * Detect this circumstance and correct it. 4048 */ 4049 if ((hw->mac.type == e1000_82571) && 4050 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4051 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4052 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4053 4054 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4055 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4056 4057 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4058 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4059 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4060 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4061 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4062 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4063 e1000_rar_set(hw, hw->mac.addr, 0); 4064 } 4065 } 4066 4067 /* 4068 * Long TTL workaround for 82541/82547 4069 */ 4070 (void) e1000_igp_ttl_workaround_82547(hw); 4071 4072 /* 4073 * Check for Adaptive IFS settings If there are lots of collisions 4074 * change the value in steps... 4075 * These properties should only be set for 10/100 4076 */ 4077 if ((hw->phy.media_type == e1000_media_type_copper) && 4078 ((Adapter->link_speed == SPEED_100) || 4079 (Adapter->link_speed == SPEED_10))) { 4080 e1000_update_adaptive(hw); 4081 } 4082 /* 4083 * Set Timer Interrupts 4084 */ 4085 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4086 4087 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4088 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4089 else 4090 e1000g_timer_tx_resched(Adapter); 4091 4092 restart_watchdog_timer(Adapter); 4093 } 4094 4095 /* 4096 * The function e1000g_link_timer() is called when the timer for link setup 4097 * is expired, which indicates the completion of the link setup. The link 4098 * state will not be updated until the link setup is completed. And the 4099 * link state will not be sent to the upper layer through mac_link_update() 4100 * in this function. It will be updated in the local timer routine or the 4101 * interrupt service routine after the interface is started (plumbed). 4102 */ 4103 static void 4104 e1000g_link_timer(void *arg) 4105 { 4106 struct e1000g *Adapter = (struct e1000g *)arg; 4107 4108 mutex_enter(&Adapter->link_lock); 4109 Adapter->link_complete = B_TRUE; 4110 Adapter->link_tid = 0; 4111 mutex_exit(&Adapter->link_lock); 4112 } 4113 4114 /* 4115 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4116 * 4117 * This function read the forced speed and duplex for 10/100 Mbps speeds 4118 * and also for 1000 Mbps speeds from the e1000g.conf file 4119 */ 4120 static void 4121 e1000g_force_speed_duplex(struct e1000g *Adapter) 4122 { 4123 int forced; 4124 struct e1000_mac_info *mac = &Adapter->shared.mac; 4125 struct e1000_phy_info *phy = &Adapter->shared.phy; 4126 4127 /* 4128 * get value out of config file 4129 */ 4130 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4131 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4132 4133 switch (forced) { 4134 case GDIAG_10_HALF: 4135 /* 4136 * Disable Auto Negotiation 4137 */ 4138 mac->autoneg = B_FALSE; 4139 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4140 break; 4141 case GDIAG_10_FULL: 4142 /* 4143 * Disable Auto Negotiation 4144 */ 4145 mac->autoneg = B_FALSE; 4146 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4147 break; 4148 case GDIAG_100_HALF: 4149 /* 4150 * Disable Auto Negotiation 4151 */ 4152 mac->autoneg = B_FALSE; 4153 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4154 break; 4155 case GDIAG_100_FULL: 4156 /* 4157 * Disable Auto Negotiation 4158 */ 4159 mac->autoneg = B_FALSE; 4160 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4161 break; 4162 case GDIAG_1000_FULL: 4163 /* 4164 * The gigabit spec requires autonegotiation. Therefore, 4165 * when the user wants to force the speed to 1000Mbps, we 4166 * enable AutoNeg, but only allow the harware to advertise 4167 * 1000Mbps. This is different from 10/100 operation, where 4168 * we are allowed to link without any negotiation. 4169 */ 4170 mac->autoneg = B_TRUE; 4171 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4172 break; 4173 default: /* obey the setting of AutoNegAdvertised */ 4174 mac->autoneg = B_TRUE; 4175 phy->autoneg_advertised = 4176 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4177 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4178 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4179 break; 4180 } /* switch */ 4181 } 4182 4183 /* 4184 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4185 * 4186 * This function reads MaxFrameSize from e1000g.conf 4187 */ 4188 static void 4189 e1000g_get_max_frame_size(struct e1000g *Adapter) 4190 { 4191 int max_frame; 4192 struct e1000_mac_info *mac = &Adapter->shared.mac; 4193 struct e1000_phy_info *phy = &Adapter->shared.phy; 4194 4195 /* 4196 * get value out of config file 4197 */ 4198 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4199 4200 switch (max_frame) { 4201 case 0: 4202 Adapter->default_mtu = ETHERMTU; 4203 break; 4204 /* 4205 * To avoid excessive memory allocation for rx buffers, 4206 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4207 */ 4208 case 1: 4209 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4210 sizeof (struct ether_vlan_header) - ETHERFCSL - 4211 E1000G_IPALIGNPRESERVEROOM; 4212 break; 4213 case 2: 4214 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4215 sizeof (struct ether_vlan_header) - ETHERFCSL - 4216 E1000G_IPALIGNPRESERVEROOM; 4217 break; 4218 case 3: 4219 if (mac->type >= e1000_82571) 4220 Adapter->default_mtu = MAXIMUM_MTU; 4221 else 4222 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4223 sizeof (struct ether_vlan_header) - ETHERFCSL - 4224 E1000G_IPALIGNPRESERVEROOM; 4225 break; 4226 default: 4227 Adapter->default_mtu = ETHERMTU; 4228 break; 4229 } /* switch */ 4230 4231 Adapter->max_frame_size = Adapter->default_mtu + 4232 sizeof (struct ether_vlan_header) + ETHERFCSL; 4233 4234 /* ich8 does not do jumbo frames */ 4235 if (mac->type == e1000_ich8lan) { 4236 Adapter->default_mtu = ETHERMTU; 4237 Adapter->max_frame_size = ETHERMTU + 4238 sizeof (struct ether_vlan_header) + ETHERFCSL; 4239 } 4240 4241 /* ich9 does not do jumbo frames on one phy type */ 4242 if ((mac->type == e1000_ich9lan) && 4243 (phy->type == e1000_phy_ife)) { 4244 Adapter->default_mtu = ETHERMTU; 4245 Adapter->max_frame_size = ETHERMTU + 4246 sizeof (struct ether_vlan_header) + ETHERFCSL; 4247 } 4248 } 4249 4250 static void 4251 arm_watchdog_timer(struct e1000g *Adapter) 4252 { 4253 Adapter->watchdog_tid = 4254 timeout(e1000g_local_timer, 4255 (void *)Adapter, 1 * drv_usectohz(1000000)); 4256 } 4257 #pragma inline(arm_watchdog_timer) 4258 4259 static void 4260 enable_watchdog_timer(struct e1000g *Adapter) 4261 { 4262 mutex_enter(&Adapter->watchdog_lock); 4263 4264 if (!Adapter->watchdog_timer_enabled) { 4265 Adapter->watchdog_timer_enabled = B_TRUE; 4266 Adapter->watchdog_timer_started = B_TRUE; 4267 arm_watchdog_timer(Adapter); 4268 } 4269 4270 mutex_exit(&Adapter->watchdog_lock); 4271 } 4272 4273 static void 4274 disable_watchdog_timer(struct e1000g *Adapter) 4275 { 4276 timeout_id_t tid; 4277 4278 mutex_enter(&Adapter->watchdog_lock); 4279 4280 Adapter->watchdog_timer_enabled = B_FALSE; 4281 Adapter->watchdog_timer_started = B_FALSE; 4282 tid = Adapter->watchdog_tid; 4283 Adapter->watchdog_tid = 0; 4284 4285 mutex_exit(&Adapter->watchdog_lock); 4286 4287 if (tid != 0) 4288 (void) untimeout(tid); 4289 } 4290 4291 static void 4292 start_watchdog_timer(struct e1000g *Adapter) 4293 { 4294 mutex_enter(&Adapter->watchdog_lock); 4295 4296 if (Adapter->watchdog_timer_enabled) { 4297 if (!Adapter->watchdog_timer_started) { 4298 Adapter->watchdog_timer_started = B_TRUE; 4299 arm_watchdog_timer(Adapter); 4300 } 4301 } 4302 4303 mutex_exit(&Adapter->watchdog_lock); 4304 } 4305 4306 static void 4307 restart_watchdog_timer(struct e1000g *Adapter) 4308 { 4309 mutex_enter(&Adapter->watchdog_lock); 4310 4311 if (Adapter->watchdog_timer_started) 4312 arm_watchdog_timer(Adapter); 4313 4314 mutex_exit(&Adapter->watchdog_lock); 4315 } 4316 4317 static void 4318 stop_watchdog_timer(struct e1000g *Adapter) 4319 { 4320 timeout_id_t tid; 4321 4322 mutex_enter(&Adapter->watchdog_lock); 4323 4324 Adapter->watchdog_timer_started = B_FALSE; 4325 tid = Adapter->watchdog_tid; 4326 Adapter->watchdog_tid = 0; 4327 4328 mutex_exit(&Adapter->watchdog_lock); 4329 4330 if (tid != 0) 4331 (void) untimeout(tid); 4332 } 4333 4334 static void 4335 stop_link_timer(struct e1000g *Adapter) 4336 { 4337 timeout_id_t tid; 4338 4339 /* Disable the link timer */ 4340 mutex_enter(&Adapter->link_lock); 4341 4342 tid = Adapter->link_tid; 4343 Adapter->link_tid = 0; 4344 4345 mutex_exit(&Adapter->link_lock); 4346 4347 if (tid != 0) 4348 (void) untimeout(tid); 4349 } 4350 4351 static void 4352 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4353 { 4354 timeout_id_t tid; 4355 4356 /* Disable the tx timer for 82547 chipset */ 4357 mutex_enter(&tx_ring->tx_lock); 4358 4359 tx_ring->timer_enable_82547 = B_FALSE; 4360 tid = tx_ring->timer_id_82547; 4361 tx_ring->timer_id_82547 = 0; 4362 4363 mutex_exit(&tx_ring->tx_lock); 4364 4365 if (tid != 0) 4366 (void) untimeout(tid); 4367 } 4368 4369 void 4370 e1000g_clear_interrupt(struct e1000g *Adapter) 4371 { 4372 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4373 0xffffffff & ~E1000_IMS_RXSEQ); 4374 } 4375 4376 void 4377 e1000g_mask_interrupt(struct e1000g *Adapter) 4378 { 4379 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4380 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4381 4382 if (Adapter->tx_intr_enable) 4383 e1000g_mask_tx_interrupt(Adapter); 4384 } 4385 4386 /* 4387 * This routine is called by e1000g_quiesce(), therefore must not block. 4388 */ 4389 void 4390 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4391 { 4392 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4393 } 4394 4395 void 4396 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4397 { 4398 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4399 } 4400 4401 void 4402 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4403 { 4404 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4405 } 4406 4407 static void 4408 e1000g_smartspeed(struct e1000g *Adapter) 4409 { 4410 struct e1000_hw *hw = &Adapter->shared; 4411 uint16_t phy_status; 4412 uint16_t phy_ctrl; 4413 4414 /* 4415 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4416 * advertising 1000Full, we don't even use the workaround 4417 */ 4418 if ((hw->phy.type != e1000_phy_igp) || 4419 !hw->mac.autoneg || 4420 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4421 return; 4422 4423 /* 4424 * True if this is the first call of this function or after every 4425 * 30 seconds of not having link 4426 */ 4427 if (Adapter->smartspeed == 0) { 4428 /* 4429 * If Master/Slave config fault is asserted twice, we 4430 * assume back-to-back 4431 */ 4432 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4433 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4434 return; 4435 4436 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4437 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4438 return; 4439 /* 4440 * We're assuming back-2-back because our status register 4441 * insists! there's a fault in the master/slave 4442 * relationship that was "negotiated" 4443 */ 4444 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4445 /* 4446 * Is the phy configured for manual configuration of 4447 * master/slave? 4448 */ 4449 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4450 /* 4451 * Yes. Then disable manual configuration (enable 4452 * auto configuration) of master/slave 4453 */ 4454 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4455 (void) e1000_write_phy_reg(hw, 4456 PHY_1000T_CTRL, phy_ctrl); 4457 /* 4458 * Effectively starting the clock 4459 */ 4460 Adapter->smartspeed++; 4461 /* 4462 * Restart autonegotiation 4463 */ 4464 if (!e1000_phy_setup_autoneg(hw) && 4465 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4466 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4467 MII_CR_RESTART_AUTO_NEG); 4468 (void) e1000_write_phy_reg(hw, 4469 PHY_CONTROL, phy_ctrl); 4470 } 4471 } 4472 return; 4473 /* 4474 * Has 6 seconds transpired still without link? Remember, 4475 * you should reset the smartspeed counter once you obtain 4476 * link 4477 */ 4478 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4479 /* 4480 * Yes. Remember, we did at the start determine that 4481 * there's a master/slave configuration fault, so we're 4482 * still assuming there's someone on the other end, but we 4483 * just haven't yet been able to talk to it. We then 4484 * re-enable auto configuration of master/slave to see if 4485 * we're running 2/3 pair cables. 4486 */ 4487 /* 4488 * If still no link, perhaps using 2/3 pair cable 4489 */ 4490 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4491 phy_ctrl |= CR_1000T_MS_ENABLE; 4492 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4493 /* 4494 * Restart autoneg with phy enabled for manual 4495 * configuration of master/slave 4496 */ 4497 if (!e1000_phy_setup_autoneg(hw) && 4498 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4499 phy_ctrl |= 4500 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4501 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4502 } 4503 /* 4504 * Hopefully, there are no more faults and we've obtained 4505 * link as a result. 4506 */ 4507 } 4508 /* 4509 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4510 * seconds) 4511 */ 4512 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4513 Adapter->smartspeed = 0; 4514 } 4515 4516 static boolean_t 4517 is_valid_mac_addr(uint8_t *mac_addr) 4518 { 4519 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4520 const uint8_t addr_test2[6] = 4521 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4522 4523 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4524 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4525 return (B_FALSE); 4526 4527 return (B_TRUE); 4528 } 4529 4530 /* 4531 * e1000g_stall_check - check for tx stall 4532 * 4533 * This function checks if the adapter is stalled (in transmit). 4534 * 4535 * It is called each time the watchdog timeout is invoked. 4536 * If the transmit descriptor reclaim continuously fails, 4537 * the watchdog value will increment by 1. If the watchdog 4538 * value exceeds the threshold, the adapter is assumed to 4539 * have stalled and need to be reset. 4540 */ 4541 static boolean_t 4542 e1000g_stall_check(struct e1000g *Adapter) 4543 { 4544 e1000g_tx_ring_t *tx_ring; 4545 4546 tx_ring = Adapter->tx_ring; 4547 4548 if (Adapter->link_state != LINK_STATE_UP) 4549 return (B_FALSE); 4550 4551 if (tx_ring->recycle_fail > 0) 4552 tx_ring->stall_watchdog++; 4553 else 4554 tx_ring->stall_watchdog = 0; 4555 4556 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4557 return (B_FALSE); 4558 4559 tx_ring->stall_watchdog = 0; 4560 tx_ring->recycle_fail = 0; 4561 4562 return (B_TRUE); 4563 } 4564 4565 #ifdef E1000G_DEBUG 4566 static enum ioc_reply 4567 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4568 { 4569 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4570 e1000g_peekpoke_t *ppd; 4571 uint64_t mem_va; 4572 uint64_t maxoff; 4573 boolean_t peek; 4574 4575 switch (iocp->ioc_cmd) { 4576 4577 case E1000G_IOC_REG_PEEK: 4578 peek = B_TRUE; 4579 break; 4580 4581 case E1000G_IOC_REG_POKE: 4582 peek = B_FALSE; 4583 break; 4584 4585 deault: 4586 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4587 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4588 iocp->ioc_cmd); 4589 return (IOC_INVAL); 4590 } 4591 4592 /* 4593 * Validate format of ioctl 4594 */ 4595 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4596 return (IOC_INVAL); 4597 if (mp->b_cont == NULL) 4598 return (IOC_INVAL); 4599 4600 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4601 4602 /* 4603 * Validate request parameters 4604 */ 4605 switch (ppd->pp_acc_space) { 4606 4607 default: 4608 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4609 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4610 ppd->pp_acc_space); 4611 return (IOC_INVAL); 4612 4613 case E1000G_PP_SPACE_REG: 4614 /* 4615 * Memory-mapped I/O space 4616 */ 4617 ASSERT(ppd->pp_acc_size == 4); 4618 if (ppd->pp_acc_size != 4) 4619 return (IOC_INVAL); 4620 4621 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4622 return (IOC_INVAL); 4623 4624 mem_va = 0; 4625 maxoff = 0x10000; 4626 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4627 break; 4628 4629 case E1000G_PP_SPACE_E1000G: 4630 /* 4631 * E1000g data structure! 4632 */ 4633 mem_va = (uintptr_t)e1000gp; 4634 maxoff = sizeof (struct e1000g); 4635 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4636 break; 4637 4638 } 4639 4640 if (ppd->pp_acc_offset >= maxoff) 4641 return (IOC_INVAL); 4642 4643 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4644 return (IOC_INVAL); 4645 4646 /* 4647 * All OK - go! 4648 */ 4649 ppd->pp_acc_offset += mem_va; 4650 (*ppfn)(e1000gp, ppd); 4651 return (peek ? IOC_REPLY : IOC_ACK); 4652 } 4653 4654 static void 4655 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4656 { 4657 ddi_acc_handle_t handle; 4658 uint32_t *regaddr; 4659 4660 handle = e1000gp->osdep.reg_handle; 4661 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4662 (uintptr_t)ppd->pp_acc_offset); 4663 4664 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4665 } 4666 4667 static void 4668 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4669 { 4670 ddi_acc_handle_t handle; 4671 uint32_t *regaddr; 4672 uint32_t value; 4673 4674 handle = e1000gp->osdep.reg_handle; 4675 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4676 (uintptr_t)ppd->pp_acc_offset); 4677 value = (uint32_t)ppd->pp_acc_data; 4678 4679 ddi_put32(handle, regaddr, value); 4680 } 4681 4682 static void 4683 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4684 { 4685 uint64_t value; 4686 void *vaddr; 4687 4688 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4689 4690 switch (ppd->pp_acc_size) { 4691 case 1: 4692 value = *(uint8_t *)vaddr; 4693 break; 4694 4695 case 2: 4696 value = *(uint16_t *)vaddr; 4697 break; 4698 4699 case 4: 4700 value = *(uint32_t *)vaddr; 4701 break; 4702 4703 case 8: 4704 value = *(uint64_t *)vaddr; 4705 break; 4706 } 4707 4708 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4709 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4710 (void *)e1000gp, (void *)ppd, value, vaddr); 4711 4712 ppd->pp_acc_data = value; 4713 } 4714 4715 static void 4716 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4717 { 4718 uint64_t value; 4719 void *vaddr; 4720 4721 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4722 value = ppd->pp_acc_data; 4723 4724 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4725 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4726 (void *)e1000gp, (void *)ppd, value, vaddr); 4727 4728 switch (ppd->pp_acc_size) { 4729 case 1: 4730 *(uint8_t *)vaddr = (uint8_t)value; 4731 break; 4732 4733 case 2: 4734 *(uint16_t *)vaddr = (uint16_t)value; 4735 break; 4736 4737 case 4: 4738 *(uint32_t *)vaddr = (uint32_t)value; 4739 break; 4740 4741 case 8: 4742 *(uint64_t *)vaddr = (uint64_t)value; 4743 break; 4744 } 4745 } 4746 #endif 4747 4748 /* 4749 * Loopback Support 4750 */ 4751 static lb_property_t lb_normal = 4752 { normal, "normal", E1000G_LB_NONE }; 4753 static lb_property_t lb_external1000 = 4754 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4755 static lb_property_t lb_external100 = 4756 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4757 static lb_property_t lb_external10 = 4758 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4759 static lb_property_t lb_phy = 4760 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4761 4762 static enum ioc_reply 4763 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4764 { 4765 lb_info_sz_t *lbsp; 4766 lb_property_t *lbpp; 4767 struct e1000_hw *hw; 4768 uint32_t *lbmp; 4769 uint32_t size; 4770 uint32_t value; 4771 4772 hw = &Adapter->shared; 4773 4774 if (mp->b_cont == NULL) 4775 return (IOC_INVAL); 4776 4777 if (!e1000g_check_loopback_support(hw)) { 4778 e1000g_log(NULL, CE_WARN, 4779 "Loopback is not supported on e1000g%d", Adapter->instance); 4780 return (IOC_INVAL); 4781 } 4782 4783 switch (iocp->ioc_cmd) { 4784 default: 4785 return (IOC_INVAL); 4786 4787 case LB_GET_INFO_SIZE: 4788 size = sizeof (lb_info_sz_t); 4789 if (iocp->ioc_count != size) 4790 return (IOC_INVAL); 4791 4792 rw_enter(&Adapter->chip_lock, RW_WRITER); 4793 e1000g_get_phy_state(Adapter); 4794 4795 /* 4796 * Workaround for hardware faults. In order to get a stable 4797 * state of phy, we will wait for a specific interval and 4798 * try again. The time delay is an experiential value based 4799 * on our testing. 4800 */ 4801 msec_delay(100); 4802 e1000g_get_phy_state(Adapter); 4803 rw_exit(&Adapter->chip_lock); 4804 4805 value = sizeof (lb_normal); 4806 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4807 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4808 (hw->phy.media_type == e1000_media_type_fiber) || 4809 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4810 value += sizeof (lb_phy); 4811 switch (hw->mac.type) { 4812 case e1000_82571: 4813 case e1000_82572: 4814 case e1000_80003es2lan: 4815 value += sizeof (lb_external1000); 4816 break; 4817 } 4818 } 4819 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4820 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4821 value += sizeof (lb_external100); 4822 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4823 value += sizeof (lb_external10); 4824 4825 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4826 *lbsp = value; 4827 break; 4828 4829 case LB_GET_INFO: 4830 value = sizeof (lb_normal); 4831 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4832 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4833 (hw->phy.media_type == e1000_media_type_fiber) || 4834 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4835 value += sizeof (lb_phy); 4836 switch (hw->mac.type) { 4837 case e1000_82571: 4838 case e1000_82572: 4839 case e1000_80003es2lan: 4840 value += sizeof (lb_external1000); 4841 break; 4842 } 4843 } 4844 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4845 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4846 value += sizeof (lb_external100); 4847 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4848 value += sizeof (lb_external10); 4849 4850 size = value; 4851 if (iocp->ioc_count != size) 4852 return (IOC_INVAL); 4853 4854 value = 0; 4855 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4856 lbpp[value++] = lb_normal; 4857 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4858 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4859 (hw->phy.media_type == e1000_media_type_fiber) || 4860 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4861 lbpp[value++] = lb_phy; 4862 switch (hw->mac.type) { 4863 case e1000_82571: 4864 case e1000_82572: 4865 case e1000_80003es2lan: 4866 lbpp[value++] = lb_external1000; 4867 break; 4868 } 4869 } 4870 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4871 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4872 lbpp[value++] = lb_external100; 4873 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4874 lbpp[value++] = lb_external10; 4875 break; 4876 4877 case LB_GET_MODE: 4878 size = sizeof (uint32_t); 4879 if (iocp->ioc_count != size) 4880 return (IOC_INVAL); 4881 4882 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4883 *lbmp = Adapter->loopback_mode; 4884 break; 4885 4886 case LB_SET_MODE: 4887 size = 0; 4888 if (iocp->ioc_count != sizeof (uint32_t)) 4889 return (IOC_INVAL); 4890 4891 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4892 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4893 return (IOC_INVAL); 4894 break; 4895 } 4896 4897 iocp->ioc_count = size; 4898 iocp->ioc_error = 0; 4899 4900 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4901 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4902 return (IOC_INVAL); 4903 } 4904 4905 return (IOC_REPLY); 4906 } 4907 4908 static boolean_t 4909 e1000g_check_loopback_support(struct e1000_hw *hw) 4910 { 4911 switch (hw->mac.type) { 4912 case e1000_82540: 4913 case e1000_82545: 4914 case e1000_82545_rev_3: 4915 case e1000_82546: 4916 case e1000_82546_rev_3: 4917 case e1000_82541: 4918 case e1000_82541_rev_2: 4919 case e1000_82547: 4920 case e1000_82547_rev_2: 4921 case e1000_82571: 4922 case e1000_82572: 4923 case e1000_82573: 4924 case e1000_82574: 4925 case e1000_80003es2lan: 4926 case e1000_ich9lan: 4927 case e1000_ich10lan: 4928 return (B_TRUE); 4929 } 4930 return (B_FALSE); 4931 } 4932 4933 static boolean_t 4934 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4935 { 4936 struct e1000_hw *hw; 4937 int i, times; 4938 boolean_t link_up; 4939 4940 if (mode == Adapter->loopback_mode) 4941 return (B_TRUE); 4942 4943 hw = &Adapter->shared; 4944 times = 0; 4945 4946 Adapter->loopback_mode = mode; 4947 4948 if (mode == E1000G_LB_NONE) { 4949 /* Reset the chip */ 4950 hw->phy.autoneg_wait_to_complete = B_TRUE; 4951 (void) e1000g_reset_adapter(Adapter); 4952 hw->phy.autoneg_wait_to_complete = B_FALSE; 4953 return (B_TRUE); 4954 } 4955 4956 again: 4957 4958 rw_enter(&Adapter->chip_lock, RW_WRITER); 4959 4960 switch (mode) { 4961 default: 4962 rw_exit(&Adapter->chip_lock); 4963 return (B_FALSE); 4964 4965 case E1000G_LB_EXTERNAL_1000: 4966 e1000g_set_external_loopback_1000(Adapter); 4967 break; 4968 4969 case E1000G_LB_EXTERNAL_100: 4970 e1000g_set_external_loopback_100(Adapter); 4971 break; 4972 4973 case E1000G_LB_EXTERNAL_10: 4974 e1000g_set_external_loopback_10(Adapter); 4975 break; 4976 4977 case E1000G_LB_INTERNAL_PHY: 4978 e1000g_set_internal_loopback(Adapter); 4979 break; 4980 } 4981 4982 times++; 4983 4984 rw_exit(&Adapter->chip_lock); 4985 4986 /* Wait for link up */ 4987 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4988 msec_delay(100); 4989 4990 rw_enter(&Adapter->chip_lock, RW_WRITER); 4991 4992 link_up = e1000g_link_up(Adapter); 4993 4994 rw_exit(&Adapter->chip_lock); 4995 4996 if (!link_up) { 4997 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4998 "Failed to get the link up"); 4999 if (times < 2) { 5000 /* Reset the link */ 5001 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5002 "Reset the link ..."); 5003 (void) e1000g_reset_adapter(Adapter); 5004 goto again; 5005 } 5006 } 5007 5008 return (B_TRUE); 5009 } 5010 5011 /* 5012 * The following loopback settings are from Intel's technical 5013 * document - "How To Loopback". All the register settings and 5014 * time delay values are directly inherited from the document 5015 * without more explanations available. 5016 */ 5017 static void 5018 e1000g_set_internal_loopback(struct e1000g *Adapter) 5019 { 5020 struct e1000_hw *hw; 5021 uint32_t ctrl; 5022 uint32_t status; 5023 uint16_t phy_ctrl; 5024 uint16_t phy_reg; 5025 uint32_t txcw; 5026 5027 hw = &Adapter->shared; 5028 5029 /* Disable Smart Power Down */ 5030 phy_spd_state(hw, B_FALSE); 5031 5032 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5033 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5034 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5035 5036 switch (hw->mac.type) { 5037 case e1000_82540: 5038 case e1000_82545: 5039 case e1000_82545_rev_3: 5040 case e1000_82546: 5041 case e1000_82546_rev_3: 5042 case e1000_82573: 5043 /* Auto-MDI/MDIX off */ 5044 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5045 /* Reset PHY to update Auto-MDI/MDIX */ 5046 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5047 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5048 /* Reset PHY to auto-neg off and force 1000 */ 5049 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5050 phy_ctrl | MII_CR_RESET); 5051 /* 5052 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5053 * See comments above e1000g_set_internal_loopback() for the 5054 * background. 5055 */ 5056 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5057 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5058 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5059 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5060 break; 5061 case e1000_80003es2lan: 5062 /* Force Link Up */ 5063 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5064 0x1CC); 5065 /* Sets PCS loopback at 1Gbs */ 5066 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5067 0x1046); 5068 break; 5069 } 5070 5071 /* 5072 * The following registers should be set for e1000_phy_bm phy type. 5073 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5074 * For others, we do not need to set these registers. 5075 */ 5076 if (hw->phy.type == e1000_phy_bm) { 5077 /* Set Default MAC Interface speed to 1GB */ 5078 e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5079 phy_reg &= ~0x0007; 5080 phy_reg |= 0x006; 5081 e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5082 /* Assert SW reset for above settings to take effect */ 5083 e1000_phy_commit(hw); 5084 msec_delay(1); 5085 /* Force Full Duplex */ 5086 e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5087 e1000_write_phy_reg(hw, PHY_REG(769, 16), phy_reg | 0x000C); 5088 /* Set Link Up (in force link) */ 5089 e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5090 e1000_write_phy_reg(hw, PHY_REG(776, 16), phy_reg | 0x0040); 5091 /* Force Link */ 5092 e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5093 e1000_write_phy_reg(hw, PHY_REG(769, 16), phy_reg | 0x0040); 5094 /* Set Early Link Enable */ 5095 e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5096 e1000_write_phy_reg(hw, PHY_REG(769, 20), phy_reg | 0x0400); 5097 } 5098 5099 /* Set loopback */ 5100 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5101 5102 msec_delay(250); 5103 5104 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5105 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5106 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5107 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5108 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5109 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5110 E1000_CTRL_FD); /* Force Duplex to FULL */ 5111 5112 switch (hw->mac.type) { 5113 case e1000_82540: 5114 case e1000_82545: 5115 case e1000_82545_rev_3: 5116 case e1000_82546: 5117 case e1000_82546_rev_3: 5118 /* 5119 * For some serdes we'll need to commit the writes now 5120 * so that the status is updated on link 5121 */ 5122 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5123 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5124 msec_delay(100); 5125 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5126 } 5127 5128 if (hw->phy.media_type == e1000_media_type_copper) { 5129 /* Invert Loss of Signal */ 5130 ctrl |= E1000_CTRL_ILOS; 5131 } else { 5132 /* Set ILOS on fiber nic if half duplex is detected */ 5133 status = E1000_READ_REG(hw, E1000_STATUS); 5134 if ((status & E1000_STATUS_FD) == 0) 5135 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5136 } 5137 break; 5138 5139 case e1000_82571: 5140 case e1000_82572: 5141 /* 5142 * The fiber/SerDes versions of this adapter do not contain an 5143 * accessible PHY. Therefore, loopback beyond MAC must be done 5144 * using SerDes analog loopback. 5145 */ 5146 if (hw->phy.media_type != e1000_media_type_copper) { 5147 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5148 txcw = E1000_READ_REG(hw, E1000_TXCW); 5149 txcw &= ~((uint32_t)1 << 31); 5150 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5151 5152 /* 5153 * Write 0x410 to Serdes Control register 5154 * to enable Serdes analog loopback 5155 */ 5156 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5157 msec_delay(10); 5158 } 5159 5160 status = E1000_READ_REG(hw, E1000_STATUS); 5161 /* Set ILOS on fiber nic if half duplex is detected */ 5162 if ((hw->phy.media_type == e1000_media_type_fiber) && 5163 ((status & E1000_STATUS_FD) == 0 || 5164 (status & E1000_STATUS_LU) == 0)) 5165 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5166 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5167 ctrl |= E1000_CTRL_SLU; 5168 break; 5169 5170 case e1000_82573: 5171 ctrl |= E1000_CTRL_ILOS; 5172 break; 5173 case e1000_ich9lan: 5174 case e1000_ich10lan: 5175 ctrl |= E1000_CTRL_SLU; 5176 break; 5177 } 5178 if (hw->phy.type == e1000_phy_bm) 5179 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5180 5181 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5182 } 5183 5184 static void 5185 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5186 { 5187 struct e1000_hw *hw; 5188 uint32_t rctl; 5189 uint32_t ctrl_ext; 5190 uint32_t ctrl; 5191 uint32_t status; 5192 uint32_t txcw; 5193 uint16_t phydata; 5194 5195 hw = &Adapter->shared; 5196 5197 /* Disable Smart Power Down */ 5198 phy_spd_state(hw, B_FALSE); 5199 5200 switch (hw->mac.type) { 5201 case e1000_82571: 5202 case e1000_82572: 5203 switch (hw->phy.media_type) { 5204 case e1000_media_type_copper: 5205 /* Force link up (Must be done before the PHY writes) */ 5206 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5207 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5208 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5209 5210 rctl = E1000_READ_REG(hw, E1000_RCTL); 5211 rctl |= (E1000_RCTL_EN | 5212 E1000_RCTL_SBP | 5213 E1000_RCTL_UPE | 5214 E1000_RCTL_MPE | 5215 E1000_RCTL_LPE | 5216 E1000_RCTL_BAM); /* 0x803E */ 5217 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5218 5219 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5220 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5221 E1000_CTRL_EXT_SDP6_DATA | 5222 E1000_CTRL_EXT_SDP7_DATA | 5223 E1000_CTRL_EXT_SDP4_DIR | 5224 E1000_CTRL_EXT_SDP6_DIR | 5225 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 5226 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5227 5228 /* 5229 * This sequence tunes the PHY's SDP and no customer 5230 * settable values. For background, see comments above 5231 * e1000g_set_internal_loopback(). 5232 */ 5233 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5234 msec_delay(10); 5235 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5236 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5237 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5238 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5239 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5240 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5241 5242 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5243 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5244 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5245 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5246 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5247 5248 msec_delay(50); 5249 break; 5250 case e1000_media_type_fiber: 5251 case e1000_media_type_internal_serdes: 5252 status = E1000_READ_REG(hw, E1000_STATUS); 5253 if (((status & E1000_STATUS_LU) == 0) || 5254 (hw->phy.media_type == 5255 e1000_media_type_internal_serdes)) { 5256 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5257 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5258 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5259 } 5260 5261 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5262 txcw = E1000_READ_REG(hw, E1000_TXCW); 5263 txcw &= ~((uint32_t)1 << 31); 5264 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5265 5266 /* 5267 * Write 0x410 to Serdes Control register 5268 * to enable Serdes analog loopback 5269 */ 5270 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5271 msec_delay(10); 5272 break; 5273 default: 5274 break; 5275 } 5276 break; 5277 case e1000_82574: 5278 case e1000_80003es2lan: 5279 case e1000_ich9lan: 5280 case e1000_ich10lan: 5281 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5282 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5283 phydata | (1 << 5)); 5284 Adapter->param_adv_autoneg = 1; 5285 Adapter->param_adv_1000fdx = 1; 5286 (void) e1000g_reset_link(Adapter); 5287 break; 5288 } 5289 } 5290 5291 static void 5292 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5293 { 5294 struct e1000_hw *hw; 5295 uint32_t ctrl; 5296 uint16_t phy_ctrl; 5297 5298 hw = &Adapter->shared; 5299 5300 /* Disable Smart Power Down */ 5301 phy_spd_state(hw, B_FALSE); 5302 5303 phy_ctrl = (MII_CR_FULL_DUPLEX | 5304 MII_CR_SPEED_100); 5305 5306 /* Force 100/FD, reset PHY */ 5307 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5308 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5309 msec_delay(10); 5310 5311 /* Force 100/FD */ 5312 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5313 phy_ctrl); /* 0x2100 */ 5314 msec_delay(10); 5315 5316 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5317 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5318 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5319 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5320 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5321 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5322 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5323 E1000_CTRL_FD); /* Force Duplex to FULL */ 5324 5325 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5326 } 5327 5328 static void 5329 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5330 { 5331 struct e1000_hw *hw; 5332 uint32_t ctrl; 5333 uint16_t phy_ctrl; 5334 5335 hw = &Adapter->shared; 5336 5337 /* Disable Smart Power Down */ 5338 phy_spd_state(hw, B_FALSE); 5339 5340 phy_ctrl = (MII_CR_FULL_DUPLEX | 5341 MII_CR_SPEED_10); 5342 5343 /* Force 10/FD, reset PHY */ 5344 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5345 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5346 msec_delay(10); 5347 5348 /* Force 10/FD */ 5349 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5350 phy_ctrl); /* 0x0100 */ 5351 msec_delay(10); 5352 5353 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5354 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5355 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5356 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5357 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5358 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5359 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5360 E1000_CTRL_FD); /* Force Duplex to FULL */ 5361 5362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5363 } 5364 5365 #ifdef __sparc 5366 static boolean_t 5367 e1000g_find_mac_address(struct e1000g *Adapter) 5368 { 5369 struct e1000_hw *hw = &Adapter->shared; 5370 uchar_t *bytes; 5371 struct ether_addr sysaddr; 5372 uint_t nelts; 5373 int err; 5374 boolean_t found = B_FALSE; 5375 5376 /* 5377 * The "vendor's factory-set address" may already have 5378 * been extracted from the chip, but if the property 5379 * "local-mac-address" is set we use that instead. 5380 * 5381 * We check whether it looks like an array of 6 5382 * bytes (which it should, if OBP set it). If we can't 5383 * make sense of it this way, we'll ignore it. 5384 */ 5385 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5386 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5387 if (err == DDI_PROP_SUCCESS) { 5388 if (nelts == ETHERADDRL) { 5389 while (nelts--) 5390 hw->mac.addr[nelts] = bytes[nelts]; 5391 found = B_TRUE; 5392 } 5393 ddi_prop_free(bytes); 5394 } 5395 5396 /* 5397 * Look up the OBP property "local-mac-address?". If the user has set 5398 * 'local-mac-address? = false', use "the system address" instead. 5399 */ 5400 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5401 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5402 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5403 if (localetheraddr(NULL, &sysaddr) != 0) { 5404 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5405 found = B_TRUE; 5406 } 5407 } 5408 ddi_prop_free(bytes); 5409 } 5410 5411 /* 5412 * Finally(!), if there's a valid "mac-address" property (created 5413 * if we netbooted from this interface), we must use this instead 5414 * of any of the above to ensure that the NFS/install server doesn't 5415 * get confused by the address changing as Solaris takes over! 5416 */ 5417 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5418 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5419 if (err == DDI_PROP_SUCCESS) { 5420 if (nelts == ETHERADDRL) { 5421 while (nelts--) 5422 hw->mac.addr[nelts] = bytes[nelts]; 5423 found = B_TRUE; 5424 } 5425 ddi_prop_free(bytes); 5426 } 5427 5428 if (found) { 5429 bcopy(hw->mac.addr, hw->mac.perm_addr, 5430 ETHERADDRL); 5431 } 5432 5433 return (found); 5434 } 5435 #endif 5436 5437 static int 5438 e1000g_add_intrs(struct e1000g *Adapter) 5439 { 5440 dev_info_t *devinfo; 5441 int intr_types; 5442 int rc; 5443 5444 devinfo = Adapter->dip; 5445 5446 /* Get supported interrupt types */ 5447 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5448 5449 if (rc != DDI_SUCCESS) { 5450 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5451 "Get supported interrupt types failed: %d\n", rc); 5452 return (DDI_FAILURE); 5453 } 5454 5455 /* 5456 * Based on Intel Technical Advisory document (TA-160), there are some 5457 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5458 * that it supports MSI, but in fact has problems. 5459 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5460 * PCI/PCI-X NICs. 5461 */ 5462 if (Adapter->shared.mac.type < e1000_82571) 5463 Adapter->msi_enable = B_FALSE; 5464 5465 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5466 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5467 5468 if (rc != DDI_SUCCESS) { 5469 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5470 "Add MSI failed, trying Legacy interrupts\n"); 5471 } else { 5472 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5473 } 5474 } 5475 5476 if ((Adapter->intr_type == 0) && 5477 (intr_types & DDI_INTR_TYPE_FIXED)) { 5478 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5479 5480 if (rc != DDI_SUCCESS) { 5481 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5482 "Add Legacy interrupts failed\n"); 5483 return (DDI_FAILURE); 5484 } 5485 5486 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5487 } 5488 5489 if (Adapter->intr_type == 0) { 5490 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5491 "No interrupts registered\n"); 5492 return (DDI_FAILURE); 5493 } 5494 5495 return (DDI_SUCCESS); 5496 } 5497 5498 /* 5499 * e1000g_intr_add() handles MSI/Legacy interrupts 5500 */ 5501 static int 5502 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5503 { 5504 dev_info_t *devinfo; 5505 int count, avail, actual; 5506 int x, y, rc, inum = 0; 5507 int flag; 5508 ddi_intr_handler_t *intr_handler; 5509 5510 devinfo = Adapter->dip; 5511 5512 /* get number of interrupts */ 5513 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5514 if ((rc != DDI_SUCCESS) || (count == 0)) { 5515 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5516 "Get interrupt number failed. Return: %d, count: %d\n", 5517 rc, count); 5518 return (DDI_FAILURE); 5519 } 5520 5521 /* get number of available interrupts */ 5522 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5523 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5524 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5525 "Get interrupt available number failed. " 5526 "Return: %d, available: %d\n", rc, avail); 5527 return (DDI_FAILURE); 5528 } 5529 5530 if (avail < count) { 5531 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5532 "Interrupts count: %d, available: %d\n", 5533 count, avail); 5534 } 5535 5536 /* Allocate an array of interrupt handles */ 5537 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5538 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5539 5540 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5541 flag = DDI_INTR_ALLOC_NORMAL; 5542 5543 /* call ddi_intr_alloc() */ 5544 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5545 count, &actual, flag); 5546 5547 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5548 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5549 "Allocate interrupts failed: %d\n", rc); 5550 5551 kmem_free(Adapter->htable, Adapter->intr_size); 5552 return (DDI_FAILURE); 5553 } 5554 5555 if (actual < count) { 5556 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5557 "Interrupts requested: %d, received: %d\n", 5558 count, actual); 5559 } 5560 5561 Adapter->intr_cnt = actual; 5562 5563 /* Get priority for first msi, assume remaining are all the same */ 5564 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5565 5566 if (rc != DDI_SUCCESS) { 5567 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5568 "Get interrupt priority failed: %d\n", rc); 5569 5570 /* Free already allocated intr */ 5571 for (y = 0; y < actual; y++) 5572 (void) ddi_intr_free(Adapter->htable[y]); 5573 5574 kmem_free(Adapter->htable, Adapter->intr_size); 5575 return (DDI_FAILURE); 5576 } 5577 5578 /* 5579 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5580 * use the interrupt service routine e1000g_intr_pciexpress() 5581 * to avoid interrupt stealing when sharing interrupt with other 5582 * devices. 5583 */ 5584 if (Adapter->shared.mac.type < e1000_82571) 5585 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5586 else 5587 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5588 5589 /* Call ddi_intr_add_handler() */ 5590 for (x = 0; x < actual; x++) { 5591 rc = ddi_intr_add_handler(Adapter->htable[x], 5592 intr_handler, (caddr_t)Adapter, NULL); 5593 5594 if (rc != DDI_SUCCESS) { 5595 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5596 "Add interrupt handler failed: %d\n", rc); 5597 5598 /* Remove already added handler */ 5599 for (y = 0; y < x; y++) 5600 (void) ddi_intr_remove_handler( 5601 Adapter->htable[y]); 5602 5603 /* Free already allocated intr */ 5604 for (y = 0; y < actual; y++) 5605 (void) ddi_intr_free(Adapter->htable[y]); 5606 5607 kmem_free(Adapter->htable, Adapter->intr_size); 5608 return (DDI_FAILURE); 5609 } 5610 } 5611 5612 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5613 5614 if (rc != DDI_SUCCESS) { 5615 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5616 "Get interrupt cap failed: %d\n", rc); 5617 5618 /* Free already allocated intr */ 5619 for (y = 0; y < actual; y++) { 5620 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5621 (void) ddi_intr_free(Adapter->htable[y]); 5622 } 5623 5624 kmem_free(Adapter->htable, Adapter->intr_size); 5625 return (DDI_FAILURE); 5626 } 5627 5628 return (DDI_SUCCESS); 5629 } 5630 5631 static int 5632 e1000g_rem_intrs(struct e1000g *Adapter) 5633 { 5634 int x; 5635 int rc; 5636 5637 for (x = 0; x < Adapter->intr_cnt; x++) { 5638 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5639 if (rc != DDI_SUCCESS) { 5640 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5641 "Remove intr handler failed: %d\n", rc); 5642 return (DDI_FAILURE); 5643 } 5644 5645 rc = ddi_intr_free(Adapter->htable[x]); 5646 if (rc != DDI_SUCCESS) { 5647 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5648 "Free intr failed: %d\n", rc); 5649 return (DDI_FAILURE); 5650 } 5651 } 5652 5653 kmem_free(Adapter->htable, Adapter->intr_size); 5654 5655 return (DDI_SUCCESS); 5656 } 5657 5658 static int 5659 e1000g_enable_intrs(struct e1000g *Adapter) 5660 { 5661 int x; 5662 int rc; 5663 5664 /* Enable interrupts */ 5665 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5666 /* Call ddi_intr_block_enable() for MSI */ 5667 rc = ddi_intr_block_enable(Adapter->htable, 5668 Adapter->intr_cnt); 5669 if (rc != DDI_SUCCESS) { 5670 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5671 "Enable block intr failed: %d\n", rc); 5672 return (DDI_FAILURE); 5673 } 5674 } else { 5675 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5676 for (x = 0; x < Adapter->intr_cnt; x++) { 5677 rc = ddi_intr_enable(Adapter->htable[x]); 5678 if (rc != DDI_SUCCESS) { 5679 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5680 "Enable intr failed: %d\n", rc); 5681 return (DDI_FAILURE); 5682 } 5683 } 5684 } 5685 5686 return (DDI_SUCCESS); 5687 } 5688 5689 static int 5690 e1000g_disable_intrs(struct e1000g *Adapter) 5691 { 5692 int x; 5693 int rc; 5694 5695 /* Disable all interrupts */ 5696 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5697 rc = ddi_intr_block_disable(Adapter->htable, 5698 Adapter->intr_cnt); 5699 if (rc != DDI_SUCCESS) { 5700 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5701 "Disable block intr failed: %d\n", rc); 5702 return (DDI_FAILURE); 5703 } 5704 } else { 5705 for (x = 0; x < Adapter->intr_cnt; x++) { 5706 rc = ddi_intr_disable(Adapter->htable[x]); 5707 if (rc != DDI_SUCCESS) { 5708 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5709 "Disable intr failed: %d\n", rc); 5710 return (DDI_FAILURE); 5711 } 5712 } 5713 } 5714 5715 return (DDI_SUCCESS); 5716 } 5717 5718 /* 5719 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5720 */ 5721 static void 5722 e1000g_get_phy_state(struct e1000g *Adapter) 5723 { 5724 struct e1000_hw *hw = &Adapter->shared; 5725 5726 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5727 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5728 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5729 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5730 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5731 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5732 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5733 &Adapter->phy_1000t_status); 5734 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5735 5736 Adapter->param_autoneg_cap = 5737 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5738 Adapter->param_pause_cap = 5739 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5740 Adapter->param_asym_pause_cap = 5741 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5742 Adapter->param_1000fdx_cap = 5743 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5744 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5745 Adapter->param_1000hdx_cap = 5746 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5747 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5748 Adapter->param_100t4_cap = 5749 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5750 Adapter->param_100fdx_cap = 5751 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5752 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5753 Adapter->param_100hdx_cap = 5754 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5755 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5756 Adapter->param_10fdx_cap = 5757 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5758 Adapter->param_10hdx_cap = 5759 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5760 5761 Adapter->param_adv_autoneg = hw->mac.autoneg; 5762 Adapter->param_adv_pause = 5763 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5764 Adapter->param_adv_asym_pause = 5765 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5766 Adapter->param_adv_1000hdx = 5767 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5768 Adapter->param_adv_100t4 = 5769 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5770 if (Adapter->param_adv_autoneg == 1) { 5771 Adapter->param_adv_1000fdx = 5772 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5773 Adapter->param_adv_100fdx = 5774 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5775 Adapter->param_adv_100hdx = 5776 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5777 Adapter->param_adv_10fdx = 5778 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5779 Adapter->param_adv_10hdx = 5780 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5781 } 5782 5783 Adapter->param_lp_autoneg = 5784 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5785 Adapter->param_lp_pause = 5786 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5787 Adapter->param_lp_asym_pause = 5788 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5789 Adapter->param_lp_1000fdx = 5790 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5791 Adapter->param_lp_1000hdx = 5792 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5793 Adapter->param_lp_100t4 = 5794 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5795 Adapter->param_lp_100fdx = 5796 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5797 Adapter->param_lp_100hdx = 5798 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5799 Adapter->param_lp_10fdx = 5800 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5801 Adapter->param_lp_10hdx = 5802 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5803 } 5804 5805 /* 5806 * FMA support 5807 */ 5808 5809 int 5810 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5811 { 5812 ddi_fm_error_t de; 5813 5814 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5815 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5816 return (de.fme_status); 5817 } 5818 5819 int 5820 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5821 { 5822 ddi_fm_error_t de; 5823 5824 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5825 return (de.fme_status); 5826 } 5827 5828 /* 5829 * The IO fault service error handling callback function 5830 */ 5831 /* ARGSUSED2 */ 5832 static int 5833 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5834 { 5835 /* 5836 * as the driver can always deal with an error in any dma or 5837 * access handle, we can just return the fme_status value. 5838 */ 5839 pci_ereport_post(dip, err, NULL); 5840 return (err->fme_status); 5841 } 5842 5843 static void 5844 e1000g_fm_init(struct e1000g *Adapter) 5845 { 5846 ddi_iblock_cookie_t iblk; 5847 int fma_acc_flag, fma_dma_flag; 5848 5849 /* Only register with IO Fault Services if we have some capability */ 5850 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5851 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5852 fma_acc_flag = 1; 5853 } else { 5854 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5855 fma_acc_flag = 0; 5856 } 5857 5858 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5859 fma_dma_flag = 1; 5860 } else { 5861 fma_dma_flag = 0; 5862 } 5863 5864 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5865 5866 if (Adapter->fm_capabilities) { 5867 5868 /* Register capabilities with IO Fault Services */ 5869 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5870 5871 /* 5872 * Initialize pci ereport capabilities if ereport capable 5873 */ 5874 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5875 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5876 pci_ereport_setup(Adapter->dip); 5877 5878 /* 5879 * Register error callback if error callback capable 5880 */ 5881 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5882 ddi_fm_handler_register(Adapter->dip, 5883 e1000g_fm_error_cb, (void*) Adapter); 5884 } 5885 } 5886 5887 static void 5888 e1000g_fm_fini(struct e1000g *Adapter) 5889 { 5890 /* Only unregister FMA capabilities if we registered some */ 5891 if (Adapter->fm_capabilities) { 5892 5893 /* 5894 * Release any resources allocated by pci_ereport_setup() 5895 */ 5896 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5897 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5898 pci_ereport_teardown(Adapter->dip); 5899 5900 /* 5901 * Un-register error callback if error callback capable 5902 */ 5903 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5904 ddi_fm_handler_unregister(Adapter->dip); 5905 5906 /* Unregister from IO Fault Services */ 5907 ddi_fm_fini(Adapter->dip); 5908 } 5909 } 5910 5911 void 5912 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5913 { 5914 uint64_t ena; 5915 char buf[FM_MAX_CLASS]; 5916 5917 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5918 ena = fm_ena_generate(0, FM_ENA_FMT1); 5919 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5920 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5921 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5922 } 5923 } 5924 5925 /* 5926 * quiesce(9E) entry point. 5927 * 5928 * This function is called when the system is single-threaded at high 5929 * PIL with preemption disabled. Therefore, this function must not be 5930 * blocked. 5931 * 5932 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5933 * DDI_FAILURE indicates an error condition and should almost never happen. 5934 */ 5935 static int 5936 e1000g_quiesce(dev_info_t *devinfo) 5937 { 5938 struct e1000g *Adapter; 5939 5940 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5941 5942 if (Adapter == NULL) 5943 return (DDI_FAILURE); 5944 5945 e1000g_clear_all_interrupts(Adapter); 5946 5947 (void) e1000_reset_hw(&Adapter->shared); 5948 5949 /* Setup our HW Tx Head & Tail descriptor pointers */ 5950 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5951 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5952 5953 /* Setup our HW Rx Head & Tail descriptor pointers */ 5954 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5955 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5956 5957 return (DDI_SUCCESS); 5958 } 5959 5960 static int 5961 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5962 uint_t pr_valsize, void *pr_val) 5963 { 5964 link_flowctrl_t fl; 5965 int err = 0; 5966 5967 ASSERT(pr_valsize > 0); 5968 switch (pr_num) { 5969 case MAC_PROP_AUTONEG: 5970 *(uint8_t *)pr_val = 5971 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5972 break; 5973 case MAC_PROP_FLOWCTRL: 5974 if (pr_valsize < sizeof (link_flowctrl_t)) 5975 return (EINVAL); 5976 fl = LINK_FLOWCTRL_BI; 5977 bcopy(&fl, pr_val, sizeof (fl)); 5978 break; 5979 case MAC_PROP_ADV_1000FDX_CAP: 5980 case MAC_PROP_EN_1000FDX_CAP: 5981 *(uint8_t *)pr_val = 5982 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5983 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5984 break; 5985 case MAC_PROP_ADV_1000HDX_CAP: 5986 case MAC_PROP_EN_1000HDX_CAP: 5987 *(uint8_t *)pr_val = 5988 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5989 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5990 break; 5991 case MAC_PROP_ADV_100FDX_CAP: 5992 case MAC_PROP_EN_100FDX_CAP: 5993 *(uint8_t *)pr_val = 5994 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5995 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5996 break; 5997 case MAC_PROP_ADV_100HDX_CAP: 5998 case MAC_PROP_EN_100HDX_CAP: 5999 *(uint8_t *)pr_val = 6000 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6001 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6002 break; 6003 case MAC_PROP_ADV_10FDX_CAP: 6004 case MAC_PROP_EN_10FDX_CAP: 6005 *(uint8_t *)pr_val = 6006 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6007 break; 6008 case MAC_PROP_ADV_10HDX_CAP: 6009 case MAC_PROP_EN_10HDX_CAP: 6010 *(uint8_t *)pr_val = 6011 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6012 break; 6013 default: 6014 err = ENOTSUP; 6015 break; 6016 } 6017 return (err); 6018 } 6019 6020 /* 6021 * synchronize the adv* and en* parameters. 6022 * 6023 * See comments in <sys/dld.h> for details of the *_en_* 6024 * parameters. The usage of ndd for setting adv parameters will 6025 * synchronize all the en parameters with the e1000g parameters, 6026 * implicitly disabling any settings made via dladm. 6027 */ 6028 static void 6029 e1000g_param_sync(struct e1000g *Adapter) 6030 { 6031 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6032 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6033 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6034 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6035 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6036 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6037 } 6038 6039 /* 6040 * e1000g_get_driver_control - tell manageability firmware that the driver 6041 * has control. 6042 */ 6043 static void 6044 e1000g_get_driver_control(struct e1000_hw *hw) 6045 { 6046 uint32_t ctrl_ext; 6047 uint32_t swsm; 6048 6049 /* tell manageability firmware the driver has taken over */ 6050 switch (hw->mac.type) { 6051 case e1000_82573: 6052 swsm = E1000_READ_REG(hw, E1000_SWSM); 6053 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6054 break; 6055 case e1000_82571: 6056 case e1000_82572: 6057 case e1000_82574: 6058 case e1000_80003es2lan: 6059 case e1000_ich8lan: 6060 case e1000_ich9lan: 6061 case e1000_ich10lan: 6062 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6063 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6064 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6065 break; 6066 default: 6067 /* no manageability firmware: do nothing */ 6068 break; 6069 } 6070 } 6071 6072 /* 6073 * e1000g_release_driver_control - tell manageability firmware that the driver 6074 * has released control. 6075 */ 6076 static void 6077 e1000g_release_driver_control(struct e1000_hw *hw) 6078 { 6079 uint32_t ctrl_ext; 6080 uint32_t swsm; 6081 6082 /* tell manageability firmware the driver has released control */ 6083 switch (hw->mac.type) { 6084 case e1000_82573: 6085 swsm = E1000_READ_REG(hw, E1000_SWSM); 6086 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6087 break; 6088 case e1000_82571: 6089 case e1000_82572: 6090 case e1000_82574: 6091 case e1000_80003es2lan: 6092 case e1000_ich8lan: 6093 case e1000_ich9lan: 6094 case e1000_ich10lan: 6095 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6096 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6097 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6098 break; 6099 default: 6100 /* no manageability firmware: do nothing */ 6101 break; 6102 } 6103 } 6104 6105 /* 6106 * Restore e1000g promiscuous mode. 6107 */ 6108 static void 6109 e1000g_restore_promisc(struct e1000g *Adapter) 6110 { 6111 if (Adapter->e1000g_promisc) { 6112 uint32_t rctl; 6113 6114 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6115 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6116 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6117 } 6118 } 6119