1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.2.13"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 68 #pragma inline(e1000g_get_itr) 69 static int e1000g_init(struct e1000g *); 70 static int e1000g_start(struct e1000g *, boolean_t); 71 static void e1000g_stop(struct e1000g *, boolean_t); 72 static int e1000g_m_start(void *); 73 static void e1000g_m_stop(void *); 74 static int e1000g_m_promisc(void *, boolean_t); 75 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 76 static int e1000g_m_unicst(void *, const uint8_t *); 77 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 78 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 79 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 81 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 82 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 83 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 84 uint_t, const void *); 85 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 86 uint_t, uint_t, void *); 87 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 88 const void *); 89 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 90 uint_t, void *); 91 static void e1000g_init_locks(struct e1000g *); 92 static void e1000g_destroy_locks(struct e1000g *); 93 static int e1000g_identify_hardware(struct e1000g *); 94 static int e1000g_regs_map(struct e1000g *); 95 static int e1000g_set_driver_params(struct e1000g *); 96 static void e1000g_set_bufsize(struct e1000g *); 97 static int e1000g_register_mac(struct e1000g *); 98 static boolean_t e1000g_rx_drain(struct e1000g *); 99 static boolean_t e1000g_tx_drain(struct e1000g *); 100 static void e1000g_init_unicst(struct e1000g *); 101 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 102 103 /* 104 * Local routines 105 */ 106 static boolean_t e1000g_reset_adapter(struct e1000g *); 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 static void e1000g_get_driver_control(struct e1000_hw *); 161 static void e1000g_release_driver_control(struct e1000_hw *); 162 163 mac_priv_prop_t e1000g_priv_props[] = { 164 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 165 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 166 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 167 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 168 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 169 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 170 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 171 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 172 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 173 {"_intr_adaptive", MAC_PROP_PERM_RW}, 174 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 175 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 176 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 177 {"_tx_recycle_num", MAC_PROP_PERM_RW} 178 }; 179 #define E1000G_MAX_PRIV_PROPS \ 180 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 181 182 183 static struct cb_ops cb_ws_ops = { 184 nulldev, /* cb_open */ 185 nulldev, /* cb_close */ 186 nodev, /* cb_strategy */ 187 nodev, /* cb_print */ 188 nodev, /* cb_dump */ 189 nodev, /* cb_read */ 190 nodev, /* cb_write */ 191 nodev, /* cb_ioctl */ 192 nodev, /* cb_devmap */ 193 nodev, /* cb_mmap */ 194 nodev, /* cb_segmap */ 195 nochpoll, /* cb_chpoll */ 196 ddi_prop_op, /* cb_prop_op */ 197 NULL, /* cb_stream */ 198 D_MP | D_HOTPLUG, /* cb_flag */ 199 CB_REV, /* cb_rev */ 200 nodev, /* cb_aread */ 201 nodev /* cb_awrite */ 202 }; 203 204 static struct dev_ops ws_ops = { 205 DEVO_REV, /* devo_rev */ 206 0, /* devo_refcnt */ 207 NULL, /* devo_getinfo */ 208 nulldev, /* devo_identify */ 209 nulldev, /* devo_probe */ 210 e1000g_attach, /* devo_attach */ 211 e1000g_detach, /* devo_detach */ 212 nodev, /* devo_reset */ 213 &cb_ws_ops, /* devo_cb_ops */ 214 NULL, /* devo_bus_ops */ 215 ddi_power, /* devo_power */ 216 e1000g_quiesce /* devo_quiesce */ 217 }; 218 219 static struct modldrv modldrv = { 220 &mod_driverops, /* Type of module. This one is a driver */ 221 ident, /* Discription string */ 222 &ws_ops, /* driver ops */ 223 }; 224 225 static struct modlinkage modlinkage = { 226 MODREV_1, &modldrv, NULL 227 }; 228 229 /* Access attributes for register mapping */ 230 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 231 DDI_DEVICE_ATTR_V0, 232 DDI_STRUCTURE_LE_ACC, 233 DDI_STRICTORDER_ACC, 234 DDI_FLAGERR_ACC 235 }; 236 237 #define E1000G_M_CALLBACK_FLAGS \ 238 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 239 240 static mac_callbacks_t e1000g_m_callbacks = { 241 E1000G_M_CALLBACK_FLAGS, 242 e1000g_m_stat, 243 e1000g_m_start, 244 e1000g_m_stop, 245 e1000g_m_promisc, 246 e1000g_m_multicst, 247 e1000g_m_unicst, 248 e1000g_m_tx, 249 NULL, 250 e1000g_m_ioctl, 251 e1000g_m_getcapab, 252 NULL, 253 NULL, 254 e1000g_m_setprop, 255 e1000g_m_getprop 256 }; 257 258 /* 259 * Global variables 260 */ 261 uint32_t e1000g_mblks_pending = 0; 262 /* 263 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 264 * Here we maintain a private dev_info list if e1000g_force_detach is 265 * enabled. If we force the driver to detach while there are still some 266 * rx buffers retained in the upper layer, we have to keep a copy of the 267 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 268 * structure will be freed after the driver is detached. However when we 269 * finally free those rx buffers released by the upper layer, we need to 270 * refer to the dev_info to free the dma buffers. So we save a copy of 271 * the dev_info for this purpose. On x86 platform, we assume this copy 272 * of dev_info is always valid, but on SPARC platform, it could be invalid 273 * after the system board level DR operation. For this reason, the global 274 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 275 */ 276 #ifdef __sparc 277 boolean_t e1000g_force_detach = B_FALSE; 278 #else 279 boolean_t e1000g_force_detach = B_TRUE; 280 #endif 281 private_devi_list_t *e1000g_private_devi_list = NULL; 282 283 /* 284 * The rwlock is defined to protect the whole processing of rx recycling 285 * and the rx packets release in detach processing to make them mutually 286 * exclusive. 287 * The rx recycling processes different rx packets in different threads, 288 * so it will be protected with RW_READER and it won't block any other rx 289 * recycling threads. 290 * While the detach processing will be protected with RW_WRITER to make 291 * it mutually exclusive with the rx recycling. 292 */ 293 krwlock_t e1000g_rx_detach_lock; 294 /* 295 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 296 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 297 * If there are many e1000g instances, the system may run out of DVMA 298 * resources during the initialization of the instances, then the flag will 299 * be changed to "USE_DMA". Because different e1000g instances are initialized 300 * in parallel, we need to use this lock to protect the flag. 301 */ 302 krwlock_t e1000g_dma_type_lock; 303 304 /* 305 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 306 * Based on the information from Intel, the 82546 chipset has some hardware 307 * problem. When one port is being reset and the other port is trying to 308 * access the eeprom, it could cause system hang or panic. To workaround this 309 * hardware problem, we use a global mutex to prevent such operations from 310 * happening simultaneously on different instances. This workaround is applied 311 * to all the devices supported by this driver. 312 */ 313 kmutex_t e1000g_nvm_lock; 314 315 /* 316 * Loadable module configuration entry points for the driver 317 */ 318 319 /* 320 * _init - module initialization 321 */ 322 int 323 _init(void) 324 { 325 int status; 326 327 mac_init_ops(&ws_ops, WSNAME); 328 status = mod_install(&modlinkage); 329 if (status != DDI_SUCCESS) 330 mac_fini_ops(&ws_ops); 331 else { 332 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 333 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 334 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 335 } 336 337 return (status); 338 } 339 340 /* 341 * _fini - module finalization 342 */ 343 int 344 _fini(void) 345 { 346 int status; 347 348 rw_enter(&e1000g_rx_detach_lock, RW_READER); 349 if (e1000g_mblks_pending != 0) { 350 rw_exit(&e1000g_rx_detach_lock); 351 return (EBUSY); 352 } 353 rw_exit(&e1000g_rx_detach_lock); 354 355 status = mod_remove(&modlinkage); 356 if (status == DDI_SUCCESS) { 357 mac_fini_ops(&ws_ops); 358 359 if (e1000g_force_detach) { 360 private_devi_list_t *devi_node; 361 362 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 363 while (e1000g_private_devi_list != NULL) { 364 devi_node = e1000g_private_devi_list; 365 e1000g_private_devi_list = 366 e1000g_private_devi_list->next; 367 368 kmem_free(devi_node->priv_dip, 369 sizeof (struct dev_info)); 370 kmem_free(devi_node, 371 sizeof (private_devi_list_t)); 372 } 373 rw_exit(&e1000g_rx_detach_lock); 374 } 375 376 rw_destroy(&e1000g_rx_detach_lock); 377 rw_destroy(&e1000g_dma_type_lock); 378 mutex_destroy(&e1000g_nvm_lock); 379 } 380 381 return (status); 382 } 383 384 /* 385 * _info - module information 386 */ 387 int 388 _info(struct modinfo *modinfop) 389 { 390 return (mod_info(&modlinkage, modinfop)); 391 } 392 393 /* 394 * e1000g_attach - driver attach 395 * 396 * This function is the device-specific initialization entry 397 * point. This entry point is required and must be written. 398 * The DDI_ATTACH command must be provided in the attach entry 399 * point. When attach() is called with cmd set to DDI_ATTACH, 400 * all normal kernel services (such as kmem_alloc(9F)) are 401 * available for use by the driver. 402 * 403 * The attach() function will be called once for each instance 404 * of the device on the system with cmd set to DDI_ATTACH. 405 * Until attach() succeeds, the only driver entry points which 406 * may be called are open(9E) and getinfo(9E). 407 */ 408 static int 409 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 410 { 411 struct e1000g *Adapter; 412 struct e1000_hw *hw; 413 struct e1000g_osdep *osdep; 414 int instance; 415 416 switch (cmd) { 417 default: 418 e1000g_log(NULL, CE_WARN, 419 "Unsupported command send to e1000g_attach... "); 420 return (DDI_FAILURE); 421 422 case DDI_RESUME: 423 return (e1000g_resume(devinfo)); 424 425 case DDI_ATTACH: 426 break; 427 } 428 429 /* 430 * get device instance number 431 */ 432 instance = ddi_get_instance(devinfo); 433 434 /* 435 * Allocate soft data structure 436 */ 437 Adapter = 438 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 439 440 Adapter->dip = devinfo; 441 Adapter->instance = instance; 442 Adapter->tx_ring->adapter = Adapter; 443 Adapter->rx_ring->adapter = Adapter; 444 445 hw = &Adapter->shared; 446 osdep = &Adapter->osdep; 447 hw->back = osdep; 448 osdep->adapter = Adapter; 449 450 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 451 452 /* 453 * Initialize for fma support 454 */ 455 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 456 0, 0x0f, 457 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 458 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 459 e1000g_fm_init(Adapter); 460 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 461 462 /* 463 * PCI Configure 464 */ 465 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 466 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 467 goto attach_fail; 468 } 469 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 470 471 /* 472 * Setup hardware 473 */ 474 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 475 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 476 goto attach_fail; 477 } 478 479 /* 480 * Map in the device registers. 481 */ 482 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 483 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 484 goto attach_fail; 485 } 486 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 487 488 /* 489 * Initialize driver parameters 490 */ 491 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 492 goto attach_fail; 493 } 494 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 495 496 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 497 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 498 goto attach_fail; 499 } 500 501 /* 502 * Initialize interrupts 503 */ 504 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 505 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 506 goto attach_fail; 507 } 508 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 509 510 /* 511 * Initialize mutex's for this device. 512 * Do this before enabling the interrupt handler and 513 * register the softint to avoid the condition where 514 * interrupt handler can try using uninitialized mutex 515 */ 516 e1000g_init_locks(Adapter); 517 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 518 519 /* 520 * Initialize Driver Counters 521 */ 522 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 523 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 524 goto attach_fail; 525 } 526 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 527 528 /* 529 * Initialize chip hardware and software structures 530 */ 531 if (e1000g_init(Adapter) != DDI_SUCCESS) { 532 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 533 goto attach_fail; 534 } 535 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 536 537 /* 538 * Register the driver to the MAC 539 */ 540 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 541 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 542 goto attach_fail; 543 } 544 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 545 546 /* 547 * Now that mutex locks are initialized, and the chip is also 548 * initialized, enable interrupts. 549 */ 550 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 551 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 552 goto attach_fail; 553 } 554 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 555 556 /* 557 * If e1000g_force_detach is enabled, in global private dip list, 558 * we will create a new entry, which maintains the priv_dip for DR 559 * supports after driver detached. 560 */ 561 if (e1000g_force_detach) { 562 private_devi_list_t *devi_node; 563 564 Adapter->priv_dip = 565 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 566 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 567 sizeof (struct dev_info)); 568 569 devi_node = 570 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 571 572 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 573 devi_node->priv_dip = Adapter->priv_dip; 574 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 575 devi_node->next = e1000g_private_devi_list; 576 e1000g_private_devi_list = devi_node; 577 rw_exit(&e1000g_rx_detach_lock); 578 } 579 580 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 581 582 return (DDI_SUCCESS); 583 584 attach_fail: 585 e1000g_unattach(devinfo, Adapter); 586 return (DDI_FAILURE); 587 } 588 589 static int 590 e1000g_register_mac(struct e1000g *Adapter) 591 { 592 struct e1000_hw *hw = &Adapter->shared; 593 mac_register_t *mac; 594 int err; 595 596 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 597 return (DDI_FAILURE); 598 599 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 600 mac->m_driver = Adapter; 601 mac->m_dip = Adapter->dip; 602 mac->m_src_addr = hw->mac.addr; 603 mac->m_callbacks = &e1000g_m_callbacks; 604 mac->m_min_sdu = 0; 605 mac->m_max_sdu = Adapter->default_mtu; 606 mac->m_margin = VLAN_TAGSZ; 607 mac->m_priv_props = e1000g_priv_props; 608 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 609 610 err = mac_register(mac, &Adapter->mh); 611 mac_free(mac); 612 613 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 614 } 615 616 static int 617 e1000g_identify_hardware(struct e1000g *Adapter) 618 { 619 struct e1000_hw *hw = &Adapter->shared; 620 struct e1000g_osdep *osdep = &Adapter->osdep; 621 622 /* Get the device id */ 623 hw->vendor_id = 624 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 625 hw->device_id = 626 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 627 hw->revision_id = 628 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 629 hw->subsystem_device_id = 630 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 631 hw->subsystem_vendor_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 633 634 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 635 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 636 "MAC type could not be set properly."); 637 return (DDI_FAILURE); 638 } 639 640 return (DDI_SUCCESS); 641 } 642 643 static int 644 e1000g_regs_map(struct e1000g *Adapter) 645 { 646 dev_info_t *devinfo = Adapter->dip; 647 struct e1000_hw *hw = &Adapter->shared; 648 struct e1000g_osdep *osdep = &Adapter->osdep; 649 off_t mem_size; 650 651 /* Get size of adapter register memory */ 652 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 653 DDI_SUCCESS) { 654 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 655 "ddi_dev_regsize for registers failed"); 656 return (DDI_FAILURE); 657 } 658 659 /* Map adapter register memory */ 660 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 661 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 662 &osdep->reg_handle)) != DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_regs_map_setup for registers failed"); 665 goto regs_map_fail; 666 } 667 668 /* ICH needs to map flash memory */ 669 if (hw->mac.type == e1000_ich8lan || 670 hw->mac.type == e1000_ich9lan || 671 hw->mac.type == e1000_ich10lan) { 672 /* get flash size */ 673 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 674 &mem_size) != DDI_SUCCESS) { 675 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 676 "ddi_dev_regsize for ICH flash failed"); 677 goto regs_map_fail; 678 } 679 680 /* map flash in */ 681 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 682 (caddr_t *)&hw->flash_address, 0, 683 mem_size, &e1000g_regs_acc_attr, 684 &osdep->ich_flash_handle) != DDI_SUCCESS) { 685 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 686 "ddi_regs_map_setup for ICH flash failed"); 687 goto regs_map_fail; 688 } 689 } 690 691 return (DDI_SUCCESS); 692 693 regs_map_fail: 694 if (osdep->reg_handle != NULL) 695 ddi_regs_map_free(&osdep->reg_handle); 696 697 return (DDI_FAILURE); 698 } 699 700 static int 701 e1000g_set_driver_params(struct e1000g *Adapter) 702 { 703 struct e1000_hw *hw; 704 uint32_t mem_bar, io_bar, bar64; 705 706 hw = &Adapter->shared; 707 708 /* Set MAC type and initialize hardware functions */ 709 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 710 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 711 "Could not setup hardware functions"); 712 return (DDI_FAILURE); 713 } 714 715 /* Get bus information */ 716 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 717 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 718 "Could not get bus information"); 719 return (DDI_FAILURE); 720 } 721 722 /* get mem_base addr */ 723 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 724 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 725 726 /* get io_base addr */ 727 if (hw->mac.type >= e1000_82544) { 728 if (bar64) { 729 /* IO BAR is different for 64 bit BAR mode */ 730 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 731 PCI_CONF_BASE4); 732 } else { 733 /* normal 32-bit BAR mode */ 734 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 735 PCI_CONF_BASE2); 736 } 737 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 738 } else { 739 /* no I/O access for adapters prior to 82544 */ 740 hw->io_base = 0x0; 741 } 742 743 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 744 745 hw->mac.autoneg_failed = B_TRUE; 746 747 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 748 hw->phy.autoneg_wait_to_complete = B_FALSE; 749 750 /* Adaptive IFS related changes */ 751 hw->mac.adaptive_ifs = B_TRUE; 752 753 /* Enable phy init script for IGP phy of 82541/82547 */ 754 if ((hw->mac.type == e1000_82547) || 755 (hw->mac.type == e1000_82541) || 756 (hw->mac.type == e1000_82547_rev_2) || 757 (hw->mac.type == e1000_82541_rev_2)) 758 e1000_init_script_state_82541(hw, B_TRUE); 759 760 /* Enable the TTL workaround for 82541/82547 */ 761 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 762 763 #ifdef __sparc 764 Adapter->strip_crc = B_TRUE; 765 #else 766 Adapter->strip_crc = B_FALSE; 767 #endif 768 769 /* Get conf file properties */ 770 e1000g_get_conf(Adapter); 771 772 /* Get speed/duplex settings in conf file */ 773 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 774 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 775 e1000g_force_speed_duplex(Adapter); 776 777 /* Get Jumbo Frames settings in conf file */ 778 e1000g_get_max_frame_size(Adapter); 779 780 /* Set Rx/Tx buffer size */ 781 e1000g_set_bufsize(Adapter); 782 783 /* Master Latency Timer */ 784 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 785 786 /* copper options */ 787 if (hw->phy.media_type == e1000_media_type_copper) { 788 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 789 hw->phy.disable_polarity_correction = B_FALSE; 790 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 791 } 792 793 /* The initial link state should be "unknown" */ 794 Adapter->link_state = LINK_STATE_UNKNOWN; 795 796 /* Initialize rx parameters */ 797 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 798 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 799 800 /* Initialize tx parameters */ 801 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 802 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 803 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 804 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 805 806 /* Initialize rx parameters */ 807 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 808 809 return (DDI_SUCCESS); 810 } 811 812 static void 813 e1000g_set_bufsize(struct e1000g *Adapter) 814 { 815 struct e1000_mac_info *mac = &Adapter->shared.mac; 816 uint64_t rx_size; 817 uint64_t tx_size; 818 819 #ifdef __sparc 820 dev_info_t *devinfo = Adapter->dip; 821 ulong_t iommu_pagesize; 822 823 /* Get the system page size */ 824 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 825 iommu_pagesize = dvma_pagesize(devinfo); 826 if (iommu_pagesize != 0) { 827 if (Adapter->sys_page_sz == iommu_pagesize) { 828 if (iommu_pagesize > 0x4000) 829 Adapter->sys_page_sz = 0x4000; 830 } else { 831 if (Adapter->sys_page_sz > iommu_pagesize) 832 Adapter->sys_page_sz = iommu_pagesize; 833 } 834 } 835 if (Adapter->lso_enable) { 836 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 837 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 838 } else { 839 Adapter->dvma_page_num = Adapter->max_frame_size / 840 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 841 } 842 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 843 #endif 844 845 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 846 847 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 848 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 849 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 850 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 851 (rx_size <= FRAME_SIZE_UPTO_8K)) 852 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 853 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 854 (rx_size <= FRAME_SIZE_UPTO_16K)) 855 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 856 else 857 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 858 859 tx_size = Adapter->max_frame_size; 860 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 861 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 862 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 863 (tx_size <= FRAME_SIZE_UPTO_8K)) 864 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 865 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 866 (tx_size <= FRAME_SIZE_UPTO_16K)) 867 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 868 else 869 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 870 871 /* 872 * For Wiseman adapters we have an requirement of having receive 873 * buffers aligned at 256 byte boundary. Since Livengood does not 874 * require this and forcing it for all hardwares will have 875 * performance implications, I am making it applicable only for 876 * Wiseman and for Jumbo frames enabled mode as rest of the time, 877 * it is okay to have normal frames...but it does involve a 878 * potential risk where we may loose data if buffer is not 879 * aligned...so all wiseman boards to have 256 byte aligned 880 * buffers 881 */ 882 if (mac->type < e1000_82543) 883 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 884 else 885 Adapter->rx_buf_align = 1; 886 } 887 888 /* 889 * e1000g_detach - driver detach 890 * 891 * The detach() function is the complement of the attach routine. 892 * If cmd is set to DDI_DETACH, detach() is used to remove the 893 * state associated with a given instance of a device node 894 * prior to the removal of that instance from the system. 895 * 896 * The detach() function will be called once for each instance 897 * of the device for which there has been a successful attach() 898 * once there are no longer any opens on the device. 899 * 900 * Interrupts routine are disabled, All memory allocated by this 901 * driver are freed. 902 */ 903 static int 904 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 905 { 906 struct e1000g *Adapter; 907 boolean_t rx_drain; 908 909 switch (cmd) { 910 default: 911 return (DDI_FAILURE); 912 913 case DDI_SUSPEND: 914 return (e1000g_suspend(devinfo)); 915 916 case DDI_DETACH: 917 break; 918 } 919 920 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 921 if (Adapter == NULL) 922 return (DDI_FAILURE); 923 924 if (mac_unregister(Adapter->mh) != 0) { 925 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 926 return (DDI_FAILURE); 927 } 928 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 929 930 931 if (Adapter->chip_state != E1000G_STOP) 932 e1000g_stop(Adapter, B_TRUE); 933 934 rx_drain = e1000g_rx_drain(Adapter); 935 936 /* 937 * If e1000g_force_detach is enabled, driver detach is safe. 938 * We will let e1000g_free_priv_devi_node routine determine 939 * whether we need to free the priv_dip entry for current 940 * driver instance. 941 */ 942 if (e1000g_force_detach) { 943 e1000g_free_priv_devi_node(Adapter, rx_drain); 944 } else { 945 if (!rx_drain) 946 return (DDI_FAILURE); 947 } 948 949 e1000g_unattach(devinfo, Adapter); 950 951 return (DDI_SUCCESS); 952 } 953 954 /* 955 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 956 * 957 * If free_flag is true, that indicates the upper layer is not holding 958 * the rx buffers, we could free the priv_dip entry safely. 959 * 960 * Otherwise, we have to keep this entry even after driver detached, 961 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 962 * so that driver could free it while all of rx buffers are returned 963 * by upper layer later. 964 */ 965 static void 966 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 967 { 968 private_devi_list_t *devi_node, *devi_del; 969 970 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 971 ASSERT(e1000g_private_devi_list != NULL); 972 ASSERT(Adapter->priv_dip != NULL); 973 974 devi_node = e1000g_private_devi_list; 975 if (devi_node->priv_dip == Adapter->priv_dip) { 976 if (free_flag) { 977 e1000g_private_devi_list = 978 devi_node->next; 979 kmem_free(devi_node->priv_dip, 980 sizeof (struct dev_info)); 981 kmem_free(devi_node, 982 sizeof (private_devi_list_t)); 983 } else { 984 ASSERT(e1000g_mblks_pending != 0); 985 devi_node->flag = 986 E1000G_PRIV_DEVI_DETACH; 987 } 988 rw_exit(&e1000g_rx_detach_lock); 989 return; 990 } 991 992 devi_node = e1000g_private_devi_list; 993 while (devi_node->next != NULL) { 994 if (devi_node->next->priv_dip == Adapter->priv_dip) { 995 if (free_flag) { 996 devi_del = devi_node->next; 997 devi_node->next = devi_del->next; 998 kmem_free(devi_del->priv_dip, 999 sizeof (struct dev_info)); 1000 kmem_free(devi_del, 1001 sizeof (private_devi_list_t)); 1002 } else { 1003 ASSERT(e1000g_mblks_pending != 0); 1004 devi_node->next->flag = 1005 E1000G_PRIV_DEVI_DETACH; 1006 } 1007 break; 1008 } 1009 devi_node = devi_node->next; 1010 } 1011 rw_exit(&e1000g_rx_detach_lock); 1012 } 1013 1014 static void 1015 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1016 { 1017 int result; 1018 1019 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1020 (void) e1000g_disable_intrs(Adapter); 1021 } 1022 1023 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1024 (void) mac_unregister(Adapter->mh); 1025 } 1026 1027 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1028 (void) e1000g_rem_intrs(Adapter); 1029 } 1030 1031 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1032 (void) ddi_prop_remove_all(devinfo); 1033 } 1034 1035 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1036 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1037 } 1038 1039 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1040 stop_link_timer(Adapter); 1041 1042 mutex_enter(&e1000g_nvm_lock); 1043 result = e1000_reset_hw(&Adapter->shared); 1044 mutex_exit(&e1000g_nvm_lock); 1045 1046 if (result != E1000_SUCCESS) { 1047 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1048 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1049 } 1050 } 1051 1052 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1053 if (Adapter->osdep.reg_handle != NULL) 1054 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1055 if (Adapter->osdep.ich_flash_handle != NULL) 1056 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1057 } 1058 1059 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1060 if (Adapter->osdep.cfg_handle != NULL) 1061 pci_config_teardown(&Adapter->osdep.cfg_handle); 1062 } 1063 1064 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1065 e1000g_destroy_locks(Adapter); 1066 } 1067 1068 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1069 e1000g_fm_fini(Adapter); 1070 } 1071 1072 e1000_remove_device(&Adapter->shared); 1073 1074 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1075 1076 /* 1077 * Another hotplug spec requirement, 1078 * run ddi_set_driver_private(devinfo, null); 1079 */ 1080 ddi_set_driver_private(devinfo, NULL); 1081 } 1082 1083 static void 1084 e1000g_init_locks(struct e1000g *Adapter) 1085 { 1086 e1000g_tx_ring_t *tx_ring; 1087 e1000g_rx_ring_t *rx_ring; 1088 1089 rw_init(&Adapter->chip_lock, NULL, 1090 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1091 mutex_init(&Adapter->link_lock, NULL, 1092 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1093 mutex_init(&Adapter->watchdog_lock, NULL, 1094 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1095 1096 tx_ring = Adapter->tx_ring; 1097 1098 mutex_init(&tx_ring->tx_lock, NULL, 1099 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1100 mutex_init(&tx_ring->usedlist_lock, NULL, 1101 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1102 mutex_init(&tx_ring->freelist_lock, NULL, 1103 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1104 1105 rx_ring = Adapter->rx_ring; 1106 1107 mutex_init(&rx_ring->rx_lock, NULL, 1108 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1109 mutex_init(&rx_ring->freelist_lock, NULL, 1110 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1111 } 1112 1113 static void 1114 e1000g_destroy_locks(struct e1000g *Adapter) 1115 { 1116 e1000g_tx_ring_t *tx_ring; 1117 e1000g_rx_ring_t *rx_ring; 1118 1119 tx_ring = Adapter->tx_ring; 1120 mutex_destroy(&tx_ring->tx_lock); 1121 mutex_destroy(&tx_ring->usedlist_lock); 1122 mutex_destroy(&tx_ring->freelist_lock); 1123 1124 rx_ring = Adapter->rx_ring; 1125 mutex_destroy(&rx_ring->rx_lock); 1126 mutex_destroy(&rx_ring->freelist_lock); 1127 1128 mutex_destroy(&Adapter->link_lock); 1129 mutex_destroy(&Adapter->watchdog_lock); 1130 rw_destroy(&Adapter->chip_lock); 1131 } 1132 1133 static int 1134 e1000g_resume(dev_info_t *devinfo) 1135 { 1136 struct e1000g *Adapter; 1137 1138 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1139 if (Adapter == NULL) 1140 return (DDI_FAILURE); 1141 1142 if (e1000g_start(Adapter, B_TRUE)) 1143 return (DDI_FAILURE); 1144 1145 return (DDI_SUCCESS); 1146 } 1147 1148 static int 1149 e1000g_suspend(dev_info_t *devinfo) 1150 { 1151 struct e1000g *Adapter; 1152 1153 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1154 if (Adapter == NULL) 1155 return (DDI_FAILURE); 1156 1157 e1000g_stop(Adapter, B_TRUE); 1158 1159 return (DDI_SUCCESS); 1160 } 1161 1162 static int 1163 e1000g_init(struct e1000g *Adapter) 1164 { 1165 uint32_t pba; 1166 uint32_t high_water; 1167 struct e1000_hw *hw; 1168 clock_t link_timeout; 1169 int result; 1170 1171 hw = &Adapter->shared; 1172 1173 rw_enter(&Adapter->chip_lock, RW_WRITER); 1174 1175 /* 1176 * reset to put the hardware in a known state 1177 * before we try to do anything with the eeprom 1178 */ 1179 mutex_enter(&e1000g_nvm_lock); 1180 result = e1000_reset_hw(hw); 1181 mutex_exit(&e1000g_nvm_lock); 1182 1183 if (result != E1000_SUCCESS) { 1184 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1185 goto init_fail; 1186 } 1187 1188 mutex_enter(&e1000g_nvm_lock); 1189 result = e1000_validate_nvm_checksum(hw); 1190 if (result < E1000_SUCCESS) { 1191 /* 1192 * Some PCI-E parts fail the first check due to 1193 * the link being in sleep state. Call it again, 1194 * if it fails a second time its a real issue. 1195 */ 1196 result = e1000_validate_nvm_checksum(hw); 1197 } 1198 mutex_exit(&e1000g_nvm_lock); 1199 1200 if (result < E1000_SUCCESS) { 1201 e1000g_log(Adapter, CE_WARN, 1202 "Invalid NVM checksum. Please contact " 1203 "the vendor to update the NVM."); 1204 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1205 goto init_fail; 1206 } 1207 1208 result = 0; 1209 #ifdef __sparc 1210 /* 1211 * First, we try to get the local ethernet address from OBP. If 1212 * failed, then we get it from the EEPROM of NIC card. 1213 */ 1214 result = e1000g_find_mac_address(Adapter); 1215 #endif 1216 /* Get the local ethernet address. */ 1217 if (!result) { 1218 mutex_enter(&e1000g_nvm_lock); 1219 result = e1000_read_mac_addr(hw); 1220 mutex_exit(&e1000g_nvm_lock); 1221 } 1222 1223 if (result < E1000_SUCCESS) { 1224 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1225 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1226 goto init_fail; 1227 } 1228 1229 /* check for valid mac address */ 1230 if (!is_valid_mac_addr(hw->mac.addr)) { 1231 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1232 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1233 goto init_fail; 1234 } 1235 1236 /* Set LAA state for 82571 chipset */ 1237 e1000_set_laa_state_82571(hw, B_TRUE); 1238 1239 /* Master Latency Timer implementation */ 1240 if (Adapter->master_latency_timer) { 1241 pci_config_put8(Adapter->osdep.cfg_handle, 1242 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1243 } 1244 1245 if (hw->mac.type < e1000_82547) { 1246 /* 1247 * Total FIFO is 64K 1248 */ 1249 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1250 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1251 else 1252 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1253 } else if ((hw->mac.type == e1000_82571) || 1254 (hw->mac.type == e1000_82572) || 1255 (hw->mac.type == e1000_80003es2lan)) { 1256 /* 1257 * Total FIFO is 48K 1258 */ 1259 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1260 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1261 else 1262 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1263 } else if (hw->mac.type == e1000_82573) { 1264 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1265 } else if (hw->mac.type == e1000_82574) { 1266 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1267 pba = E1000_READ_REG(hw, E1000_PBA); 1268 } else if (hw->mac.type == e1000_ich8lan) { 1269 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1270 } else if (hw->mac.type == e1000_ich9lan) { 1271 pba = E1000_PBA_10K; 1272 } else if (hw->mac.type == e1000_ich10lan) { 1273 pba = E1000_PBA_10K; 1274 } else { 1275 /* 1276 * Total FIFO is 40K 1277 */ 1278 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1279 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1280 else 1281 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1282 } 1283 E1000_WRITE_REG(hw, E1000_PBA, pba); 1284 1285 /* 1286 * These parameters set thresholds for the adapter's generation(Tx) 1287 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1288 * settings. Flow control is enabled or disabled in the configuration 1289 * file. 1290 * High-water mark is set down from the top of the rx fifo (not 1291 * sensitive to max_frame_size) and low-water is set just below 1292 * high-water mark. 1293 * The high water mark must be low enough to fit one full frame above 1294 * it in the rx FIFO. Should be the lower of: 1295 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1296 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1297 * Rx FIFO size minus one full frame. 1298 */ 1299 high_water = min(((pba << 10) * 9 / 10), 1300 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan || 1301 hw->mac.type == e1000_ich10lan) ? 1302 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1303 ((pba << 10) - Adapter->max_frame_size))); 1304 1305 hw->fc.high_water = high_water & 0xFFF8; 1306 hw->fc.low_water = hw->fc.high_water - 8; 1307 1308 if (hw->mac.type == e1000_80003es2lan) 1309 hw->fc.pause_time = 0xFFFF; 1310 else 1311 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1312 hw->fc.send_xon = B_TRUE; 1313 1314 /* 1315 * Reset the adapter hardware the second time. 1316 */ 1317 mutex_enter(&e1000g_nvm_lock); 1318 result = e1000_reset_hw(hw); 1319 mutex_exit(&e1000g_nvm_lock); 1320 1321 if (result != E1000_SUCCESS) { 1322 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1323 goto init_fail; 1324 } 1325 1326 /* disable wakeup control by default */ 1327 if (hw->mac.type >= e1000_82544) 1328 E1000_WRITE_REG(hw, E1000_WUC, 0); 1329 1330 /* MWI setup */ 1331 e1000_pci_set_mwi(hw); 1332 1333 /* 1334 * Configure/Initialize hardware 1335 */ 1336 mutex_enter(&e1000g_nvm_lock); 1337 result = e1000_init_hw(hw); 1338 mutex_exit(&e1000g_nvm_lock); 1339 1340 if (result < E1000_SUCCESS) { 1341 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1342 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1343 goto init_fail; 1344 } 1345 1346 /* 1347 * Restore LED settings to the default from EEPROM 1348 * to meet the standard for Sun platforms. 1349 */ 1350 (void) e1000_cleanup_led(hw); 1351 1352 /* Disable Smart Power Down */ 1353 phy_spd_state(hw, B_FALSE); 1354 1355 /* Make sure driver has control */ 1356 e1000g_get_driver_control(hw); 1357 1358 /* 1359 * Initialize unicast addresses. 1360 */ 1361 e1000g_init_unicst(Adapter); 1362 1363 /* 1364 * Setup and initialize the mctable structures. After this routine 1365 * completes Multicast table will be set 1366 */ 1367 e1000g_setup_multicast(Adapter); 1368 msec_delay(5); 1369 1370 /* 1371 * Implement Adaptive IFS 1372 */ 1373 e1000_reset_adaptive(hw); 1374 1375 /* Setup Interrupt Throttling Register */ 1376 if (hw->mac.type >= e1000_82540) { 1377 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1378 } else 1379 Adapter->intr_adaptive = B_FALSE; 1380 1381 /* Start the timer for link setup */ 1382 if (hw->mac.autoneg) 1383 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1384 else 1385 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1386 1387 mutex_enter(&Adapter->link_lock); 1388 if (hw->phy.autoneg_wait_to_complete) { 1389 Adapter->link_complete = B_TRUE; 1390 } else { 1391 Adapter->link_complete = B_FALSE; 1392 Adapter->link_tid = timeout(e1000g_link_timer, 1393 (void *)Adapter, link_timeout); 1394 } 1395 mutex_exit(&Adapter->link_lock); 1396 1397 /* Enable PCI-Ex master */ 1398 if (hw->bus.type == e1000_bus_type_pci_express) { 1399 e1000_enable_pciex_master(hw); 1400 } 1401 1402 /* Save the state of the phy */ 1403 e1000g_get_phy_state(Adapter); 1404 1405 e1000g_param_sync(Adapter); 1406 1407 Adapter->init_count++; 1408 1409 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1410 goto init_fail; 1411 } 1412 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1413 goto init_fail; 1414 } 1415 1416 rw_exit(&Adapter->chip_lock); 1417 1418 return (DDI_SUCCESS); 1419 1420 init_fail: 1421 rw_exit(&Adapter->chip_lock); 1422 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1423 return (DDI_FAILURE); 1424 } 1425 1426 /* 1427 * Check if the link is up 1428 */ 1429 static boolean_t 1430 e1000g_link_up(struct e1000g *Adapter) 1431 { 1432 struct e1000_hw *hw; 1433 boolean_t link_up; 1434 1435 hw = &Adapter->shared; 1436 1437 (void) e1000_check_for_link(hw); 1438 1439 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1440 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1441 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1442 (hw->mac.serdes_has_link))) { 1443 link_up = B_TRUE; 1444 } else { 1445 link_up = B_FALSE; 1446 } 1447 1448 return (link_up); 1449 } 1450 1451 static void 1452 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1453 { 1454 struct iocblk *iocp; 1455 struct e1000g *e1000gp; 1456 enum ioc_reply status; 1457 1458 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1459 iocp->ioc_error = 0; 1460 e1000gp = (struct e1000g *)arg; 1461 1462 ASSERT(e1000gp); 1463 if (e1000gp == NULL) { 1464 miocnak(q, mp, 0, EINVAL); 1465 return; 1466 } 1467 1468 switch (iocp->ioc_cmd) { 1469 1470 case LB_GET_INFO_SIZE: 1471 case LB_GET_INFO: 1472 case LB_GET_MODE: 1473 case LB_SET_MODE: 1474 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1475 break; 1476 1477 1478 #ifdef E1000G_DEBUG 1479 case E1000G_IOC_REG_PEEK: 1480 case E1000G_IOC_REG_POKE: 1481 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1482 break; 1483 case E1000G_IOC_CHIP_RESET: 1484 e1000gp->reset_count++; 1485 if (e1000g_reset_adapter(e1000gp)) 1486 status = IOC_ACK; 1487 else 1488 status = IOC_INVAL; 1489 break; 1490 #endif 1491 default: 1492 status = IOC_INVAL; 1493 break; 1494 } 1495 1496 /* 1497 * Decide how to reply 1498 */ 1499 switch (status) { 1500 default: 1501 case IOC_INVAL: 1502 /* 1503 * Error, reply with a NAK and EINVAL or the specified error 1504 */ 1505 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1506 EINVAL : iocp->ioc_error); 1507 break; 1508 1509 case IOC_DONE: 1510 /* 1511 * OK, reply already sent 1512 */ 1513 break; 1514 1515 case IOC_ACK: 1516 /* 1517 * OK, reply with an ACK 1518 */ 1519 miocack(q, mp, 0, 0); 1520 break; 1521 1522 case IOC_REPLY: 1523 /* 1524 * OK, send prepared reply as ACK or NAK 1525 */ 1526 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1527 M_IOCACK : M_IOCNAK; 1528 qreply(q, mp); 1529 break; 1530 } 1531 } 1532 1533 static int 1534 e1000g_m_start(void *arg) 1535 { 1536 struct e1000g *Adapter = (struct e1000g *)arg; 1537 1538 return (e1000g_start(Adapter, B_TRUE)); 1539 } 1540 1541 static int 1542 e1000g_start(struct e1000g *Adapter, boolean_t global) 1543 { 1544 if (global) { 1545 /* Allocate dma resources for descriptors and buffers */ 1546 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1547 e1000g_log(Adapter, CE_WARN, 1548 "Alloc DMA resources failed"); 1549 return (ENOTACTIVE); 1550 } 1551 Adapter->rx_buffer_setup = B_FALSE; 1552 } 1553 1554 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1555 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1556 e1000g_log(Adapter, CE_WARN, 1557 "Adapter initialization failed"); 1558 if (global) 1559 e1000g_release_dma_resources(Adapter); 1560 return (ENOTACTIVE); 1561 } 1562 } 1563 1564 rw_enter(&Adapter->chip_lock, RW_WRITER); 1565 1566 /* Setup and initialize the transmit structures */ 1567 e1000g_tx_setup(Adapter); 1568 msec_delay(5); 1569 1570 /* Setup and initialize the receive structures */ 1571 e1000g_rx_setup(Adapter); 1572 msec_delay(5); 1573 1574 e1000g_mask_interrupt(Adapter); 1575 1576 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1577 rw_exit(&Adapter->chip_lock); 1578 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1579 return (ENOTACTIVE); 1580 } 1581 1582 Adapter->chip_state = E1000G_START; 1583 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1584 1585 rw_exit(&Adapter->chip_lock); 1586 1587 /* Enable and start the watchdog timer */ 1588 enable_watchdog_timer(Adapter); 1589 1590 return (0); 1591 } 1592 1593 static void 1594 e1000g_m_stop(void *arg) 1595 { 1596 struct e1000g *Adapter = (struct e1000g *)arg; 1597 1598 e1000g_stop(Adapter, B_TRUE); 1599 } 1600 1601 static void 1602 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1603 { 1604 int result; 1605 1606 /* Set stop flags */ 1607 rw_enter(&Adapter->chip_lock, RW_WRITER); 1608 1609 Adapter->chip_state = E1000G_STOP; 1610 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1611 1612 rw_exit(&Adapter->chip_lock); 1613 1614 /* Drain tx sessions */ 1615 (void) e1000g_tx_drain(Adapter); 1616 1617 /* Disable and stop all the timers */ 1618 disable_watchdog_timer(Adapter); 1619 stop_link_timer(Adapter); 1620 stop_82547_timer(Adapter->tx_ring); 1621 1622 /* Stop the chip and release pending resources */ 1623 rw_enter(&Adapter->chip_lock, RW_WRITER); 1624 1625 /* Tell firmware driver is no longer in control */ 1626 e1000g_release_driver_control(&Adapter->shared); 1627 1628 e1000g_clear_all_interrupts(Adapter); 1629 1630 mutex_enter(&e1000g_nvm_lock); 1631 result = e1000_reset_hw(&Adapter->shared); 1632 mutex_exit(&e1000g_nvm_lock); 1633 1634 if (result != E1000_SUCCESS) { 1635 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1636 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1637 } 1638 1639 /* Release resources still held by the TX descriptors */ 1640 e1000g_tx_clean(Adapter); 1641 1642 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1643 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1644 1645 /* Clean the pending rx jumbo packet fragment */ 1646 e1000g_rx_clean(Adapter); 1647 1648 rw_exit(&Adapter->chip_lock); 1649 1650 if (global) 1651 e1000g_release_dma_resources(Adapter); 1652 } 1653 1654 static void 1655 e1000g_rx_clean(struct e1000g *Adapter) 1656 { 1657 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1658 1659 if (rx_ring->rx_mblk != NULL) { 1660 freemsg(rx_ring->rx_mblk); 1661 rx_ring->rx_mblk = NULL; 1662 rx_ring->rx_mblk_tail = NULL; 1663 rx_ring->rx_mblk_len = 0; 1664 } 1665 } 1666 1667 static void 1668 e1000g_tx_clean(struct e1000g *Adapter) 1669 { 1670 e1000g_tx_ring_t *tx_ring; 1671 p_tx_sw_packet_t packet; 1672 mblk_t *mp; 1673 mblk_t *nmp; 1674 uint32_t packet_count; 1675 1676 tx_ring = Adapter->tx_ring; 1677 1678 /* 1679 * Here we don't need to protect the lists using 1680 * the usedlist_lock and freelist_lock, for they 1681 * have been protected by the chip_lock. 1682 */ 1683 mp = NULL; 1684 nmp = NULL; 1685 packet_count = 0; 1686 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1687 while (packet != NULL) { 1688 if (packet->mp != NULL) { 1689 /* Assemble the message chain */ 1690 if (mp == NULL) { 1691 mp = packet->mp; 1692 nmp = packet->mp; 1693 } else { 1694 nmp->b_next = packet->mp; 1695 nmp = packet->mp; 1696 } 1697 /* Disconnect the message from the sw packet */ 1698 packet->mp = NULL; 1699 } 1700 1701 e1000g_free_tx_swpkt(packet); 1702 packet_count++; 1703 1704 packet = (p_tx_sw_packet_t) 1705 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1706 } 1707 1708 if (mp != NULL) 1709 freemsgchain(mp); 1710 1711 if (packet_count > 0) { 1712 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1713 QUEUE_INIT_LIST(&tx_ring->used_list); 1714 1715 /* Setup TX descriptor pointers */ 1716 tx_ring->tbd_next = tx_ring->tbd_first; 1717 tx_ring->tbd_oldest = tx_ring->tbd_first; 1718 1719 /* Setup our HW Tx Head & Tail descriptor pointers */ 1720 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1721 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1722 } 1723 } 1724 1725 static boolean_t 1726 e1000g_tx_drain(struct e1000g *Adapter) 1727 { 1728 int i; 1729 boolean_t done; 1730 e1000g_tx_ring_t *tx_ring; 1731 1732 tx_ring = Adapter->tx_ring; 1733 1734 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1735 for (i = 0; i < TX_DRAIN_TIME; i++) { 1736 mutex_enter(&tx_ring->usedlist_lock); 1737 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1738 mutex_exit(&tx_ring->usedlist_lock); 1739 1740 if (done) 1741 break; 1742 1743 msec_delay(1); 1744 } 1745 1746 return (done); 1747 } 1748 1749 static boolean_t 1750 e1000g_rx_drain(struct e1000g *Adapter) 1751 { 1752 e1000g_rx_ring_t *rx_ring; 1753 p_rx_sw_packet_t packet; 1754 boolean_t done; 1755 1756 rx_ring = Adapter->rx_ring; 1757 done = B_TRUE; 1758 1759 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1760 1761 while (rx_ring->pending_list != NULL) { 1762 packet = rx_ring->pending_list; 1763 rx_ring->pending_list = 1764 rx_ring->pending_list->next; 1765 1766 if (packet->flag == E1000G_RX_SW_STOP) { 1767 packet->flag = E1000G_RX_SW_DETACH; 1768 done = B_FALSE; 1769 } else { 1770 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1771 ASSERT(packet->mp == NULL); 1772 e1000g_free_rx_sw_packet(packet); 1773 } 1774 } 1775 1776 rw_exit(&e1000g_rx_detach_lock); 1777 1778 return (done); 1779 } 1780 1781 static boolean_t 1782 e1000g_reset_adapter(struct e1000g *Adapter) 1783 { 1784 e1000g_stop(Adapter, B_FALSE); 1785 1786 if (e1000g_start(Adapter, B_FALSE)) { 1787 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1788 return (B_FALSE); 1789 } 1790 1791 return (B_TRUE); 1792 } 1793 1794 boolean_t 1795 e1000g_global_reset(struct e1000g *Adapter) 1796 { 1797 e1000g_stop(Adapter, B_TRUE); 1798 1799 Adapter->init_count = 0; 1800 1801 if (e1000g_start(Adapter, B_TRUE)) { 1802 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1803 return (B_FALSE); 1804 } 1805 1806 return (B_TRUE); 1807 } 1808 1809 /* 1810 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1811 * 1812 * This interrupt service routine is for PCI-Express adapters. 1813 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1814 * bit is set. 1815 */ 1816 static uint_t 1817 e1000g_intr_pciexpress(caddr_t arg) 1818 { 1819 struct e1000g *Adapter; 1820 uint32_t icr; 1821 1822 Adapter = (struct e1000g *)(uintptr_t)arg; 1823 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1824 1825 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1826 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1827 1828 if (icr & E1000_ICR_INT_ASSERTED) { 1829 /* 1830 * E1000_ICR_INT_ASSERTED bit was set: 1831 * Read(Clear) the ICR, claim this interrupt, 1832 * look for work to do. 1833 */ 1834 e1000g_intr_work(Adapter, icr); 1835 return (DDI_INTR_CLAIMED); 1836 } else { 1837 /* 1838 * E1000_ICR_INT_ASSERTED bit was not set: 1839 * Don't claim this interrupt, return immediately. 1840 */ 1841 return (DDI_INTR_UNCLAIMED); 1842 } 1843 } 1844 1845 /* 1846 * e1000g_intr - ISR for PCI/PCI-X chipsets 1847 * 1848 * This interrupt service routine is for PCI/PCI-X adapters. 1849 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1850 * bit is set or not. 1851 */ 1852 static uint_t 1853 e1000g_intr(caddr_t arg) 1854 { 1855 struct e1000g *Adapter; 1856 uint32_t icr; 1857 1858 Adapter = (struct e1000g *)(uintptr_t)arg; 1859 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1860 1861 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1862 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1863 1864 if (icr) { 1865 /* 1866 * Any bit was set in ICR: 1867 * Read(Clear) the ICR, claim this interrupt, 1868 * look for work to do. 1869 */ 1870 e1000g_intr_work(Adapter, icr); 1871 return (DDI_INTR_CLAIMED); 1872 } else { 1873 /* 1874 * No bit was set in ICR: 1875 * Don't claim this interrupt, return immediately. 1876 */ 1877 return (DDI_INTR_UNCLAIMED); 1878 } 1879 } 1880 1881 /* 1882 * e1000g_intr_work - actual processing of ISR 1883 * 1884 * Read(clear) the ICR contents and call appropriate interrupt 1885 * processing routines. 1886 */ 1887 static void 1888 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1889 { 1890 struct e1000_hw *hw; 1891 hw = &Adapter->shared; 1892 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1893 uint32_t itr; 1894 1895 Adapter->rx_pkt_cnt = 0; 1896 Adapter->tx_pkt_cnt = 0; 1897 1898 rw_enter(&Adapter->chip_lock, RW_READER); 1899 /* 1900 * Here we need to check the "chip_state" flag within the chip_lock to 1901 * ensure the receive routine will not execute when the adapter is 1902 * being reset. 1903 */ 1904 if (Adapter->chip_state != E1000G_START) { 1905 rw_exit(&Adapter->chip_lock); 1906 return; 1907 } 1908 1909 if (icr & E1000_ICR_RXT0) { 1910 mblk_t *mp; 1911 1912 mutex_enter(&Adapter->rx_ring->rx_lock); 1913 mp = e1000g_receive(Adapter); 1914 mutex_exit(&Adapter->rx_ring->rx_lock); 1915 1916 rw_exit(&Adapter->chip_lock); 1917 1918 if (mp != NULL) 1919 mac_rx(Adapter->mh, Adapter->mrh, mp); 1920 } else 1921 rw_exit(&Adapter->chip_lock); 1922 1923 if (icr & E1000_ICR_TXDW) { 1924 if (!Adapter->tx_intr_enable) 1925 e1000g_clear_tx_interrupt(Adapter); 1926 1927 /* Recycle the tx descriptors */ 1928 rw_enter(&Adapter->chip_lock, RW_READER); 1929 (void) e1000g_recycle(tx_ring); 1930 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1931 rw_exit(&Adapter->chip_lock); 1932 1933 /* Schedule the re-transmit */ 1934 if (tx_ring->resched_needed && 1935 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1936 tx_ring->resched_needed = B_FALSE; 1937 mac_tx_update(Adapter->mh); 1938 E1000G_STAT(tx_ring->stat_reschedule); 1939 } 1940 } 1941 1942 if (Adapter->intr_adaptive) { 1943 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1944 Adapter->intr_throttling_rate); 1945 if (itr) { 1946 E1000_WRITE_REG(hw, E1000_ITR, itr); 1947 Adapter->intr_throttling_rate = itr; 1948 } 1949 } 1950 1951 /* 1952 * The Receive Sequence errors RXSEQ and the link status change LSC 1953 * are checked to detect that the cable has been pulled out. For 1954 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1955 * are an indication that cable is not connected. 1956 */ 1957 if ((icr & E1000_ICR_RXSEQ) || 1958 (icr & E1000_ICR_LSC) || 1959 (icr & E1000_ICR_GPI_EN1)) { 1960 boolean_t link_changed; 1961 timeout_id_t tid = 0; 1962 1963 stop_watchdog_timer(Adapter); 1964 1965 rw_enter(&Adapter->chip_lock, RW_WRITER); 1966 1967 /* 1968 * Because we got a link-status-change interrupt, force 1969 * e1000_check_for_link() to look at phy 1970 */ 1971 Adapter->shared.mac.get_link_status = B_TRUE; 1972 1973 /* e1000g_link_check takes care of link status change */ 1974 link_changed = e1000g_link_check(Adapter); 1975 1976 /* Get new phy state */ 1977 e1000g_get_phy_state(Adapter); 1978 1979 /* 1980 * If the link timer has not timed out, we'll not notify 1981 * the upper layer with any link state until the link is up. 1982 */ 1983 if (link_changed && !Adapter->link_complete) { 1984 if (Adapter->link_state == LINK_STATE_UP) { 1985 mutex_enter(&Adapter->link_lock); 1986 Adapter->link_complete = B_TRUE; 1987 tid = Adapter->link_tid; 1988 Adapter->link_tid = 0; 1989 mutex_exit(&Adapter->link_lock); 1990 } else { 1991 link_changed = B_FALSE; 1992 } 1993 } 1994 rw_exit(&Adapter->chip_lock); 1995 1996 if (link_changed) { 1997 if (tid != 0) 1998 (void) untimeout(tid); 1999 2000 /* 2001 * Workaround for esb2. Data stuck in fifo on a link 2002 * down event. Stop receiver here and reset in watchdog. 2003 */ 2004 if ((Adapter->link_state == LINK_STATE_DOWN) && 2005 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2006 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2007 E1000_WRITE_REG(hw, E1000_RCTL, 2008 rctl & ~E1000_RCTL_EN); 2009 e1000g_log(Adapter, CE_WARN, 2010 "ESB2 receiver disabled"); 2011 Adapter->esb2_workaround = B_TRUE; 2012 } 2013 2014 mac_link_update(Adapter->mh, Adapter->link_state); 2015 } 2016 2017 start_watchdog_timer(Adapter); 2018 } 2019 } 2020 2021 static uint32_t 2022 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2023 { 2024 uint32_t new_itr; 2025 2026 /* 2027 * Determine a propper itr according to rx/tx packet count 2028 * per interrupt, the value of itr are based on document 2029 * and testing. 2030 */ 2031 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2032 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2033 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2034 goto itr_done; 2035 } 2036 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2037 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2038 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2039 goto itr_done; 2040 } 2041 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2042 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2043 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2044 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2045 } else 2046 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2047 2048 itr_done: 2049 if (cur_itr == new_itr) 2050 return (0); 2051 else 2052 return (new_itr); 2053 } 2054 2055 static void 2056 e1000g_init_unicst(struct e1000g *Adapter) 2057 { 2058 struct e1000_hw *hw; 2059 int slot; 2060 2061 hw = &Adapter->shared; 2062 2063 if (!Adapter->unicst_init) { 2064 /* Initialize the multiple unicast addresses */ 2065 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2066 2067 if ((hw->mac.type == e1000_82571) && 2068 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2069 Adapter->unicst_total--; 2070 2071 Adapter->unicst_avail = Adapter->unicst_total - 1; 2072 2073 /* Store the default mac address */ 2074 e1000_rar_set(hw, hw->mac.addr, 0); 2075 if ((hw->mac.type == e1000_82571) && 2076 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2077 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2078 2079 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2080 ETHERADDRL); 2081 Adapter->unicst_addr[0].mac.set = 1; 2082 2083 for (slot = 1; slot < Adapter->unicst_total; slot++) 2084 Adapter->unicst_addr[slot].mac.set = 0; 2085 2086 Adapter->unicst_init = B_TRUE; 2087 } else { 2088 /* Recover the default mac address */ 2089 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2090 ETHERADDRL); 2091 2092 /* Store the default mac address */ 2093 e1000_rar_set(hw, hw->mac.addr, 0); 2094 if ((hw->mac.type == e1000_82571) && 2095 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2096 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2097 2098 /* Re-configure the RAR registers */ 2099 for (slot = 1; slot < Adapter->unicst_total; slot++) 2100 e1000_rar_set(hw, 2101 Adapter->unicst_addr[slot].mac.addr, slot); 2102 } 2103 2104 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2105 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2106 } 2107 2108 static int 2109 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2110 { 2111 struct e1000g *Adapter; 2112 2113 Adapter = (struct e1000g *)arg; 2114 2115 /* Store the default MAC address */ 2116 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2117 2118 /* Set MAC address in address slot 0, which is the default address */ 2119 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2120 } 2121 2122 static int 2123 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2124 mac_addr_slot_t slot) 2125 { 2126 struct e1000_hw *hw; 2127 2128 hw = &Adapter->shared; 2129 2130 rw_enter(&Adapter->chip_lock, RW_WRITER); 2131 2132 /* 2133 * The first revision of Wiseman silicon (rev 2.0) has an errata 2134 * that requires the receiver to be in reset when any of the 2135 * receive address registers (RAR regs) are accessed. The first 2136 * rev of Wiseman silicon also requires MWI to be disabled when 2137 * a global reset or a receive reset is issued. So before we 2138 * initialize the RARs, we check the rev of the Wiseman controller 2139 * and work around any necessary HW errata. 2140 */ 2141 if ((hw->mac.type == e1000_82542) && 2142 (hw->revision_id == E1000_REVISION_2)) { 2143 e1000_pci_clear_mwi(hw); 2144 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2145 msec_delay(5); 2146 } 2147 2148 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2149 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2150 2151 if (slot == 0) { 2152 if ((hw->mac.type == e1000_82571) && 2153 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2154 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2155 } 2156 2157 /* 2158 * If we are using Wiseman rev 2.0 silicon, we will have previously 2159 * put the receive in reset, and disabled MWI, to work around some 2160 * HW errata. Now we should take the receiver out of reset, and 2161 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2162 */ 2163 if ((hw->mac.type == e1000_82542) && 2164 (hw->revision_id == E1000_REVISION_2)) { 2165 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2166 msec_delay(1); 2167 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2168 e1000_pci_set_mwi(hw); 2169 e1000g_rx_setup(Adapter); 2170 } 2171 2172 rw_exit(&Adapter->chip_lock); 2173 2174 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2175 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2176 return (EIO); 2177 } 2178 2179 return (0); 2180 } 2181 2182 /* 2183 * e1000g_m_unicst_add() - will find an unused address slot, set the 2184 * address value to the one specified, reserve that slot and enable 2185 * the NIC to start filtering on the new MAC address. 2186 * Returns 0 on success. 2187 */ 2188 static int 2189 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2190 { 2191 struct e1000g *Adapter = (struct e1000g *)arg; 2192 mac_addr_slot_t slot; 2193 int err; 2194 2195 if (mac_unicst_verify(Adapter->mh, 2196 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2197 return (EINVAL); 2198 2199 rw_enter(&Adapter->chip_lock, RW_WRITER); 2200 if (Adapter->unicst_avail == 0) { 2201 /* no slots available */ 2202 rw_exit(&Adapter->chip_lock); 2203 return (ENOSPC); 2204 } 2205 2206 /* 2207 * Primary/default address is in slot 0. The next addresses 2208 * are the multiple MAC addresses. So multiple MAC address 0 2209 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2210 * MAC address resides in slot 1. 2211 */ 2212 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2213 if (Adapter->unicst_addr[slot].mac.set == 0) { 2214 Adapter->unicst_addr[slot].mac.set = 1; 2215 break; 2216 } 2217 } 2218 2219 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2220 2221 Adapter->unicst_avail--; 2222 rw_exit(&Adapter->chip_lock); 2223 2224 maddr->mma_slot = slot; 2225 2226 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2227 rw_enter(&Adapter->chip_lock, RW_WRITER); 2228 Adapter->unicst_addr[slot].mac.set = 0; 2229 Adapter->unicst_avail++; 2230 rw_exit(&Adapter->chip_lock); 2231 } 2232 2233 return (err); 2234 } 2235 2236 /* 2237 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2238 * call to e1000g_m_unicst_add(). The slot number that was returned in 2239 * e1000g_m_unicst_add() is passed in the call to remove the address. 2240 * Returns 0 on success. 2241 */ 2242 static int 2243 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2244 { 2245 struct e1000g *Adapter = (struct e1000g *)arg; 2246 int err; 2247 2248 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2249 return (EINVAL); 2250 2251 rw_enter(&Adapter->chip_lock, RW_WRITER); 2252 if (Adapter->unicst_addr[slot].mac.set == 1) { 2253 Adapter->unicst_addr[slot].mac.set = 0; 2254 Adapter->unicst_avail++; 2255 rw_exit(&Adapter->chip_lock); 2256 2257 /* Copy the default address to the passed slot */ 2258 if ((err = e1000g_unicst_set(Adapter, 2259 Adapter->unicst_addr[0].mac.addr, slot)) != 0) { 2260 rw_enter(&Adapter->chip_lock, RW_WRITER); 2261 Adapter->unicst_addr[slot].mac.set = 1; 2262 Adapter->unicst_avail--; 2263 rw_exit(&Adapter->chip_lock); 2264 } 2265 return (err); 2266 } 2267 rw_exit(&Adapter->chip_lock); 2268 2269 return (EINVAL); 2270 } 2271 2272 /* 2273 * e1000g_m_unicst_modify() - modifies the value of an address that 2274 * has been added by e1000g_m_unicst_add(). The new address, address 2275 * length and the slot number that was returned in the call to add 2276 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2277 * set to 0. Returns 0 on success. 2278 */ 2279 static int 2280 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2281 { 2282 struct e1000g *Adapter = (struct e1000g *)arg; 2283 mac_addr_slot_t slot; 2284 2285 if (mac_unicst_verify(Adapter->mh, 2286 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2287 return (EINVAL); 2288 2289 slot = maddr->mma_slot; 2290 2291 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2292 return (EINVAL); 2293 2294 rw_enter(&Adapter->chip_lock, RW_WRITER); 2295 if (Adapter->unicst_addr[slot].mac.set == 1) { 2296 rw_exit(&Adapter->chip_lock); 2297 2298 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2299 } 2300 rw_exit(&Adapter->chip_lock); 2301 2302 return (EINVAL); 2303 } 2304 2305 /* 2306 * e1000g_m_unicst_get() - will get the MAC address and all other 2307 * information related to the address slot passed in mac_multi_addr_t. 2308 * mma_flags should be set to 0 in the call. 2309 * On return, mma_flags can take the following values: 2310 * 1) MMAC_SLOT_UNUSED 2311 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2312 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2313 * 4) MMAC_SLOT_USED 2314 */ 2315 static int 2316 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2317 { 2318 struct e1000g *Adapter = (struct e1000g *)arg; 2319 mac_addr_slot_t slot; 2320 2321 slot = maddr->mma_slot; 2322 2323 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2324 return (EINVAL); 2325 2326 rw_enter(&Adapter->chip_lock, RW_WRITER); 2327 if (Adapter->unicst_addr[slot].mac.set == 1) { 2328 bcopy(Adapter->unicst_addr[slot].mac.addr, 2329 maddr->mma_addr, ETHERADDRL); 2330 maddr->mma_flags = MMAC_SLOT_USED; 2331 } else { 2332 maddr->mma_flags = MMAC_SLOT_UNUSED; 2333 } 2334 rw_exit(&Adapter->chip_lock); 2335 2336 return (0); 2337 } 2338 2339 static int 2340 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2341 { 2342 struct e1000_hw *hw = &Adapter->shared; 2343 int res = 0; 2344 2345 rw_enter(&Adapter->chip_lock, RW_WRITER); 2346 2347 if ((multiaddr[0] & 01) == 0) { 2348 res = EINVAL; 2349 goto done; 2350 } 2351 2352 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2353 res = ENOENT; 2354 goto done; 2355 } 2356 2357 bcopy(multiaddr, 2358 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2359 Adapter->mcast_count++; 2360 2361 /* 2362 * Update the MC table in the hardware 2363 */ 2364 e1000g_clear_interrupt(Adapter); 2365 2366 e1000g_setup_multicast(Adapter); 2367 2368 if ((hw->mac.type == e1000_82542) && 2369 (hw->revision_id == E1000_REVISION_2)) 2370 e1000g_rx_setup(Adapter); 2371 2372 e1000g_mask_interrupt(Adapter); 2373 2374 done: 2375 rw_exit(&Adapter->chip_lock); 2376 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2377 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2378 res = EIO; 2379 } 2380 2381 return (res); 2382 } 2383 2384 static int 2385 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2386 { 2387 struct e1000_hw *hw = &Adapter->shared; 2388 unsigned i; 2389 2390 rw_enter(&Adapter->chip_lock, RW_WRITER); 2391 2392 for (i = 0; i < Adapter->mcast_count; i++) { 2393 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2394 ETHERADDRL) == 0) { 2395 for (i++; i < Adapter->mcast_count; i++) { 2396 Adapter->mcast_table[i - 1] = 2397 Adapter->mcast_table[i]; 2398 } 2399 Adapter->mcast_count--; 2400 break; 2401 } 2402 } 2403 2404 /* 2405 * Update the MC table in the hardware 2406 */ 2407 e1000g_clear_interrupt(Adapter); 2408 2409 e1000g_setup_multicast(Adapter); 2410 2411 if ((hw->mac.type == e1000_82542) && 2412 (hw->revision_id == E1000_REVISION_2)) 2413 e1000g_rx_setup(Adapter); 2414 2415 e1000g_mask_interrupt(Adapter); 2416 2417 done: 2418 rw_exit(&Adapter->chip_lock); 2419 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2420 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2421 return (EIO); 2422 } 2423 2424 return (0); 2425 } 2426 2427 /* 2428 * e1000g_setup_multicast - setup multicast data structures 2429 * 2430 * This routine initializes all of the multicast related structures. 2431 */ 2432 void 2433 e1000g_setup_multicast(struct e1000g *Adapter) 2434 { 2435 uint8_t *mc_addr_list; 2436 uint32_t mc_addr_count; 2437 uint32_t rctl; 2438 struct e1000_hw *hw; 2439 2440 hw = &Adapter->shared; 2441 2442 /* 2443 * The e1000g has the ability to do perfect filtering of 16 2444 * addresses. The driver uses one of the e1000g's 16 receive 2445 * address registers for its node/network/mac/individual address. 2446 * So, we have room for up to 15 multicast addresses in the CAM, 2447 * additional MC addresses are handled by the MTA (Multicast Table 2448 * Array) 2449 */ 2450 2451 rctl = E1000_READ_REG(hw, E1000_RCTL); 2452 2453 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2454 2455 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2456 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2457 "Adapter requested more than %d MC Addresses.\n", 2458 MAX_NUM_MULTICAST_ADDRESSES); 2459 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2460 } else { 2461 /* 2462 * Set the number of MC addresses that we are being 2463 * requested to use 2464 */ 2465 mc_addr_count = Adapter->mcast_count; 2466 } 2467 /* 2468 * The Wiseman 2.0 silicon has an errata by which the receiver will 2469 * hang while writing to the receive address registers if the receiver 2470 * is not in reset before writing to the registers. Updating the RAR 2471 * is done during the setting up of the multicast table, hence the 2472 * receiver has to be put in reset before updating the multicast table 2473 * and then taken out of reset at the end 2474 */ 2475 /* 2476 * if WMI was enabled then dis able it before issueing the global 2477 * reset to the hardware. 2478 */ 2479 /* 2480 * Only required for WISEMAN_2_0 2481 */ 2482 if ((hw->mac.type == e1000_82542) && 2483 (hw->revision_id == E1000_REVISION_2)) { 2484 e1000_pci_clear_mwi(hw); 2485 /* 2486 * The e1000g must be in reset before changing any RA 2487 * registers. Reset receive unit. The chip will remain in 2488 * the reset state until software explicitly restarts it. 2489 */ 2490 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2491 /* Allow receiver time to go in to reset */ 2492 msec_delay(5); 2493 } 2494 2495 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2496 Adapter->unicst_total, hw->mac.rar_entry_count); 2497 2498 /* 2499 * Only for Wiseman_2_0 2500 * If MWI was enabled then re-enable it after issueing (as we 2501 * disabled it up there) the receive reset command. 2502 * Wainwright does not have a receive reset command and only thing 2503 * close to it is global reset which will require tx setup also 2504 */ 2505 if ((hw->mac.type == e1000_82542) && 2506 (hw->revision_id == E1000_REVISION_2)) { 2507 /* 2508 * if WMI was enabled then reenable it after issueing the 2509 * global or receive reset to the hardware. 2510 */ 2511 2512 /* 2513 * Take receiver out of reset 2514 * clear E1000_RCTL_RST bit (and all others) 2515 */ 2516 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2517 msec_delay(5); 2518 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2519 e1000_pci_set_mwi(hw); 2520 } 2521 2522 /* 2523 * Restore original value 2524 */ 2525 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2526 } 2527 2528 int 2529 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2530 { 2531 struct e1000g *Adapter = (struct e1000g *)arg; 2532 2533 return ((add) ? multicst_add(Adapter, addr) 2534 : multicst_remove(Adapter, addr)); 2535 } 2536 2537 int 2538 e1000g_m_promisc(void *arg, boolean_t on) 2539 { 2540 struct e1000g *Adapter = (struct e1000g *)arg; 2541 uint32_t rctl; 2542 2543 rw_enter(&Adapter->chip_lock, RW_WRITER); 2544 2545 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2546 2547 if (on) 2548 rctl |= 2549 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2550 else 2551 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2552 2553 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2554 2555 Adapter->e1000g_promisc = on; 2556 2557 rw_exit(&Adapter->chip_lock); 2558 2559 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2560 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2561 return (EIO); 2562 } 2563 2564 return (0); 2565 } 2566 2567 static boolean_t 2568 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2569 { 2570 struct e1000g *Adapter = (struct e1000g *)arg; 2571 2572 switch (cap) { 2573 case MAC_CAPAB_HCKSUM: { 2574 uint32_t *txflags = cap_data; 2575 2576 if (Adapter->tx_hcksum_enable) 2577 *txflags = HCKSUM_IPHDRCKSUM | 2578 HCKSUM_INET_PARTIAL; 2579 else 2580 return (B_FALSE); 2581 break; 2582 } 2583 case MAC_CAPAB_POLL: 2584 /* 2585 * There's nothing for us to fill in, simply returning 2586 * B_TRUE stating that we support polling is sufficient. 2587 */ 2588 break; 2589 2590 case MAC_CAPAB_MULTIADDRESS: { 2591 multiaddress_capab_t *mmacp = cap_data; 2592 2593 /* 2594 * The number of MAC addresses made available by 2595 * this capability is one less than the total as 2596 * the primary address in slot 0 is counted in 2597 * the total. 2598 */ 2599 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2600 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2601 /* No multiple factory addresses, set mma_flag to 0 */ 2602 mmacp->maddr_flag = 0; 2603 mmacp->maddr_handle = Adapter; 2604 mmacp->maddr_add = e1000g_m_unicst_add; 2605 mmacp->maddr_remove = e1000g_m_unicst_remove; 2606 mmacp->maddr_modify = e1000g_m_unicst_modify; 2607 mmacp->maddr_get = e1000g_m_unicst_get; 2608 mmacp->maddr_reserve = NULL; 2609 break; 2610 } 2611 2612 case MAC_CAPAB_LSO: { 2613 mac_capab_lso_t *cap_lso = cap_data; 2614 2615 if (Adapter->lso_enable) { 2616 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2617 cap_lso->lso_basic_tcp_ipv4.lso_max = 2618 E1000_LSO_MAXLEN; 2619 } else 2620 return (B_FALSE); 2621 break; 2622 } 2623 2624 default: 2625 return (B_FALSE); 2626 } 2627 return (B_TRUE); 2628 } 2629 2630 static boolean_t 2631 e1000g_param_locked(mac_prop_id_t pr_num) 2632 { 2633 /* 2634 * All en_* parameters are locked (read-only) while 2635 * the device is in any sort of loopback mode ... 2636 */ 2637 switch (pr_num) { 2638 case MAC_PROP_EN_1000FDX_CAP: 2639 case MAC_PROP_EN_1000HDX_CAP: 2640 case MAC_PROP_EN_100FDX_CAP: 2641 case MAC_PROP_EN_100HDX_CAP: 2642 case MAC_PROP_EN_10FDX_CAP: 2643 case MAC_PROP_EN_10HDX_CAP: 2644 case MAC_PROP_AUTONEG: 2645 case MAC_PROP_FLOWCTRL: 2646 return (B_TRUE); 2647 } 2648 return (B_FALSE); 2649 } 2650 2651 /* 2652 * callback function for set/get of properties 2653 */ 2654 static int 2655 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2656 uint_t pr_valsize, const void *pr_val) 2657 { 2658 struct e1000g *Adapter = arg; 2659 struct e1000_mac_info *mac = &Adapter->shared.mac; 2660 struct e1000_phy_info *phy = &Adapter->shared.phy; 2661 struct e1000_fc_info *fc = &Adapter->shared.fc; 2662 int err = 0; 2663 link_flowctrl_t flowctrl; 2664 uint32_t cur_mtu, new_mtu; 2665 uint64_t tmp = 0; 2666 2667 rw_enter(&Adapter->chip_lock, RW_WRITER); 2668 if (Adapter->loopback_mode != E1000G_LB_NONE && 2669 e1000g_param_locked(pr_num)) { 2670 /* 2671 * All en_* parameters are locked (read-only) 2672 * while the device is in any sort of loopback mode. 2673 */ 2674 rw_exit(&Adapter->chip_lock); 2675 return (EBUSY); 2676 } 2677 2678 switch (pr_num) { 2679 case MAC_PROP_EN_1000FDX_CAP: 2680 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2681 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2682 goto reset; 2683 case MAC_PROP_EN_1000HDX_CAP: 2684 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2685 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2686 goto reset; 2687 case MAC_PROP_EN_100FDX_CAP: 2688 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2689 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2690 goto reset; 2691 case MAC_PROP_EN_100HDX_CAP: 2692 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2693 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2694 goto reset; 2695 case MAC_PROP_EN_10FDX_CAP: 2696 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2697 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2698 goto reset; 2699 case MAC_PROP_EN_10HDX_CAP: 2700 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2701 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2702 goto reset; 2703 case MAC_PROP_AUTONEG: 2704 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2705 goto reset; 2706 case MAC_PROP_FLOWCTRL: 2707 fc->send_xon = B_TRUE; 2708 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2709 2710 switch (flowctrl) { 2711 default: 2712 err = EINVAL; 2713 break; 2714 case LINK_FLOWCTRL_NONE: 2715 fc->type = e1000_fc_none; 2716 break; 2717 case LINK_FLOWCTRL_RX: 2718 fc->type = e1000_fc_rx_pause; 2719 break; 2720 case LINK_FLOWCTRL_TX: 2721 fc->type = e1000_fc_tx_pause; 2722 break; 2723 case LINK_FLOWCTRL_BI: 2724 fc->type = e1000_fc_full; 2725 break; 2726 } 2727 reset: 2728 if (err == 0) { 2729 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2730 err = EINVAL; 2731 } 2732 break; 2733 case MAC_PROP_ADV_1000FDX_CAP: 2734 case MAC_PROP_ADV_1000HDX_CAP: 2735 case MAC_PROP_ADV_100FDX_CAP: 2736 case MAC_PROP_ADV_100HDX_CAP: 2737 case MAC_PROP_ADV_10FDX_CAP: 2738 case MAC_PROP_ADV_10HDX_CAP: 2739 case MAC_PROP_STATUS: 2740 case MAC_PROP_SPEED: 2741 case MAC_PROP_DUPLEX: 2742 err = ENOTSUP; /* read-only prop. Can't set this. */ 2743 break; 2744 case MAC_PROP_MTU: 2745 cur_mtu = Adapter->default_mtu; 2746 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2747 if (new_mtu == cur_mtu) { 2748 err = 0; 2749 break; 2750 } 2751 2752 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2753 ETHERFCSL; 2754 if ((tmp < DEFAULT_FRAME_SIZE) || 2755 (tmp > MAXIMUM_FRAME_SIZE)) { 2756 err = EINVAL; 2757 break; 2758 } 2759 2760 /* ich8 does not support jumbo frames */ 2761 if ((mac->type == e1000_ich8lan) && 2762 (tmp > DEFAULT_FRAME_SIZE)) { 2763 err = EINVAL; 2764 break; 2765 } 2766 /* ich9 does not do jumbo frames on one phy type */ 2767 if ((mac->type == e1000_ich9lan) && 2768 (phy->type == e1000_phy_ife) && 2769 (tmp > DEFAULT_FRAME_SIZE)) { 2770 err = EINVAL; 2771 break; 2772 } 2773 if (Adapter->chip_state != E1000G_STOP) { 2774 err = EBUSY; 2775 break; 2776 } 2777 2778 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2779 if (err == 0) { 2780 Adapter->max_frame_size = (uint32_t)tmp; 2781 Adapter->default_mtu = new_mtu; 2782 e1000g_set_bufsize(Adapter); 2783 } 2784 break; 2785 case MAC_PROP_PRIVATE: 2786 err = e1000g_set_priv_prop(Adapter, pr_name, 2787 pr_valsize, pr_val); 2788 break; 2789 default: 2790 err = ENOTSUP; 2791 break; 2792 } 2793 rw_exit(&Adapter->chip_lock); 2794 return (err); 2795 } 2796 2797 static int 2798 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2799 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2800 { 2801 struct e1000g *Adapter = arg; 2802 struct e1000_fc_info *fc = &Adapter->shared.fc; 2803 int err = 0; 2804 link_flowctrl_t flowctrl; 2805 uint64_t tmp = 0; 2806 2807 if (pr_valsize == 0) 2808 return (EINVAL); 2809 2810 bzero(pr_val, pr_valsize); 2811 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2812 return (e1000g_get_def_val(Adapter, pr_num, 2813 pr_valsize, pr_val)); 2814 } 2815 2816 switch (pr_num) { 2817 case MAC_PROP_DUPLEX: 2818 if (pr_valsize >= sizeof (link_duplex_t)) { 2819 bcopy(&Adapter->link_duplex, pr_val, 2820 sizeof (link_duplex_t)); 2821 } else 2822 err = EINVAL; 2823 break; 2824 case MAC_PROP_SPEED: 2825 if (pr_valsize >= sizeof (uint64_t)) { 2826 tmp = Adapter->link_speed * 1000000ull; 2827 bcopy(&tmp, pr_val, sizeof (tmp)); 2828 } else 2829 err = EINVAL; 2830 break; 2831 case MAC_PROP_AUTONEG: 2832 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2833 break; 2834 case MAC_PROP_FLOWCTRL: 2835 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2836 switch (fc->type) { 2837 case e1000_fc_none: 2838 flowctrl = LINK_FLOWCTRL_NONE; 2839 break; 2840 case e1000_fc_rx_pause: 2841 flowctrl = LINK_FLOWCTRL_RX; 2842 break; 2843 case e1000_fc_tx_pause: 2844 flowctrl = LINK_FLOWCTRL_TX; 2845 break; 2846 case e1000_fc_full: 2847 flowctrl = LINK_FLOWCTRL_BI; 2848 break; 2849 } 2850 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2851 } else 2852 err = EINVAL; 2853 break; 2854 case MAC_PROP_ADV_1000FDX_CAP: 2855 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2856 break; 2857 case MAC_PROP_EN_1000FDX_CAP: 2858 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2859 break; 2860 case MAC_PROP_ADV_1000HDX_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2862 break; 2863 case MAC_PROP_EN_1000HDX_CAP: 2864 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2865 break; 2866 case MAC_PROP_ADV_100FDX_CAP: 2867 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2868 break; 2869 case MAC_PROP_EN_100FDX_CAP: 2870 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2871 break; 2872 case MAC_PROP_ADV_100HDX_CAP: 2873 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2874 break; 2875 case MAC_PROP_EN_100HDX_CAP: 2876 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2877 break; 2878 case MAC_PROP_ADV_10FDX_CAP: 2879 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2880 break; 2881 case MAC_PROP_EN_10FDX_CAP: 2882 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2883 break; 2884 case MAC_PROP_ADV_10HDX_CAP: 2885 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2886 break; 2887 case MAC_PROP_EN_10HDX_CAP: 2888 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2889 break; 2890 case MAC_PROP_ADV_100T4_CAP: 2891 case MAC_PROP_EN_100T4_CAP: 2892 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2893 break; 2894 case MAC_PROP_PRIVATE: 2895 err = e1000g_get_priv_prop(Adapter, pr_name, 2896 pr_flags, pr_valsize, pr_val); 2897 break; 2898 default: 2899 err = ENOTSUP; 2900 break; 2901 } 2902 return (err); 2903 } 2904 2905 /* ARGSUSED2 */ 2906 static int 2907 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2908 uint_t pr_valsize, const void *pr_val) 2909 { 2910 int err = 0; 2911 long result; 2912 struct e1000_hw *hw = &Adapter->shared; 2913 2914 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2915 if (pr_val == NULL) { 2916 err = EINVAL; 2917 return (err); 2918 } 2919 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2920 if (result < MIN_TX_BCOPY_THRESHOLD || 2921 result > MAX_TX_BCOPY_THRESHOLD) 2922 err = EINVAL; 2923 else { 2924 Adapter->tx_bcopy_thresh = (uint32_t)result; 2925 } 2926 return (err); 2927 } 2928 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2929 if (pr_val == NULL) { 2930 err = EINVAL; 2931 return (err); 2932 } 2933 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2934 if (result < 0 || result > 1) 2935 err = EINVAL; 2936 else { 2937 Adapter->tx_intr_enable = (result == 1) ? 2938 B_TRUE: B_FALSE; 2939 if (Adapter->tx_intr_enable) 2940 e1000g_mask_tx_interrupt(Adapter); 2941 else 2942 e1000g_clear_tx_interrupt(Adapter); 2943 if (e1000g_check_acc_handle( 2944 Adapter->osdep.reg_handle) != DDI_FM_OK) 2945 ddi_fm_service_impact(Adapter->dip, 2946 DDI_SERVICE_DEGRADED); 2947 } 2948 return (err); 2949 } 2950 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2951 if (pr_val == NULL) { 2952 err = EINVAL; 2953 return (err); 2954 } 2955 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2956 if (result < MIN_TX_INTR_DELAY || 2957 result > MAX_TX_INTR_DELAY) 2958 err = EINVAL; 2959 else { 2960 Adapter->tx_intr_delay = (uint32_t)result; 2961 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2962 if (e1000g_check_acc_handle( 2963 Adapter->osdep.reg_handle) != DDI_FM_OK) 2964 ddi_fm_service_impact(Adapter->dip, 2965 DDI_SERVICE_DEGRADED); 2966 } 2967 return (err); 2968 } 2969 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2970 if (pr_val == NULL) { 2971 err = EINVAL; 2972 return (err); 2973 } 2974 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2975 if (result < MIN_TX_INTR_ABS_DELAY || 2976 result > MAX_TX_INTR_ABS_DELAY) 2977 err = EINVAL; 2978 else { 2979 Adapter->tx_intr_abs_delay = (uint32_t)result; 2980 E1000_WRITE_REG(hw, E1000_TADV, 2981 Adapter->tx_intr_abs_delay); 2982 if (e1000g_check_acc_handle( 2983 Adapter->osdep.reg_handle) != DDI_FM_OK) 2984 ddi_fm_service_impact(Adapter->dip, 2985 DDI_SERVICE_DEGRADED); 2986 } 2987 return (err); 2988 } 2989 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2990 if (pr_val == NULL) { 2991 err = EINVAL; 2992 return (err); 2993 } 2994 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2995 if (result < MIN_RX_BCOPY_THRESHOLD || 2996 result > MAX_RX_BCOPY_THRESHOLD) 2997 err = EINVAL; 2998 else 2999 Adapter->rx_bcopy_thresh = (uint32_t)result; 3000 return (err); 3001 } 3002 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3003 if (pr_val == NULL) { 3004 err = EINVAL; 3005 return (err); 3006 } 3007 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3008 if (result < MIN_RX_LIMIT_ON_INTR || 3009 result > MAX_RX_LIMIT_ON_INTR) 3010 err = EINVAL; 3011 else 3012 Adapter->rx_limit_onintr = (uint32_t)result; 3013 return (err); 3014 } 3015 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3016 if (pr_val == NULL) { 3017 err = EINVAL; 3018 return (err); 3019 } 3020 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3021 if (result < MIN_RX_INTR_DELAY || 3022 result > MAX_RX_INTR_DELAY) 3023 err = EINVAL; 3024 else { 3025 Adapter->rx_intr_delay = (uint32_t)result; 3026 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3027 if (e1000g_check_acc_handle( 3028 Adapter->osdep.reg_handle) != DDI_FM_OK) 3029 ddi_fm_service_impact(Adapter->dip, 3030 DDI_SERVICE_DEGRADED); 3031 } 3032 return (err); 3033 } 3034 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3035 if (pr_val == NULL) { 3036 err = EINVAL; 3037 return (err); 3038 } 3039 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3040 if (result < MIN_RX_INTR_ABS_DELAY || 3041 result > MAX_RX_INTR_ABS_DELAY) 3042 err = EINVAL; 3043 else { 3044 Adapter->rx_intr_abs_delay = (uint32_t)result; 3045 E1000_WRITE_REG(hw, E1000_RADV, 3046 Adapter->rx_intr_abs_delay); 3047 if (e1000g_check_acc_handle( 3048 Adapter->osdep.reg_handle) != DDI_FM_OK) 3049 ddi_fm_service_impact(Adapter->dip, 3050 DDI_SERVICE_DEGRADED); 3051 } 3052 return (err); 3053 } 3054 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3055 if (pr_val == NULL) { 3056 err = EINVAL; 3057 return (err); 3058 } 3059 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3060 if (result < MIN_INTR_THROTTLING || 3061 result > MAX_INTR_THROTTLING) 3062 err = EINVAL; 3063 else { 3064 if (hw->mac.type >= e1000_82540) { 3065 Adapter->intr_throttling_rate = 3066 (uint32_t)result; 3067 E1000_WRITE_REG(hw, E1000_ITR, 3068 Adapter->intr_throttling_rate); 3069 if (e1000g_check_acc_handle( 3070 Adapter->osdep.reg_handle) != DDI_FM_OK) 3071 ddi_fm_service_impact(Adapter->dip, 3072 DDI_SERVICE_DEGRADED); 3073 } else 3074 err = EINVAL; 3075 } 3076 return (err); 3077 } 3078 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3079 if (pr_val == NULL) { 3080 err = EINVAL; 3081 return (err); 3082 } 3083 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3084 if (result < 0 || result > 1) 3085 err = EINVAL; 3086 else { 3087 if (hw->mac.type >= e1000_82540) { 3088 Adapter->intr_adaptive = (result == 1) ? 3089 B_TRUE : B_FALSE; 3090 } else { 3091 err = EINVAL; 3092 } 3093 } 3094 return (err); 3095 } 3096 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3097 if (pr_val == NULL) { 3098 err = EINVAL; 3099 return (err); 3100 } 3101 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3102 if (result < MIN_TX_RECYCLE_THRESHOLD || 3103 result > MAX_TX_RECYCLE_THRESHOLD) 3104 err = EINVAL; 3105 else 3106 Adapter->tx_recycle_thresh = (uint32_t)result; 3107 return (err); 3108 } 3109 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3110 if (pr_val == NULL) { 3111 err = EINVAL; 3112 return (err); 3113 } 3114 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3115 if (result < MIN_TX_RECYCLE_NUM || 3116 result > MAX_TX_RECYCLE_NUM) 3117 err = EINVAL; 3118 else 3119 Adapter->tx_recycle_num = (uint32_t)result; 3120 return (err); 3121 } 3122 return (ENOTSUP); 3123 } 3124 3125 static int 3126 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3127 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3128 { 3129 int err = ENOTSUP; 3130 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3131 int value; 3132 3133 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3134 if (is_default) 3135 goto done; 3136 value = Adapter->param_adv_pause; 3137 err = 0; 3138 goto done; 3139 } 3140 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3141 if (is_default) 3142 goto done; 3143 value = Adapter->param_adv_asym_pause; 3144 err = 0; 3145 goto done; 3146 } 3147 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3148 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3149 Adapter->tx_bcopy_thresh); 3150 err = 0; 3151 goto done; 3152 } 3153 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3154 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3155 Adapter->tx_intr_enable); 3156 err = 0; 3157 goto done; 3158 } 3159 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3160 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3161 Adapter->tx_intr_delay); 3162 err = 0; 3163 goto done; 3164 } 3165 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3166 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3167 Adapter->tx_intr_abs_delay); 3168 err = 0; 3169 goto done; 3170 } 3171 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3172 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3173 Adapter->rx_bcopy_thresh); 3174 err = 0; 3175 goto done; 3176 } 3177 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3178 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3179 Adapter->rx_limit_onintr); 3180 err = 0; 3181 goto done; 3182 } 3183 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3184 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3185 Adapter->rx_intr_delay); 3186 err = 0; 3187 goto done; 3188 } 3189 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3190 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3191 Adapter->rx_intr_abs_delay); 3192 err = 0; 3193 goto done; 3194 } 3195 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3196 value = (is_default ? DEFAULT_INTR_THROTTLING : 3197 Adapter->intr_throttling_rate); 3198 err = 0; 3199 goto done; 3200 } 3201 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3202 value = (is_default ? 1 : Adapter->intr_adaptive); 3203 err = 0; 3204 goto done; 3205 } 3206 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3207 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3208 Adapter->tx_recycle_thresh); 3209 err = 0; 3210 goto done; 3211 } 3212 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3213 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3214 Adapter->tx_recycle_num); 3215 err = 0; 3216 goto done; 3217 } 3218 done: 3219 if (err == 0) { 3220 (void) snprintf(pr_val, pr_valsize, "%d", value); 3221 } 3222 return (err); 3223 } 3224 3225 /* 3226 * e1000g_get_conf - get configurations set in e1000g.conf 3227 * This routine gets user-configured values out of the configuration 3228 * file e1000g.conf. 3229 * 3230 * For each configurable value, there is a minimum, a maximum, and a 3231 * default. 3232 * If user does not configure a value, use the default. 3233 * If user configures below the minimum, use the minumum. 3234 * If user configures above the maximum, use the maxumum. 3235 */ 3236 static void 3237 e1000g_get_conf(struct e1000g *Adapter) 3238 { 3239 struct e1000_hw *hw = &Adapter->shared; 3240 boolean_t tbi_compatibility = B_FALSE; 3241 3242 /* 3243 * get each configurable property from e1000g.conf 3244 */ 3245 3246 /* 3247 * NumTxDescriptors 3248 */ 3249 Adapter->tx_desc_num = 3250 e1000g_get_prop(Adapter, "NumTxDescriptors", 3251 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3252 DEFAULT_NUM_TX_DESCRIPTOR); 3253 3254 /* 3255 * NumRxDescriptors 3256 */ 3257 Adapter->rx_desc_num = 3258 e1000g_get_prop(Adapter, "NumRxDescriptors", 3259 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3260 DEFAULT_NUM_RX_DESCRIPTOR); 3261 3262 /* 3263 * NumRxFreeList 3264 */ 3265 Adapter->rx_freelist_num = 3266 e1000g_get_prop(Adapter, "NumRxFreeList", 3267 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3268 DEFAULT_NUM_RX_FREELIST); 3269 3270 /* 3271 * NumTxPacketList 3272 */ 3273 Adapter->tx_freelist_num = 3274 e1000g_get_prop(Adapter, "NumTxPacketList", 3275 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3276 DEFAULT_NUM_TX_FREELIST); 3277 3278 /* 3279 * FlowControl 3280 */ 3281 hw->fc.send_xon = B_TRUE; 3282 hw->fc.type = 3283 e1000g_get_prop(Adapter, "FlowControl", 3284 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3285 /* 4 is the setting that says "let the eeprom decide" */ 3286 if (hw->fc.type == 4) 3287 hw->fc.type = e1000_fc_default; 3288 3289 /* 3290 * Max Num Receive Packets on Interrupt 3291 */ 3292 Adapter->rx_limit_onintr = 3293 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3294 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3295 DEFAULT_RX_LIMIT_ON_INTR); 3296 3297 /* 3298 * PHY master slave setting 3299 */ 3300 hw->phy.ms_type = 3301 e1000g_get_prop(Adapter, "SetMasterSlave", 3302 e1000_ms_hw_default, e1000_ms_auto, 3303 e1000_ms_hw_default); 3304 3305 /* 3306 * Parameter which controls TBI mode workaround, which is only 3307 * needed on certain switches such as Cisco 6500/Foundry 3308 */ 3309 tbi_compatibility = 3310 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3311 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3312 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3313 3314 /* 3315 * MSI Enable 3316 */ 3317 Adapter->msi_enable = 3318 e1000g_get_prop(Adapter, "MSIEnable", 3319 0, 1, DEFAULT_MSI_ENABLE); 3320 3321 /* 3322 * Interrupt Throttling Rate 3323 */ 3324 Adapter->intr_throttling_rate = 3325 e1000g_get_prop(Adapter, "intr_throttling_rate", 3326 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3327 DEFAULT_INTR_THROTTLING); 3328 3329 /* 3330 * Adaptive Interrupt Blanking Enable/Disable 3331 * It is enabled by default 3332 */ 3333 Adapter->intr_adaptive = 3334 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3335 B_TRUE : B_FALSE; 3336 3337 /* 3338 * Tx recycle threshold 3339 */ 3340 Adapter->tx_recycle_thresh = 3341 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3342 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3343 DEFAULT_TX_RECYCLE_THRESHOLD); 3344 3345 /* 3346 * Tx recycle descriptor number 3347 */ 3348 Adapter->tx_recycle_num = 3349 e1000g_get_prop(Adapter, "tx_recycle_num", 3350 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3351 DEFAULT_TX_RECYCLE_NUM); 3352 3353 /* 3354 * Hardware checksum enable/disable parameter 3355 */ 3356 Adapter->tx_hcksum_enable = 3357 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3358 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3359 /* 3360 * Checksum on/off selection via global parameters. 3361 * 3362 * If the chip is flagged as not capable of (correctly) 3363 * handling checksumming, we don't enable it on either 3364 * Rx or Tx side. Otherwise, we take this chip's settings 3365 * from the patchable global defaults. 3366 * 3367 * We advertise our capabilities only if TX offload is 3368 * enabled. On receive, the stack will accept checksummed 3369 * packets anyway, even if we haven't said we can deliver 3370 * them. 3371 */ 3372 switch (hw->mac.type) { 3373 case e1000_82540: 3374 case e1000_82544: 3375 case e1000_82545: 3376 case e1000_82545_rev_3: 3377 case e1000_82546: 3378 case e1000_82546_rev_3: 3379 case e1000_82571: 3380 case e1000_82572: 3381 case e1000_82573: 3382 case e1000_80003es2lan: 3383 break; 3384 /* 3385 * For the following Intel PRO/1000 chipsets, we have not 3386 * tested the hardware checksum offload capability, so we 3387 * disable the capability for them. 3388 * e1000_82542, 3389 * e1000_82543, 3390 * e1000_82541, 3391 * e1000_82541_rev_2, 3392 * e1000_82547, 3393 * e1000_82547_rev_2, 3394 */ 3395 default: 3396 Adapter->tx_hcksum_enable = B_FALSE; 3397 } 3398 3399 /* 3400 * Large Send Offloading(LSO) Enable/Disable 3401 * If the tx hardware checksum is not enabled, LSO should be 3402 * disabled. 3403 */ 3404 Adapter->lso_enable = 3405 e1000g_get_prop(Adapter, "lso_enable", 3406 0, 1, DEFAULT_LSO_ENABLE); 3407 3408 switch (hw->mac.type) { 3409 case e1000_82546: 3410 case e1000_82546_rev_3: 3411 if (Adapter->lso_enable) 3412 Adapter->lso_premature_issue = B_TRUE; 3413 /* FALLTHRU */ 3414 case e1000_82571: 3415 case e1000_82572: 3416 case e1000_82573: 3417 break; 3418 default: 3419 Adapter->lso_enable = B_FALSE; 3420 } 3421 3422 if (!Adapter->tx_hcksum_enable) { 3423 Adapter->lso_premature_issue = B_FALSE; 3424 Adapter->lso_enable = B_FALSE; 3425 } 3426 } 3427 3428 /* 3429 * e1000g_get_prop - routine to read properties 3430 * 3431 * Get a user-configure property value out of the configuration 3432 * file e1000g.conf. 3433 * 3434 * Caller provides name of the property, a default value, a minimum 3435 * value, and a maximum value. 3436 * 3437 * Return configured value of the property, with default, minimum and 3438 * maximum properly applied. 3439 */ 3440 static int 3441 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3442 char *propname, /* name of the property */ 3443 int minval, /* minimum acceptable value */ 3444 int maxval, /* maximim acceptable value */ 3445 int defval) /* default value */ 3446 { 3447 int propval; /* value returned for requested property */ 3448 int *props; /* point to array of properties returned */ 3449 uint_t nprops; /* number of property value returned */ 3450 3451 /* 3452 * get the array of properties from the config file 3453 */ 3454 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3455 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3456 /* got some properties, test if we got enough */ 3457 if (Adapter->instance < nprops) { 3458 propval = props[Adapter->instance]; 3459 } else { 3460 /* not enough properties configured */ 3461 propval = defval; 3462 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3463 "Not Enough %s values found in e1000g.conf" 3464 " - set to %d\n", 3465 propname, propval); 3466 } 3467 3468 /* free memory allocated for properties */ 3469 ddi_prop_free(props); 3470 3471 } else { 3472 propval = defval; 3473 } 3474 3475 /* 3476 * enforce limits 3477 */ 3478 if (propval > maxval) { 3479 propval = maxval; 3480 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3481 "Too High %s value in e1000g.conf - set to %d\n", 3482 propname, propval); 3483 } 3484 3485 if (propval < minval) { 3486 propval = minval; 3487 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3488 "Too Low %s value in e1000g.conf - set to %d\n", 3489 propname, propval); 3490 } 3491 3492 return (propval); 3493 } 3494 3495 static boolean_t 3496 e1000g_link_check(struct e1000g *Adapter) 3497 { 3498 uint16_t speed, duplex, phydata; 3499 boolean_t link_changed = B_FALSE; 3500 struct e1000_hw *hw; 3501 uint32_t reg_tarc; 3502 3503 hw = &Adapter->shared; 3504 3505 if (e1000g_link_up(Adapter)) { 3506 /* 3507 * The Link is up, check whether it was marked as down earlier 3508 */ 3509 if (Adapter->link_state != LINK_STATE_UP) { 3510 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3511 Adapter->link_speed = speed; 3512 Adapter->link_duplex = duplex; 3513 Adapter->link_state = LINK_STATE_UP; 3514 link_changed = B_TRUE; 3515 3516 Adapter->tx_link_down_timeout = 0; 3517 3518 if ((hw->mac.type == e1000_82571) || 3519 (hw->mac.type == e1000_82572)) { 3520 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3521 if (speed == SPEED_1000) 3522 reg_tarc |= (1 << 21); 3523 else 3524 reg_tarc &= ~(1 << 21); 3525 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3526 } 3527 } 3528 Adapter->smartspeed = 0; 3529 } else { 3530 if (Adapter->link_state != LINK_STATE_DOWN) { 3531 Adapter->link_speed = 0; 3532 Adapter->link_duplex = 0; 3533 Adapter->link_state = LINK_STATE_DOWN; 3534 link_changed = B_TRUE; 3535 3536 /* 3537 * SmartSpeed workaround for Tabor/TanaX, When the 3538 * driver loses link disable auto master/slave 3539 * resolution. 3540 */ 3541 if (hw->phy.type == e1000_phy_igp) { 3542 (void) e1000_read_phy_reg(hw, 3543 PHY_1000T_CTRL, &phydata); 3544 phydata |= CR_1000T_MS_ENABLE; 3545 (void) e1000_write_phy_reg(hw, 3546 PHY_1000T_CTRL, phydata); 3547 } 3548 } else { 3549 e1000g_smartspeed(Adapter); 3550 } 3551 3552 if (Adapter->chip_state == E1000G_START) { 3553 if (Adapter->tx_link_down_timeout < 3554 MAX_TX_LINK_DOWN_TIMEOUT) { 3555 Adapter->tx_link_down_timeout++; 3556 } else if (Adapter->tx_link_down_timeout == 3557 MAX_TX_LINK_DOWN_TIMEOUT) { 3558 e1000g_tx_clean(Adapter); 3559 Adapter->tx_link_down_timeout++; 3560 } 3561 } 3562 } 3563 3564 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3565 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3566 3567 return (link_changed); 3568 } 3569 3570 /* 3571 * e1000g_reset_link - Using the link properties to setup the link 3572 */ 3573 int 3574 e1000g_reset_link(struct e1000g *Adapter) 3575 { 3576 struct e1000_mac_info *mac; 3577 struct e1000_phy_info *phy; 3578 boolean_t invalid; 3579 3580 mac = &Adapter->shared.mac; 3581 phy = &Adapter->shared.phy; 3582 invalid = B_FALSE; 3583 3584 if (Adapter->param_adv_autoneg == 1) { 3585 mac->autoneg = B_TRUE; 3586 phy->autoneg_advertised = 0; 3587 3588 /* 3589 * 1000hdx is not supported for autonegotiation 3590 */ 3591 if (Adapter->param_adv_1000fdx == 1) 3592 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3593 3594 if (Adapter->param_adv_100fdx == 1) 3595 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3596 3597 if (Adapter->param_adv_100hdx == 1) 3598 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3599 3600 if (Adapter->param_adv_10fdx == 1) 3601 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3602 3603 if (Adapter->param_adv_10hdx == 1) 3604 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3605 3606 if (phy->autoneg_advertised == 0) 3607 invalid = B_TRUE; 3608 } else { 3609 mac->autoneg = B_FALSE; 3610 3611 /* 3612 * 1000fdx and 1000hdx are not supported for forced link 3613 */ 3614 if (Adapter->param_adv_100fdx == 1) 3615 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3616 else if (Adapter->param_adv_100hdx == 1) 3617 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3618 else if (Adapter->param_adv_10fdx == 1) 3619 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3620 else if (Adapter->param_adv_10hdx == 1) 3621 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3622 else 3623 invalid = B_TRUE; 3624 3625 } 3626 3627 if (invalid) { 3628 e1000g_log(Adapter, CE_WARN, 3629 "Invalid link sets. Setup link to" 3630 "support autonegotiation with all link capabilities."); 3631 mac->autoneg = B_TRUE; 3632 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3633 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3634 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3635 } 3636 3637 return (e1000_setup_link(&Adapter->shared)); 3638 } 3639 3640 static void 3641 e1000g_local_timer(void *ws) 3642 { 3643 struct e1000g *Adapter = (struct e1000g *)ws; 3644 struct e1000_hw *hw; 3645 e1000g_ether_addr_t ether_addr; 3646 boolean_t link_changed; 3647 3648 hw = &Adapter->shared; 3649 3650 if (Adapter->chip_state == E1000G_ERROR) { 3651 Adapter->reset_count++; 3652 if (e1000g_global_reset(Adapter)) 3653 ddi_fm_service_impact(Adapter->dip, 3654 DDI_SERVICE_RESTORED); 3655 else 3656 ddi_fm_service_impact(Adapter->dip, 3657 DDI_SERVICE_LOST); 3658 return; 3659 } 3660 3661 if (e1000g_stall_check(Adapter)) { 3662 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3663 "Tx stall detected. Activate automatic recovery.\n"); 3664 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3665 Adapter->reset_count++; 3666 if (e1000g_reset_adapter(Adapter)) 3667 ddi_fm_service_impact(Adapter->dip, 3668 DDI_SERVICE_RESTORED); 3669 else 3670 ddi_fm_service_impact(Adapter->dip, 3671 DDI_SERVICE_LOST); 3672 return; 3673 } 3674 3675 link_changed = B_FALSE; 3676 rw_enter(&Adapter->chip_lock, RW_READER); 3677 if (Adapter->link_complete) 3678 link_changed = e1000g_link_check(Adapter); 3679 rw_exit(&Adapter->chip_lock); 3680 3681 if (link_changed) 3682 mac_link_update(Adapter->mh, Adapter->link_state); 3683 3684 /* 3685 * Workaround for esb2. Data stuck in fifo on a link 3686 * down event. Reset the adapter to recover it. 3687 */ 3688 if (Adapter->esb2_workaround) { 3689 Adapter->esb2_workaround = B_FALSE; 3690 (void) e1000g_reset_adapter(Adapter); 3691 } 3692 3693 /* 3694 * With 82571 controllers, any locally administered address will 3695 * be overwritten when there is a reset on the other port. 3696 * Detect this circumstance and correct it. 3697 */ 3698 if ((hw->mac.type == e1000_82571) && 3699 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3700 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3701 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3702 3703 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3704 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3705 3706 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3707 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3708 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3709 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3710 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3711 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3712 e1000_rar_set(hw, hw->mac.addr, 0); 3713 } 3714 } 3715 3716 /* 3717 * Long TTL workaround for 82541/82547 3718 */ 3719 (void) e1000_igp_ttl_workaround_82547(hw); 3720 3721 /* 3722 * Check for Adaptive IFS settings If there are lots of collisions 3723 * change the value in steps... 3724 * These properties should only be set for 10/100 3725 */ 3726 if ((hw->phy.media_type == e1000_media_type_copper) && 3727 ((Adapter->link_speed == SPEED_100) || 3728 (Adapter->link_speed == SPEED_10))) { 3729 e1000_update_adaptive(hw); 3730 } 3731 /* 3732 * Set Timer Interrupts 3733 */ 3734 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3735 3736 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3737 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3738 3739 restart_watchdog_timer(Adapter); 3740 } 3741 3742 /* 3743 * The function e1000g_link_timer() is called when the timer for link setup 3744 * is expired, which indicates the completion of the link setup. The link 3745 * state will not be updated until the link setup is completed. And the 3746 * link state will not be sent to the upper layer through mac_link_update() 3747 * in this function. It will be updated in the local timer routine or the 3748 * interrupt service routine after the interface is started (plumbed). 3749 */ 3750 static void 3751 e1000g_link_timer(void *arg) 3752 { 3753 struct e1000g *Adapter = (struct e1000g *)arg; 3754 3755 mutex_enter(&Adapter->link_lock); 3756 Adapter->link_complete = B_TRUE; 3757 Adapter->link_tid = 0; 3758 mutex_exit(&Adapter->link_lock); 3759 } 3760 3761 /* 3762 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3763 * 3764 * This function read the forced speed and duplex for 10/100 Mbps speeds 3765 * and also for 1000 Mbps speeds from the e1000g.conf file 3766 */ 3767 static void 3768 e1000g_force_speed_duplex(struct e1000g *Adapter) 3769 { 3770 int forced; 3771 struct e1000_mac_info *mac = &Adapter->shared.mac; 3772 struct e1000_phy_info *phy = &Adapter->shared.phy; 3773 3774 /* 3775 * get value out of config file 3776 */ 3777 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3778 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3779 3780 switch (forced) { 3781 case GDIAG_10_HALF: 3782 /* 3783 * Disable Auto Negotiation 3784 */ 3785 mac->autoneg = B_FALSE; 3786 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3787 break; 3788 case GDIAG_10_FULL: 3789 /* 3790 * Disable Auto Negotiation 3791 */ 3792 mac->autoneg = B_FALSE; 3793 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3794 break; 3795 case GDIAG_100_HALF: 3796 /* 3797 * Disable Auto Negotiation 3798 */ 3799 mac->autoneg = B_FALSE; 3800 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3801 break; 3802 case GDIAG_100_FULL: 3803 /* 3804 * Disable Auto Negotiation 3805 */ 3806 mac->autoneg = B_FALSE; 3807 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3808 break; 3809 case GDIAG_1000_FULL: 3810 /* 3811 * The gigabit spec requires autonegotiation. Therefore, 3812 * when the user wants to force the speed to 1000Mbps, we 3813 * enable AutoNeg, but only allow the harware to advertise 3814 * 1000Mbps. This is different from 10/100 operation, where 3815 * we are allowed to link without any negotiation. 3816 */ 3817 mac->autoneg = B_TRUE; 3818 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3819 break; 3820 default: /* obey the setting of AutoNegAdvertised */ 3821 mac->autoneg = B_TRUE; 3822 phy->autoneg_advertised = 3823 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3824 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3825 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3826 break; 3827 } /* switch */ 3828 } 3829 3830 /* 3831 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3832 * 3833 * This function reads MaxFrameSize from e1000g.conf 3834 */ 3835 static void 3836 e1000g_get_max_frame_size(struct e1000g *Adapter) 3837 { 3838 int max_frame; 3839 struct e1000_mac_info *mac = &Adapter->shared.mac; 3840 struct e1000_phy_info *phy = &Adapter->shared.phy; 3841 3842 /* 3843 * get value out of config file 3844 */ 3845 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3846 3847 switch (max_frame) { 3848 case 0: 3849 Adapter->default_mtu = ETHERMTU; 3850 break; 3851 /* 3852 * To avoid excessive memory allocation for rx buffers, 3853 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3854 */ 3855 case 1: 3856 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3857 sizeof (struct ether_vlan_header) - ETHERFCSL - 3858 E1000G_IPALIGNPRESERVEROOM; 3859 break; 3860 case 2: 3861 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3862 sizeof (struct ether_vlan_header) - ETHERFCSL - 3863 E1000G_IPALIGNPRESERVEROOM; 3864 break; 3865 case 3: 3866 if (mac->type >= e1000_82571) 3867 Adapter->default_mtu = MAXIMUM_MTU; 3868 else 3869 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3870 sizeof (struct ether_vlan_header) - ETHERFCSL - 3871 E1000G_IPALIGNPRESERVEROOM; 3872 break; 3873 default: 3874 Adapter->default_mtu = ETHERMTU; 3875 break; 3876 } /* switch */ 3877 3878 Adapter->max_frame_size = Adapter->default_mtu + 3879 sizeof (struct ether_vlan_header) + ETHERFCSL; 3880 3881 /* ich8 does not do jumbo frames */ 3882 if (mac->type == e1000_ich8lan) { 3883 Adapter->max_frame_size = ETHERMTU + 3884 sizeof (struct ether_vlan_header) + ETHERFCSL; 3885 } 3886 3887 /* ich9 does not do jumbo frames on one phy type */ 3888 if ((mac->type == e1000_ich9lan) && 3889 (phy->type == e1000_phy_ife)) { 3890 Adapter->max_frame_size = ETHERMTU + 3891 sizeof (struct ether_vlan_header) + ETHERFCSL; 3892 } 3893 } 3894 3895 static void 3896 arm_watchdog_timer(struct e1000g *Adapter) 3897 { 3898 Adapter->watchdog_tid = 3899 timeout(e1000g_local_timer, 3900 (void *)Adapter, 1 * drv_usectohz(1000000)); 3901 } 3902 #pragma inline(arm_watchdog_timer) 3903 3904 static void 3905 enable_watchdog_timer(struct e1000g *Adapter) 3906 { 3907 mutex_enter(&Adapter->watchdog_lock); 3908 3909 if (!Adapter->watchdog_timer_enabled) { 3910 Adapter->watchdog_timer_enabled = B_TRUE; 3911 Adapter->watchdog_timer_started = B_TRUE; 3912 arm_watchdog_timer(Adapter); 3913 } 3914 3915 mutex_exit(&Adapter->watchdog_lock); 3916 } 3917 3918 static void 3919 disable_watchdog_timer(struct e1000g *Adapter) 3920 { 3921 timeout_id_t tid; 3922 3923 mutex_enter(&Adapter->watchdog_lock); 3924 3925 Adapter->watchdog_timer_enabled = B_FALSE; 3926 Adapter->watchdog_timer_started = B_FALSE; 3927 tid = Adapter->watchdog_tid; 3928 Adapter->watchdog_tid = 0; 3929 3930 mutex_exit(&Adapter->watchdog_lock); 3931 3932 if (tid != 0) 3933 (void) untimeout(tid); 3934 } 3935 3936 static void 3937 start_watchdog_timer(struct e1000g *Adapter) 3938 { 3939 mutex_enter(&Adapter->watchdog_lock); 3940 3941 if (Adapter->watchdog_timer_enabled) { 3942 if (!Adapter->watchdog_timer_started) { 3943 Adapter->watchdog_timer_started = B_TRUE; 3944 arm_watchdog_timer(Adapter); 3945 } 3946 } 3947 3948 mutex_exit(&Adapter->watchdog_lock); 3949 } 3950 3951 static void 3952 restart_watchdog_timer(struct e1000g *Adapter) 3953 { 3954 mutex_enter(&Adapter->watchdog_lock); 3955 3956 if (Adapter->watchdog_timer_started) 3957 arm_watchdog_timer(Adapter); 3958 3959 mutex_exit(&Adapter->watchdog_lock); 3960 } 3961 3962 static void 3963 stop_watchdog_timer(struct e1000g *Adapter) 3964 { 3965 timeout_id_t tid; 3966 3967 mutex_enter(&Adapter->watchdog_lock); 3968 3969 Adapter->watchdog_timer_started = B_FALSE; 3970 tid = Adapter->watchdog_tid; 3971 Adapter->watchdog_tid = 0; 3972 3973 mutex_exit(&Adapter->watchdog_lock); 3974 3975 if (tid != 0) 3976 (void) untimeout(tid); 3977 } 3978 3979 static void 3980 stop_link_timer(struct e1000g *Adapter) 3981 { 3982 timeout_id_t tid; 3983 3984 /* Disable the link timer */ 3985 mutex_enter(&Adapter->link_lock); 3986 3987 tid = Adapter->link_tid; 3988 Adapter->link_tid = 0; 3989 3990 mutex_exit(&Adapter->link_lock); 3991 3992 if (tid != 0) 3993 (void) untimeout(tid); 3994 } 3995 3996 static void 3997 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3998 { 3999 timeout_id_t tid; 4000 4001 /* Disable the tx timer for 82547 chipset */ 4002 mutex_enter(&tx_ring->tx_lock); 4003 4004 tx_ring->timer_enable_82547 = B_FALSE; 4005 tid = tx_ring->timer_id_82547; 4006 tx_ring->timer_id_82547 = 0; 4007 4008 mutex_exit(&tx_ring->tx_lock); 4009 4010 if (tid != 0) 4011 (void) untimeout(tid); 4012 } 4013 4014 void 4015 e1000g_clear_interrupt(struct e1000g *Adapter) 4016 { 4017 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4018 0xffffffff & ~E1000_IMS_RXSEQ); 4019 } 4020 4021 void 4022 e1000g_mask_interrupt(struct e1000g *Adapter) 4023 { 4024 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4025 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4026 4027 if (Adapter->tx_intr_enable) 4028 e1000g_mask_tx_interrupt(Adapter); 4029 } 4030 4031 /* 4032 * This routine is called by e1000g_quiesce(), therefore must not block. 4033 */ 4034 void 4035 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4036 { 4037 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4038 } 4039 4040 void 4041 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4042 { 4043 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4044 } 4045 4046 void 4047 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4048 { 4049 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4050 } 4051 4052 static void 4053 e1000g_smartspeed(struct e1000g *Adapter) 4054 { 4055 struct e1000_hw *hw = &Adapter->shared; 4056 uint16_t phy_status; 4057 uint16_t phy_ctrl; 4058 4059 /* 4060 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4061 * advertising 1000Full, we don't even use the workaround 4062 */ 4063 if ((hw->phy.type != e1000_phy_igp) || 4064 !hw->mac.autoneg || 4065 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4066 return; 4067 4068 /* 4069 * True if this is the first call of this function or after every 4070 * 30 seconds of not having link 4071 */ 4072 if (Adapter->smartspeed == 0) { 4073 /* 4074 * If Master/Slave config fault is asserted twice, we 4075 * assume back-to-back 4076 */ 4077 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4078 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4079 return; 4080 4081 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4082 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4083 return; 4084 /* 4085 * We're assuming back-2-back because our status register 4086 * insists! there's a fault in the master/slave 4087 * relationship that was "negotiated" 4088 */ 4089 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4090 /* 4091 * Is the phy configured for manual configuration of 4092 * master/slave? 4093 */ 4094 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4095 /* 4096 * Yes. Then disable manual configuration (enable 4097 * auto configuration) of master/slave 4098 */ 4099 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4100 (void) e1000_write_phy_reg(hw, 4101 PHY_1000T_CTRL, phy_ctrl); 4102 /* 4103 * Effectively starting the clock 4104 */ 4105 Adapter->smartspeed++; 4106 /* 4107 * Restart autonegotiation 4108 */ 4109 if (!e1000_phy_setup_autoneg(hw) && 4110 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4111 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4112 MII_CR_RESTART_AUTO_NEG); 4113 (void) e1000_write_phy_reg(hw, 4114 PHY_CONTROL, phy_ctrl); 4115 } 4116 } 4117 return; 4118 /* 4119 * Has 6 seconds transpired still without link? Remember, 4120 * you should reset the smartspeed counter once you obtain 4121 * link 4122 */ 4123 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4124 /* 4125 * Yes. Remember, we did at the start determine that 4126 * there's a master/slave configuration fault, so we're 4127 * still assuming there's someone on the other end, but we 4128 * just haven't yet been able to talk to it. We then 4129 * re-enable auto configuration of master/slave to see if 4130 * we're running 2/3 pair cables. 4131 */ 4132 /* 4133 * If still no link, perhaps using 2/3 pair cable 4134 */ 4135 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4136 phy_ctrl |= CR_1000T_MS_ENABLE; 4137 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4138 /* 4139 * Restart autoneg with phy enabled for manual 4140 * configuration of master/slave 4141 */ 4142 if (!e1000_phy_setup_autoneg(hw) && 4143 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4144 phy_ctrl |= 4145 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4146 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4147 } 4148 /* 4149 * Hopefully, there are no more faults and we've obtained 4150 * link as a result. 4151 */ 4152 } 4153 /* 4154 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4155 * seconds) 4156 */ 4157 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4158 Adapter->smartspeed = 0; 4159 } 4160 4161 static boolean_t 4162 is_valid_mac_addr(uint8_t *mac_addr) 4163 { 4164 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4165 const uint8_t addr_test2[6] = 4166 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4167 4168 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4169 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4170 return (B_FALSE); 4171 4172 return (B_TRUE); 4173 } 4174 4175 /* 4176 * e1000g_stall_check - check for tx stall 4177 * 4178 * This function checks if the adapter is stalled (in transmit). 4179 * 4180 * It is called each time the watchdog timeout is invoked. 4181 * If the transmit descriptor reclaim continuously fails, 4182 * the watchdog value will increment by 1. If the watchdog 4183 * value exceeds the threshold, the adapter is assumed to 4184 * have stalled and need to be reset. 4185 */ 4186 static boolean_t 4187 e1000g_stall_check(struct e1000g *Adapter) 4188 { 4189 e1000g_tx_ring_t *tx_ring; 4190 4191 tx_ring = Adapter->tx_ring; 4192 4193 if (Adapter->link_state != LINK_STATE_UP) 4194 return (B_FALSE); 4195 4196 if (tx_ring->recycle_fail > 0) 4197 tx_ring->stall_watchdog++; 4198 else 4199 tx_ring->stall_watchdog = 0; 4200 4201 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4202 return (B_FALSE); 4203 4204 tx_ring->stall_watchdog = 0; 4205 tx_ring->recycle_fail = 0; 4206 4207 return (B_TRUE); 4208 } 4209 4210 #ifdef E1000G_DEBUG 4211 static enum ioc_reply 4212 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4213 { 4214 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4215 e1000g_peekpoke_t *ppd; 4216 uint64_t mem_va; 4217 uint64_t maxoff; 4218 boolean_t peek; 4219 4220 switch (iocp->ioc_cmd) { 4221 4222 case E1000G_IOC_REG_PEEK: 4223 peek = B_TRUE; 4224 break; 4225 4226 case E1000G_IOC_REG_POKE: 4227 peek = B_FALSE; 4228 break; 4229 4230 deault: 4231 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4232 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4233 iocp->ioc_cmd); 4234 return (IOC_INVAL); 4235 } 4236 4237 /* 4238 * Validate format of ioctl 4239 */ 4240 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4241 return (IOC_INVAL); 4242 if (mp->b_cont == NULL) 4243 return (IOC_INVAL); 4244 4245 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4246 4247 /* 4248 * Validate request parameters 4249 */ 4250 switch (ppd->pp_acc_space) { 4251 4252 default: 4253 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4254 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4255 ppd->pp_acc_space); 4256 return (IOC_INVAL); 4257 4258 case E1000G_PP_SPACE_REG: 4259 /* 4260 * Memory-mapped I/O space 4261 */ 4262 ASSERT(ppd->pp_acc_size == 4); 4263 if (ppd->pp_acc_size != 4) 4264 return (IOC_INVAL); 4265 4266 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4267 return (IOC_INVAL); 4268 4269 mem_va = 0; 4270 maxoff = 0x10000; 4271 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4272 break; 4273 4274 case E1000G_PP_SPACE_E1000G: 4275 /* 4276 * E1000g data structure! 4277 */ 4278 mem_va = (uintptr_t)e1000gp; 4279 maxoff = sizeof (struct e1000g); 4280 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4281 break; 4282 4283 } 4284 4285 if (ppd->pp_acc_offset >= maxoff) 4286 return (IOC_INVAL); 4287 4288 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4289 return (IOC_INVAL); 4290 4291 /* 4292 * All OK - go! 4293 */ 4294 ppd->pp_acc_offset += mem_va; 4295 (*ppfn)(e1000gp, ppd); 4296 return (peek ? IOC_REPLY : IOC_ACK); 4297 } 4298 4299 static void 4300 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4301 { 4302 ddi_acc_handle_t handle; 4303 uint32_t *regaddr; 4304 4305 handle = e1000gp->osdep.reg_handle; 4306 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4307 (uintptr_t)ppd->pp_acc_offset); 4308 4309 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4310 } 4311 4312 static void 4313 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4314 { 4315 ddi_acc_handle_t handle; 4316 uint32_t *regaddr; 4317 uint32_t value; 4318 4319 handle = e1000gp->osdep.reg_handle; 4320 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4321 (uintptr_t)ppd->pp_acc_offset); 4322 value = (uint32_t)ppd->pp_acc_data; 4323 4324 ddi_put32(handle, regaddr, value); 4325 } 4326 4327 static void 4328 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4329 { 4330 uint64_t value; 4331 void *vaddr; 4332 4333 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4334 4335 switch (ppd->pp_acc_size) { 4336 case 1: 4337 value = *(uint8_t *)vaddr; 4338 break; 4339 4340 case 2: 4341 value = *(uint16_t *)vaddr; 4342 break; 4343 4344 case 4: 4345 value = *(uint32_t *)vaddr; 4346 break; 4347 4348 case 8: 4349 value = *(uint64_t *)vaddr; 4350 break; 4351 } 4352 4353 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4354 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4355 (void *)e1000gp, (void *)ppd, value, vaddr); 4356 4357 ppd->pp_acc_data = value; 4358 } 4359 4360 static void 4361 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4362 { 4363 uint64_t value; 4364 void *vaddr; 4365 4366 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4367 value = ppd->pp_acc_data; 4368 4369 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4370 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4371 (void *)e1000gp, (void *)ppd, value, vaddr); 4372 4373 switch (ppd->pp_acc_size) { 4374 case 1: 4375 *(uint8_t *)vaddr = (uint8_t)value; 4376 break; 4377 4378 case 2: 4379 *(uint16_t *)vaddr = (uint16_t)value; 4380 break; 4381 4382 case 4: 4383 *(uint32_t *)vaddr = (uint32_t)value; 4384 break; 4385 4386 case 8: 4387 *(uint64_t *)vaddr = (uint64_t)value; 4388 break; 4389 } 4390 } 4391 #endif 4392 4393 /* 4394 * Loopback Support 4395 */ 4396 static lb_property_t lb_normal = 4397 { normal, "normal", E1000G_LB_NONE }; 4398 static lb_property_t lb_external1000 = 4399 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4400 static lb_property_t lb_external100 = 4401 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4402 static lb_property_t lb_external10 = 4403 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4404 static lb_property_t lb_phy = 4405 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4406 4407 static enum ioc_reply 4408 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4409 { 4410 lb_info_sz_t *lbsp; 4411 lb_property_t *lbpp; 4412 struct e1000_hw *hw; 4413 uint32_t *lbmp; 4414 uint32_t size; 4415 uint32_t value; 4416 4417 hw = &Adapter->shared; 4418 4419 if (mp->b_cont == NULL) 4420 return (IOC_INVAL); 4421 4422 if (!e1000g_check_loopback_support(hw)) { 4423 e1000g_log(NULL, CE_WARN, 4424 "Loopback is not supported on e1000g%d", Adapter->instance); 4425 return (IOC_INVAL); 4426 } 4427 4428 switch (iocp->ioc_cmd) { 4429 default: 4430 return (IOC_INVAL); 4431 4432 case LB_GET_INFO_SIZE: 4433 size = sizeof (lb_info_sz_t); 4434 if (iocp->ioc_count != size) 4435 return (IOC_INVAL); 4436 4437 rw_enter(&Adapter->chip_lock, RW_WRITER); 4438 e1000g_get_phy_state(Adapter); 4439 4440 /* 4441 * Workaround for hardware faults. In order to get a stable 4442 * state of phy, we will wait for a specific interval and 4443 * try again. The time delay is an experiential value based 4444 * on our testing. 4445 */ 4446 msec_delay(100); 4447 e1000g_get_phy_state(Adapter); 4448 rw_exit(&Adapter->chip_lock); 4449 4450 value = sizeof (lb_normal); 4451 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4452 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4453 (hw->phy.media_type == e1000_media_type_fiber) || 4454 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4455 value += sizeof (lb_phy); 4456 switch (hw->mac.type) { 4457 case e1000_82571: 4458 case e1000_82572: 4459 case e1000_80003es2lan: 4460 value += sizeof (lb_external1000); 4461 break; 4462 } 4463 } 4464 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4465 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4466 value += sizeof (lb_external100); 4467 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4468 value += sizeof (lb_external10); 4469 4470 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4471 *lbsp = value; 4472 break; 4473 4474 case LB_GET_INFO: 4475 value = sizeof (lb_normal); 4476 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4477 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4478 (hw->phy.media_type == e1000_media_type_fiber) || 4479 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4480 value += sizeof (lb_phy); 4481 switch (hw->mac.type) { 4482 case e1000_82571: 4483 case e1000_82572: 4484 case e1000_80003es2lan: 4485 value += sizeof (lb_external1000); 4486 break; 4487 } 4488 } 4489 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4490 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4491 value += sizeof (lb_external100); 4492 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4493 value += sizeof (lb_external10); 4494 4495 size = value; 4496 if (iocp->ioc_count != size) 4497 return (IOC_INVAL); 4498 4499 value = 0; 4500 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4501 lbpp[value++] = lb_normal; 4502 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4503 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4504 (hw->phy.media_type == e1000_media_type_fiber) || 4505 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4506 lbpp[value++] = lb_phy; 4507 switch (hw->mac.type) { 4508 case e1000_82571: 4509 case e1000_82572: 4510 case e1000_80003es2lan: 4511 lbpp[value++] = lb_external1000; 4512 break; 4513 } 4514 } 4515 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4516 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4517 lbpp[value++] = lb_external100; 4518 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4519 lbpp[value++] = lb_external10; 4520 break; 4521 4522 case LB_GET_MODE: 4523 size = sizeof (uint32_t); 4524 if (iocp->ioc_count != size) 4525 return (IOC_INVAL); 4526 4527 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4528 *lbmp = Adapter->loopback_mode; 4529 break; 4530 4531 case LB_SET_MODE: 4532 size = 0; 4533 if (iocp->ioc_count != sizeof (uint32_t)) 4534 return (IOC_INVAL); 4535 4536 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4537 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4538 return (IOC_INVAL); 4539 break; 4540 } 4541 4542 iocp->ioc_count = size; 4543 iocp->ioc_error = 0; 4544 4545 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4546 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4547 return (IOC_INVAL); 4548 } 4549 4550 return (IOC_REPLY); 4551 } 4552 4553 static boolean_t 4554 e1000g_check_loopback_support(struct e1000_hw *hw) 4555 { 4556 switch (hw->mac.type) { 4557 case e1000_82540: 4558 case e1000_82545: 4559 case e1000_82545_rev_3: 4560 case e1000_82546: 4561 case e1000_82546_rev_3: 4562 case e1000_82541: 4563 case e1000_82541_rev_2: 4564 case e1000_82547: 4565 case e1000_82547_rev_2: 4566 case e1000_82571: 4567 case e1000_82572: 4568 case e1000_82573: 4569 case e1000_80003es2lan: 4570 return (B_TRUE); 4571 } 4572 return (B_FALSE); 4573 } 4574 4575 static boolean_t 4576 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4577 { 4578 struct e1000_hw *hw; 4579 int i, times; 4580 boolean_t link_up; 4581 4582 if (mode == Adapter->loopback_mode) 4583 return (B_TRUE); 4584 4585 hw = &Adapter->shared; 4586 times = 0; 4587 4588 Adapter->loopback_mode = mode; 4589 4590 if (mode == E1000G_LB_NONE) { 4591 /* Reset the chip */ 4592 hw->phy.autoneg_wait_to_complete = B_TRUE; 4593 (void) e1000g_reset_adapter(Adapter); 4594 hw->phy.autoneg_wait_to_complete = B_FALSE; 4595 return (B_TRUE); 4596 } 4597 4598 again: 4599 4600 rw_enter(&Adapter->chip_lock, RW_WRITER); 4601 4602 switch (mode) { 4603 default: 4604 rw_exit(&Adapter->chip_lock); 4605 return (B_FALSE); 4606 4607 case E1000G_LB_EXTERNAL_1000: 4608 e1000g_set_external_loopback_1000(Adapter); 4609 break; 4610 4611 case E1000G_LB_EXTERNAL_100: 4612 e1000g_set_external_loopback_100(Adapter); 4613 break; 4614 4615 case E1000G_LB_EXTERNAL_10: 4616 e1000g_set_external_loopback_10(Adapter); 4617 break; 4618 4619 case E1000G_LB_INTERNAL_PHY: 4620 e1000g_set_internal_loopback(Adapter); 4621 break; 4622 } 4623 4624 times++; 4625 4626 rw_exit(&Adapter->chip_lock); 4627 4628 /* Wait for link up */ 4629 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4630 msec_delay(100); 4631 4632 rw_enter(&Adapter->chip_lock, RW_WRITER); 4633 4634 link_up = e1000g_link_up(Adapter); 4635 4636 rw_exit(&Adapter->chip_lock); 4637 4638 if (!link_up) { 4639 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4640 "Failed to get the link up"); 4641 if (times < 2) { 4642 /* Reset the link */ 4643 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4644 "Reset the link ..."); 4645 (void) e1000g_reset_adapter(Adapter); 4646 goto again; 4647 } 4648 } 4649 4650 return (B_TRUE); 4651 } 4652 4653 /* 4654 * The following loopback settings are from Intel's technical 4655 * document - "How To Loopback". All the register settings and 4656 * time delay values are directly inherited from the document 4657 * without more explanations available. 4658 */ 4659 static void 4660 e1000g_set_internal_loopback(struct e1000g *Adapter) 4661 { 4662 struct e1000_hw *hw; 4663 uint32_t ctrl; 4664 uint32_t status; 4665 uint16_t phy_ctrl; 4666 uint32_t txcw; 4667 4668 hw = &Adapter->shared; 4669 4670 /* Disable Smart Power Down */ 4671 phy_spd_state(hw, B_FALSE); 4672 4673 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4674 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4675 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4676 4677 switch (hw->mac.type) { 4678 case e1000_82540: 4679 case e1000_82545: 4680 case e1000_82545_rev_3: 4681 case e1000_82546: 4682 case e1000_82546_rev_3: 4683 case e1000_82573: 4684 /* Auto-MDI/MDIX off */ 4685 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4686 /* Reset PHY to update Auto-MDI/MDIX */ 4687 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4688 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4689 /* Reset PHY to auto-neg off and force 1000 */ 4690 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4691 phy_ctrl | MII_CR_RESET); 4692 /* 4693 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4694 * See comments above e1000g_set_internal_loopback() for the 4695 * background. 4696 */ 4697 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4698 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4699 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4700 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4701 break; 4702 case e1000_80003es2lan: 4703 /* Force Link Up */ 4704 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4705 0x1CC); 4706 /* Sets PCS loopback at 1Gbs */ 4707 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4708 0x1046); 4709 break; 4710 } 4711 4712 /* Set loopback */ 4713 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4714 4715 msec_delay(250); 4716 4717 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4718 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4719 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4720 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4721 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4722 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4723 E1000_CTRL_FD); /* Force Duplex to FULL */ 4724 4725 switch (hw->mac.type) { 4726 case e1000_82540: 4727 case e1000_82545: 4728 case e1000_82545_rev_3: 4729 case e1000_82546: 4730 case e1000_82546_rev_3: 4731 /* 4732 * For some serdes we'll need to commit the writes now 4733 * so that the status is updated on link 4734 */ 4735 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4736 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4737 msec_delay(100); 4738 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4739 } 4740 4741 if (hw->phy.media_type == e1000_media_type_copper) { 4742 /* Invert Loss of Signal */ 4743 ctrl |= E1000_CTRL_ILOS; 4744 } else { 4745 /* Set ILOS on fiber nic if half duplex is detected */ 4746 status = E1000_READ_REG(hw, E1000_STATUS); 4747 if ((status & E1000_STATUS_FD) == 0) 4748 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4749 } 4750 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4751 break; 4752 4753 case e1000_82571: 4754 case e1000_82572: 4755 /* 4756 * The fiber/SerDes versions of this adapter do not contain an 4757 * accessible PHY. Therefore, loopback beyond MAC must be done 4758 * using SerDes analog loopback. 4759 */ 4760 if (hw->phy.media_type != e1000_media_type_copper) { 4761 status = E1000_READ_REG(hw, E1000_STATUS); 4762 /* Set ILOS on fiber nic if half duplex is detected */ 4763 if (((status & E1000_STATUS_LU) == 0) || 4764 ((status & E1000_STATUS_FD) == 0) || 4765 (hw->phy.media_type == 4766 e1000_media_type_internal_serdes)) 4767 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4768 4769 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4770 txcw = E1000_READ_REG(hw, E1000_TXCW); 4771 txcw &= ~((uint32_t)1 << 31); 4772 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4773 4774 /* 4775 * Write 0x410 to Serdes Control register 4776 * to enable Serdes analog loopback 4777 */ 4778 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4779 msec_delay(10); 4780 } 4781 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4782 break; 4783 4784 case e1000_82573: 4785 ctrl |= E1000_CTRL_ILOS; 4786 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4787 break; 4788 } 4789 } 4790 4791 static void 4792 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4793 { 4794 struct e1000_hw *hw; 4795 uint32_t rctl; 4796 uint32_t ctrl_ext; 4797 uint32_t ctrl; 4798 uint32_t status; 4799 uint32_t txcw; 4800 uint16_t phydata; 4801 4802 hw = &Adapter->shared; 4803 4804 /* Disable Smart Power Down */ 4805 phy_spd_state(hw, B_FALSE); 4806 4807 switch (hw->mac.type) { 4808 case e1000_82571: 4809 case e1000_82572: 4810 switch (hw->phy.media_type) { 4811 case e1000_media_type_copper: 4812 /* Force link up (Must be done before the PHY writes) */ 4813 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4814 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4815 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4816 4817 rctl = E1000_READ_REG(hw, E1000_RCTL); 4818 rctl |= (E1000_RCTL_EN | 4819 E1000_RCTL_SBP | 4820 E1000_RCTL_UPE | 4821 E1000_RCTL_MPE | 4822 E1000_RCTL_LPE | 4823 E1000_RCTL_BAM); /* 0x803E */ 4824 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4825 4826 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4827 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4828 E1000_CTRL_EXT_SDP6_DATA | 4829 E1000_CTRL_EXT_SDP7_DATA | 4830 E1000_CTRL_EXT_SDP4_DIR | 4831 E1000_CTRL_EXT_SDP6_DIR | 4832 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4833 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4834 4835 /* 4836 * This sequence tunes the PHY's SDP and no customer 4837 * settable values. For background, see comments above 4838 * e1000g_set_internal_loopback(). 4839 */ 4840 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 4841 msec_delay(10); 4842 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 4843 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 4844 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 4845 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 4846 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 4847 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 4848 4849 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 4850 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4851 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4852 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4853 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4854 4855 msec_delay(50); 4856 break; 4857 case e1000_media_type_fiber: 4858 case e1000_media_type_internal_serdes: 4859 status = E1000_READ_REG(hw, E1000_STATUS); 4860 if (((status & E1000_STATUS_LU) == 0) || 4861 (hw->phy.media_type == 4862 e1000_media_type_internal_serdes)) { 4863 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4864 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4865 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4866 } 4867 4868 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4869 txcw = E1000_READ_REG(hw, E1000_TXCW); 4870 txcw &= ~((uint32_t)1 << 31); 4871 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4872 4873 /* 4874 * Write 0x410 to Serdes Control register 4875 * to enable Serdes analog loopback 4876 */ 4877 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4878 msec_delay(10); 4879 break; 4880 default: 4881 break; 4882 } 4883 break; 4884 case e1000_80003es2lan: 4885 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4886 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 4887 phydata | (1 << 5)); 4888 Adapter->param_adv_autoneg = 1; 4889 Adapter->param_adv_1000fdx = 1; 4890 (void) e1000g_reset_link(Adapter); 4891 break; 4892 } 4893 } 4894 4895 static void 4896 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4897 { 4898 struct e1000_hw *hw; 4899 uint32_t ctrl; 4900 uint16_t phy_ctrl; 4901 4902 hw = &Adapter->shared; 4903 4904 /* Disable Smart Power Down */ 4905 phy_spd_state(hw, B_FALSE); 4906 4907 phy_ctrl = (MII_CR_FULL_DUPLEX | 4908 MII_CR_SPEED_100); 4909 4910 /* Force 100/FD, reset PHY */ 4911 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4912 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4913 msec_delay(10); 4914 4915 /* Force 100/FD */ 4916 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4917 phy_ctrl); /* 0x2100 */ 4918 msec_delay(10); 4919 4920 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4921 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4922 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4923 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4924 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4925 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4926 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4927 E1000_CTRL_FD); /* Force Duplex to FULL */ 4928 4929 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4930 } 4931 4932 static void 4933 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4934 { 4935 struct e1000_hw *hw; 4936 uint32_t ctrl; 4937 uint16_t phy_ctrl; 4938 4939 hw = &Adapter->shared; 4940 4941 /* Disable Smart Power Down */ 4942 phy_spd_state(hw, B_FALSE); 4943 4944 phy_ctrl = (MII_CR_FULL_DUPLEX | 4945 MII_CR_SPEED_10); 4946 4947 /* Force 10/FD, reset PHY */ 4948 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4949 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4950 msec_delay(10); 4951 4952 /* Force 10/FD */ 4953 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4954 phy_ctrl); /* 0x0100 */ 4955 msec_delay(10); 4956 4957 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4958 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4959 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4960 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4961 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4962 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4963 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4964 E1000_CTRL_FD); /* Force Duplex to FULL */ 4965 4966 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4967 } 4968 4969 #ifdef __sparc 4970 static boolean_t 4971 e1000g_find_mac_address(struct e1000g *Adapter) 4972 { 4973 struct e1000_hw *hw = &Adapter->shared; 4974 uchar_t *bytes; 4975 struct ether_addr sysaddr; 4976 uint_t nelts; 4977 int err; 4978 boolean_t found = B_FALSE; 4979 4980 /* 4981 * The "vendor's factory-set address" may already have 4982 * been extracted from the chip, but if the property 4983 * "local-mac-address" is set we use that instead. 4984 * 4985 * We check whether it looks like an array of 6 4986 * bytes (which it should, if OBP set it). If we can't 4987 * make sense of it this way, we'll ignore it. 4988 */ 4989 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4990 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4991 if (err == DDI_PROP_SUCCESS) { 4992 if (nelts == ETHERADDRL) { 4993 while (nelts--) 4994 hw->mac.addr[nelts] = bytes[nelts]; 4995 found = B_TRUE; 4996 } 4997 ddi_prop_free(bytes); 4998 } 4999 5000 /* 5001 * Look up the OBP property "local-mac-address?". If the user has set 5002 * 'local-mac-address? = false', use "the system address" instead. 5003 */ 5004 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5005 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5006 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5007 if (localetheraddr(NULL, &sysaddr) != 0) { 5008 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5009 found = B_TRUE; 5010 } 5011 } 5012 ddi_prop_free(bytes); 5013 } 5014 5015 /* 5016 * Finally(!), if there's a valid "mac-address" property (created 5017 * if we netbooted from this interface), we must use this instead 5018 * of any of the above to ensure that the NFS/install server doesn't 5019 * get confused by the address changing as Solaris takes over! 5020 */ 5021 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5022 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5023 if (err == DDI_PROP_SUCCESS) { 5024 if (nelts == ETHERADDRL) { 5025 while (nelts--) 5026 hw->mac.addr[nelts] = bytes[nelts]; 5027 found = B_TRUE; 5028 } 5029 ddi_prop_free(bytes); 5030 } 5031 5032 if (found) { 5033 bcopy(hw->mac.addr, hw->mac.perm_addr, 5034 ETHERADDRL); 5035 } 5036 5037 return (found); 5038 } 5039 #endif 5040 5041 static int 5042 e1000g_add_intrs(struct e1000g *Adapter) 5043 { 5044 dev_info_t *devinfo; 5045 int intr_types; 5046 int rc; 5047 5048 devinfo = Adapter->dip; 5049 5050 /* Get supported interrupt types */ 5051 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5052 5053 if (rc != DDI_SUCCESS) { 5054 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5055 "Get supported interrupt types failed: %d\n", rc); 5056 return (DDI_FAILURE); 5057 } 5058 5059 /* 5060 * Based on Intel Technical Advisory document (TA-160), there are some 5061 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5062 * that it supports MSI, but in fact has problems. 5063 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5064 * PCI/PCI-X NICs. 5065 */ 5066 if (Adapter->shared.mac.type < e1000_82571) 5067 Adapter->msi_enable = B_FALSE; 5068 5069 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5070 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5071 5072 if (rc != DDI_SUCCESS) { 5073 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5074 "Add MSI failed, trying Legacy interrupts\n"); 5075 } else { 5076 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5077 } 5078 } 5079 5080 if ((Adapter->intr_type == 0) && 5081 (intr_types & DDI_INTR_TYPE_FIXED)) { 5082 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5083 5084 if (rc != DDI_SUCCESS) { 5085 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5086 "Add Legacy interrupts failed\n"); 5087 return (DDI_FAILURE); 5088 } 5089 5090 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5091 } 5092 5093 if (Adapter->intr_type == 0) { 5094 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5095 "No interrupts registered\n"); 5096 return (DDI_FAILURE); 5097 } 5098 5099 return (DDI_SUCCESS); 5100 } 5101 5102 /* 5103 * e1000g_intr_add() handles MSI/Legacy interrupts 5104 */ 5105 static int 5106 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5107 { 5108 dev_info_t *devinfo; 5109 int count, avail, actual; 5110 int x, y, rc, inum = 0; 5111 int flag; 5112 ddi_intr_handler_t *intr_handler; 5113 5114 devinfo = Adapter->dip; 5115 5116 /* get number of interrupts */ 5117 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5118 if ((rc != DDI_SUCCESS) || (count == 0)) { 5119 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5120 "Get interrupt number failed. Return: %d, count: %d\n", 5121 rc, count); 5122 return (DDI_FAILURE); 5123 } 5124 5125 /* get number of available interrupts */ 5126 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5127 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5128 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5129 "Get interrupt available number failed. " 5130 "Return: %d, available: %d\n", rc, avail); 5131 return (DDI_FAILURE); 5132 } 5133 5134 if (avail < count) { 5135 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5136 "Interrupts count: %d, available: %d\n", 5137 count, avail); 5138 } 5139 5140 /* Allocate an array of interrupt handles */ 5141 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5142 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5143 5144 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5145 flag = DDI_INTR_ALLOC_NORMAL; 5146 5147 /* call ddi_intr_alloc() */ 5148 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5149 count, &actual, flag); 5150 5151 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5152 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5153 "Allocate interrupts failed: %d\n", rc); 5154 5155 kmem_free(Adapter->htable, Adapter->intr_size); 5156 return (DDI_FAILURE); 5157 } 5158 5159 if (actual < count) { 5160 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5161 "Interrupts requested: %d, received: %d\n", 5162 count, actual); 5163 } 5164 5165 Adapter->intr_cnt = actual; 5166 5167 /* Get priority for first msi, assume remaining are all the same */ 5168 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5169 5170 if (rc != DDI_SUCCESS) { 5171 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5172 "Get interrupt priority failed: %d\n", rc); 5173 5174 /* Free already allocated intr */ 5175 for (y = 0; y < actual; y++) 5176 (void) ddi_intr_free(Adapter->htable[y]); 5177 5178 kmem_free(Adapter->htable, Adapter->intr_size); 5179 return (DDI_FAILURE); 5180 } 5181 5182 /* 5183 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5184 * use the interrupt service routine e1000g_intr_pciexpress() 5185 * to avoid interrupt stealing when sharing interrupt with other 5186 * devices. 5187 */ 5188 if (Adapter->shared.mac.type < e1000_82571) 5189 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5190 else 5191 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5192 5193 /* Call ddi_intr_add_handler() */ 5194 for (x = 0; x < actual; x++) { 5195 rc = ddi_intr_add_handler(Adapter->htable[x], 5196 intr_handler, (caddr_t)Adapter, NULL); 5197 5198 if (rc != DDI_SUCCESS) { 5199 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5200 "Add interrupt handler failed: %d\n", rc); 5201 5202 /* Remove already added handler */ 5203 for (y = 0; y < x; y++) 5204 (void) ddi_intr_remove_handler( 5205 Adapter->htable[y]); 5206 5207 /* Free already allocated intr */ 5208 for (y = 0; y < actual; y++) 5209 (void) ddi_intr_free(Adapter->htable[y]); 5210 5211 kmem_free(Adapter->htable, Adapter->intr_size); 5212 return (DDI_FAILURE); 5213 } 5214 } 5215 5216 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5217 5218 if (rc != DDI_SUCCESS) { 5219 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5220 "Get interrupt cap failed: %d\n", rc); 5221 5222 /* Free already allocated intr */ 5223 for (y = 0; y < actual; y++) { 5224 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5225 (void) ddi_intr_free(Adapter->htable[y]); 5226 } 5227 5228 kmem_free(Adapter->htable, Adapter->intr_size); 5229 return (DDI_FAILURE); 5230 } 5231 5232 return (DDI_SUCCESS); 5233 } 5234 5235 static int 5236 e1000g_rem_intrs(struct e1000g *Adapter) 5237 { 5238 int x; 5239 int rc; 5240 5241 for (x = 0; x < Adapter->intr_cnt; x++) { 5242 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5243 if (rc != DDI_SUCCESS) { 5244 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5245 "Remove intr handler failed: %d\n", rc); 5246 return (DDI_FAILURE); 5247 } 5248 5249 rc = ddi_intr_free(Adapter->htable[x]); 5250 if (rc != DDI_SUCCESS) { 5251 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5252 "Free intr failed: %d\n", rc); 5253 return (DDI_FAILURE); 5254 } 5255 } 5256 5257 kmem_free(Adapter->htable, Adapter->intr_size); 5258 5259 return (DDI_SUCCESS); 5260 } 5261 5262 static int 5263 e1000g_enable_intrs(struct e1000g *Adapter) 5264 { 5265 int x; 5266 int rc; 5267 5268 /* Enable interrupts */ 5269 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5270 /* Call ddi_intr_block_enable() for MSI */ 5271 rc = ddi_intr_block_enable(Adapter->htable, 5272 Adapter->intr_cnt); 5273 if (rc != DDI_SUCCESS) { 5274 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5275 "Enable block intr failed: %d\n", rc); 5276 return (DDI_FAILURE); 5277 } 5278 } else { 5279 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5280 for (x = 0; x < Adapter->intr_cnt; x++) { 5281 rc = ddi_intr_enable(Adapter->htable[x]); 5282 if (rc != DDI_SUCCESS) { 5283 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5284 "Enable intr failed: %d\n", rc); 5285 return (DDI_FAILURE); 5286 } 5287 } 5288 } 5289 5290 return (DDI_SUCCESS); 5291 } 5292 5293 static int 5294 e1000g_disable_intrs(struct e1000g *Adapter) 5295 { 5296 int x; 5297 int rc; 5298 5299 /* Disable all interrupts */ 5300 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5301 rc = ddi_intr_block_disable(Adapter->htable, 5302 Adapter->intr_cnt); 5303 if (rc != DDI_SUCCESS) { 5304 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5305 "Disable block intr failed: %d\n", rc); 5306 return (DDI_FAILURE); 5307 } 5308 } else { 5309 for (x = 0; x < Adapter->intr_cnt; x++) { 5310 rc = ddi_intr_disable(Adapter->htable[x]); 5311 if (rc != DDI_SUCCESS) { 5312 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5313 "Disable intr failed: %d\n", rc); 5314 return (DDI_FAILURE); 5315 } 5316 } 5317 } 5318 5319 return (DDI_SUCCESS); 5320 } 5321 5322 /* 5323 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5324 */ 5325 static void 5326 e1000g_get_phy_state(struct e1000g *Adapter) 5327 { 5328 struct e1000_hw *hw = &Adapter->shared; 5329 5330 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5331 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5332 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5333 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5334 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5335 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5336 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5337 &Adapter->phy_1000t_status); 5338 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5339 5340 Adapter->param_autoneg_cap = 5341 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5342 Adapter->param_pause_cap = 5343 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5344 Adapter->param_asym_pause_cap = 5345 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5346 Adapter->param_1000fdx_cap = 5347 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5348 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5349 Adapter->param_1000hdx_cap = 5350 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5351 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5352 Adapter->param_100t4_cap = 5353 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5354 Adapter->param_100fdx_cap = 5355 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5356 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5357 Adapter->param_100hdx_cap = 5358 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5359 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5360 Adapter->param_10fdx_cap = 5361 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5362 Adapter->param_10hdx_cap = 5363 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5364 5365 Adapter->param_adv_autoneg = hw->mac.autoneg; 5366 Adapter->param_adv_pause = 5367 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5368 Adapter->param_adv_asym_pause = 5369 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5370 Adapter->param_adv_1000hdx = 5371 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5372 Adapter->param_adv_100t4 = 5373 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5374 if (Adapter->param_adv_autoneg == 1) { 5375 Adapter->param_adv_1000fdx = 5376 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5377 Adapter->param_adv_100fdx = 5378 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5379 Adapter->param_adv_100hdx = 5380 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5381 Adapter->param_adv_10fdx = 5382 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5383 Adapter->param_adv_10hdx = 5384 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5385 } 5386 5387 Adapter->param_lp_autoneg = 5388 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5389 Adapter->param_lp_pause = 5390 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5391 Adapter->param_lp_asym_pause = 5392 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5393 Adapter->param_lp_1000fdx = 5394 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5395 Adapter->param_lp_1000hdx = 5396 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5397 Adapter->param_lp_100t4 = 5398 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5399 Adapter->param_lp_100fdx = 5400 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5401 Adapter->param_lp_100hdx = 5402 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5403 Adapter->param_lp_10fdx = 5404 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5405 Adapter->param_lp_10hdx = 5406 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5407 } 5408 5409 /* 5410 * FMA support 5411 */ 5412 5413 int 5414 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5415 { 5416 ddi_fm_error_t de; 5417 5418 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5419 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5420 return (de.fme_status); 5421 } 5422 5423 int 5424 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5425 { 5426 ddi_fm_error_t de; 5427 5428 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5429 return (de.fme_status); 5430 } 5431 5432 /* 5433 * The IO fault service error handling callback function 5434 */ 5435 /* ARGSUSED2 */ 5436 static int 5437 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5438 { 5439 /* 5440 * as the driver can always deal with an error in any dma or 5441 * access handle, we can just return the fme_status value. 5442 */ 5443 pci_ereport_post(dip, err, NULL); 5444 return (err->fme_status); 5445 } 5446 5447 static void 5448 e1000g_fm_init(struct e1000g *Adapter) 5449 { 5450 ddi_iblock_cookie_t iblk; 5451 int fma_acc_flag, fma_dma_flag; 5452 5453 /* Only register with IO Fault Services if we have some capability */ 5454 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5455 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5456 fma_acc_flag = 1; 5457 } else { 5458 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5459 fma_acc_flag = 0; 5460 } 5461 5462 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5463 fma_dma_flag = 1; 5464 } else { 5465 fma_dma_flag = 0; 5466 } 5467 5468 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5469 5470 if (Adapter->fm_capabilities) { 5471 5472 /* Register capabilities with IO Fault Services */ 5473 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5474 5475 /* 5476 * Initialize pci ereport capabilities if ereport capable 5477 */ 5478 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5479 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5480 pci_ereport_setup(Adapter->dip); 5481 5482 /* 5483 * Register error callback if error callback capable 5484 */ 5485 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5486 ddi_fm_handler_register(Adapter->dip, 5487 e1000g_fm_error_cb, (void*) Adapter); 5488 } 5489 } 5490 5491 static void 5492 e1000g_fm_fini(struct e1000g *Adapter) 5493 { 5494 /* Only unregister FMA capabilities if we registered some */ 5495 if (Adapter->fm_capabilities) { 5496 5497 /* 5498 * Release any resources allocated by pci_ereport_setup() 5499 */ 5500 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5501 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5502 pci_ereport_teardown(Adapter->dip); 5503 5504 /* 5505 * Un-register error callback if error callback capable 5506 */ 5507 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5508 ddi_fm_handler_unregister(Adapter->dip); 5509 5510 /* Unregister from IO Fault Services */ 5511 ddi_fm_fini(Adapter->dip); 5512 } 5513 } 5514 5515 void 5516 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5517 { 5518 uint64_t ena; 5519 char buf[FM_MAX_CLASS]; 5520 5521 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5522 ena = fm_ena_generate(0, FM_ENA_FMT1); 5523 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5524 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5525 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5526 } 5527 } 5528 5529 /* 5530 * quiesce(9E) entry point. 5531 * 5532 * This function is called when the system is single-threaded at high 5533 * PIL with preemption disabled. Therefore, this function must not be 5534 * blocked. 5535 * 5536 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5537 * DDI_FAILURE indicates an error condition and should almost never happen. 5538 */ 5539 static int 5540 e1000g_quiesce(dev_info_t *devinfo) 5541 { 5542 struct e1000g *Adapter; 5543 5544 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5545 5546 if (Adapter == NULL) 5547 return (DDI_FAILURE); 5548 5549 e1000g_clear_all_interrupts(Adapter); 5550 5551 (void) e1000_reset_hw(&Adapter->shared); 5552 5553 /* Setup our HW Tx Head & Tail descriptor pointers */ 5554 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5555 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5556 5557 /* Setup our HW Rx Head & Tail descriptor pointers */ 5558 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5559 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5560 5561 return (DDI_SUCCESS); 5562 } 5563 5564 static int 5565 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5566 uint_t pr_valsize, void *pr_val) 5567 { 5568 link_flowctrl_t fl; 5569 int err = 0; 5570 5571 ASSERT(pr_valsize > 0); 5572 switch (pr_num) { 5573 case MAC_PROP_AUTONEG: 5574 *(uint8_t *)pr_val = 5575 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5576 break; 5577 case MAC_PROP_FLOWCTRL: 5578 if (pr_valsize < sizeof (link_flowctrl_t)) 5579 return (EINVAL); 5580 fl = LINK_FLOWCTRL_BI; 5581 bcopy(&fl, pr_val, sizeof (fl)); 5582 break; 5583 case MAC_PROP_ADV_1000FDX_CAP: 5584 case MAC_PROP_EN_1000FDX_CAP: 5585 *(uint8_t *)pr_val = 5586 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5587 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5588 break; 5589 case MAC_PROP_ADV_1000HDX_CAP: 5590 case MAC_PROP_EN_1000HDX_CAP: 5591 *(uint8_t *)pr_val = 5592 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5593 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5594 break; 5595 case MAC_PROP_ADV_100FDX_CAP: 5596 case MAC_PROP_EN_100FDX_CAP: 5597 *(uint8_t *)pr_val = 5598 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5599 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5600 break; 5601 case MAC_PROP_ADV_100HDX_CAP: 5602 case MAC_PROP_EN_100HDX_CAP: 5603 *(uint8_t *)pr_val = 5604 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5605 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5606 break; 5607 case MAC_PROP_ADV_10FDX_CAP: 5608 case MAC_PROP_EN_10FDX_CAP: 5609 *(uint8_t *)pr_val = 5610 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5611 break; 5612 case MAC_PROP_ADV_10HDX_CAP: 5613 case MAC_PROP_EN_10HDX_CAP: 5614 *(uint8_t *)pr_val = 5615 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5616 break; 5617 default: 5618 err = ENOTSUP; 5619 break; 5620 } 5621 return (err); 5622 } 5623 5624 /* 5625 * synchronize the adv* and en* parameters. 5626 * 5627 * See comments in <sys/dld.h> for details of the *_en_* 5628 * parameters. The usage of ndd for setting adv parameters will 5629 * synchronize all the en parameters with the e1000g parameters, 5630 * implicitly disabling any settings made via dladm. 5631 */ 5632 static void 5633 e1000g_param_sync(struct e1000g *Adapter) 5634 { 5635 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5636 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5637 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5638 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5639 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5640 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5641 } 5642 5643 /* 5644 * e1000g_get_driver_control - tell manageability firmware that the driver 5645 * has control. 5646 */ 5647 static void 5648 e1000g_get_driver_control(struct e1000_hw *hw) 5649 { 5650 uint32_t ctrl_ext; 5651 uint32_t swsm; 5652 5653 /* tell manageability firmware the driver has taken over */ 5654 switch (hw->mac.type) { 5655 case e1000_82573: 5656 swsm = E1000_READ_REG(hw, E1000_SWSM); 5657 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5658 break; 5659 case e1000_82571: 5660 case e1000_82572: 5661 case e1000_82574: 5662 case e1000_80003es2lan: 5663 case e1000_ich8lan: 5664 case e1000_ich9lan: 5665 case e1000_ich10lan: 5666 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5667 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5668 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 5669 break; 5670 default: 5671 /* no manageability firmware: do nothing */ 5672 break; 5673 } 5674 } 5675 5676 /* 5677 * e1000g_release_driver_control - tell manageability firmware that the driver 5678 * has released control. 5679 */ 5680 static void 5681 e1000g_release_driver_control(struct e1000_hw *hw) 5682 { 5683 uint32_t ctrl_ext; 5684 uint32_t swsm; 5685 5686 /* tell manageability firmware the driver has released control */ 5687 switch (hw->mac.type) { 5688 case e1000_82573: 5689 swsm = E1000_READ_REG(hw, E1000_SWSM); 5690 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 5691 break; 5692 case e1000_82571: 5693 case e1000_82572: 5694 case e1000_82574: 5695 case e1000_80003es2lan: 5696 case e1000_ich8lan: 5697 case e1000_ich9lan: 5698 case e1000_ich10lan: 5699 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5700 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5701 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 5702 break; 5703 default: 5704 /* no manageability firmware: do nothing */ 5705 break; 5706 } 5707 } 5708