1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include "e1000g_sw.h" 47 #include "e1000g_debug.h" 48 49 static char ident[] = "Intel PRO/1000 Ethernet 5.2.10"; 50 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 51 static char e1000g_version[] = "Driver Ver. 5.2.10"; 52 53 /* 54 * Proto types for DDI entry points 55 */ 56 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 57 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 58 59 /* 60 * init and intr routines prototype 61 */ 62 static int e1000g_resume(dev_info_t *); 63 static int e1000g_suspend(dev_info_t *); 64 static uint_t e1000g_intr_pciexpress(caddr_t); 65 static uint_t e1000g_intr(caddr_t); 66 static void e1000g_intr_work(struct e1000g *, uint32_t); 67 #pragma inline(e1000g_intr_work) 68 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 69 #pragma inline(e1000g_get_itr) 70 static int e1000g_init(struct e1000g *); 71 static int e1000g_start(struct e1000g *, boolean_t); 72 static void e1000g_stop(struct e1000g *, boolean_t); 73 static int e1000g_m_start(void *); 74 static void e1000g_m_stop(void *); 75 static int e1000g_m_promisc(void *, boolean_t); 76 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 77 static int e1000g_m_unicst(void *, const uint8_t *); 78 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 79 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 80 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 81 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 82 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 83 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 84 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 85 uint_t, const void *); 86 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 87 uint_t, uint_t, void *); 88 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 89 const void *); 90 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 91 uint_t, void *); 92 static void e1000g_init_locks(struct e1000g *); 93 static void e1000g_destroy_locks(struct e1000g *); 94 static int e1000g_identify_hardware(struct e1000g *); 95 static int e1000g_regs_map(struct e1000g *); 96 static int e1000g_set_driver_params(struct e1000g *); 97 static void e1000g_set_bufsize(struct e1000g *); 98 static int e1000g_register_mac(struct e1000g *); 99 static boolean_t e1000g_rx_drain(struct e1000g *); 100 static boolean_t e1000g_tx_drain(struct e1000g *); 101 static void e1000g_init_unicst(struct e1000g *); 102 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 103 104 /* 105 * Local routines 106 */ 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 138 static void e1000g_set_internal_loopback(struct e1000g *); 139 static void e1000g_set_external_loopback_1000(struct e1000g *); 140 static void e1000g_set_external_loopback_100(struct e1000g *); 141 static void e1000g_set_external_loopback_10(struct e1000g *); 142 static int e1000g_add_intrs(struct e1000g *); 143 static int e1000g_intr_add(struct e1000g *, int); 144 static int e1000g_rem_intrs(struct e1000g *); 145 static int e1000g_enable_intrs(struct e1000g *); 146 static int e1000g_disable_intrs(struct e1000g *); 147 static boolean_t e1000g_link_up(struct e1000g *); 148 #ifdef __sparc 149 static boolean_t e1000g_find_mac_address(struct e1000g *); 150 #endif 151 static void e1000g_get_phy_state(struct e1000g *); 152 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 153 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 154 const void *impl_data); 155 static void e1000g_fm_init(struct e1000g *Adapter); 156 static void e1000g_fm_fini(struct e1000g *Adapter); 157 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 158 static void e1000g_param_sync(struct e1000g *); 159 160 mac_priv_prop_t e1000g_priv_props[] = { 161 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 162 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 163 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 164 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 165 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 166 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 167 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 168 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 169 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 170 {"_intr_adaptive", MAC_PROP_PERM_RW}, 171 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 172 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 173 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 174 {"_tx_recycle_num", MAC_PROP_PERM_RW} 175 }; 176 #define E1000G_MAX_PRIV_PROPS \ 177 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 178 179 180 static struct cb_ops cb_ws_ops = { 181 nulldev, /* cb_open */ 182 nulldev, /* cb_close */ 183 nodev, /* cb_strategy */ 184 nodev, /* cb_print */ 185 nodev, /* cb_dump */ 186 nodev, /* cb_read */ 187 nodev, /* cb_write */ 188 nodev, /* cb_ioctl */ 189 nodev, /* cb_devmap */ 190 nodev, /* cb_mmap */ 191 nodev, /* cb_segmap */ 192 nochpoll, /* cb_chpoll */ 193 ddi_prop_op, /* cb_prop_op */ 194 NULL, /* cb_stream */ 195 D_MP | D_HOTPLUG, /* cb_flag */ 196 CB_REV, /* cb_rev */ 197 nodev, /* cb_aread */ 198 nodev /* cb_awrite */ 199 }; 200 201 static struct dev_ops ws_ops = { 202 DEVO_REV, /* devo_rev */ 203 0, /* devo_refcnt */ 204 NULL, /* devo_getinfo */ 205 nulldev, /* devo_identify */ 206 nulldev, /* devo_probe */ 207 e1000g_attach, /* devo_attach */ 208 e1000g_detach, /* devo_detach */ 209 nodev, /* devo_reset */ 210 &cb_ws_ops, /* devo_cb_ops */ 211 NULL, /* devo_bus_ops */ 212 ddi_power /* devo_power */ 213 }; 214 215 static struct modldrv modldrv = { 216 &mod_driverops, /* Type of module. This one is a driver */ 217 ident, /* Discription string */ 218 &ws_ops, /* driver ops */ 219 }; 220 221 static struct modlinkage modlinkage = { 222 MODREV_1, &modldrv, NULL 223 }; 224 225 /* Access attributes for register mapping */ 226 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 227 DDI_DEVICE_ATTR_V0, 228 DDI_STRUCTURE_LE_ACC, 229 DDI_STRICTORDER_ACC, 230 DDI_FLAGERR_ACC 231 }; 232 233 #define E1000G_M_CALLBACK_FLAGS \ 234 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 235 236 static mac_callbacks_t e1000g_m_callbacks = { 237 E1000G_M_CALLBACK_FLAGS, 238 e1000g_m_stat, 239 e1000g_m_start, 240 e1000g_m_stop, 241 e1000g_m_promisc, 242 e1000g_m_multicst, 243 e1000g_m_unicst, 244 e1000g_m_tx, 245 NULL, 246 e1000g_m_ioctl, 247 e1000g_m_getcapab, 248 NULL, 249 NULL, 250 e1000g_m_setprop, 251 e1000g_m_getprop 252 }; 253 254 /* 255 * Global variables 256 */ 257 uint32_t e1000g_mblks_pending = 0; 258 /* 259 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 260 * Here we maintain a private dev_info list if e1000g_force_detach is 261 * enabled. If we force the driver to detach while there are still some 262 * rx buffers retained in the upper layer, we have to keep a copy of the 263 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 264 * structure will be freed after the driver is detached. However when we 265 * finally free those rx buffers released by the upper layer, we need to 266 * refer to the dev_info to free the dma buffers. So we save a copy of 267 * the dev_info for this purpose. On x86 platform, we assume this copy 268 * of dev_info is always valid, but on SPARC platform, it could be invalid 269 * after the system board level DR operation. For this reason, the global 270 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 271 */ 272 #ifdef __sparc 273 boolean_t e1000g_force_detach = B_FALSE; 274 #else 275 boolean_t e1000g_force_detach = B_TRUE; 276 #endif 277 private_devi_list_t *e1000g_private_devi_list = NULL; 278 279 /* 280 * The rwlock is defined to protect the whole processing of rx recycling 281 * and the rx packets release in detach processing to make them mutually 282 * exclusive. 283 * The rx recycling processes different rx packets in different threads, 284 * so it will be protected with RW_READER and it won't block any other rx 285 * recycling threads. 286 * While the detach processing will be protected with RW_WRITER to make 287 * it mutually exclusive with the rx recycling. 288 */ 289 krwlock_t e1000g_rx_detach_lock; 290 /* 291 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 292 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 293 * If there are many e1000g instances, the system may run out of DVMA 294 * resources during the initialization of the instances, then the flag will 295 * be changed to "USE_DMA". Because different e1000g instances are initialized 296 * in parallel, we need to use this lock to protect the flag. 297 */ 298 krwlock_t e1000g_dma_type_lock; 299 300 301 /* 302 * Loadable module configuration entry points for the driver 303 */ 304 305 /* 306 * _init - module initialization 307 */ 308 int 309 _init(void) 310 { 311 int status; 312 313 mac_init_ops(&ws_ops, WSNAME); 314 status = mod_install(&modlinkage); 315 if (status != DDI_SUCCESS) 316 mac_fini_ops(&ws_ops); 317 else { 318 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 319 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 320 } 321 322 return (status); 323 } 324 325 /* 326 * _fini - module finalization 327 */ 328 int 329 _fini(void) 330 { 331 int status; 332 333 rw_enter(&e1000g_rx_detach_lock, RW_READER); 334 if (e1000g_mblks_pending != 0) { 335 rw_exit(&e1000g_rx_detach_lock); 336 return (EBUSY); 337 } 338 rw_exit(&e1000g_rx_detach_lock); 339 340 status = mod_remove(&modlinkage); 341 if (status == DDI_SUCCESS) { 342 mac_fini_ops(&ws_ops); 343 344 if (e1000g_force_detach) { 345 private_devi_list_t *devi_node; 346 347 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 348 while (e1000g_private_devi_list != NULL) { 349 devi_node = e1000g_private_devi_list; 350 e1000g_private_devi_list = 351 e1000g_private_devi_list->next; 352 353 kmem_free(devi_node->priv_dip, 354 sizeof (struct dev_info)); 355 kmem_free(devi_node, 356 sizeof (private_devi_list_t)); 357 } 358 rw_exit(&e1000g_rx_detach_lock); 359 } 360 361 rw_destroy(&e1000g_rx_detach_lock); 362 rw_destroy(&e1000g_dma_type_lock); 363 } 364 365 return (status); 366 } 367 368 /* 369 * _info - module information 370 */ 371 int 372 _info(struct modinfo *modinfop) 373 { 374 return (mod_info(&modlinkage, modinfop)); 375 } 376 377 /* 378 * e1000g_attach - driver attach 379 * 380 * This function is the device-specific initialization entry 381 * point. This entry point is required and must be written. 382 * The DDI_ATTACH command must be provided in the attach entry 383 * point. When attach() is called with cmd set to DDI_ATTACH, 384 * all normal kernel services (such as kmem_alloc(9F)) are 385 * available for use by the driver. 386 * 387 * The attach() function will be called once for each instance 388 * of the device on the system with cmd set to DDI_ATTACH. 389 * Until attach() succeeds, the only driver entry points which 390 * may be called are open(9E) and getinfo(9E). 391 */ 392 static int 393 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 394 { 395 struct e1000g *Adapter; 396 struct e1000_hw *hw; 397 struct e1000g_osdep *osdep; 398 int instance; 399 400 switch (cmd) { 401 default: 402 e1000g_log(NULL, CE_WARN, 403 "Unsupported command send to e1000g_attach... "); 404 return (DDI_FAILURE); 405 406 case DDI_RESUME: 407 return (e1000g_resume(devinfo)); 408 409 case DDI_ATTACH: 410 break; 411 } 412 413 /* 414 * get device instance number 415 */ 416 instance = ddi_get_instance(devinfo); 417 418 /* 419 * Allocate soft data structure 420 */ 421 Adapter = 422 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 423 424 Adapter->dip = devinfo; 425 Adapter->instance = instance; 426 Adapter->tx_ring->adapter = Adapter; 427 Adapter->rx_ring->adapter = Adapter; 428 429 hw = &Adapter->shared; 430 osdep = &Adapter->osdep; 431 hw->back = osdep; 432 osdep->adapter = Adapter; 433 434 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 435 436 /* 437 * Initialize for fma support 438 */ 439 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 440 0, 0x0f, 441 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 442 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 443 e1000g_fm_init(Adapter); 444 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 445 446 /* 447 * PCI Configure 448 */ 449 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 450 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 451 goto attach_fail; 452 } 453 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 454 455 /* 456 * Setup hardware 457 */ 458 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 459 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 460 goto attach_fail; 461 } 462 463 /* 464 * Map in the device registers. 465 */ 466 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 467 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 468 goto attach_fail; 469 } 470 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 471 472 /* 473 * Initialize driver parameters 474 */ 475 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 476 goto attach_fail; 477 } 478 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 479 480 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 481 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 482 goto attach_fail; 483 } 484 485 /* 486 * Initialize interrupts 487 */ 488 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 489 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 490 goto attach_fail; 491 } 492 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 493 494 /* 495 * Initialize mutex's for this device. 496 * Do this before enabling the interrupt handler and 497 * register the softint to avoid the condition where 498 * interrupt handler can try using uninitialized mutex 499 */ 500 e1000g_init_locks(Adapter); 501 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 502 503 /* 504 * Initialize Driver Counters 505 */ 506 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 507 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 508 goto attach_fail; 509 } 510 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 511 512 /* 513 * Initialize chip hardware and software structures 514 */ 515 if (e1000g_init(Adapter) != DDI_SUCCESS) { 516 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 517 goto attach_fail; 518 } 519 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 520 521 /* 522 * Register the driver to the MAC 523 */ 524 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 525 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 526 goto attach_fail; 527 } 528 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 529 530 /* 531 * Now that mutex locks are initialized, and the chip is also 532 * initialized, enable interrupts. 533 */ 534 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 535 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 536 goto attach_fail; 537 } 538 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 539 540 /* 541 * If e1000g_force_detach is enabled, in global private dip list, 542 * we will create a new entry, which maintains the priv_dip for DR 543 * supports after driver detached. 544 */ 545 if (e1000g_force_detach) { 546 private_devi_list_t *devi_node; 547 548 Adapter->priv_dip = 549 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 550 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 551 sizeof (struct dev_info)); 552 553 devi_node = 554 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 555 556 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 557 devi_node->priv_dip = Adapter->priv_dip; 558 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 559 devi_node->next = e1000g_private_devi_list; 560 e1000g_private_devi_list = devi_node; 561 rw_exit(&e1000g_rx_detach_lock); 562 } 563 564 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 565 566 return (DDI_SUCCESS); 567 568 attach_fail: 569 e1000g_unattach(devinfo, Adapter); 570 return (DDI_FAILURE); 571 } 572 573 static int 574 e1000g_register_mac(struct e1000g *Adapter) 575 { 576 struct e1000_hw *hw = &Adapter->shared; 577 mac_register_t *mac; 578 int err; 579 580 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 581 return (DDI_FAILURE); 582 583 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 584 mac->m_driver = Adapter; 585 mac->m_dip = Adapter->dip; 586 mac->m_src_addr = hw->mac.addr; 587 mac->m_callbacks = &e1000g_m_callbacks; 588 mac->m_min_sdu = 0; 589 mac->m_max_sdu = Adapter->default_mtu; 590 mac->m_margin = VLAN_TAGSZ; 591 mac->m_priv_props = e1000g_priv_props; 592 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 593 594 err = mac_register(mac, &Adapter->mh); 595 mac_free(mac); 596 597 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 598 } 599 600 static int 601 e1000g_identify_hardware(struct e1000g *Adapter) 602 { 603 struct e1000_hw *hw = &Adapter->shared; 604 struct e1000g_osdep *osdep = &Adapter->osdep; 605 606 /* Get the device id */ 607 hw->vendor_id = 608 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 609 hw->device_id = 610 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 611 hw->revision_id = 612 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 613 hw->subsystem_device_id = 614 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 615 hw->subsystem_vendor_id = 616 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 617 618 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 619 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 620 "MAC type could not be set properly."); 621 return (DDI_FAILURE); 622 } 623 624 return (DDI_SUCCESS); 625 } 626 627 static int 628 e1000g_regs_map(struct e1000g *Adapter) 629 { 630 dev_info_t *devinfo = Adapter->dip; 631 struct e1000_hw *hw = &Adapter->shared; 632 struct e1000g_osdep *osdep = &Adapter->osdep; 633 off_t mem_size; 634 635 /* 636 * first get the size of device register to be mapped. The 637 * second parameter is the register we are interested. I our 638 * wiseman 0 is for config registers and 1 is for memory mapped 639 * registers Mem size should have memory mapped region size 640 */ 641 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 642 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 643 "ddi_dev_regsize for registers failed"); 644 return (DDI_FAILURE); 645 } 646 647 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 648 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 649 &osdep->reg_handle)) != DDI_SUCCESS) { 650 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 651 "ddi_regs_map_setup for registers failed"); 652 goto regs_map_fail; 653 } 654 655 /* ICH needs to map flash memory */ 656 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 657 /* get flash size */ 658 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 659 &mem_size) != DDI_SUCCESS) { 660 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 661 "ddi_dev_regsize for ICH flash failed"); 662 goto regs_map_fail; 663 } 664 665 /* map flash in */ 666 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 667 (caddr_t *)&hw->flash_address, 0, 668 mem_size, &e1000g_regs_acc_attr, 669 &osdep->ich_flash_handle) != DDI_SUCCESS) { 670 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 671 "ddi_regs_map_setup for ICH flash failed"); 672 goto regs_map_fail; 673 } 674 } 675 676 return (DDI_SUCCESS); 677 678 regs_map_fail: 679 if (osdep->reg_handle != NULL) 680 ddi_regs_map_free(&osdep->reg_handle); 681 682 return (DDI_FAILURE); 683 } 684 685 static int 686 e1000g_set_driver_params(struct e1000g *Adapter) 687 { 688 struct e1000_hw *hw; 689 uint32_t mem_bar, io_bar, bar64; 690 691 hw = &Adapter->shared; 692 693 /* Set MAC type and initialize hardware functions */ 694 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 695 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 696 "Could not setup hardware functions"); 697 return (DDI_FAILURE); 698 } 699 700 /* Get bus information */ 701 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 702 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 703 "Could not get bus information"); 704 return (DDI_FAILURE); 705 } 706 707 /* get mem_base addr */ 708 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 709 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 710 711 /* get io_base addr */ 712 if (hw->mac.type >= e1000_82544) { 713 if (bar64) { 714 /* IO BAR is different for 64 bit BAR mode */ 715 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 716 PCI_CONF_BASE4); 717 } else { 718 /* normal 32-bit BAR mode */ 719 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 720 PCI_CONF_BASE2); 721 } 722 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 723 } else { 724 /* no I/O access for adapters prior to 82544 */ 725 hw->io_base = 0x0; 726 } 727 728 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 729 730 hw->mac.autoneg_failed = B_TRUE; 731 732 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 733 hw->phy.autoneg_wait_to_complete = B_FALSE; 734 735 /* Adaptive IFS related changes */ 736 hw->mac.adaptive_ifs = B_TRUE; 737 738 /* Enable phy init script for IGP phy of 82541/82547 */ 739 if ((hw->mac.type == e1000_82547) || 740 (hw->mac.type == e1000_82541) || 741 (hw->mac.type == e1000_82547_rev_2) || 742 (hw->mac.type == e1000_82541_rev_2)) 743 e1000_init_script_state_82541(hw, B_TRUE); 744 745 /* Enable the TTL workaround for 82541/82547 */ 746 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 747 748 #ifdef __sparc 749 Adapter->strip_crc = B_TRUE; 750 #else 751 Adapter->strip_crc = B_FALSE; 752 #endif 753 754 /* Get conf file properties */ 755 e1000g_get_conf(Adapter); 756 757 /* Get speed/duplex settings in conf file */ 758 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 759 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 760 e1000g_force_speed_duplex(Adapter); 761 762 /* Get Jumbo Frames settings in conf file */ 763 e1000g_get_max_frame_size(Adapter); 764 765 /* Set Rx/Tx buffer size */ 766 e1000g_set_bufsize(Adapter); 767 768 /* Master Latency Timer */ 769 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 770 771 /* copper options */ 772 if (hw->phy.media_type == e1000_media_type_copper) { 773 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 774 hw->phy.disable_polarity_correction = B_FALSE; 775 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 776 } 777 778 /* The initial link state should be "unknown" */ 779 Adapter->link_state = LINK_STATE_UNKNOWN; 780 781 /* Initialize rx parameters */ 782 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 783 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 784 785 /* Initialize tx parameters */ 786 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 787 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 788 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 789 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 790 791 /* Initialize rx parameters */ 792 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 793 794 return (DDI_SUCCESS); 795 } 796 797 static void 798 e1000g_set_bufsize(struct e1000g *Adapter) 799 { 800 struct e1000_mac_info *mac = &Adapter->shared.mac; 801 uint64_t rx_size; 802 uint64_t tx_size; 803 804 #ifdef __sparc 805 dev_info_t *devinfo = Adapter->dip; 806 ulong_t iommu_pagesize; 807 808 /* Get the system page size */ 809 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 810 iommu_pagesize = dvma_pagesize(devinfo); 811 if (iommu_pagesize != 0) { 812 if (Adapter->sys_page_sz == iommu_pagesize) { 813 if (iommu_pagesize > 0x4000) 814 Adapter->sys_page_sz = 0x4000; 815 } else { 816 if (Adapter->sys_page_sz > iommu_pagesize) 817 Adapter->sys_page_sz = iommu_pagesize; 818 } 819 } 820 if (Adapter->lso_enable) { 821 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 822 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 823 } else { 824 Adapter->dvma_page_num = Adapter->max_frame_size / 825 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 826 } 827 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 828 #endif 829 830 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 831 832 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 833 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 834 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 835 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 836 (rx_size <= FRAME_SIZE_UPTO_8K)) 837 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 838 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 839 (rx_size <= FRAME_SIZE_UPTO_16K)) 840 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 841 else 842 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 843 844 tx_size = Adapter->max_frame_size; 845 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 846 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 847 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 848 (tx_size <= FRAME_SIZE_UPTO_8K)) 849 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 850 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 851 (tx_size <= FRAME_SIZE_UPTO_16K)) 852 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 853 else 854 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 855 856 /* 857 * For Wiseman adapters we have an requirement of having receive 858 * buffers aligned at 256 byte boundary. Since Livengood does not 859 * require this and forcing it for all hardwares will have 860 * performance implications, I am making it applicable only for 861 * Wiseman and for Jumbo frames enabled mode as rest of the time, 862 * it is okay to have normal frames...but it does involve a 863 * potential risk where we may loose data if buffer is not 864 * aligned...so all wiseman boards to have 256 byte aligned 865 * buffers 866 */ 867 if (mac->type < e1000_82543) 868 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 869 else 870 Adapter->rx_buf_align = 1; 871 } 872 873 /* 874 * e1000g_detach - driver detach 875 * 876 * The detach() function is the complement of the attach routine. 877 * If cmd is set to DDI_DETACH, detach() is used to remove the 878 * state associated with a given instance of a device node 879 * prior to the removal of that instance from the system. 880 * 881 * The detach() function will be called once for each instance 882 * of the device for which there has been a successful attach() 883 * once there are no longer any opens on the device. 884 * 885 * Interrupts routine are disabled, All memory allocated by this 886 * driver are freed. 887 */ 888 static int 889 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 890 { 891 struct e1000g *Adapter; 892 boolean_t rx_drain; 893 894 switch (cmd) { 895 default: 896 return (DDI_FAILURE); 897 898 case DDI_SUSPEND: 899 return (e1000g_suspend(devinfo)); 900 901 case DDI_DETACH: 902 break; 903 } 904 905 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 906 if (Adapter == NULL) 907 return (DDI_FAILURE); 908 909 if (mac_unregister(Adapter->mh) != 0) { 910 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 911 return (DDI_FAILURE); 912 } 913 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 914 915 916 if (Adapter->chip_state != E1000G_STOP) 917 e1000g_stop(Adapter, B_TRUE); 918 919 rx_drain = e1000g_rx_drain(Adapter); 920 921 /* 922 * If e1000g_force_detach is enabled, driver detach is safe. 923 * We will let e1000g_free_priv_devi_node routine determine 924 * whether we need to free the priv_dip entry for current 925 * driver instance. 926 */ 927 if (e1000g_force_detach) { 928 e1000g_free_priv_devi_node(Adapter, rx_drain); 929 } else { 930 if (!rx_drain) 931 return (DDI_FAILURE); 932 } 933 934 e1000g_unattach(devinfo, Adapter); 935 936 return (DDI_SUCCESS); 937 } 938 939 /* 940 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 941 * 942 * If free_flag is true, that indicates the upper layer is not holding 943 * the rx buffers, we could free the priv_dip entry safely. 944 * 945 * Otherwise, we have to keep this entry even after driver detached, 946 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 947 * so that driver could free it while all of rx buffers are returned 948 * by upper layer later. 949 */ 950 static void 951 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 952 { 953 private_devi_list_t *devi_node, *devi_del; 954 955 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 956 ASSERT(e1000g_private_devi_list != NULL); 957 ASSERT(Adapter->priv_dip != NULL); 958 959 devi_node = e1000g_private_devi_list; 960 if (devi_node->priv_dip == Adapter->priv_dip) { 961 if (free_flag) { 962 e1000g_private_devi_list = 963 devi_node->next; 964 kmem_free(devi_node->priv_dip, 965 sizeof (struct dev_info)); 966 kmem_free(devi_node, 967 sizeof (private_devi_list_t)); 968 } else { 969 ASSERT(e1000g_mblks_pending != 0); 970 devi_node->flag = 971 E1000G_PRIV_DEVI_DETACH; 972 } 973 rw_exit(&e1000g_rx_detach_lock); 974 return; 975 } 976 977 devi_node = e1000g_private_devi_list; 978 while (devi_node->next != NULL) { 979 if (devi_node->next->priv_dip == Adapter->priv_dip) { 980 if (free_flag) { 981 devi_del = devi_node->next; 982 devi_node->next = devi_del->next; 983 kmem_free(devi_del->priv_dip, 984 sizeof (struct dev_info)); 985 kmem_free(devi_del, 986 sizeof (private_devi_list_t)); 987 } else { 988 ASSERT(e1000g_mblks_pending != 0); 989 devi_node->next->flag = 990 E1000G_PRIV_DEVI_DETACH; 991 } 992 break; 993 } 994 devi_node = devi_node->next; 995 } 996 rw_exit(&e1000g_rx_detach_lock); 997 } 998 999 static void 1000 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1001 { 1002 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1003 (void) e1000g_disable_intrs(Adapter); 1004 } 1005 1006 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1007 (void) mac_unregister(Adapter->mh); 1008 } 1009 1010 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1011 (void) e1000g_rem_intrs(Adapter); 1012 } 1013 1014 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1015 (void) ddi_prop_remove_all(devinfo); 1016 } 1017 1018 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1019 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1020 } 1021 1022 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1023 stop_link_timer(Adapter); 1024 if (e1000_reset_hw(&Adapter->shared) != 0) { 1025 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1026 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1027 } 1028 } 1029 1030 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1031 if (Adapter->osdep.reg_handle != NULL) 1032 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1033 if (Adapter->osdep.ich_flash_handle != NULL) 1034 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1035 } 1036 1037 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1038 if (Adapter->osdep.cfg_handle != NULL) 1039 pci_config_teardown(&Adapter->osdep.cfg_handle); 1040 } 1041 1042 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1043 e1000g_destroy_locks(Adapter); 1044 } 1045 1046 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1047 e1000g_fm_fini(Adapter); 1048 } 1049 1050 e1000_remove_device(&Adapter->shared); 1051 1052 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1053 1054 /* 1055 * Another hotplug spec requirement, 1056 * run ddi_set_driver_private(devinfo, null); 1057 */ 1058 ddi_set_driver_private(devinfo, NULL); 1059 } 1060 1061 static void 1062 e1000g_init_locks(struct e1000g *Adapter) 1063 { 1064 e1000g_tx_ring_t *tx_ring; 1065 e1000g_rx_ring_t *rx_ring; 1066 1067 rw_init(&Adapter->chip_lock, NULL, 1068 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1069 mutex_init(&Adapter->link_lock, NULL, 1070 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1071 mutex_init(&Adapter->watchdog_lock, NULL, 1072 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1073 1074 tx_ring = Adapter->tx_ring; 1075 1076 mutex_init(&tx_ring->tx_lock, NULL, 1077 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1078 mutex_init(&tx_ring->usedlist_lock, NULL, 1079 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1080 mutex_init(&tx_ring->freelist_lock, NULL, 1081 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1082 1083 rx_ring = Adapter->rx_ring; 1084 1085 mutex_init(&rx_ring->freelist_lock, NULL, 1086 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1087 } 1088 1089 static void 1090 e1000g_destroy_locks(struct e1000g *Adapter) 1091 { 1092 e1000g_tx_ring_t *tx_ring; 1093 e1000g_rx_ring_t *rx_ring; 1094 1095 tx_ring = Adapter->tx_ring; 1096 mutex_destroy(&tx_ring->tx_lock); 1097 mutex_destroy(&tx_ring->usedlist_lock); 1098 mutex_destroy(&tx_ring->freelist_lock); 1099 1100 rx_ring = Adapter->rx_ring; 1101 mutex_destroy(&rx_ring->freelist_lock); 1102 1103 mutex_destroy(&Adapter->link_lock); 1104 mutex_destroy(&Adapter->watchdog_lock); 1105 rw_destroy(&Adapter->chip_lock); 1106 } 1107 1108 static int 1109 e1000g_resume(dev_info_t *devinfo) 1110 { 1111 struct e1000g *Adapter; 1112 1113 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1114 if (Adapter == NULL) 1115 return (DDI_FAILURE); 1116 1117 if (e1000g_start(Adapter, B_TRUE)) 1118 return (DDI_FAILURE); 1119 1120 return (DDI_SUCCESS); 1121 } 1122 1123 static int 1124 e1000g_suspend(dev_info_t *devinfo) 1125 { 1126 struct e1000g *Adapter; 1127 1128 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1129 if (Adapter == NULL) 1130 return (DDI_FAILURE); 1131 1132 e1000g_stop(Adapter, B_TRUE); 1133 1134 return (DDI_SUCCESS); 1135 } 1136 1137 static int 1138 e1000g_init(struct e1000g *Adapter) 1139 { 1140 uint32_t pba; 1141 uint32_t high_water; 1142 struct e1000_hw *hw; 1143 clock_t link_timeout; 1144 1145 hw = &Adapter->shared; 1146 1147 rw_enter(&Adapter->chip_lock, RW_WRITER); 1148 1149 /* 1150 * reset to put the hardware in a known state 1151 * before we try to do anything with the eeprom 1152 */ 1153 if (e1000_reset_hw(hw) != 0) { 1154 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1155 goto init_fail; 1156 } 1157 1158 if (e1000_validate_nvm_checksum(hw) < 0) { 1159 /* 1160 * Some PCI-E parts fail the first check due to 1161 * the link being in sleep state. Call it again, 1162 * if it fails a second time its a real issue. 1163 */ 1164 if (e1000_validate_nvm_checksum(hw) < 0) { 1165 e1000g_log(Adapter, CE_WARN, 1166 "Invalid NVM checksum. Please contact " 1167 "the vendor to update the NVM."); 1168 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1169 goto init_fail; 1170 } 1171 } 1172 1173 #ifdef __sparc 1174 /* 1175 * Firstly, we try to get the local ethernet address from OBP. If 1176 * fail, we get from EEPROM of NIC card. 1177 */ 1178 if (!e1000g_find_mac_address(Adapter)) { 1179 if (e1000_read_mac_addr(hw) < 0) { 1180 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1181 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1182 goto init_fail; 1183 } 1184 } 1185 #else 1186 /* Get the local ethernet address. */ 1187 if (e1000_read_mac_addr(hw) < 0) { 1188 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1189 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1190 goto init_fail; 1191 } 1192 #endif 1193 1194 /* check for valid mac address */ 1195 if (!is_valid_mac_addr(hw->mac.addr)) { 1196 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1197 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1198 goto init_fail; 1199 } 1200 1201 /* Set LAA state for 82571 chipset */ 1202 e1000_set_laa_state_82571(hw, B_TRUE); 1203 1204 /* Master Latency Timer implementation */ 1205 if (Adapter->master_latency_timer) { 1206 pci_config_put8(Adapter->osdep.cfg_handle, 1207 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1208 } 1209 1210 if (hw->mac.type < e1000_82547) { 1211 /* 1212 * Total FIFO is 64K 1213 */ 1214 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1215 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1216 else 1217 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1218 } else if (hw->mac.type >= e1000_82571 && 1219 hw->mac.type <= e1000_82572) { 1220 /* 1221 * Total FIFO is 48K 1222 */ 1223 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1224 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1225 else 1226 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1227 } else if (hw->mac.type == e1000_ich8lan) { 1228 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1229 } else if (hw->mac.type == e1000_ich9lan) { 1230 pba = E1000_PBA_12K; 1231 } else { 1232 /* 1233 * Total FIFO is 40K 1234 */ 1235 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1236 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1237 else 1238 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1239 } 1240 E1000_WRITE_REG(hw, E1000_PBA, pba); 1241 1242 /* 1243 * These parameters set thresholds for the adapter's generation(Tx) 1244 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1245 * settings. Flow control is enabled or disabled in the configuration 1246 * file. 1247 * High-water mark is set down from the top of the rx fifo (not 1248 * sensitive to max_frame_size) and low-water is set just below 1249 * high-water mark. 1250 * The high water mark must be low enough to fit one full frame above 1251 * it in the rx FIFO. Should be the lower of: 1252 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1253 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1254 * Rx FIFO size minus one full frame. 1255 */ 1256 high_water = min(((pba << 10) * 9 / 10), 1257 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1258 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1259 ((pba << 10) - Adapter->max_frame_size))); 1260 1261 hw->fc.high_water = high_water & 0xFFF8; 1262 hw->fc.low_water = hw->fc.high_water - 8; 1263 1264 if (hw->mac.type == e1000_80003es2lan) 1265 hw->fc.pause_time = 0xFFFF; 1266 else 1267 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1268 hw->fc.send_xon = B_TRUE; 1269 1270 /* 1271 * Reset the adapter hardware the second time. 1272 */ 1273 if (e1000_reset_hw(hw) != 0) { 1274 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1275 goto init_fail; 1276 } 1277 1278 /* disable wakeup control by default */ 1279 if (hw->mac.type >= e1000_82544) 1280 E1000_WRITE_REG(hw, E1000_WUC, 0); 1281 1282 /* MWI setup */ 1283 e1000_pci_set_mwi(hw); 1284 1285 /* 1286 * Configure/Initialize hardware 1287 */ 1288 if (e1000_init_hw(hw) < 0) { 1289 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1290 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1291 goto init_fail; 1292 } 1293 1294 /* Disable Smart Power Down */ 1295 phy_spd_state(hw, B_FALSE); 1296 1297 /* Make sure driver has control */ 1298 e1000g_get_driver_control(hw); 1299 1300 /* 1301 * Initialize unicast addresses. 1302 */ 1303 e1000g_init_unicst(Adapter); 1304 1305 /* 1306 * Setup and initialize the mctable structures. After this routine 1307 * completes Multicast table will be set 1308 */ 1309 e1000g_setup_multicast(Adapter); 1310 msec_delay(5); 1311 1312 /* 1313 * Implement Adaptive IFS 1314 */ 1315 e1000_reset_adaptive(hw); 1316 1317 /* Setup Interrupt Throttling Register */ 1318 if (hw->mac.type >= e1000_82540) { 1319 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1320 } else 1321 Adapter->intr_adaptive = B_FALSE; 1322 1323 /* Start the timer for link setup */ 1324 if (hw->mac.autoneg) 1325 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1326 else 1327 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1328 1329 mutex_enter(&Adapter->link_lock); 1330 if (hw->phy.autoneg_wait_to_complete) { 1331 Adapter->link_complete = B_TRUE; 1332 } else { 1333 Adapter->link_complete = B_FALSE; 1334 Adapter->link_tid = timeout(e1000g_link_timer, 1335 (void *)Adapter, link_timeout); 1336 } 1337 mutex_exit(&Adapter->link_lock); 1338 1339 /* Enable PCI-Ex master */ 1340 if (hw->bus.type == e1000_bus_type_pci_express) { 1341 e1000_enable_pciex_master(hw); 1342 } 1343 1344 /* Save the state of the phy */ 1345 e1000g_get_phy_state(Adapter); 1346 1347 e1000g_param_sync(Adapter); 1348 1349 Adapter->init_count++; 1350 1351 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1352 goto init_fail; 1353 } 1354 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1355 goto init_fail; 1356 } 1357 1358 rw_exit(&Adapter->chip_lock); 1359 1360 return (DDI_SUCCESS); 1361 1362 init_fail: 1363 rw_exit(&Adapter->chip_lock); 1364 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1365 return (DDI_FAILURE); 1366 } 1367 1368 /* 1369 * Check if the link is up 1370 */ 1371 static boolean_t 1372 e1000g_link_up(struct e1000g *Adapter) 1373 { 1374 struct e1000_hw *hw; 1375 boolean_t link_up; 1376 1377 hw = &Adapter->shared; 1378 1379 e1000_check_for_link(hw); 1380 1381 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1382 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1383 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1384 (hw->mac.serdes_has_link))) { 1385 link_up = B_TRUE; 1386 } else { 1387 link_up = B_FALSE; 1388 } 1389 1390 return (link_up); 1391 } 1392 1393 static void 1394 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1395 { 1396 struct iocblk *iocp; 1397 struct e1000g *e1000gp; 1398 enum ioc_reply status; 1399 int err; 1400 1401 iocp = (struct iocblk *)mp->b_rptr; 1402 iocp->ioc_error = 0; 1403 e1000gp = (struct e1000g *)arg; 1404 1405 ASSERT(e1000gp); 1406 if (e1000gp == NULL) { 1407 miocnak(q, mp, 0, EINVAL); 1408 return; 1409 } 1410 1411 switch (iocp->ioc_cmd) { 1412 1413 case LB_GET_INFO_SIZE: 1414 case LB_GET_INFO: 1415 case LB_GET_MODE: 1416 case LB_SET_MODE: 1417 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1418 break; 1419 1420 1421 #ifdef E1000G_DEBUG 1422 case E1000G_IOC_REG_PEEK: 1423 case E1000G_IOC_REG_POKE: 1424 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1425 break; 1426 case E1000G_IOC_CHIP_RESET: 1427 e1000gp->reset_count++; 1428 if (e1000g_reset(e1000gp)) 1429 status = IOC_ACK; 1430 else 1431 status = IOC_INVAL; 1432 break; 1433 #endif 1434 default: 1435 status = IOC_INVAL; 1436 break; 1437 } 1438 1439 /* 1440 * Decide how to reply 1441 */ 1442 switch (status) { 1443 default: 1444 case IOC_INVAL: 1445 /* 1446 * Error, reply with a NAK and EINVAL or the specified error 1447 */ 1448 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1449 EINVAL : iocp->ioc_error); 1450 break; 1451 1452 case IOC_DONE: 1453 /* 1454 * OK, reply already sent 1455 */ 1456 break; 1457 1458 case IOC_ACK: 1459 /* 1460 * OK, reply with an ACK 1461 */ 1462 miocack(q, mp, 0, 0); 1463 break; 1464 1465 case IOC_REPLY: 1466 /* 1467 * OK, send prepared reply as ACK or NAK 1468 */ 1469 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1470 M_IOCACK : M_IOCNAK; 1471 qreply(q, mp); 1472 break; 1473 } 1474 } 1475 1476 static int 1477 e1000g_m_start(void *arg) 1478 { 1479 struct e1000g *Adapter = (struct e1000g *)arg; 1480 1481 return (e1000g_start(Adapter, B_TRUE)); 1482 } 1483 1484 static int 1485 e1000g_start(struct e1000g *Adapter, boolean_t global) 1486 { 1487 if (global) { 1488 /* Allocate dma resources for descriptors and buffers */ 1489 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1490 e1000g_log(Adapter, CE_WARN, 1491 "Alloc DMA resources failed"); 1492 return (ENOTACTIVE); 1493 } 1494 Adapter->rx_buffer_setup = B_FALSE; 1495 } 1496 1497 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1498 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1499 e1000g_log(Adapter, CE_WARN, 1500 "Adapter initialization failed"); 1501 if (global) 1502 e1000g_release_dma_resources(Adapter); 1503 return (ENOTACTIVE); 1504 } 1505 } 1506 1507 rw_enter(&Adapter->chip_lock, RW_WRITER); 1508 1509 /* Setup and initialize the transmit structures */ 1510 e1000g_tx_setup(Adapter); 1511 msec_delay(5); 1512 1513 /* Setup and initialize the receive structures */ 1514 e1000g_rx_setup(Adapter); 1515 msec_delay(5); 1516 1517 e1000g_mask_interrupt(Adapter); 1518 1519 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1520 rw_exit(&Adapter->chip_lock); 1521 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1522 return (ENOTACTIVE); 1523 } 1524 1525 Adapter->chip_state = E1000G_START; 1526 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1527 1528 rw_exit(&Adapter->chip_lock); 1529 1530 /* Enable and start the watchdog timer */ 1531 enable_watchdog_timer(Adapter); 1532 1533 return (0); 1534 } 1535 1536 static void 1537 e1000g_m_stop(void *arg) 1538 { 1539 struct e1000g *Adapter = (struct e1000g *)arg; 1540 1541 e1000g_stop(Adapter, B_TRUE); 1542 } 1543 1544 static void 1545 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1546 { 1547 /* Set stop flags */ 1548 rw_enter(&Adapter->chip_lock, RW_WRITER); 1549 1550 Adapter->chip_state = E1000G_STOP; 1551 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1552 1553 rw_exit(&Adapter->chip_lock); 1554 1555 /* Drain tx sessions */ 1556 (void) e1000g_tx_drain(Adapter); 1557 1558 /* Disable and stop all the timers */ 1559 disable_watchdog_timer(Adapter); 1560 stop_link_timer(Adapter); 1561 stop_82547_timer(Adapter->tx_ring); 1562 1563 /* Stop the chip and release pending resources */ 1564 rw_enter(&Adapter->chip_lock, RW_WRITER); 1565 1566 e1000g_clear_all_interrupts(Adapter); 1567 if (e1000_reset_hw(&Adapter->shared) != 0) { 1568 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1569 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1570 } 1571 1572 /* Release resources still held by the TX descriptors */ 1573 e1000g_tx_clean(Adapter); 1574 1575 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1576 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1577 1578 /* Clean the pending rx jumbo packet fragment */ 1579 e1000g_rx_clean(Adapter); 1580 1581 rw_exit(&Adapter->chip_lock); 1582 1583 if (global) 1584 e1000g_release_dma_resources(Adapter); 1585 } 1586 1587 static void 1588 e1000g_rx_clean(struct e1000g *Adapter) 1589 { 1590 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1591 1592 if (rx_ring->rx_mblk != NULL) { 1593 freemsg(rx_ring->rx_mblk); 1594 rx_ring->rx_mblk = NULL; 1595 rx_ring->rx_mblk_tail = NULL; 1596 rx_ring->rx_mblk_len = 0; 1597 } 1598 } 1599 1600 static void 1601 e1000g_tx_clean(struct e1000g *Adapter) 1602 { 1603 e1000g_tx_ring_t *tx_ring; 1604 p_tx_sw_packet_t packet; 1605 mblk_t *mp; 1606 mblk_t *nmp; 1607 uint32_t packet_count; 1608 1609 tx_ring = Adapter->tx_ring; 1610 1611 /* 1612 * Here we don't need to protect the lists using 1613 * the usedlist_lock and freelist_lock, for they 1614 * have been protected by the chip_lock. 1615 */ 1616 mp = NULL; 1617 nmp = NULL; 1618 packet_count = 0; 1619 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1620 while (packet != NULL) { 1621 if (packet->mp != NULL) { 1622 /* Assemble the message chain */ 1623 if (mp == NULL) { 1624 mp = packet->mp; 1625 nmp = packet->mp; 1626 } else { 1627 nmp->b_next = packet->mp; 1628 nmp = packet->mp; 1629 } 1630 /* Disconnect the message from the sw packet */ 1631 packet->mp = NULL; 1632 } 1633 1634 e1000g_free_tx_swpkt(packet); 1635 packet_count++; 1636 1637 packet = (p_tx_sw_packet_t) 1638 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1639 } 1640 1641 if (mp != NULL) 1642 freemsgchain(mp); 1643 1644 if (packet_count > 0) { 1645 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1646 QUEUE_INIT_LIST(&tx_ring->used_list); 1647 1648 /* Setup TX descriptor pointers */ 1649 tx_ring->tbd_next = tx_ring->tbd_first; 1650 tx_ring->tbd_oldest = tx_ring->tbd_first; 1651 1652 /* Setup our HW Tx Head & Tail descriptor pointers */ 1653 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1654 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1655 } 1656 } 1657 1658 static boolean_t 1659 e1000g_tx_drain(struct e1000g *Adapter) 1660 { 1661 int i; 1662 boolean_t done; 1663 e1000g_tx_ring_t *tx_ring; 1664 1665 tx_ring = Adapter->tx_ring; 1666 1667 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1668 for (i = 0; i < TX_DRAIN_TIME; i++) { 1669 mutex_enter(&tx_ring->usedlist_lock); 1670 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1671 mutex_exit(&tx_ring->usedlist_lock); 1672 1673 if (done) 1674 break; 1675 1676 msec_delay(1); 1677 } 1678 1679 return (done); 1680 } 1681 1682 static boolean_t 1683 e1000g_rx_drain(struct e1000g *Adapter) 1684 { 1685 e1000g_rx_ring_t *rx_ring; 1686 p_rx_sw_packet_t packet; 1687 boolean_t done; 1688 1689 rx_ring = Adapter->rx_ring; 1690 done = B_TRUE; 1691 1692 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1693 1694 while (rx_ring->pending_list != NULL) { 1695 packet = rx_ring->pending_list; 1696 rx_ring->pending_list = 1697 rx_ring->pending_list->next; 1698 1699 if (packet->flag == E1000G_RX_SW_STOP) { 1700 packet->flag = E1000G_RX_SW_DETACH; 1701 done = B_FALSE; 1702 } else { 1703 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1704 ASSERT(packet->mp == NULL); 1705 e1000g_free_rx_sw_packet(packet); 1706 } 1707 } 1708 1709 rw_exit(&e1000g_rx_detach_lock); 1710 1711 return (done); 1712 } 1713 1714 boolean_t 1715 e1000g_reset(struct e1000g *Adapter) 1716 { 1717 e1000g_stop(Adapter, B_FALSE); 1718 1719 if (e1000g_start(Adapter, B_FALSE)) { 1720 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1721 return (B_FALSE); 1722 } 1723 1724 return (B_TRUE); 1725 } 1726 1727 boolean_t 1728 e1000g_global_reset(struct e1000g *Adapter) 1729 { 1730 e1000g_stop(Adapter, B_TRUE); 1731 1732 Adapter->init_count = 0; 1733 1734 if (e1000g_start(Adapter, B_TRUE)) { 1735 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1736 return (B_FALSE); 1737 } 1738 1739 return (B_TRUE); 1740 } 1741 1742 /* 1743 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1744 * 1745 * This interrupt service routine is for PCI-Express adapters. 1746 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1747 * bit is set. 1748 */ 1749 static uint_t 1750 e1000g_intr_pciexpress(caddr_t arg) 1751 { 1752 struct e1000g *Adapter; 1753 uint32_t icr; 1754 1755 Adapter = (struct e1000g *)arg; 1756 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1757 1758 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1759 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1760 1761 if (icr & E1000_ICR_INT_ASSERTED) { 1762 /* 1763 * E1000_ICR_INT_ASSERTED bit was set: 1764 * Read(Clear) the ICR, claim this interrupt, 1765 * look for work to do. 1766 */ 1767 e1000g_intr_work(Adapter, icr); 1768 return (DDI_INTR_CLAIMED); 1769 } else { 1770 /* 1771 * E1000_ICR_INT_ASSERTED bit was not set: 1772 * Don't claim this interrupt, return immediately. 1773 */ 1774 return (DDI_INTR_UNCLAIMED); 1775 } 1776 } 1777 1778 /* 1779 * e1000g_intr - ISR for PCI/PCI-X chipsets 1780 * 1781 * This interrupt service routine is for PCI/PCI-X adapters. 1782 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1783 * bit is set or not. 1784 */ 1785 static uint_t 1786 e1000g_intr(caddr_t arg) 1787 { 1788 struct e1000g *Adapter; 1789 uint32_t icr; 1790 1791 Adapter = (struct e1000g *)arg; 1792 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1793 1794 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1795 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1796 1797 if (icr) { 1798 /* 1799 * Any bit was set in ICR: 1800 * Read(Clear) the ICR, claim this interrupt, 1801 * look for work to do. 1802 */ 1803 e1000g_intr_work(Adapter, icr); 1804 return (DDI_INTR_CLAIMED); 1805 } else { 1806 /* 1807 * No bit was set in ICR: 1808 * Don't claim this interrupt, return immediately. 1809 */ 1810 return (DDI_INTR_UNCLAIMED); 1811 } 1812 } 1813 1814 /* 1815 * e1000g_intr_work - actual processing of ISR 1816 * 1817 * Read(clear) the ICR contents and call appropriate interrupt 1818 * processing routines. 1819 */ 1820 static void 1821 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1822 { 1823 struct e1000_hw *hw; 1824 hw = &Adapter->shared; 1825 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1826 uint32_t itr; 1827 1828 Adapter->rx_pkt_cnt = 0; 1829 Adapter->tx_pkt_cnt = 0; 1830 1831 rw_enter(&Adapter->chip_lock, RW_READER); 1832 /* 1833 * Here we need to check the "chip_state" flag within the chip_lock to 1834 * ensure the receive routine will not execute when the adapter is 1835 * being reset. 1836 */ 1837 if (Adapter->chip_state != E1000G_START) { 1838 rw_exit(&Adapter->chip_lock); 1839 return; 1840 } 1841 1842 if (icr & E1000_ICR_RXT0) { 1843 mblk_t *mp; 1844 1845 mutex_enter(&Adapter->rx_ring->rx_lock); 1846 mp = e1000g_receive(Adapter); 1847 mutex_exit(&Adapter->rx_ring->rx_lock); 1848 1849 rw_exit(&Adapter->chip_lock); 1850 1851 if (mp != NULL) 1852 mac_rx(Adapter->mh, Adapter->mrh, mp); 1853 } else 1854 rw_exit(&Adapter->chip_lock); 1855 1856 if (icr & E1000_ICR_TXDW) { 1857 if (!Adapter->tx_intr_enable) 1858 e1000g_clear_tx_interrupt(Adapter); 1859 1860 /* Recycle the tx descriptors */ 1861 rw_enter(&Adapter->chip_lock, RW_READER); 1862 e1000g_recycle(tx_ring); 1863 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1864 rw_exit(&Adapter->chip_lock); 1865 1866 /* Schedule the re-transmit */ 1867 if (tx_ring->resched_needed && 1868 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1869 tx_ring->resched_needed = B_FALSE; 1870 mac_tx_update(Adapter->mh); 1871 E1000G_STAT(tx_ring->stat_reschedule); 1872 } 1873 } 1874 1875 if (Adapter->intr_adaptive) { 1876 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1877 Adapter->intr_throttling_rate); 1878 if (itr) { 1879 E1000_WRITE_REG(hw, E1000_ITR, itr); 1880 Adapter->intr_throttling_rate = itr; 1881 } 1882 } 1883 1884 /* 1885 * The Receive Sequence errors RXSEQ and the link status change LSC 1886 * are checked to detect that the cable has been pulled out. For 1887 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1888 * are an indication that cable is not connected. 1889 */ 1890 if ((icr & E1000_ICR_RXSEQ) || 1891 (icr & E1000_ICR_LSC) || 1892 (icr & E1000_ICR_GPI_EN1)) { 1893 boolean_t link_changed; 1894 timeout_id_t tid = 0; 1895 1896 stop_watchdog_timer(Adapter); 1897 1898 rw_enter(&Adapter->chip_lock, RW_WRITER); 1899 1900 /* 1901 * Because we got a link-status-change interrupt, force 1902 * e1000_check_for_link() to look at phy 1903 */ 1904 Adapter->shared.mac.get_link_status = B_TRUE; 1905 1906 /* e1000g_link_check takes care of link status change */ 1907 link_changed = e1000g_link_check(Adapter); 1908 1909 /* Get new phy state */ 1910 e1000g_get_phy_state(Adapter); 1911 1912 /* 1913 * If the link timer has not timed out, we'll not notify 1914 * the upper layer with any link state until the link is up. 1915 */ 1916 if (link_changed && !Adapter->link_complete) { 1917 if (Adapter->link_state == LINK_STATE_UP) { 1918 mutex_enter(&Adapter->link_lock); 1919 Adapter->link_complete = B_TRUE; 1920 tid = Adapter->link_tid; 1921 Adapter->link_tid = 0; 1922 mutex_exit(&Adapter->link_lock); 1923 } else { 1924 link_changed = B_FALSE; 1925 } 1926 } 1927 rw_exit(&Adapter->chip_lock); 1928 1929 if (link_changed) { 1930 if (tid != 0) 1931 (void) untimeout(tid); 1932 1933 /* 1934 * Workaround for esb2. Data stuck in fifo on a link 1935 * down event. Reset the adapter to recover it. 1936 */ 1937 if ((Adapter->link_state == LINK_STATE_DOWN) && 1938 (Adapter->shared.mac.type == e1000_80003es2lan)) 1939 (void) e1000g_reset(Adapter); 1940 1941 mac_link_update(Adapter->mh, Adapter->link_state); 1942 } 1943 1944 start_watchdog_timer(Adapter); 1945 } 1946 } 1947 1948 static uint32_t 1949 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 1950 { 1951 uint32_t new_itr; 1952 1953 /* 1954 * Determine a propper itr according to rx/tx packet count 1955 * per interrupt, the value of itr are based on document 1956 * and testing. 1957 */ 1958 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 1959 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 1960 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1961 goto itr_done; 1962 } 1963 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 1964 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 1965 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1966 goto itr_done; 1967 } 1968 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 1969 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 1970 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 1971 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1972 } else 1973 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1974 1975 itr_done: 1976 if (cur_itr == new_itr) 1977 return (0); 1978 else 1979 return (new_itr); 1980 } 1981 1982 static void 1983 e1000g_init_unicst(struct e1000g *Adapter) 1984 { 1985 struct e1000_hw *hw; 1986 int slot; 1987 1988 hw = &Adapter->shared; 1989 1990 if (!Adapter->unicst_init) { 1991 /* Initialize the multiple unicast addresses */ 1992 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1993 1994 if ((hw->mac.type == e1000_82571) && 1995 (e1000_get_laa_state_82571(hw) == B_TRUE)) 1996 Adapter->unicst_total--; 1997 1998 Adapter->unicst_avail = Adapter->unicst_total - 1; 1999 2000 /* Store the default mac address */ 2001 e1000_rar_set(hw, hw->mac.addr, 0); 2002 if ((hw->mac.type == e1000_82571) && 2003 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2004 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2005 2006 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2007 ETHERADDRL); 2008 Adapter->unicst_addr[0].mac.set = 1; 2009 2010 for (slot = 1; slot < Adapter->unicst_total; slot++) 2011 Adapter->unicst_addr[slot].mac.set = 0; 2012 2013 Adapter->unicst_init = B_TRUE; 2014 } else { 2015 /* Recover the default mac address */ 2016 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2017 ETHERADDRL); 2018 2019 /* Store the default mac address */ 2020 e1000_rar_set(hw, hw->mac.addr, 0); 2021 if ((hw->mac.type == e1000_82571) && 2022 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2023 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2024 2025 /* Re-configure the RAR registers */ 2026 for (slot = 1; slot < Adapter->unicst_total; slot++) 2027 e1000_rar_set(hw, 2028 Adapter->unicst_addr[slot].mac.addr, slot); 2029 } 2030 2031 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2032 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2033 } 2034 2035 static int 2036 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2037 { 2038 struct e1000g *Adapter; 2039 2040 Adapter = (struct e1000g *)arg; 2041 2042 /* Store the default MAC address */ 2043 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2044 2045 /* Set MAC address in address slot 0, which is the default address */ 2046 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2047 } 2048 2049 static int 2050 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2051 mac_addr_slot_t slot) 2052 { 2053 struct e1000_hw *hw; 2054 2055 hw = &Adapter->shared; 2056 2057 rw_enter(&Adapter->chip_lock, RW_WRITER); 2058 2059 /* 2060 * The first revision of Wiseman silicon (rev 2.0) has an errata 2061 * that requires the receiver to be in reset when any of the 2062 * receive address registers (RAR regs) are accessed. The first 2063 * rev of Wiseman silicon also requires MWI to be disabled when 2064 * a global reset or a receive reset is issued. So before we 2065 * initialize the RARs, we check the rev of the Wiseman controller 2066 * and work around any necessary HW errata. 2067 */ 2068 if ((hw->mac.type == e1000_82542) && 2069 (hw->revision_id == E1000_REVISION_2)) { 2070 e1000_pci_clear_mwi(hw); 2071 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2072 msec_delay(5); 2073 } 2074 2075 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2076 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2077 2078 if (slot == 0) { 2079 if ((hw->mac.type == e1000_82571) && 2080 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2081 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2082 } 2083 2084 /* 2085 * If we are using Wiseman rev 2.0 silicon, we will have previously 2086 * put the receive in reset, and disabled MWI, to work around some 2087 * HW errata. Now we should take the receiver out of reset, and 2088 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2089 */ 2090 if ((hw->mac.type == e1000_82542) && 2091 (hw->revision_id == E1000_REVISION_2)) { 2092 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2093 msec_delay(1); 2094 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2095 e1000_pci_set_mwi(hw); 2096 e1000g_rx_setup(Adapter); 2097 } 2098 2099 rw_exit(&Adapter->chip_lock); 2100 2101 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2102 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2103 return (EIO); 2104 } 2105 2106 return (0); 2107 } 2108 2109 /* 2110 * e1000g_m_unicst_add() - will find an unused address slot, set the 2111 * address value to the one specified, reserve that slot and enable 2112 * the NIC to start filtering on the new MAC address. 2113 * Returns 0 on success. 2114 */ 2115 static int 2116 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2117 { 2118 struct e1000g *Adapter = (struct e1000g *)arg; 2119 mac_addr_slot_t slot; 2120 int err; 2121 2122 if (mac_unicst_verify(Adapter->mh, 2123 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2124 return (EINVAL); 2125 2126 rw_enter(&Adapter->chip_lock, RW_WRITER); 2127 if (Adapter->unicst_avail == 0) { 2128 /* no slots available */ 2129 rw_exit(&Adapter->chip_lock); 2130 return (ENOSPC); 2131 } 2132 2133 /* 2134 * Primary/default address is in slot 0. The next addresses 2135 * are the multiple MAC addresses. So multiple MAC address 0 2136 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2137 * MAC address resides in slot 1. 2138 */ 2139 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2140 if (Adapter->unicst_addr[slot].mac.set == 0) { 2141 Adapter->unicst_addr[slot].mac.set = 1; 2142 break; 2143 } 2144 } 2145 2146 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2147 2148 Adapter->unicst_avail--; 2149 rw_exit(&Adapter->chip_lock); 2150 2151 maddr->mma_slot = slot; 2152 2153 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2154 rw_enter(&Adapter->chip_lock, RW_WRITER); 2155 Adapter->unicst_addr[slot].mac.set = 0; 2156 Adapter->unicst_avail++; 2157 rw_exit(&Adapter->chip_lock); 2158 } 2159 2160 return (err); 2161 } 2162 2163 /* 2164 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2165 * call to e1000g_m_unicst_add(). The slot number that was returned in 2166 * e1000g_m_unicst_add() is passed in the call to remove the address. 2167 * Returns 0 on success. 2168 */ 2169 static int 2170 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2171 { 2172 struct e1000g *Adapter = (struct e1000g *)arg; 2173 int err; 2174 2175 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2176 return (EINVAL); 2177 2178 rw_enter(&Adapter->chip_lock, RW_WRITER); 2179 if (Adapter->unicst_addr[slot].mac.set == 1) { 2180 Adapter->unicst_addr[slot].mac.set = 0; 2181 Adapter->unicst_avail++; 2182 rw_exit(&Adapter->chip_lock); 2183 2184 /* Copy the default address to the passed slot */ 2185 if (err = e1000g_unicst_set(Adapter, 2186 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2187 rw_enter(&Adapter->chip_lock, RW_WRITER); 2188 Adapter->unicst_addr[slot].mac.set = 1; 2189 Adapter->unicst_avail--; 2190 rw_exit(&Adapter->chip_lock); 2191 } 2192 return (err); 2193 } 2194 rw_exit(&Adapter->chip_lock); 2195 2196 return (EINVAL); 2197 } 2198 2199 /* 2200 * e1000g_m_unicst_modify() - modifies the value of an address that 2201 * has been added by e1000g_m_unicst_add(). The new address, address 2202 * length and the slot number that was returned in the call to add 2203 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2204 * set to 0. Returns 0 on success. 2205 */ 2206 static int 2207 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2208 { 2209 struct e1000g *Adapter = (struct e1000g *)arg; 2210 mac_addr_slot_t slot; 2211 2212 if (mac_unicst_verify(Adapter->mh, 2213 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2214 return (EINVAL); 2215 2216 slot = maddr->mma_slot; 2217 2218 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2219 return (EINVAL); 2220 2221 rw_enter(&Adapter->chip_lock, RW_WRITER); 2222 if (Adapter->unicst_addr[slot].mac.set == 1) { 2223 rw_exit(&Adapter->chip_lock); 2224 2225 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2226 } 2227 rw_exit(&Adapter->chip_lock); 2228 2229 return (EINVAL); 2230 } 2231 2232 /* 2233 * e1000g_m_unicst_get() - will get the MAC address and all other 2234 * information related to the address slot passed in mac_multi_addr_t. 2235 * mma_flags should be set to 0 in the call. 2236 * On return, mma_flags can take the following values: 2237 * 1) MMAC_SLOT_UNUSED 2238 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2239 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2240 * 4) MMAC_SLOT_USED 2241 */ 2242 static int 2243 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2244 { 2245 struct e1000g *Adapter = (struct e1000g *)arg; 2246 mac_addr_slot_t slot; 2247 2248 slot = maddr->mma_slot; 2249 2250 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2251 return (EINVAL); 2252 2253 rw_enter(&Adapter->chip_lock, RW_WRITER); 2254 if (Adapter->unicst_addr[slot].mac.set == 1) { 2255 bcopy(Adapter->unicst_addr[slot].mac.addr, 2256 maddr->mma_addr, ETHERADDRL); 2257 maddr->mma_flags = MMAC_SLOT_USED; 2258 } else { 2259 maddr->mma_flags = MMAC_SLOT_UNUSED; 2260 } 2261 rw_exit(&Adapter->chip_lock); 2262 2263 return (0); 2264 } 2265 2266 static int 2267 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2268 { 2269 struct e1000_hw *hw = &Adapter->shared; 2270 unsigned i; 2271 int res = 0; 2272 2273 rw_enter(&Adapter->chip_lock, RW_WRITER); 2274 2275 if ((multiaddr[0] & 01) == 0) { 2276 res = EINVAL; 2277 goto done; 2278 } 2279 2280 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2281 res = ENOENT; 2282 goto done; 2283 } 2284 2285 bcopy(multiaddr, 2286 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2287 Adapter->mcast_count++; 2288 2289 /* 2290 * Update the MC table in the hardware 2291 */ 2292 e1000g_clear_interrupt(Adapter); 2293 2294 e1000g_setup_multicast(Adapter); 2295 2296 if ((hw->mac.type == e1000_82542) && 2297 (hw->revision_id == E1000_REVISION_2)) 2298 e1000g_rx_setup(Adapter); 2299 2300 e1000g_mask_interrupt(Adapter); 2301 2302 done: 2303 rw_exit(&Adapter->chip_lock); 2304 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2305 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2306 res = EIO; 2307 } 2308 2309 return (res); 2310 } 2311 2312 static int 2313 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2314 { 2315 struct e1000_hw *hw = &Adapter->shared; 2316 unsigned i; 2317 2318 rw_enter(&Adapter->chip_lock, RW_WRITER); 2319 2320 for (i = 0; i < Adapter->mcast_count; i++) { 2321 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2322 ETHERADDRL) == 0) { 2323 for (i++; i < Adapter->mcast_count; i++) { 2324 Adapter->mcast_table[i - 1] = 2325 Adapter->mcast_table[i]; 2326 } 2327 Adapter->mcast_count--; 2328 break; 2329 } 2330 } 2331 2332 /* 2333 * Update the MC table in the hardware 2334 */ 2335 e1000g_clear_interrupt(Adapter); 2336 2337 e1000g_setup_multicast(Adapter); 2338 2339 if ((hw->mac.type == e1000_82542) && 2340 (hw->revision_id == E1000_REVISION_2)) 2341 e1000g_rx_setup(Adapter); 2342 2343 e1000g_mask_interrupt(Adapter); 2344 2345 done: 2346 rw_exit(&Adapter->chip_lock); 2347 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2348 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2349 return (EIO); 2350 } 2351 2352 return (0); 2353 } 2354 2355 /* 2356 * e1000g_setup_multicast - setup multicast data structures 2357 * 2358 * This routine initializes all of the multicast related structures. 2359 */ 2360 void 2361 e1000g_setup_multicast(struct e1000g *Adapter) 2362 { 2363 uint8_t *mc_addr_list; 2364 uint32_t mc_addr_count; 2365 uint32_t rctl; 2366 struct e1000_hw *hw; 2367 2368 hw = &Adapter->shared; 2369 2370 /* 2371 * The e1000g has the ability to do perfect filtering of 16 2372 * addresses. The driver uses one of the e1000g's 16 receive 2373 * address registers for its node/network/mac/individual address. 2374 * So, we have room for up to 15 multicast addresses in the CAM, 2375 * additional MC addresses are handled by the MTA (Multicast Table 2376 * Array) 2377 */ 2378 2379 rctl = E1000_READ_REG(hw, E1000_RCTL); 2380 2381 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2382 2383 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2384 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2385 "Adapter requested more than %d MC Addresses.\n", 2386 MAX_NUM_MULTICAST_ADDRESSES); 2387 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2388 } else { 2389 /* 2390 * Set the number of MC addresses that we are being 2391 * requested to use 2392 */ 2393 mc_addr_count = Adapter->mcast_count; 2394 } 2395 /* 2396 * The Wiseman 2.0 silicon has an errata by which the receiver will 2397 * hang while writing to the receive address registers if the receiver 2398 * is not in reset before writing to the registers. Updating the RAR 2399 * is done during the setting up of the multicast table, hence the 2400 * receiver has to be put in reset before updating the multicast table 2401 * and then taken out of reset at the end 2402 */ 2403 /* 2404 * if WMI was enabled then dis able it before issueing the global 2405 * reset to the hardware. 2406 */ 2407 /* 2408 * Only required for WISEMAN_2_0 2409 */ 2410 if ((hw->mac.type == e1000_82542) && 2411 (hw->revision_id == E1000_REVISION_2)) { 2412 e1000_pci_clear_mwi(hw); 2413 /* 2414 * The e1000g must be in reset before changing any RA 2415 * registers. Reset receive unit. The chip will remain in 2416 * the reset state until software explicitly restarts it. 2417 */ 2418 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2419 /* Allow receiver time to go in to reset */ 2420 msec_delay(5); 2421 } 2422 2423 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2424 Adapter->unicst_total, hw->mac.rar_entry_count); 2425 2426 /* 2427 * Only for Wiseman_2_0 2428 * If MWI was enabled then re-enable it after issueing (as we 2429 * disabled it up there) the receive reset command. 2430 * Wainwright does not have a receive reset command and only thing 2431 * close to it is global reset which will require tx setup also 2432 */ 2433 if ((hw->mac.type == e1000_82542) && 2434 (hw->revision_id == E1000_REVISION_2)) { 2435 /* 2436 * if WMI was enabled then reenable it after issueing the 2437 * global or receive reset to the hardware. 2438 */ 2439 2440 /* 2441 * Take receiver out of reset 2442 * clear E1000_RCTL_RST bit (and all others) 2443 */ 2444 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2445 msec_delay(5); 2446 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2447 e1000_pci_set_mwi(hw); 2448 } 2449 2450 /* 2451 * Restore original value 2452 */ 2453 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2454 } 2455 2456 int 2457 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2458 { 2459 struct e1000g *Adapter = (struct e1000g *)arg; 2460 2461 return ((add) ? multicst_add(Adapter, addr) 2462 : multicst_remove(Adapter, addr)); 2463 } 2464 2465 int 2466 e1000g_m_promisc(void *arg, boolean_t on) 2467 { 2468 struct e1000g *Adapter = (struct e1000g *)arg; 2469 uint32_t rctl; 2470 2471 rw_enter(&Adapter->chip_lock, RW_WRITER); 2472 2473 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2474 2475 if (on) 2476 rctl |= 2477 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2478 else 2479 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2480 2481 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2482 2483 Adapter->e1000g_promisc = on; 2484 2485 rw_exit(&Adapter->chip_lock); 2486 2487 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2488 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2489 return (EIO); 2490 } 2491 2492 return (0); 2493 } 2494 2495 static boolean_t 2496 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2497 { 2498 struct e1000g *Adapter = (struct e1000g *)arg; 2499 struct e1000_hw *hw = &Adapter->shared; 2500 2501 switch (cap) { 2502 case MAC_CAPAB_HCKSUM: { 2503 uint32_t *txflags = cap_data; 2504 2505 if (Adapter->tx_hcksum_enable) 2506 *txflags = HCKSUM_IPHDRCKSUM | 2507 HCKSUM_INET_PARTIAL; 2508 else 2509 return (B_FALSE); 2510 break; 2511 } 2512 case MAC_CAPAB_POLL: 2513 /* 2514 * There's nothing for us to fill in, simply returning 2515 * B_TRUE stating that we support polling is sufficient. 2516 */ 2517 break; 2518 2519 case MAC_CAPAB_MULTIADDRESS: { 2520 multiaddress_capab_t *mmacp = cap_data; 2521 2522 /* 2523 * The number of MAC addresses made available by 2524 * this capability is one less than the total as 2525 * the primary address in slot 0 is counted in 2526 * the total. 2527 */ 2528 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2529 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2530 /* No multiple factory addresses, set mma_flag to 0 */ 2531 mmacp->maddr_flag = 0; 2532 mmacp->maddr_handle = Adapter; 2533 mmacp->maddr_add = e1000g_m_unicst_add; 2534 mmacp->maddr_remove = e1000g_m_unicst_remove; 2535 mmacp->maddr_modify = e1000g_m_unicst_modify; 2536 mmacp->maddr_get = e1000g_m_unicst_get; 2537 mmacp->maddr_reserve = NULL; 2538 break; 2539 } 2540 2541 case MAC_CAPAB_LSO: { 2542 mac_capab_lso_t *cap_lso = cap_data; 2543 2544 if (Adapter->lso_enable) { 2545 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2546 cap_lso->lso_basic_tcp_ipv4.lso_max = 2547 E1000_LSO_MAXLEN; 2548 } else 2549 return (B_FALSE); 2550 break; 2551 } 2552 2553 default: 2554 return (B_FALSE); 2555 } 2556 return (B_TRUE); 2557 } 2558 2559 static boolean_t 2560 e1000g_param_locked(mac_prop_id_t pr_num) 2561 { 2562 /* 2563 * All en_* parameters are locked (read-only) while 2564 * the device is in any sort of loopback mode ... 2565 */ 2566 switch (pr_num) { 2567 case MAC_PROP_EN_1000FDX_CAP: 2568 case MAC_PROP_EN_1000HDX_CAP: 2569 case MAC_PROP_EN_100FDX_CAP: 2570 case MAC_PROP_EN_100HDX_CAP: 2571 case MAC_PROP_EN_10FDX_CAP: 2572 case MAC_PROP_EN_10HDX_CAP: 2573 case MAC_PROP_AUTONEG: 2574 case MAC_PROP_FLOWCTRL: 2575 return (B_TRUE); 2576 } 2577 return (B_FALSE); 2578 } 2579 2580 /* 2581 * callback function for set/get of properties 2582 */ 2583 static int 2584 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2585 uint_t pr_valsize, const void *pr_val) 2586 { 2587 struct e1000g *Adapter = arg; 2588 struct e1000_mac_info *mac = &Adapter->shared.mac; 2589 struct e1000_phy_info *phy = &Adapter->shared.phy; 2590 struct e1000_fc_info *fc = &Adapter->shared.fc; 2591 int err = 0; 2592 link_flowctrl_t flowctrl; 2593 uint32_t cur_mtu, new_mtu; 2594 uint64_t tmp = 0; 2595 2596 rw_enter(&Adapter->chip_lock, RW_WRITER); 2597 if (Adapter->loopback_mode != E1000G_LB_NONE && 2598 e1000g_param_locked(pr_num)) { 2599 /* 2600 * All en_* parameters are locked (read-only) 2601 * while the device is in any sort of loopback mode. 2602 */ 2603 rw_exit(&Adapter->chip_lock); 2604 return (EBUSY); 2605 } 2606 2607 switch (pr_num) { 2608 case MAC_PROP_EN_1000FDX_CAP: 2609 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2610 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2611 goto reset; 2612 case MAC_PROP_EN_1000HDX_CAP: 2613 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2614 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2615 goto reset; 2616 case MAC_PROP_EN_100FDX_CAP: 2617 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2618 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2619 goto reset; 2620 case MAC_PROP_EN_100HDX_CAP: 2621 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2622 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2623 goto reset; 2624 case MAC_PROP_EN_10FDX_CAP: 2625 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2626 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2627 goto reset; 2628 case MAC_PROP_EN_10HDX_CAP: 2629 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2630 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2631 goto reset; 2632 case MAC_PROP_AUTONEG: 2633 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2634 goto reset; 2635 case MAC_PROP_FLOWCTRL: 2636 fc->send_xon = B_TRUE; 2637 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2638 2639 switch (flowctrl) { 2640 default: 2641 err = EINVAL; 2642 break; 2643 case LINK_FLOWCTRL_NONE: 2644 fc->type = e1000_fc_none; 2645 break; 2646 case LINK_FLOWCTRL_RX: 2647 fc->type = e1000_fc_rx_pause; 2648 break; 2649 case LINK_FLOWCTRL_TX: 2650 fc->type = e1000_fc_tx_pause; 2651 break; 2652 case LINK_FLOWCTRL_BI: 2653 fc->type = e1000_fc_full; 2654 break; 2655 } 2656 reset: 2657 if (err == 0) { 2658 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2659 err = EINVAL; 2660 } 2661 break; 2662 case MAC_PROP_ADV_1000FDX_CAP: 2663 case MAC_PROP_ADV_1000HDX_CAP: 2664 case MAC_PROP_ADV_100FDX_CAP: 2665 case MAC_PROP_ADV_100HDX_CAP: 2666 case MAC_PROP_ADV_10FDX_CAP: 2667 case MAC_PROP_ADV_10HDX_CAP: 2668 case MAC_PROP_STATUS: 2669 case MAC_PROP_SPEED: 2670 case MAC_PROP_DUPLEX: 2671 err = ENOTSUP; /* read-only prop. Can't set this. */ 2672 break; 2673 case MAC_PROP_MTU: 2674 cur_mtu = Adapter->default_mtu; 2675 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2676 if (new_mtu == cur_mtu) { 2677 err = 0; 2678 break; 2679 } 2680 2681 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2682 ETHERFCSL; 2683 if ((tmp < DEFAULT_FRAME_SIZE) || 2684 (tmp > MAXIMUM_FRAME_SIZE)) { 2685 err = EINVAL; 2686 break; 2687 } 2688 2689 /* ich8 doed not support jumbo frames */ 2690 if ((mac->type == e1000_ich8lan) && 2691 (tmp > DEFAULT_FRAME_SIZE)) { 2692 err = EINVAL; 2693 break; 2694 } 2695 /* ich9 does not do jumbo frames on one phy type */ 2696 if ((mac->type == e1000_ich9lan) && 2697 (phy->type == e1000_phy_ife) && 2698 (tmp > DEFAULT_FRAME_SIZE)) { 2699 err = EINVAL; 2700 break; 2701 } 2702 if (Adapter->chip_state != E1000G_STOP) { 2703 err = EBUSY; 2704 break; 2705 } 2706 2707 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2708 if (err == 0) { 2709 Adapter->max_frame_size = tmp; 2710 Adapter->default_mtu = new_mtu; 2711 e1000g_set_bufsize(Adapter); 2712 } 2713 break; 2714 case MAC_PROP_PRIVATE: 2715 err = e1000g_set_priv_prop(Adapter, pr_name, 2716 pr_valsize, pr_val); 2717 break; 2718 default: 2719 err = ENOTSUP; 2720 break; 2721 } 2722 rw_exit(&Adapter->chip_lock); 2723 return (err); 2724 } 2725 2726 static int 2727 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2728 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2729 { 2730 struct e1000g *Adapter = arg; 2731 struct e1000_mac_info *mac = &Adapter->shared.mac; 2732 struct e1000_fc_info *fc = &Adapter->shared.fc; 2733 int err = 0; 2734 link_flowctrl_t flowctrl; 2735 uint64_t tmp = 0; 2736 2737 if (pr_valsize == 0) 2738 return (EINVAL); 2739 2740 bzero(pr_val, pr_valsize); 2741 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2742 return (e1000g_get_def_val(Adapter, pr_num, 2743 pr_valsize, pr_val)); 2744 } 2745 2746 switch (pr_num) { 2747 case MAC_PROP_DUPLEX: 2748 if (pr_valsize >= sizeof (link_duplex_t)) { 2749 bcopy(&Adapter->link_duplex, pr_val, 2750 sizeof (link_duplex_t)); 2751 } else 2752 err = EINVAL; 2753 break; 2754 case MAC_PROP_SPEED: 2755 if (pr_valsize >= sizeof (uint64_t)) { 2756 tmp = Adapter->link_speed * 1000000ull; 2757 bcopy(&tmp, pr_val, sizeof (tmp)); 2758 } else 2759 err = EINVAL; 2760 break; 2761 case MAC_PROP_AUTONEG: 2762 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2763 break; 2764 case MAC_PROP_FLOWCTRL: 2765 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2766 switch (fc->type) { 2767 case e1000_fc_none: 2768 flowctrl = LINK_FLOWCTRL_NONE; 2769 break; 2770 case e1000_fc_rx_pause: 2771 flowctrl = LINK_FLOWCTRL_RX; 2772 break; 2773 case e1000_fc_tx_pause: 2774 flowctrl = LINK_FLOWCTRL_TX; 2775 break; 2776 case e1000_fc_full: 2777 flowctrl = LINK_FLOWCTRL_BI; 2778 break; 2779 } 2780 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2781 } else 2782 err = EINVAL; 2783 break; 2784 case MAC_PROP_ADV_1000FDX_CAP: 2785 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2786 break; 2787 case MAC_PROP_EN_1000FDX_CAP: 2788 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2789 break; 2790 case MAC_PROP_ADV_1000HDX_CAP: 2791 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2792 break; 2793 case MAC_PROP_EN_1000HDX_CAP: 2794 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2795 break; 2796 case MAC_PROP_ADV_100FDX_CAP: 2797 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2798 break; 2799 case MAC_PROP_EN_100FDX_CAP: 2800 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2801 break; 2802 case MAC_PROP_ADV_100HDX_CAP: 2803 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2804 break; 2805 case MAC_PROP_EN_100HDX_CAP: 2806 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2807 break; 2808 case MAC_PROP_ADV_10FDX_CAP: 2809 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2810 break; 2811 case MAC_PROP_EN_10FDX_CAP: 2812 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2813 break; 2814 case MAC_PROP_ADV_10HDX_CAP: 2815 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2816 break; 2817 case MAC_PROP_EN_10HDX_CAP: 2818 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2819 break; 2820 case MAC_PROP_ADV_100T4_CAP: 2821 case MAC_PROP_EN_100T4_CAP: 2822 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2823 break; 2824 case MAC_PROP_PRIVATE: 2825 err = e1000g_get_priv_prop(Adapter, pr_name, 2826 pr_flags, pr_valsize, pr_val); 2827 break; 2828 default: 2829 err = ENOTSUP; 2830 break; 2831 } 2832 return (err); 2833 } 2834 2835 /* ARGUSED */ 2836 static int 2837 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2838 uint_t pr_valsize, const void *pr_val) 2839 { 2840 int err = 0; 2841 long result; 2842 struct e1000_hw *hw = &Adapter->shared; 2843 2844 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2845 if (pr_val == NULL) { 2846 err = EINVAL; 2847 return (err); 2848 } 2849 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2850 if (result < MIN_TX_BCOPY_THRESHOLD || 2851 result > MAX_TX_BCOPY_THRESHOLD) 2852 err = EINVAL; 2853 else { 2854 Adapter->tx_bcopy_thresh = (uint32_t)result; 2855 } 2856 return (err); 2857 } 2858 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2859 if (pr_val == NULL) { 2860 err = EINVAL; 2861 return (err); 2862 } 2863 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2864 if (result < 0 || result > 1) 2865 err = EINVAL; 2866 else { 2867 Adapter->tx_intr_enable = (result == 1) ? 2868 B_TRUE: B_FALSE; 2869 if (Adapter->tx_intr_enable) 2870 e1000g_mask_tx_interrupt(Adapter); 2871 else 2872 e1000g_clear_tx_interrupt(Adapter); 2873 if (e1000g_check_acc_handle( 2874 Adapter->osdep.reg_handle) != DDI_FM_OK) 2875 ddi_fm_service_impact(Adapter->dip, 2876 DDI_SERVICE_DEGRADED); 2877 } 2878 return (err); 2879 } 2880 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2881 if (pr_val == NULL) { 2882 err = EINVAL; 2883 return (err); 2884 } 2885 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2886 if (result < MIN_TX_INTR_DELAY || 2887 result > MAX_TX_INTR_DELAY) 2888 err = EINVAL; 2889 else { 2890 Adapter->tx_intr_delay = (uint32_t)result; 2891 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2892 if (e1000g_check_acc_handle( 2893 Adapter->osdep.reg_handle) != DDI_FM_OK) 2894 ddi_fm_service_impact(Adapter->dip, 2895 DDI_SERVICE_DEGRADED); 2896 } 2897 return (err); 2898 } 2899 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2900 if (pr_val == NULL) { 2901 err = EINVAL; 2902 return (err); 2903 } 2904 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2905 if (result < MIN_TX_INTR_ABS_DELAY || 2906 result > MAX_TX_INTR_ABS_DELAY) 2907 err = EINVAL; 2908 else { 2909 Adapter->tx_intr_abs_delay = (uint32_t)result; 2910 E1000_WRITE_REG(hw, E1000_TADV, 2911 Adapter->tx_intr_abs_delay); 2912 if (e1000g_check_acc_handle( 2913 Adapter->osdep.reg_handle) != DDI_FM_OK) 2914 ddi_fm_service_impact(Adapter->dip, 2915 DDI_SERVICE_DEGRADED); 2916 } 2917 return (err); 2918 } 2919 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2920 if (pr_val == NULL) { 2921 err = EINVAL; 2922 return (err); 2923 } 2924 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2925 if (result < MIN_RX_BCOPY_THRESHOLD || 2926 result > MAX_RX_BCOPY_THRESHOLD) 2927 err = EINVAL; 2928 else 2929 Adapter->rx_bcopy_thresh = (uint32_t)result; 2930 return (err); 2931 } 2932 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2933 if (pr_val == NULL) { 2934 err = EINVAL; 2935 return (err); 2936 } 2937 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2938 if (result < MIN_RX_LIMIT_ON_INTR || 2939 result > MAX_RX_LIMIT_ON_INTR) 2940 err = EINVAL; 2941 else 2942 Adapter->rx_limit_onintr = (uint32_t)result; 2943 return (err); 2944 } 2945 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 2946 if (pr_val == NULL) { 2947 err = EINVAL; 2948 return (err); 2949 } 2950 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2951 if (result < MIN_RX_INTR_DELAY || 2952 result > MAX_RX_INTR_DELAY) 2953 err = EINVAL; 2954 else { 2955 Adapter->rx_intr_delay = (uint32_t)result; 2956 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 2957 if (e1000g_check_acc_handle( 2958 Adapter->osdep.reg_handle) != DDI_FM_OK) 2959 ddi_fm_service_impact(Adapter->dip, 2960 DDI_SERVICE_DEGRADED); 2961 } 2962 return (err); 2963 } 2964 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 2965 if (pr_val == NULL) { 2966 err = EINVAL; 2967 return (err); 2968 } 2969 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2970 if (result < MIN_RX_INTR_ABS_DELAY || 2971 result > MAX_RX_INTR_ABS_DELAY) 2972 err = EINVAL; 2973 else { 2974 Adapter->rx_intr_abs_delay = (uint32_t)result; 2975 E1000_WRITE_REG(hw, E1000_RADV, 2976 Adapter->rx_intr_abs_delay); 2977 if (e1000g_check_acc_handle( 2978 Adapter->osdep.reg_handle) != DDI_FM_OK) 2979 ddi_fm_service_impact(Adapter->dip, 2980 DDI_SERVICE_DEGRADED); 2981 } 2982 return (err); 2983 } 2984 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 2985 if (pr_val == NULL) { 2986 err = EINVAL; 2987 return (err); 2988 } 2989 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2990 if (result < MIN_INTR_THROTTLING || 2991 result > MAX_INTR_THROTTLING) 2992 err = EINVAL; 2993 else { 2994 if (hw->mac.type >= e1000_82540) { 2995 Adapter->intr_throttling_rate = 2996 (uint32_t)result; 2997 E1000_WRITE_REG(hw, E1000_ITR, 2998 Adapter->intr_throttling_rate); 2999 if (e1000g_check_acc_handle( 3000 Adapter->osdep.reg_handle) != DDI_FM_OK) 3001 ddi_fm_service_impact(Adapter->dip, 3002 DDI_SERVICE_DEGRADED); 3003 } else 3004 err = EINVAL; 3005 } 3006 return (err); 3007 } 3008 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3009 if (pr_val == NULL) { 3010 err = EINVAL; 3011 return (err); 3012 } 3013 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3014 if (result < 0 || result > 1) 3015 err = EINVAL; 3016 else { 3017 if (hw->mac.type >= e1000_82540) { 3018 Adapter->intr_adaptive = (result == 1) ? 3019 B_TRUE : B_FALSE; 3020 } else { 3021 err = EINVAL; 3022 } 3023 } 3024 return (err); 3025 } 3026 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3027 if (pr_val == NULL) { 3028 err = EINVAL; 3029 return (err); 3030 } 3031 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3032 if (result < MIN_TX_RECYCLE_THRESHOLD || 3033 result > MAX_TX_RECYCLE_THRESHOLD) 3034 err = EINVAL; 3035 else 3036 Adapter->tx_recycle_thresh = (uint32_t)result; 3037 return (err); 3038 } 3039 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3040 if (pr_val == NULL) { 3041 err = EINVAL; 3042 return (err); 3043 } 3044 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3045 if (result < MIN_TX_RECYCLE_NUM || 3046 result > MAX_TX_RECYCLE_NUM) 3047 err = EINVAL; 3048 else 3049 Adapter->tx_recycle_num = (uint32_t)result; 3050 return (err); 3051 } 3052 return (ENOTSUP); 3053 } 3054 3055 static int 3056 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3057 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3058 { 3059 char valstr[MAXNAMELEN]; 3060 int err = ENOTSUP; 3061 uint_t strsize; 3062 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3063 int value; 3064 3065 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3066 if (is_default) 3067 goto done; 3068 value = Adapter->param_adv_pause; 3069 err = 0; 3070 goto done; 3071 } 3072 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3073 if (is_default) 3074 goto done; 3075 value = Adapter->param_adv_asym_pause; 3076 err = 0; 3077 goto done; 3078 } 3079 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3080 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3081 Adapter->tx_bcopy_thresh); 3082 err = 0; 3083 goto done; 3084 } 3085 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3086 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3087 Adapter->tx_intr_enable); 3088 err = 0; 3089 goto done; 3090 } 3091 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3092 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3093 Adapter->tx_intr_delay); 3094 err = 0; 3095 goto done; 3096 } 3097 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3098 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3099 Adapter->tx_intr_abs_delay); 3100 err = 0; 3101 goto done; 3102 } 3103 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3104 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3105 Adapter->rx_bcopy_thresh); 3106 err = 0; 3107 goto done; 3108 } 3109 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3110 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3111 Adapter->rx_limit_onintr); 3112 err = 0; 3113 goto done; 3114 } 3115 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3116 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3117 Adapter->rx_intr_delay); 3118 err = 0; 3119 goto done; 3120 } 3121 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3122 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3123 Adapter->rx_intr_abs_delay); 3124 err = 0; 3125 goto done; 3126 } 3127 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3128 value = (is_default ? DEFAULT_INTR_THROTTLING : 3129 Adapter->intr_throttling_rate); 3130 err = 0; 3131 goto done; 3132 } 3133 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3134 value = (is_default ? 1 : Adapter->intr_adaptive); 3135 err = 0; 3136 goto done; 3137 } 3138 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3139 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3140 Adapter->tx_recycle_thresh); 3141 err = 0; 3142 goto done; 3143 } 3144 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3145 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3146 Adapter->tx_recycle_num); 3147 err = 0; 3148 goto done; 3149 } 3150 done: 3151 if (err == 0) { 3152 (void) snprintf(pr_val, pr_valsize, "%d", value); 3153 } 3154 return (err); 3155 } 3156 3157 /* 3158 * e1000g_get_conf - get configurations set in e1000g.conf 3159 * This routine gets user-configured values out of the configuration 3160 * file e1000g.conf. 3161 * 3162 * For each configurable value, there is a minimum, a maximum, and a 3163 * default. 3164 * If user does not configure a value, use the default. 3165 * If user configures below the minimum, use the minumum. 3166 * If user configures above the maximum, use the maxumum. 3167 */ 3168 static void 3169 e1000g_get_conf(struct e1000g *Adapter) 3170 { 3171 struct e1000_hw *hw = &Adapter->shared; 3172 boolean_t tbi_compatibility = B_FALSE; 3173 3174 /* 3175 * get each configurable property from e1000g.conf 3176 */ 3177 3178 /* 3179 * NumTxDescriptors 3180 */ 3181 Adapter->tx_desc_num = 3182 e1000g_get_prop(Adapter, "NumTxDescriptors", 3183 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3184 DEFAULT_NUM_TX_DESCRIPTOR); 3185 3186 /* 3187 * NumRxDescriptors 3188 */ 3189 Adapter->rx_desc_num = 3190 e1000g_get_prop(Adapter, "NumRxDescriptors", 3191 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3192 DEFAULT_NUM_RX_DESCRIPTOR); 3193 3194 /* 3195 * NumRxFreeList 3196 */ 3197 Adapter->rx_freelist_num = 3198 e1000g_get_prop(Adapter, "NumRxFreeList", 3199 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3200 DEFAULT_NUM_RX_FREELIST); 3201 3202 /* 3203 * NumTxPacketList 3204 */ 3205 Adapter->tx_freelist_num = 3206 e1000g_get_prop(Adapter, "NumTxPacketList", 3207 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3208 DEFAULT_NUM_TX_FREELIST); 3209 3210 /* 3211 * FlowControl 3212 */ 3213 hw->fc.send_xon = B_TRUE; 3214 hw->fc.type = 3215 e1000g_get_prop(Adapter, "FlowControl", 3216 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3217 /* 4 is the setting that says "let the eeprom decide" */ 3218 if (hw->fc.type == 4) 3219 hw->fc.type = e1000_fc_default; 3220 3221 /* 3222 * Max Num Receive Packets on Interrupt 3223 */ 3224 Adapter->rx_limit_onintr = 3225 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3226 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3227 DEFAULT_RX_LIMIT_ON_INTR); 3228 3229 /* 3230 * PHY master slave setting 3231 */ 3232 hw->phy.ms_type = 3233 e1000g_get_prop(Adapter, "SetMasterSlave", 3234 e1000_ms_hw_default, e1000_ms_auto, 3235 e1000_ms_hw_default); 3236 3237 /* 3238 * Parameter which controls TBI mode workaround, which is only 3239 * needed on certain switches such as Cisco 6500/Foundry 3240 */ 3241 tbi_compatibility = 3242 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3243 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3244 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3245 3246 /* 3247 * MSI Enable 3248 */ 3249 Adapter->msi_enable = 3250 e1000g_get_prop(Adapter, "MSIEnable", 3251 0, 1, DEFAULT_MSI_ENABLE); 3252 3253 /* 3254 * Interrupt Throttling Rate 3255 */ 3256 Adapter->intr_throttling_rate = 3257 e1000g_get_prop(Adapter, "intr_throttling_rate", 3258 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3259 DEFAULT_INTR_THROTTLING); 3260 3261 /* 3262 * Adaptive Interrupt Blanking Enable/Disable 3263 * It is enabled by default 3264 */ 3265 Adapter->intr_adaptive = 3266 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3267 B_TRUE : B_FALSE; 3268 3269 /* 3270 * Tx recycle threshold 3271 */ 3272 Adapter->tx_recycle_thresh = 3273 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3274 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3275 DEFAULT_TX_RECYCLE_THRESHOLD); 3276 3277 /* 3278 * Tx recycle descriptor number 3279 */ 3280 Adapter->tx_recycle_num = 3281 e1000g_get_prop(Adapter, "tx_recycle_num", 3282 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3283 DEFAULT_TX_RECYCLE_NUM); 3284 3285 /* 3286 * Hardware checksum enable/disable parameter 3287 */ 3288 Adapter->tx_hcksum_enable = 3289 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3290 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3291 /* 3292 * Checksum on/off selection via global parameters. 3293 * 3294 * If the chip is flagged as not capable of (correctly) 3295 * handling checksumming, we don't enable it on either 3296 * Rx or Tx side. Otherwise, we take this chip's settings 3297 * from the patchable global defaults. 3298 * 3299 * We advertise our capabilities only if TX offload is 3300 * enabled. On receive, the stack will accept checksummed 3301 * packets anyway, even if we haven't said we can deliver 3302 * them. 3303 */ 3304 switch (hw->mac.type) { 3305 case e1000_82540: 3306 case e1000_82544: 3307 case e1000_82545: 3308 case e1000_82545_rev_3: 3309 case e1000_82546: 3310 case e1000_82546_rev_3: 3311 case e1000_82571: 3312 case e1000_82572: 3313 case e1000_82573: 3314 case e1000_80003es2lan: 3315 break; 3316 /* 3317 * For the following Intel PRO/1000 chipsets, we have not 3318 * tested the hardware checksum offload capability, so we 3319 * disable the capability for them. 3320 * e1000_82542, 3321 * e1000_82543, 3322 * e1000_82541, 3323 * e1000_82541_rev_2, 3324 * e1000_82547, 3325 * e1000_82547_rev_2, 3326 */ 3327 default: 3328 Adapter->tx_hcksum_enable = B_FALSE; 3329 } 3330 3331 /* 3332 * Large Send Offloading(LSO) Enable/Disable 3333 * If the tx hardware checksum is not enabled, LSO should be 3334 * disabled. 3335 */ 3336 Adapter->lso_enable = 3337 e1000g_get_prop(Adapter, "lso_enable", 3338 0, 1, DEFAULT_LSO_ENABLE); 3339 3340 switch (hw->mac.type) { 3341 case e1000_82546: 3342 case e1000_82546_rev_3: 3343 if (Adapter->lso_enable) 3344 Adapter->lso_premature_issue = B_TRUE; 3345 case e1000_82571: 3346 case e1000_82572: 3347 case e1000_82573: 3348 break; 3349 default: 3350 Adapter->lso_enable = B_FALSE; 3351 } 3352 3353 if (!Adapter->tx_hcksum_enable) { 3354 Adapter->lso_premature_issue = B_FALSE; 3355 Adapter->lso_enable = B_FALSE; 3356 } 3357 } 3358 3359 /* 3360 * e1000g_get_prop - routine to read properties 3361 * 3362 * Get a user-configure property value out of the configuration 3363 * file e1000g.conf. 3364 * 3365 * Caller provides name of the property, a default value, a minimum 3366 * value, and a maximum value. 3367 * 3368 * Return configured value of the property, with default, minimum and 3369 * maximum properly applied. 3370 */ 3371 static int 3372 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3373 char *propname, /* name of the property */ 3374 int minval, /* minimum acceptable value */ 3375 int maxval, /* maximim acceptable value */ 3376 int defval) /* default value */ 3377 { 3378 int propval; /* value returned for requested property */ 3379 int *props; /* point to array of properties returned */ 3380 uint_t nprops; /* number of property value returned */ 3381 3382 /* 3383 * get the array of properties from the config file 3384 */ 3385 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3386 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3387 /* got some properties, test if we got enough */ 3388 if (Adapter->instance < nprops) { 3389 propval = props[Adapter->instance]; 3390 } else { 3391 /* not enough properties configured */ 3392 propval = defval; 3393 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3394 "Not Enough %s values found in e1000g.conf" 3395 " - set to %d\n", 3396 propname, propval); 3397 } 3398 3399 /* free memory allocated for properties */ 3400 ddi_prop_free(props); 3401 3402 } else { 3403 propval = defval; 3404 } 3405 3406 /* 3407 * enforce limits 3408 */ 3409 if (propval > maxval) { 3410 propval = maxval; 3411 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3412 "Too High %s value in e1000g.conf - set to %d\n", 3413 propname, propval); 3414 } 3415 3416 if (propval < minval) { 3417 propval = minval; 3418 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3419 "Too Low %s value in e1000g.conf - set to %d\n", 3420 propname, propval); 3421 } 3422 3423 return (propval); 3424 } 3425 3426 static boolean_t 3427 e1000g_link_check(struct e1000g *Adapter) 3428 { 3429 uint16_t speed, duplex, phydata; 3430 boolean_t link_changed = B_FALSE; 3431 struct e1000_hw *hw; 3432 uint32_t reg_tarc; 3433 3434 hw = &Adapter->shared; 3435 3436 if (e1000g_link_up(Adapter)) { 3437 /* 3438 * The Link is up, check whether it was marked as down earlier 3439 */ 3440 if (Adapter->link_state != LINK_STATE_UP) { 3441 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3442 Adapter->link_speed = speed; 3443 Adapter->link_duplex = duplex; 3444 Adapter->link_state = LINK_STATE_UP; 3445 link_changed = B_TRUE; 3446 3447 Adapter->tx_link_down_timeout = 0; 3448 3449 if ((hw->mac.type == e1000_82571) || 3450 (hw->mac.type == e1000_82572)) { 3451 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3452 if (speed == SPEED_1000) 3453 reg_tarc |= (1 << 21); 3454 else 3455 reg_tarc &= ~(1 << 21); 3456 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3457 } 3458 } 3459 Adapter->smartspeed = 0; 3460 } else { 3461 if (Adapter->link_state != LINK_STATE_DOWN) { 3462 Adapter->link_speed = 0; 3463 Adapter->link_duplex = 0; 3464 Adapter->link_state = LINK_STATE_DOWN; 3465 link_changed = B_TRUE; 3466 3467 /* 3468 * SmartSpeed workaround for Tabor/TanaX, When the 3469 * driver loses link disable auto master/slave 3470 * resolution. 3471 */ 3472 if (hw->phy.type == e1000_phy_igp) { 3473 e1000_read_phy_reg(hw, 3474 PHY_1000T_CTRL, &phydata); 3475 phydata |= CR_1000T_MS_ENABLE; 3476 e1000_write_phy_reg(hw, 3477 PHY_1000T_CTRL, phydata); 3478 } 3479 } else { 3480 e1000g_smartspeed(Adapter); 3481 } 3482 3483 if (Adapter->chip_state == E1000G_START) { 3484 if (Adapter->tx_link_down_timeout < 3485 MAX_TX_LINK_DOWN_TIMEOUT) { 3486 Adapter->tx_link_down_timeout++; 3487 } else if (Adapter->tx_link_down_timeout == 3488 MAX_TX_LINK_DOWN_TIMEOUT) { 3489 e1000g_tx_clean(Adapter); 3490 Adapter->tx_link_down_timeout++; 3491 } 3492 } 3493 } 3494 3495 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3496 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3497 3498 return (link_changed); 3499 } 3500 3501 /* 3502 * e1000g_reset_link - Using the link properties to setup the link 3503 */ 3504 int 3505 e1000g_reset_link(struct e1000g *Adapter) 3506 { 3507 struct e1000_mac_info *mac; 3508 struct e1000_phy_info *phy; 3509 boolean_t invalid; 3510 3511 mac = &Adapter->shared.mac; 3512 phy = &Adapter->shared.phy; 3513 invalid = B_FALSE; 3514 3515 if (Adapter->param_adv_autoneg == 1) { 3516 mac->autoneg = B_TRUE; 3517 phy->autoneg_advertised = 0; 3518 3519 /* 3520 * 1000hdx is not supported for autonegotiation 3521 */ 3522 if (Adapter->param_adv_1000fdx == 1) 3523 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3524 3525 if (Adapter->param_adv_100fdx == 1) 3526 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3527 3528 if (Adapter->param_adv_100hdx == 1) 3529 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3530 3531 if (Adapter->param_adv_10fdx == 1) 3532 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3533 3534 if (Adapter->param_adv_10hdx == 1) 3535 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3536 3537 if (phy->autoneg_advertised == 0) 3538 invalid = B_TRUE; 3539 } else { 3540 mac->autoneg = B_FALSE; 3541 3542 /* 3543 * 1000fdx and 1000hdx are not supported for forced link 3544 */ 3545 if (Adapter->param_adv_100fdx == 1) 3546 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3547 else if (Adapter->param_adv_100hdx == 1) 3548 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3549 else if (Adapter->param_adv_10fdx == 1) 3550 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3551 else if (Adapter->param_adv_10hdx == 1) 3552 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3553 else 3554 invalid = B_TRUE; 3555 3556 } 3557 3558 if (invalid) { 3559 e1000g_log(Adapter, CE_WARN, 3560 "Invalid link sets. Setup link to" 3561 "support autonegotiation with all link capabilities."); 3562 mac->autoneg = B_TRUE; 3563 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3564 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3565 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3566 } 3567 3568 return (e1000_setup_link(&Adapter->shared)); 3569 } 3570 3571 static void 3572 e1000g_local_timer(void *ws) 3573 { 3574 struct e1000g *Adapter = (struct e1000g *)ws; 3575 struct e1000_hw *hw; 3576 e1000g_ether_addr_t ether_addr; 3577 boolean_t link_changed; 3578 3579 hw = &Adapter->shared; 3580 3581 if (Adapter->chip_state == E1000G_ERROR) { 3582 Adapter->reset_count++; 3583 if (e1000g_global_reset(Adapter)) 3584 ddi_fm_service_impact(Adapter->dip, 3585 DDI_SERVICE_RESTORED); 3586 else 3587 ddi_fm_service_impact(Adapter->dip, 3588 DDI_SERVICE_LOST); 3589 return; 3590 } 3591 3592 if (e1000g_stall_check(Adapter)) { 3593 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3594 "Tx stall detected. Activate automatic recovery.\n"); 3595 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3596 Adapter->reset_count++; 3597 if (e1000g_reset(Adapter)) 3598 ddi_fm_service_impact(Adapter->dip, 3599 DDI_SERVICE_RESTORED); 3600 else 3601 ddi_fm_service_impact(Adapter->dip, 3602 DDI_SERVICE_LOST); 3603 return; 3604 } 3605 3606 link_changed = B_FALSE; 3607 rw_enter(&Adapter->chip_lock, RW_READER); 3608 if (Adapter->link_complete) 3609 link_changed = e1000g_link_check(Adapter); 3610 rw_exit(&Adapter->chip_lock); 3611 3612 if (link_changed) { 3613 /* 3614 * Workaround for esb2. Data stuck in fifo on a link 3615 * down event. Reset the adapter to recover it. 3616 */ 3617 if ((Adapter->link_state == LINK_STATE_DOWN) && 3618 (hw->mac.type == e1000_80003es2lan)) 3619 (void) e1000g_reset(Adapter); 3620 3621 mac_link_update(Adapter->mh, Adapter->link_state); 3622 } 3623 3624 /* 3625 * With 82571 controllers, any locally administered address will 3626 * be overwritten when there is a reset on the other port. 3627 * Detect this circumstance and correct it. 3628 */ 3629 if ((hw->mac.type == e1000_82571) && 3630 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3631 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3632 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3633 3634 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3635 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3636 3637 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3638 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3639 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3640 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3641 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3642 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3643 e1000_rar_set(hw, hw->mac.addr, 0); 3644 } 3645 } 3646 3647 /* 3648 * Long TTL workaround for 82541/82547 3649 */ 3650 e1000_igp_ttl_workaround_82547(hw); 3651 3652 /* 3653 * Check for Adaptive IFS settings If there are lots of collisions 3654 * change the value in steps... 3655 * These properties should only be set for 10/100 3656 */ 3657 if ((hw->phy.media_type == e1000_media_type_copper) && 3658 ((Adapter->link_speed == SPEED_100) || 3659 (Adapter->link_speed == SPEED_10))) { 3660 e1000_update_adaptive(hw); 3661 } 3662 /* 3663 * Set Timer Interrupts 3664 */ 3665 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3666 3667 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3668 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3669 3670 restart_watchdog_timer(Adapter); 3671 } 3672 3673 /* 3674 * The function e1000g_link_timer() is called when the timer for link setup 3675 * is expired, which indicates the completion of the link setup. The link 3676 * state will not be updated until the link setup is completed. And the 3677 * link state will not be sent to the upper layer through mac_link_update() 3678 * in this function. It will be updated in the local timer routine or the 3679 * interrupt service routine after the interface is started (plumbed). 3680 */ 3681 static void 3682 e1000g_link_timer(void *arg) 3683 { 3684 struct e1000g *Adapter = (struct e1000g *)arg; 3685 3686 mutex_enter(&Adapter->link_lock); 3687 Adapter->link_complete = B_TRUE; 3688 Adapter->link_tid = 0; 3689 mutex_exit(&Adapter->link_lock); 3690 } 3691 3692 /* 3693 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3694 * 3695 * This function read the forced speed and duplex for 10/100 Mbps speeds 3696 * and also for 1000 Mbps speeds from the e1000g.conf file 3697 */ 3698 static void 3699 e1000g_force_speed_duplex(struct e1000g *Adapter) 3700 { 3701 int forced; 3702 struct e1000_mac_info *mac = &Adapter->shared.mac; 3703 struct e1000_phy_info *phy = &Adapter->shared.phy; 3704 3705 /* 3706 * get value out of config file 3707 */ 3708 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3709 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3710 3711 switch (forced) { 3712 case GDIAG_10_HALF: 3713 /* 3714 * Disable Auto Negotiation 3715 */ 3716 mac->autoneg = B_FALSE; 3717 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3718 break; 3719 case GDIAG_10_FULL: 3720 /* 3721 * Disable Auto Negotiation 3722 */ 3723 mac->autoneg = B_FALSE; 3724 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3725 break; 3726 case GDIAG_100_HALF: 3727 /* 3728 * Disable Auto Negotiation 3729 */ 3730 mac->autoneg = B_FALSE; 3731 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3732 break; 3733 case GDIAG_100_FULL: 3734 /* 3735 * Disable Auto Negotiation 3736 */ 3737 mac->autoneg = B_FALSE; 3738 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3739 break; 3740 case GDIAG_1000_FULL: 3741 /* 3742 * The gigabit spec requires autonegotiation. Therefore, 3743 * when the user wants to force the speed to 1000Mbps, we 3744 * enable AutoNeg, but only allow the harware to advertise 3745 * 1000Mbps. This is different from 10/100 operation, where 3746 * we are allowed to link without any negotiation. 3747 */ 3748 mac->autoneg = B_TRUE; 3749 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3750 break; 3751 default: /* obey the setting of AutoNegAdvertised */ 3752 mac->autoneg = B_TRUE; 3753 phy->autoneg_advertised = 3754 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3755 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3756 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3757 break; 3758 } /* switch */ 3759 } 3760 3761 /* 3762 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3763 * 3764 * This function reads MaxFrameSize from e1000g.conf 3765 */ 3766 static void 3767 e1000g_get_max_frame_size(struct e1000g *Adapter) 3768 { 3769 int max_frame; 3770 struct e1000_mac_info *mac = &Adapter->shared.mac; 3771 struct e1000_phy_info *phy = &Adapter->shared.phy; 3772 3773 /* 3774 * get value out of config file 3775 */ 3776 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3777 3778 switch (max_frame) { 3779 case 0: 3780 Adapter->default_mtu = ETHERMTU; 3781 break; 3782 /* 3783 * To avoid excessive memory allocation for rx buffers, 3784 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3785 */ 3786 case 1: 3787 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3788 sizeof (struct ether_vlan_header) - ETHERFCSL - 3789 E1000G_IPALIGNPRESERVEROOM; 3790 break; 3791 case 2: 3792 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3793 sizeof (struct ether_vlan_header) - ETHERFCSL - 3794 E1000G_IPALIGNPRESERVEROOM; 3795 break; 3796 case 3: 3797 if (mac->type >= e1000_82571) 3798 Adapter->default_mtu = MAXIMUM_MTU; 3799 else 3800 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3801 sizeof (struct ether_vlan_header) - ETHERFCSL - 3802 E1000G_IPALIGNPRESERVEROOM; 3803 break; 3804 default: 3805 Adapter->default_mtu = ETHERMTU; 3806 break; 3807 } /* switch */ 3808 3809 Adapter->max_frame_size = Adapter->default_mtu + 3810 sizeof (struct ether_vlan_header) + ETHERFCSL; 3811 3812 /* ich8 does not do jumbo frames */ 3813 if (mac->type == e1000_ich8lan) { 3814 Adapter->max_frame_size = ETHERMAX; 3815 } 3816 3817 /* ich9 does not do jumbo frames on one phy type */ 3818 if ((mac->type == e1000_ich9lan) && 3819 (phy->type == e1000_phy_ife)) { 3820 Adapter->max_frame_size = ETHERMAX; 3821 } 3822 } 3823 3824 static void 3825 arm_watchdog_timer(struct e1000g *Adapter) 3826 { 3827 Adapter->watchdog_tid = 3828 timeout(e1000g_local_timer, 3829 (void *)Adapter, 1 * drv_usectohz(1000000)); 3830 } 3831 #pragma inline(arm_watchdog_timer) 3832 3833 static void 3834 enable_watchdog_timer(struct e1000g *Adapter) 3835 { 3836 mutex_enter(&Adapter->watchdog_lock); 3837 3838 if (!Adapter->watchdog_timer_enabled) { 3839 Adapter->watchdog_timer_enabled = B_TRUE; 3840 Adapter->watchdog_timer_started = B_TRUE; 3841 arm_watchdog_timer(Adapter); 3842 } 3843 3844 mutex_exit(&Adapter->watchdog_lock); 3845 } 3846 3847 static void 3848 disable_watchdog_timer(struct e1000g *Adapter) 3849 { 3850 timeout_id_t tid; 3851 3852 mutex_enter(&Adapter->watchdog_lock); 3853 3854 Adapter->watchdog_timer_enabled = B_FALSE; 3855 Adapter->watchdog_timer_started = B_FALSE; 3856 tid = Adapter->watchdog_tid; 3857 Adapter->watchdog_tid = 0; 3858 3859 mutex_exit(&Adapter->watchdog_lock); 3860 3861 if (tid != 0) 3862 (void) untimeout(tid); 3863 } 3864 3865 static void 3866 start_watchdog_timer(struct e1000g *Adapter) 3867 { 3868 mutex_enter(&Adapter->watchdog_lock); 3869 3870 if (Adapter->watchdog_timer_enabled) { 3871 if (!Adapter->watchdog_timer_started) { 3872 Adapter->watchdog_timer_started = B_TRUE; 3873 arm_watchdog_timer(Adapter); 3874 } 3875 } 3876 3877 mutex_exit(&Adapter->watchdog_lock); 3878 } 3879 3880 static void 3881 restart_watchdog_timer(struct e1000g *Adapter) 3882 { 3883 mutex_enter(&Adapter->watchdog_lock); 3884 3885 if (Adapter->watchdog_timer_started) 3886 arm_watchdog_timer(Adapter); 3887 3888 mutex_exit(&Adapter->watchdog_lock); 3889 } 3890 3891 static void 3892 stop_watchdog_timer(struct e1000g *Adapter) 3893 { 3894 timeout_id_t tid; 3895 3896 mutex_enter(&Adapter->watchdog_lock); 3897 3898 Adapter->watchdog_timer_started = B_FALSE; 3899 tid = Adapter->watchdog_tid; 3900 Adapter->watchdog_tid = 0; 3901 3902 mutex_exit(&Adapter->watchdog_lock); 3903 3904 if (tid != 0) 3905 (void) untimeout(tid); 3906 } 3907 3908 static void 3909 stop_link_timer(struct e1000g *Adapter) 3910 { 3911 timeout_id_t tid; 3912 3913 /* Disable the link timer */ 3914 mutex_enter(&Adapter->link_lock); 3915 3916 tid = Adapter->link_tid; 3917 Adapter->link_tid = 0; 3918 3919 mutex_exit(&Adapter->link_lock); 3920 3921 if (tid != 0) 3922 (void) untimeout(tid); 3923 } 3924 3925 static void 3926 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3927 { 3928 timeout_id_t tid; 3929 3930 /* Disable the tx timer for 82547 chipset */ 3931 mutex_enter(&tx_ring->tx_lock); 3932 3933 tx_ring->timer_enable_82547 = B_FALSE; 3934 tid = tx_ring->timer_id_82547; 3935 tx_ring->timer_id_82547 = 0; 3936 3937 mutex_exit(&tx_ring->tx_lock); 3938 3939 if (tid != 0) 3940 (void) untimeout(tid); 3941 } 3942 3943 void 3944 e1000g_clear_interrupt(struct e1000g *Adapter) 3945 { 3946 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3947 0xffffffff & ~E1000_IMS_RXSEQ); 3948 } 3949 3950 void 3951 e1000g_mask_interrupt(struct e1000g *Adapter) 3952 { 3953 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3954 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 3955 3956 if (Adapter->tx_intr_enable) 3957 e1000g_mask_tx_interrupt(Adapter); 3958 } 3959 3960 void 3961 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3962 { 3963 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3964 } 3965 3966 void 3967 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3968 { 3969 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 3970 } 3971 3972 void 3973 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3974 { 3975 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 3976 } 3977 3978 static void 3979 e1000g_smartspeed(struct e1000g *Adapter) 3980 { 3981 struct e1000_hw *hw = &Adapter->shared; 3982 uint16_t phy_status; 3983 uint16_t phy_ctrl; 3984 3985 /* 3986 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3987 * advertising 1000Full, we don't even use the workaround 3988 */ 3989 if ((hw->phy.type != e1000_phy_igp) || 3990 !hw->mac.autoneg || 3991 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3992 return; 3993 3994 /* 3995 * True if this is the first call of this function or after every 3996 * 30 seconds of not having link 3997 */ 3998 if (Adapter->smartspeed == 0) { 3999 /* 4000 * If Master/Slave config fault is asserted twice, we 4001 * assume back-to-back 4002 */ 4003 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4004 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4005 return; 4006 4007 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4008 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4009 return; 4010 /* 4011 * We're assuming back-2-back because our status register 4012 * insists! there's a fault in the master/slave 4013 * relationship that was "negotiated" 4014 */ 4015 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4016 /* 4017 * Is the phy configured for manual configuration of 4018 * master/slave? 4019 */ 4020 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4021 /* 4022 * Yes. Then disable manual configuration (enable 4023 * auto configuration) of master/slave 4024 */ 4025 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4026 e1000_write_phy_reg(hw, 4027 PHY_1000T_CTRL, phy_ctrl); 4028 /* 4029 * Effectively starting the clock 4030 */ 4031 Adapter->smartspeed++; 4032 /* 4033 * Restart autonegotiation 4034 */ 4035 if (!e1000_phy_setup_autoneg(hw) && 4036 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4037 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4038 MII_CR_RESTART_AUTO_NEG); 4039 e1000_write_phy_reg(hw, 4040 PHY_CONTROL, phy_ctrl); 4041 } 4042 } 4043 return; 4044 /* 4045 * Has 6 seconds transpired still without link? Remember, 4046 * you should reset the smartspeed counter once you obtain 4047 * link 4048 */ 4049 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4050 /* 4051 * Yes. Remember, we did at the start determine that 4052 * there's a master/slave configuration fault, so we're 4053 * still assuming there's someone on the other end, but we 4054 * just haven't yet been able to talk to it. We then 4055 * re-enable auto configuration of master/slave to see if 4056 * we're running 2/3 pair cables. 4057 */ 4058 /* 4059 * If still no link, perhaps using 2/3 pair cable 4060 */ 4061 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4062 phy_ctrl |= CR_1000T_MS_ENABLE; 4063 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4064 /* 4065 * Restart autoneg with phy enabled for manual 4066 * configuration of master/slave 4067 */ 4068 if (!e1000_phy_setup_autoneg(hw) && 4069 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4070 phy_ctrl |= 4071 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4072 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4073 } 4074 /* 4075 * Hopefully, there are no more faults and we've obtained 4076 * link as a result. 4077 */ 4078 } 4079 /* 4080 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4081 * seconds) 4082 */ 4083 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4084 Adapter->smartspeed = 0; 4085 } 4086 4087 static boolean_t 4088 is_valid_mac_addr(uint8_t *mac_addr) 4089 { 4090 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4091 const uint8_t addr_test2[6] = 4092 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4093 4094 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4095 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4096 return (B_FALSE); 4097 4098 return (B_TRUE); 4099 } 4100 4101 /* 4102 * e1000g_stall_check - check for tx stall 4103 * 4104 * This function checks if the adapter is stalled (in transmit). 4105 * 4106 * It is called each time the watchdog timeout is invoked. 4107 * If the transmit descriptor reclaim continuously fails, 4108 * the watchdog value will increment by 1. If the watchdog 4109 * value exceeds the threshold, the adapter is assumed to 4110 * have stalled and need to be reset. 4111 */ 4112 static boolean_t 4113 e1000g_stall_check(struct e1000g *Adapter) 4114 { 4115 e1000g_tx_ring_t *tx_ring; 4116 4117 tx_ring = Adapter->tx_ring; 4118 4119 if (Adapter->link_state != LINK_STATE_UP) 4120 return (B_FALSE); 4121 4122 if (tx_ring->recycle_fail > 0) 4123 tx_ring->stall_watchdog++; 4124 else 4125 tx_ring->stall_watchdog = 0; 4126 4127 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4128 return (B_FALSE); 4129 4130 tx_ring->stall_watchdog = 0; 4131 tx_ring->recycle_fail = 0; 4132 4133 return (B_TRUE); 4134 } 4135 4136 #ifdef E1000G_DEBUG 4137 static enum ioc_reply 4138 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4139 { 4140 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4141 e1000g_peekpoke_t *ppd; 4142 uint64_t mem_va; 4143 uint64_t maxoff; 4144 boolean_t peek; 4145 4146 switch (iocp->ioc_cmd) { 4147 4148 case E1000G_IOC_REG_PEEK: 4149 peek = B_TRUE; 4150 break; 4151 4152 case E1000G_IOC_REG_POKE: 4153 peek = B_FALSE; 4154 break; 4155 4156 deault: 4157 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4158 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4159 iocp->ioc_cmd); 4160 return (IOC_INVAL); 4161 } 4162 4163 /* 4164 * Validate format of ioctl 4165 */ 4166 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4167 return (IOC_INVAL); 4168 if (mp->b_cont == NULL) 4169 return (IOC_INVAL); 4170 4171 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 4172 4173 /* 4174 * Validate request parameters 4175 */ 4176 switch (ppd->pp_acc_space) { 4177 4178 default: 4179 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4180 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4181 ppd->pp_acc_space); 4182 return (IOC_INVAL); 4183 4184 case E1000G_PP_SPACE_REG: 4185 /* 4186 * Memory-mapped I/O space 4187 */ 4188 ASSERT(ppd->pp_acc_size == 4); 4189 if (ppd->pp_acc_size != 4) 4190 return (IOC_INVAL); 4191 4192 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4193 return (IOC_INVAL); 4194 4195 mem_va = 0; 4196 maxoff = 0x10000; 4197 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4198 break; 4199 4200 case E1000G_PP_SPACE_E1000G: 4201 /* 4202 * E1000g data structure! 4203 */ 4204 mem_va = (uintptr_t)e1000gp; 4205 maxoff = sizeof (struct e1000g); 4206 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4207 break; 4208 4209 } 4210 4211 if (ppd->pp_acc_offset >= maxoff) 4212 return (IOC_INVAL); 4213 4214 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4215 return (IOC_INVAL); 4216 4217 /* 4218 * All OK - go! 4219 */ 4220 ppd->pp_acc_offset += mem_va; 4221 (*ppfn)(e1000gp, ppd); 4222 return (peek ? IOC_REPLY : IOC_ACK); 4223 } 4224 4225 static void 4226 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4227 { 4228 ddi_acc_handle_t handle; 4229 uint32_t *regaddr; 4230 4231 handle = e1000gp->osdep.reg_handle; 4232 regaddr = 4233 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4234 4235 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4236 } 4237 4238 static void 4239 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4240 { 4241 ddi_acc_handle_t handle; 4242 uint32_t *regaddr; 4243 uint32_t value; 4244 4245 handle = e1000gp->osdep.reg_handle; 4246 regaddr = 4247 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4248 value = (uint32_t)ppd->pp_acc_data; 4249 4250 ddi_put32(handle, regaddr, value); 4251 } 4252 4253 static void 4254 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4255 { 4256 uint64_t value; 4257 void *vaddr; 4258 4259 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4260 4261 switch (ppd->pp_acc_size) { 4262 case 1: 4263 value = *(uint8_t *)vaddr; 4264 break; 4265 4266 case 2: 4267 value = *(uint16_t *)vaddr; 4268 break; 4269 4270 case 4: 4271 value = *(uint32_t *)vaddr; 4272 break; 4273 4274 case 8: 4275 value = *(uint64_t *)vaddr; 4276 break; 4277 } 4278 4279 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4280 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4281 (void *)e1000gp, (void *)ppd, value, vaddr); 4282 4283 ppd->pp_acc_data = value; 4284 } 4285 4286 static void 4287 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4288 { 4289 uint64_t value; 4290 void *vaddr; 4291 4292 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4293 value = ppd->pp_acc_data; 4294 4295 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4296 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4297 (void *)e1000gp, (void *)ppd, value, vaddr); 4298 4299 switch (ppd->pp_acc_size) { 4300 case 1: 4301 *(uint8_t *)vaddr = (uint8_t)value; 4302 break; 4303 4304 case 2: 4305 *(uint16_t *)vaddr = (uint16_t)value; 4306 break; 4307 4308 case 4: 4309 *(uint32_t *)vaddr = (uint32_t)value; 4310 break; 4311 4312 case 8: 4313 *(uint64_t *)vaddr = (uint64_t)value; 4314 break; 4315 } 4316 } 4317 #endif 4318 4319 /* 4320 * Loopback Support 4321 */ 4322 static lb_property_t lb_normal = 4323 { normal, "normal", E1000G_LB_NONE }; 4324 static lb_property_t lb_external1000 = 4325 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4326 static lb_property_t lb_external100 = 4327 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4328 static lb_property_t lb_external10 = 4329 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4330 static lb_property_t lb_phy = 4331 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4332 4333 static enum ioc_reply 4334 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4335 { 4336 lb_info_sz_t *lbsp; 4337 lb_property_t *lbpp; 4338 struct e1000_hw *hw; 4339 uint32_t *lbmp; 4340 uint32_t size; 4341 uint32_t value; 4342 4343 hw = &Adapter->shared; 4344 4345 if (mp->b_cont == NULL) 4346 return (IOC_INVAL); 4347 4348 switch (iocp->ioc_cmd) { 4349 default: 4350 return (IOC_INVAL); 4351 4352 case LB_GET_INFO_SIZE: 4353 size = sizeof (lb_info_sz_t); 4354 if (iocp->ioc_count != size) 4355 return (IOC_INVAL); 4356 4357 rw_enter(&Adapter->chip_lock, RW_WRITER); 4358 e1000g_get_phy_state(Adapter); 4359 4360 /* 4361 * Workaround for hardware faults. In order to get a stable 4362 * state of phy, we will wait for a specific interval and 4363 * try again. The time delay is an experiential value based 4364 * on our testing. 4365 */ 4366 msec_delay(100); 4367 e1000g_get_phy_state(Adapter); 4368 rw_exit(&Adapter->chip_lock); 4369 4370 value = sizeof (lb_normal); 4371 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4372 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4373 (hw->phy.media_type == e1000_media_type_fiber) || 4374 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4375 value += sizeof (lb_phy); 4376 switch (hw->mac.type) { 4377 case e1000_82571: 4378 case e1000_82572: 4379 value += sizeof (lb_external1000); 4380 break; 4381 } 4382 } 4383 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4384 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4385 value += sizeof (lb_external100); 4386 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4387 value += sizeof (lb_external10); 4388 4389 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 4390 *lbsp = value; 4391 break; 4392 4393 case LB_GET_INFO: 4394 value = sizeof (lb_normal); 4395 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4396 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4397 (hw->phy.media_type == e1000_media_type_fiber) || 4398 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4399 value += sizeof (lb_phy); 4400 switch (hw->mac.type) { 4401 case e1000_82571: 4402 case e1000_82572: 4403 value += sizeof (lb_external1000); 4404 break; 4405 } 4406 } 4407 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4408 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4409 value += sizeof (lb_external100); 4410 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4411 value += sizeof (lb_external10); 4412 4413 size = value; 4414 if (iocp->ioc_count != size) 4415 return (IOC_INVAL); 4416 4417 value = 0; 4418 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 4419 lbpp[value++] = lb_normal; 4420 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4421 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4422 (hw->phy.media_type == e1000_media_type_fiber) || 4423 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4424 lbpp[value++] = lb_phy; 4425 switch (hw->mac.type) { 4426 case e1000_82571: 4427 case e1000_82572: 4428 lbpp[value++] = lb_external1000; 4429 break; 4430 } 4431 } 4432 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4433 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4434 lbpp[value++] = lb_external100; 4435 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4436 lbpp[value++] = lb_external10; 4437 break; 4438 4439 case LB_GET_MODE: 4440 size = sizeof (uint32_t); 4441 if (iocp->ioc_count != size) 4442 return (IOC_INVAL); 4443 4444 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4445 *lbmp = Adapter->loopback_mode; 4446 break; 4447 4448 case LB_SET_MODE: 4449 size = 0; 4450 if (iocp->ioc_count != sizeof (uint32_t)) 4451 return (IOC_INVAL); 4452 4453 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4454 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4455 return (IOC_INVAL); 4456 break; 4457 } 4458 4459 iocp->ioc_count = size; 4460 iocp->ioc_error = 0; 4461 4462 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4463 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4464 return (IOC_INVAL); 4465 } 4466 4467 return (IOC_REPLY); 4468 } 4469 4470 static boolean_t 4471 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4472 { 4473 struct e1000_hw *hw; 4474 int i, times; 4475 boolean_t link_up; 4476 4477 if (mode == Adapter->loopback_mode) 4478 return (B_TRUE); 4479 4480 hw = &Adapter->shared; 4481 times = 0; 4482 4483 Adapter->loopback_mode = mode; 4484 4485 if (mode == E1000G_LB_NONE) { 4486 /* Reset the chip */ 4487 hw->phy.autoneg_wait_to_complete = B_TRUE; 4488 (void) e1000g_reset(Adapter); 4489 hw->phy.autoneg_wait_to_complete = B_FALSE; 4490 return (B_TRUE); 4491 } 4492 4493 again: 4494 4495 rw_enter(&Adapter->chip_lock, RW_WRITER); 4496 4497 switch (mode) { 4498 default: 4499 rw_exit(&Adapter->chip_lock); 4500 return (B_FALSE); 4501 4502 case E1000G_LB_EXTERNAL_1000: 4503 e1000g_set_external_loopback_1000(Adapter); 4504 break; 4505 4506 case E1000G_LB_EXTERNAL_100: 4507 e1000g_set_external_loopback_100(Adapter); 4508 break; 4509 4510 case E1000G_LB_EXTERNAL_10: 4511 e1000g_set_external_loopback_10(Adapter); 4512 break; 4513 4514 case E1000G_LB_INTERNAL_PHY: 4515 e1000g_set_internal_loopback(Adapter); 4516 break; 4517 } 4518 4519 times++; 4520 4521 rw_exit(&Adapter->chip_lock); 4522 4523 /* Wait for link up */ 4524 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4525 msec_delay(100); 4526 4527 rw_enter(&Adapter->chip_lock, RW_WRITER); 4528 4529 link_up = e1000g_link_up(Adapter); 4530 4531 rw_exit(&Adapter->chip_lock); 4532 4533 if (!link_up) { 4534 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4535 "Failed to get the link up"); 4536 if (times < 2) { 4537 /* Reset the link */ 4538 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4539 "Reset the link ..."); 4540 (void) e1000g_reset(Adapter); 4541 goto again; 4542 } 4543 } 4544 4545 return (B_TRUE); 4546 } 4547 4548 /* 4549 * The following loopback settings are from Intel's technical 4550 * document - "How To Loopback". All the register settings and 4551 * time delay values are directly inherited from the document 4552 * without more explanations available. 4553 */ 4554 static void 4555 e1000g_set_internal_loopback(struct e1000g *Adapter) 4556 { 4557 struct e1000_hw *hw; 4558 uint32_t ctrl; 4559 uint32_t status; 4560 uint16_t phy_ctrl; 4561 uint32_t txcw; 4562 4563 hw = &Adapter->shared; 4564 4565 /* Disable Smart Power Down */ 4566 phy_spd_state(hw, B_FALSE); 4567 4568 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4569 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4570 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4571 4572 switch (hw->mac.type) { 4573 case e1000_82540: 4574 case e1000_82545: 4575 case e1000_82545_rev_3: 4576 case e1000_82546: 4577 case e1000_82546_rev_3: 4578 case e1000_82573: 4579 /* Auto-MDI/MDIX off */ 4580 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4581 /* Reset PHY to update Auto-MDI/MDIX */ 4582 e1000_write_phy_reg(hw, PHY_CONTROL, 4583 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4584 /* Reset PHY to auto-neg off and force 1000 */ 4585 e1000_write_phy_reg(hw, PHY_CONTROL, 4586 phy_ctrl | MII_CR_RESET); 4587 /* 4588 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4589 * See comments above e1000g_set_internal_loopback() for the 4590 * background. 4591 */ 4592 e1000_write_phy_reg(hw, 29, 0x001F); 4593 e1000_write_phy_reg(hw, 30, 0x8FFC); 4594 e1000_write_phy_reg(hw, 29, 0x001A); 4595 e1000_write_phy_reg(hw, 30, 0x8FF0); 4596 break; 4597 } 4598 4599 /* Set loopback */ 4600 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4601 4602 msec_delay(250); 4603 4604 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4605 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4606 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4607 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4608 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4609 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4610 E1000_CTRL_FD); /* Force Duplex to FULL */ 4611 4612 switch (hw->mac.type) { 4613 case e1000_82540: 4614 case e1000_82545: 4615 case e1000_82545_rev_3: 4616 case e1000_82546: 4617 case e1000_82546_rev_3: 4618 /* 4619 * For some serdes we'll need to commit the writes now 4620 * so that the status is updated on link 4621 */ 4622 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4623 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4624 msec_delay(100); 4625 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4626 } 4627 4628 if (hw->phy.media_type == e1000_media_type_copper) { 4629 /* Invert Loss of Signal */ 4630 ctrl |= E1000_CTRL_ILOS; 4631 } else { 4632 /* Set ILOS on fiber nic if half duplex is detected */ 4633 status = E1000_READ_REG(hw, E1000_STATUS); 4634 if ((status & E1000_STATUS_FD) == 0) 4635 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4636 } 4637 break; 4638 4639 case e1000_82571: 4640 case e1000_82572: 4641 /* 4642 * The fiber/SerDes versions of this adapter do not contain an 4643 * accessible PHY. Therefore, loopback beyond MAC must be done 4644 * using SerDes analog loopback. 4645 */ 4646 if (hw->phy.media_type != e1000_media_type_copper) { 4647 status = E1000_READ_REG(hw, E1000_STATUS); 4648 /* Set ILOS on fiber nic if half duplex is detected */ 4649 if (((status & E1000_STATUS_LU) == 0) || 4650 ((status & E1000_STATUS_FD) == 0) || 4651 (hw->phy.media_type == 4652 e1000_media_type_internal_serdes)) 4653 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4654 4655 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4656 txcw = E1000_READ_REG(hw, E1000_TXCW); 4657 txcw &= ~((uint32_t)1 << 31); 4658 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4659 4660 /* 4661 * Write 0x410 to Serdes Control register 4662 * to enable Serdes analog loopback 4663 */ 4664 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4665 msec_delay(10); 4666 } 4667 break; 4668 4669 case e1000_82573: 4670 ctrl |= E1000_CTRL_ILOS; 4671 break; 4672 } 4673 4674 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4675 4676 } 4677 4678 static void 4679 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4680 { 4681 struct e1000_hw *hw; 4682 uint32_t rctl; 4683 uint32_t ctrl_ext; 4684 uint32_t ctrl; 4685 uint32_t status; 4686 uint32_t txcw; 4687 4688 hw = &Adapter->shared; 4689 4690 /* Disable Smart Power Down */ 4691 phy_spd_state(hw, B_FALSE); 4692 4693 switch (hw->phy.media_type) { 4694 case e1000_media_type_copper: 4695 /* Force link up (Must be done before the PHY writes) */ 4696 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4697 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4698 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4699 4700 rctl = E1000_READ_REG(hw, E1000_RCTL); 4701 rctl |= (E1000_RCTL_EN | 4702 E1000_RCTL_SBP | 4703 E1000_RCTL_UPE | 4704 E1000_RCTL_MPE | 4705 E1000_RCTL_LPE | 4706 E1000_RCTL_BAM); /* 0x803E */ 4707 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4708 4709 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4710 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4711 E1000_CTRL_EXT_SDP6_DATA | 4712 E1000_CTRL_EXT_SDP7_DATA | 4713 E1000_CTRL_EXT_SDP4_DIR | 4714 E1000_CTRL_EXT_SDP6_DIR | 4715 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4716 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4717 4718 /* 4719 * This sequence tunes the PHY's SDP and no customer 4720 * settable values. For background, see comments above 4721 * e1000g_set_internal_loopback(). 4722 */ 4723 e1000_write_phy_reg(hw, 0x0, 0x140); 4724 msec_delay(10); 4725 e1000_write_phy_reg(hw, 0x9, 0x1A00); 4726 e1000_write_phy_reg(hw, 0x12, 0xC10); 4727 e1000_write_phy_reg(hw, 0x12, 0x1C10); 4728 e1000_write_phy_reg(hw, 0x1F37, 0x76); 4729 e1000_write_phy_reg(hw, 0x1F33, 0x1); 4730 e1000_write_phy_reg(hw, 0x1F33, 0x0); 4731 4732 e1000_write_phy_reg(hw, 0x1F35, 0x65); 4733 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4734 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4735 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4736 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4737 4738 msec_delay(50); 4739 break; 4740 case e1000_media_type_fiber: 4741 case e1000_media_type_internal_serdes: 4742 status = E1000_READ_REG(hw, E1000_STATUS); 4743 if (((status & E1000_STATUS_LU) == 0) || 4744 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4745 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4746 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4747 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4748 } 4749 4750 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4751 txcw = E1000_READ_REG(hw, E1000_TXCW); 4752 txcw &= ~((uint32_t)1 << 31); 4753 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4754 4755 /* 4756 * Write 0x410 to Serdes Control register 4757 * to enable Serdes analog loopback 4758 */ 4759 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4760 msec_delay(10); 4761 break; 4762 default: 4763 break; 4764 } 4765 } 4766 4767 static void 4768 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4769 { 4770 struct e1000_hw *hw; 4771 uint32_t ctrl; 4772 uint16_t phy_ctrl; 4773 4774 hw = &Adapter->shared; 4775 4776 /* Disable Smart Power Down */ 4777 phy_spd_state(hw, B_FALSE); 4778 4779 phy_ctrl = (MII_CR_FULL_DUPLEX | 4780 MII_CR_SPEED_100); 4781 4782 /* Force 100/FD, reset PHY */ 4783 e1000_write_phy_reg(hw, PHY_CONTROL, 4784 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4785 msec_delay(10); 4786 4787 /* Force 100/FD */ 4788 e1000_write_phy_reg(hw, PHY_CONTROL, 4789 phy_ctrl); /* 0x2100 */ 4790 msec_delay(10); 4791 4792 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4793 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4794 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4795 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4796 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4797 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4798 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4799 E1000_CTRL_FD); /* Force Duplex to FULL */ 4800 4801 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4802 } 4803 4804 static void 4805 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4806 { 4807 struct e1000_hw *hw; 4808 uint32_t ctrl; 4809 uint16_t phy_ctrl; 4810 4811 hw = &Adapter->shared; 4812 4813 /* Disable Smart Power Down */ 4814 phy_spd_state(hw, B_FALSE); 4815 4816 phy_ctrl = (MII_CR_FULL_DUPLEX | 4817 MII_CR_SPEED_10); 4818 4819 /* Force 10/FD, reset PHY */ 4820 e1000_write_phy_reg(hw, PHY_CONTROL, 4821 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4822 msec_delay(10); 4823 4824 /* Force 10/FD */ 4825 e1000_write_phy_reg(hw, PHY_CONTROL, 4826 phy_ctrl); /* 0x0100 */ 4827 msec_delay(10); 4828 4829 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4830 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4831 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4832 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4833 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4834 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4835 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4836 E1000_CTRL_FD); /* Force Duplex to FULL */ 4837 4838 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4839 } 4840 4841 #ifdef __sparc 4842 static boolean_t 4843 e1000g_find_mac_address(struct e1000g *Adapter) 4844 { 4845 struct e1000_hw *hw = &Adapter->shared; 4846 uchar_t *bytes; 4847 struct ether_addr sysaddr; 4848 uint_t nelts; 4849 int err; 4850 boolean_t found = B_FALSE; 4851 4852 /* 4853 * The "vendor's factory-set address" may already have 4854 * been extracted from the chip, but if the property 4855 * "local-mac-address" is set we use that instead. 4856 * 4857 * We check whether it looks like an array of 6 4858 * bytes (which it should, if OBP set it). If we can't 4859 * make sense of it this way, we'll ignore it. 4860 */ 4861 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4862 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4863 if (err == DDI_PROP_SUCCESS) { 4864 if (nelts == ETHERADDRL) { 4865 while (nelts--) 4866 hw->mac.addr[nelts] = bytes[nelts]; 4867 found = B_TRUE; 4868 } 4869 ddi_prop_free(bytes); 4870 } 4871 4872 /* 4873 * Look up the OBP property "local-mac-address?". If the user has set 4874 * 'local-mac-address? = false', use "the system address" instead. 4875 */ 4876 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4877 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4878 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4879 if (localetheraddr(NULL, &sysaddr) != 0) { 4880 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4881 found = B_TRUE; 4882 } 4883 } 4884 ddi_prop_free(bytes); 4885 } 4886 4887 /* 4888 * Finally(!), if there's a valid "mac-address" property (created 4889 * if we netbooted from this interface), we must use this instead 4890 * of any of the above to ensure that the NFS/install server doesn't 4891 * get confused by the address changing as Solaris takes over! 4892 */ 4893 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4894 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4895 if (err == DDI_PROP_SUCCESS) { 4896 if (nelts == ETHERADDRL) { 4897 while (nelts--) 4898 hw->mac.addr[nelts] = bytes[nelts]; 4899 found = B_TRUE; 4900 } 4901 ddi_prop_free(bytes); 4902 } 4903 4904 if (found) { 4905 bcopy(hw->mac.addr, hw->mac.perm_addr, 4906 ETHERADDRL); 4907 } 4908 4909 return (found); 4910 } 4911 #endif 4912 4913 static int 4914 e1000g_add_intrs(struct e1000g *Adapter) 4915 { 4916 dev_info_t *devinfo; 4917 int intr_types; 4918 int rc; 4919 4920 devinfo = Adapter->dip; 4921 4922 /* Get supported interrupt types */ 4923 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4924 4925 if (rc != DDI_SUCCESS) { 4926 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4927 "Get supported interrupt types failed: %d\n", rc); 4928 return (DDI_FAILURE); 4929 } 4930 4931 /* 4932 * Based on Intel Technical Advisory document (TA-160), there are some 4933 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4934 * that it supports MSI, but in fact has problems. 4935 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4936 * PCI/PCI-X NICs. 4937 */ 4938 if (Adapter->shared.mac.type < e1000_82571) 4939 Adapter->msi_enable = B_FALSE; 4940 4941 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 4942 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4943 4944 if (rc != DDI_SUCCESS) { 4945 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4946 "Add MSI failed, trying Legacy interrupts\n"); 4947 } else { 4948 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4949 } 4950 } 4951 4952 if ((Adapter->intr_type == 0) && 4953 (intr_types & DDI_INTR_TYPE_FIXED)) { 4954 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4955 4956 if (rc != DDI_SUCCESS) { 4957 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4958 "Add Legacy interrupts failed\n"); 4959 return (DDI_FAILURE); 4960 } 4961 4962 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4963 } 4964 4965 if (Adapter->intr_type == 0) { 4966 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4967 "No interrupts registered\n"); 4968 return (DDI_FAILURE); 4969 } 4970 4971 return (DDI_SUCCESS); 4972 } 4973 4974 /* 4975 * e1000g_intr_add() handles MSI/Legacy interrupts 4976 */ 4977 static int 4978 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4979 { 4980 dev_info_t *devinfo; 4981 int count, avail, actual; 4982 int x, y, rc, inum = 0; 4983 int flag; 4984 ddi_intr_handler_t *intr_handler; 4985 4986 devinfo = Adapter->dip; 4987 4988 /* get number of interrupts */ 4989 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4990 if ((rc != DDI_SUCCESS) || (count == 0)) { 4991 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4992 "Get interrupt number failed. Return: %d, count: %d\n", 4993 rc, count); 4994 return (DDI_FAILURE); 4995 } 4996 4997 /* get number of available interrupts */ 4998 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4999 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5000 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5001 "Get interrupt available number failed. " 5002 "Return: %d, available: %d\n", rc, avail); 5003 return (DDI_FAILURE); 5004 } 5005 5006 if (avail < count) { 5007 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5008 "Interrupts count: %d, available: %d\n", 5009 count, avail); 5010 } 5011 5012 /* Allocate an array of interrupt handles */ 5013 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5014 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5015 5016 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5017 flag = DDI_INTR_ALLOC_NORMAL; 5018 5019 /* call ddi_intr_alloc() */ 5020 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5021 count, &actual, flag); 5022 5023 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5024 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5025 "Allocate interrupts failed: %d\n", rc); 5026 5027 kmem_free(Adapter->htable, Adapter->intr_size); 5028 return (DDI_FAILURE); 5029 } 5030 5031 if (actual < count) { 5032 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5033 "Interrupts requested: %d, received: %d\n", 5034 count, actual); 5035 } 5036 5037 Adapter->intr_cnt = actual; 5038 5039 /* Get priority for first msi, assume remaining are all the same */ 5040 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5041 5042 if (rc != DDI_SUCCESS) { 5043 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5044 "Get interrupt priority failed: %d\n", rc); 5045 5046 /* Free already allocated intr */ 5047 for (y = 0; y < actual; y++) 5048 (void) ddi_intr_free(Adapter->htable[y]); 5049 5050 kmem_free(Adapter->htable, Adapter->intr_size); 5051 return (DDI_FAILURE); 5052 } 5053 5054 /* 5055 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5056 * use the interrupt service routine e1000g_intr_pciexpress() 5057 * to avoid interrupt stealing when sharing interrupt with other 5058 * devices. 5059 */ 5060 if (Adapter->shared.mac.type < e1000_82571) 5061 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5062 else 5063 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5064 5065 /* Call ddi_intr_add_handler() */ 5066 for (x = 0; x < actual; x++) { 5067 rc = ddi_intr_add_handler(Adapter->htable[x], 5068 intr_handler, (caddr_t)Adapter, NULL); 5069 5070 if (rc != DDI_SUCCESS) { 5071 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5072 "Add interrupt handler failed: %d\n", rc); 5073 5074 /* Remove already added handler */ 5075 for (y = 0; y < x; y++) 5076 (void) ddi_intr_remove_handler( 5077 Adapter->htable[y]); 5078 5079 /* Free already allocated intr */ 5080 for (y = 0; y < actual; y++) 5081 (void) ddi_intr_free(Adapter->htable[y]); 5082 5083 kmem_free(Adapter->htable, Adapter->intr_size); 5084 return (DDI_FAILURE); 5085 } 5086 } 5087 5088 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5089 5090 if (rc != DDI_SUCCESS) { 5091 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5092 "Get interrupt cap failed: %d\n", rc); 5093 5094 /* Free already allocated intr */ 5095 for (y = 0; y < actual; y++) { 5096 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5097 (void) ddi_intr_free(Adapter->htable[y]); 5098 } 5099 5100 kmem_free(Adapter->htable, Adapter->intr_size); 5101 return (DDI_FAILURE); 5102 } 5103 5104 return (DDI_SUCCESS); 5105 } 5106 5107 static int 5108 e1000g_rem_intrs(struct e1000g *Adapter) 5109 { 5110 int x; 5111 int rc; 5112 5113 for (x = 0; x < Adapter->intr_cnt; x++) { 5114 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5115 if (rc != DDI_SUCCESS) { 5116 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5117 "Remove intr handler failed: %d\n", rc); 5118 return (DDI_FAILURE); 5119 } 5120 5121 rc = ddi_intr_free(Adapter->htable[x]); 5122 if (rc != DDI_SUCCESS) { 5123 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5124 "Free intr failed: %d\n", rc); 5125 return (DDI_FAILURE); 5126 } 5127 } 5128 5129 kmem_free(Adapter->htable, Adapter->intr_size); 5130 5131 return (DDI_SUCCESS); 5132 } 5133 5134 static int 5135 e1000g_enable_intrs(struct e1000g *Adapter) 5136 { 5137 int x; 5138 int rc; 5139 5140 /* Enable interrupts */ 5141 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5142 /* Call ddi_intr_block_enable() for MSI */ 5143 rc = ddi_intr_block_enable(Adapter->htable, 5144 Adapter->intr_cnt); 5145 if (rc != DDI_SUCCESS) { 5146 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5147 "Enable block intr failed: %d\n", rc); 5148 return (DDI_FAILURE); 5149 } 5150 } else { 5151 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5152 for (x = 0; x < Adapter->intr_cnt; x++) { 5153 rc = ddi_intr_enable(Adapter->htable[x]); 5154 if (rc != DDI_SUCCESS) { 5155 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5156 "Enable intr failed: %d\n", rc); 5157 return (DDI_FAILURE); 5158 } 5159 } 5160 } 5161 5162 return (DDI_SUCCESS); 5163 } 5164 5165 static int 5166 e1000g_disable_intrs(struct e1000g *Adapter) 5167 { 5168 int x; 5169 int rc; 5170 5171 /* Disable all interrupts */ 5172 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5173 rc = ddi_intr_block_disable(Adapter->htable, 5174 Adapter->intr_cnt); 5175 if (rc != DDI_SUCCESS) { 5176 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5177 "Disable block intr failed: %d\n", rc); 5178 return (DDI_FAILURE); 5179 } 5180 } else { 5181 for (x = 0; x < Adapter->intr_cnt; x++) { 5182 rc = ddi_intr_disable(Adapter->htable[x]); 5183 if (rc != DDI_SUCCESS) { 5184 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5185 "Disable intr failed: %d\n", rc); 5186 return (DDI_FAILURE); 5187 } 5188 } 5189 } 5190 5191 return (DDI_SUCCESS); 5192 } 5193 5194 /* 5195 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5196 */ 5197 static void 5198 e1000g_get_phy_state(struct e1000g *Adapter) 5199 { 5200 struct e1000_hw *hw = &Adapter->shared; 5201 5202 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5203 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5204 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5205 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5206 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5207 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5208 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 5209 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5210 5211 Adapter->param_autoneg_cap = 5212 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5213 Adapter->param_pause_cap = 5214 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5215 Adapter->param_asym_pause_cap = 5216 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5217 Adapter->param_1000fdx_cap = 5218 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5219 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5220 Adapter->param_1000hdx_cap = 5221 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5222 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5223 Adapter->param_100t4_cap = 5224 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5225 Adapter->param_100fdx_cap = 5226 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5227 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5228 Adapter->param_100hdx_cap = 5229 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5230 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5231 Adapter->param_10fdx_cap = 5232 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5233 Adapter->param_10hdx_cap = 5234 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5235 5236 Adapter->param_adv_autoneg = hw->mac.autoneg; 5237 Adapter->param_adv_pause = 5238 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5239 Adapter->param_adv_asym_pause = 5240 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5241 Adapter->param_adv_1000hdx = 5242 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5243 Adapter->param_adv_100t4 = 5244 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5245 if (Adapter->param_adv_autoneg == 1) { 5246 Adapter->param_adv_1000fdx = 5247 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5248 Adapter->param_adv_100fdx = 5249 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5250 Adapter->param_adv_100hdx = 5251 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5252 Adapter->param_adv_10fdx = 5253 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5254 Adapter->param_adv_10hdx = 5255 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5256 } 5257 5258 Adapter->param_lp_autoneg = 5259 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5260 Adapter->param_lp_pause = 5261 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5262 Adapter->param_lp_asym_pause = 5263 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5264 Adapter->param_lp_1000fdx = 5265 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5266 Adapter->param_lp_1000hdx = 5267 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5268 Adapter->param_lp_100t4 = 5269 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5270 Adapter->param_lp_100fdx = 5271 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5272 Adapter->param_lp_100hdx = 5273 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5274 Adapter->param_lp_10fdx = 5275 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5276 Adapter->param_lp_10hdx = 5277 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5278 } 5279 5280 /* 5281 * FMA support 5282 */ 5283 5284 int 5285 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5286 { 5287 ddi_fm_error_t de; 5288 5289 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5290 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5291 return (de.fme_status); 5292 } 5293 5294 int 5295 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5296 { 5297 ddi_fm_error_t de; 5298 5299 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5300 return (de.fme_status); 5301 } 5302 5303 /* 5304 * The IO fault service error handling callback function 5305 */ 5306 static int 5307 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5308 { 5309 /* 5310 * as the driver can always deal with an error in any dma or 5311 * access handle, we can just return the fme_status value. 5312 */ 5313 pci_ereport_post(dip, err, NULL); 5314 return (err->fme_status); 5315 } 5316 5317 static void 5318 e1000g_fm_init(struct e1000g *Adapter) 5319 { 5320 ddi_iblock_cookie_t iblk; 5321 int fma_acc_flag, fma_dma_flag; 5322 5323 /* Only register with IO Fault Services if we have some capability */ 5324 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5325 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5326 fma_acc_flag = 1; 5327 } else { 5328 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5329 fma_acc_flag = 0; 5330 } 5331 5332 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5333 fma_dma_flag = 1; 5334 } else { 5335 fma_dma_flag = 0; 5336 } 5337 5338 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5339 5340 if (Adapter->fm_capabilities) { 5341 5342 /* Register capabilities with IO Fault Services */ 5343 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5344 5345 /* 5346 * Initialize pci ereport capabilities if ereport capable 5347 */ 5348 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5349 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5350 pci_ereport_setup(Adapter->dip); 5351 5352 /* 5353 * Register error callback if error callback capable 5354 */ 5355 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5356 ddi_fm_handler_register(Adapter->dip, 5357 e1000g_fm_error_cb, (void*) Adapter); 5358 } 5359 } 5360 5361 static void 5362 e1000g_fm_fini(struct e1000g *Adapter) 5363 { 5364 /* Only unregister FMA capabilities if we registered some */ 5365 if (Adapter->fm_capabilities) { 5366 5367 /* 5368 * Release any resources allocated by pci_ereport_setup() 5369 */ 5370 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5371 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5372 pci_ereport_teardown(Adapter->dip); 5373 5374 /* 5375 * Un-register error callback if error callback capable 5376 */ 5377 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5378 ddi_fm_handler_unregister(Adapter->dip); 5379 5380 /* Unregister from IO Fault Services */ 5381 ddi_fm_fini(Adapter->dip); 5382 } 5383 } 5384 5385 void 5386 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5387 { 5388 uint64_t ena; 5389 char buf[FM_MAX_CLASS]; 5390 5391 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5392 ena = fm_ena_generate(0, FM_ENA_FMT1); 5393 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5394 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5395 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5396 } 5397 } 5398 5399 static int 5400 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5401 uint_t pr_valsize, void *pr_val) 5402 { 5403 link_flowctrl_t fl; 5404 uint32_t fc; 5405 int err = 0; 5406 5407 ASSERT(pr_valsize > 0); 5408 switch (pr_num) { 5409 case MAC_PROP_AUTONEG: 5410 *(uint8_t *)pr_val = 5411 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5412 break; 5413 case MAC_PROP_FLOWCTRL: 5414 if (pr_valsize < sizeof (link_flowctrl_t)) 5415 return (EINVAL); 5416 fl = LINK_FLOWCTRL_BI; 5417 bcopy(&fl, pr_val, sizeof (fl)); 5418 break; 5419 case MAC_PROP_ADV_1000FDX_CAP: 5420 case MAC_PROP_EN_1000FDX_CAP: 5421 *(uint8_t *)pr_val = 5422 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5423 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5424 break; 5425 case MAC_PROP_ADV_1000HDX_CAP: 5426 case MAC_PROP_EN_1000HDX_CAP: 5427 *(uint8_t *)pr_val = 5428 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5429 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5430 break; 5431 case MAC_PROP_ADV_100FDX_CAP: 5432 case MAC_PROP_EN_100FDX_CAP: 5433 *(uint8_t *)pr_val = 5434 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5435 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5436 case MAC_PROP_ADV_100HDX_CAP: 5437 case MAC_PROP_EN_100HDX_CAP: 5438 *(uint8_t *)pr_val = 5439 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5440 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5441 break; 5442 case MAC_PROP_ADV_10FDX_CAP: 5443 case MAC_PROP_EN_10FDX_CAP: 5444 *(uint8_t *)pr_val = 5445 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5446 break; 5447 case MAC_PROP_ADV_10HDX_CAP: 5448 case MAC_PROP_EN_10HDX_CAP: 5449 *(uint8_t *)pr_val = 5450 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5451 break; 5452 default: 5453 err = ENOTSUP; 5454 break; 5455 } 5456 return (err); 5457 } 5458 5459 /* 5460 * synchronize the adv* and en* parameters. 5461 * 5462 * See comments in <sys/dld.h> for details of the *_en_* 5463 * parameters. The usage of ndd for setting adv parameters will 5464 * synchronize all the en parameters with the e1000g parameters, 5465 * implicity disalbing any settings made via dladm. 5466 */ 5467 static void 5468 e1000g_param_sync(struct e1000g *Adapter) 5469 { 5470 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5471 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5472 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5473 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5474 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5475 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5476 } 5477