1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000_OSDEP_H 27 #define _E1000_OSDEP_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/types.h> 34 #include <sys/conf.h> 35 #include <sys/debug.h> 36 #include <sys/stropts.h> 37 #include <sys/stream.h> 38 #include <sys/strlog.h> 39 #include <sys/kmem.h> 40 #include <sys/stat.h> 41 #include <sys/kstat.h> 42 #include <sys/modctl.h> 43 #include <sys/errno.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 #include <sys/pci.h> 47 #include <sys/atomic.h> 48 #include <sys/note.h> 49 #include <sys/mutex.h> 50 #include <sys/pci_cap.h> 51 #include "e1000g_debug.h" 52 53 #define usec_delay(x) drv_usecwait(x) 54 #define msec_delay(x) drv_usecwait(x * 1000) 55 #define msec_delay_irq msec_delay 56 57 #ifdef E1000G_DEBUG 58 #define DEBUGOUT(S) \ 59 E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) 60 #define DEBUGOUT1(S, A) \ 61 E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) 62 #define DEBUGOUT2(S, A, B) \ 63 E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) 64 #define DEBUGOUT3(S, A, B, C) \ 65 E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) 66 #define DEBUGFUNC(F) \ 67 E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) 68 #else 69 #define DEBUGOUT(S) 70 #define DEBUGOUT1(S, A) 71 #define DEBUGOUT2(S, A, B) 72 #define DEBUGOUT3(S, A, B, C) 73 #define DEBUGFUNC(F) 74 #endif 75 76 #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 77 78 #define false 0 79 #define true 1 80 #define FALSE false 81 #define TRUE true 82 83 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 84 #define PCI_COMMAND_REGISTER 0x04 85 #define PCI_EX_CONF_CAP 0xE0 86 #define ADAPTER_REG_SET 1 /* solaris mapping of adapter registers */ 87 #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 88 89 #define RECEIVE_BUFFER_ALIGN_SIZE 256 90 #define E1000_MDALIGN 4096 91 #define E1000_MDALIGN_82546 65536 92 #define E1000_ERT_2048 0x100 93 94 /* PHY Extended Status Register */ 95 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 96 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 97 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 98 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 99 100 /* 101 * required by shared code 102 */ 103 #define E1000_WRITE_FLUSH(a) (void)E1000_READ_REG(a, E1000_STATUS) 104 105 #define E1000_WRITE_REG(hw, reg, value) \ 106 {\ 107 if ((hw)->mac.type != e1000_82542) \ 108 ddi_put32((OS_DEP(hw))->reg_handle, \ 109 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \ 110 value); \ 111 else \ 112 ddi_put32((OS_DEP(hw))->reg_handle, \ 113 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 114 e1000_translate_register_82542(reg)), \ 115 value); \ 116 } 117 118 #define E1000_READ_REG(hw, reg) (\ 119 ((hw)->mac.type != e1000_82542) ? \ 120 ddi_get32((OS_DEP(hw))->reg_handle, \ 121 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \ 122 ddi_get32((OS_DEP(hw))->reg_handle, \ 123 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 124 e1000_translate_register_82542(reg)))) 125 126 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 127 {\ 128 if ((hw)->mac.type != e1000_82542) \ 129 ddi_put32((OS_DEP(hw))->reg_handle, \ 130 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 131 reg + ((offset) << 2)),\ 132 value); \ 133 else \ 134 ddi_put32((OS_DEP(hw))->reg_handle, \ 135 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 136 e1000_translate_register_82542(reg) + \ 137 ((offset) << 2)), value); \ 138 } 139 140 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ 141 ((hw)->mac.type != e1000_82542) ? \ 142 ddi_get32((OS_DEP(hw))->reg_handle, \ 143 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + \ 144 ((offset) << 2))) : \ 145 ddi_get32((OS_DEP(hw))->reg_handle, \ 146 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 147 e1000_translate_register_82542(reg) + \ 148 ((offset) << 2)))) 149 150 151 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ 152 E1000_WRITE_REG_ARRAY(a, reg, offset, value) 153 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ 154 E1000_READ_REG_ARRAY(a, reg, offset) 155 156 157 #define E1000_READ_FLASH_REG(hw, reg) \ 158 ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 159 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg))) 160 161 #define E1000_READ_FLASH_REG16(hw, reg) \ 162 ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 163 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg))) 164 165 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 166 ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 167 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 168 169 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 170 ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 171 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 172 173 #define UNREFERENCED_1PARAMETER(_p) _NOTE(ARGUNUSED(_p)) 174 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q)) 175 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r)) 176 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s)) 177 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) \ 178 _NOTE(ARGUNUSED(_p, _q, _r, _s, _t)) 179 180 typedef int8_t s8; 181 typedef int16_t s16; 182 typedef int32_t s32; 183 typedef int64_t s64; 184 typedef uint8_t u8; 185 typedef uint16_t u16; 186 typedef uint32_t u32; 187 typedef uint64_t u64; 188 typedef boolean_t bool; 189 190 #define __le16 u16 191 #define __le32 u32 192 #define __le64 u64 193 194 struct e1000g_osdep { 195 ddi_acc_handle_t reg_handle; 196 ddi_acc_handle_t cfg_handle; 197 ddi_acc_handle_t ich_flash_handle; 198 ddi_acc_handle_t io_reg_handle; 199 struct e1000g *adapter; 200 }; 201 202 /* Shared Code Mutex Defines */ 203 #define E1000_MUTEX kmutex_t 204 #define E1000_MUTEX_INIT(mutex) mutex_init(mutex, NULL, \ 205 MUTEX_DRIVER, NULL) 206 #define E1000_MUTEX_DESTROY(mutex) mutex_destroy(mutex) 207 208 #define E1000_MUTEX_LOCK(mutex) mutex_enter(mutex) 209 #define E1000_MUTEX_TRYLOCK(mutex) mutex_tryenter(mutex) 210 #define E1000_MUTEX_UNLOCK(mutex) mutex_exit(mutex) 211 212 #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 213 #define E1000_WRITE_REG_IO E1000_WRITE_REG 214 #else /* on x86, use port io routines */ 215 #define E1000_WRITE_REG_IO(a, reg, val) { \ 216 ddi_put32((OS_DEP(a))->io_reg_handle, \ 217 (uint32_t *)(a)->io_base, \ 218 reg); \ 219 ddi_put32((OS_DEP(a))->io_reg_handle, \ 220 (uint32_t *)((a)->io_base + 4), \ 221 val); \ 222 } 223 #endif /* __sparc */ 224 225 #ifdef __cplusplus 226 } 227 #endif 228 229 #endif /* _E1000_OSDEP_H */ 230