1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82576 Gigabit Network Connection 40 * 82576 Quad Port Gigabit Mezzanine Adapter 41 * 82580 Gigabit Network Connection 42 * I350 Gigabit Network Connection 43 */ 44 45 #include "e1000_api.h" 46 #include "e1000_i210.h" 47 48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51 static void e1000_release_phy_82575(struct e1000_hw *hw); 52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53 static void e1000_release_nvm_82575(struct e1000_hw *hw); 54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 57 u16 *duplex); 58 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61 u16 *data); 62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65 u32 offset, u16 *data); 66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67 u32 offset, u16 data); 68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69 bool active); 70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71 bool active); 72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73 bool active); 74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80 u32 offset, u16 data); 81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84 u16 *speed, u16 *duplex); 85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99 u16 offset); 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101 u16 offset); 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw); 106 107 static void e1000_i2c_start(struct e1000_hw *hw); 108 static void e1000_i2c_stop(struct e1000_hw *hw); 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw); 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117 static bool e1000_get_i2c_data(u32 *i2cctl); 118 119 static const u16 e1000_82580_rxpbs_table[] = { 120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 121 #define E1000_82580_RXPBS_TABLE_SIZE \ 122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 123 124 125 /** 126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 127 * @hw: pointer to the HW structure 128 * 129 * Called to determine if the I2C pins are being used for I2C or as an 130 * external MDIO interface since the two options are mutually exclusive. 131 **/ 132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 133 { 134 u32 reg = 0; 135 bool ext_mdio = FALSE; 136 137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 138 139 switch (hw->mac.type) { 140 case e1000_82575: 141 case e1000_82576: 142 reg = E1000_READ_REG(hw, E1000_MDIC); 143 ext_mdio = !!(reg & E1000_MDIC_DEST); 144 break; 145 case e1000_82580: 146 case e1000_i350: 147 case e1000_i210: 148 case e1000_i211: 149 reg = E1000_READ_REG(hw, E1000_MDICNFG); 150 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 151 break; 152 default: 153 break; 154 } 155 return ext_mdio; 156 } 157 158 /** 159 * e1000_init_phy_params_82575 - Init PHY func ptrs. 160 * @hw: pointer to the HW structure 161 **/ 162 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 163 { 164 struct e1000_phy_info *phy = &hw->phy; 165 s32 ret_val = E1000_SUCCESS; 166 u32 ctrl_ext; 167 168 DEBUGFUNC("e1000_init_phy_params_82575"); 169 170 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 171 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 172 173 if (hw->phy.media_type != e1000_media_type_copper) { 174 phy->type = e1000_phy_none; 175 goto out; 176 } 177 178 phy->ops.power_up = e1000_power_up_phy_copper; 179 phy->ops.power_down = e1000_power_down_phy_copper_82575; 180 181 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 182 phy->reset_delay_us = 100; 183 184 phy->ops.acquire = e1000_acquire_phy_82575; 185 phy->ops.check_reset_block = e1000_check_reset_block_generic; 186 phy->ops.commit = e1000_phy_sw_reset_generic; 187 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 188 phy->ops.release = e1000_release_phy_82575; 189 190 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 191 192 if (e1000_sgmii_active_82575(hw)) { 193 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 194 ctrl_ext |= E1000_CTRL_I2C_ENA; 195 } else { 196 phy->ops.reset = e1000_phy_hw_reset_generic; 197 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 198 } 199 200 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 201 e1000_reset_mdicnfg_82580(hw); 202 203 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 204 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 205 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 206 } else { 207 switch (hw->mac.type) { 208 case e1000_82580: 209 case e1000_i350: 210 phy->ops.read_reg = e1000_read_phy_reg_82580; 211 phy->ops.write_reg = e1000_write_phy_reg_82580; 212 break; 213 case e1000_i210: 214 case e1000_i211: 215 phy->ops.read_reg = e1000_read_phy_reg_gs40g; 216 phy->ops.write_reg = e1000_write_phy_reg_gs40g; 217 break; 218 default: 219 phy->ops.read_reg = e1000_read_phy_reg_igp; 220 phy->ops.write_reg = e1000_write_phy_reg_igp; 221 } 222 } 223 224 /* Set phy->phy_addr and phy->id. */ 225 ret_val = e1000_get_phy_id_82575(hw); 226 227 /* Verify phy id and set remaining function pointers */ 228 switch (phy->id) { 229 case I347AT4_E_PHY_ID: 230 case M88E1112_E_PHY_ID: 231 case M88E1340M_E_PHY_ID: 232 case M88E1111_I_PHY_ID: 233 phy->type = e1000_phy_m88; 234 phy->ops.check_polarity = e1000_check_polarity_m88; 235 phy->ops.get_info = e1000_get_phy_info_m88; 236 if (phy->id == I347AT4_E_PHY_ID || 237 phy->id == M88E1112_E_PHY_ID || 238 phy->id == M88E1340M_E_PHY_ID) 239 phy->ops.get_cable_length = 240 e1000_get_cable_length_m88_gen2; 241 else 242 phy->ops.get_cable_length = e1000_get_cable_length_m88; 243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 244 break; 245 case IGP03E1000_E_PHY_ID: 246 case IGP04E1000_E_PHY_ID: 247 phy->type = e1000_phy_igp_3; 248 phy->ops.check_polarity = e1000_check_polarity_igp; 249 phy->ops.get_info = e1000_get_phy_info_igp; 250 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 252 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 253 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 254 break; 255 case I82580_I_PHY_ID: 256 case I350_I_PHY_ID: 257 phy->type = e1000_phy_82580; 258 phy->ops.check_polarity = e1000_check_polarity_82577; 259 phy->ops.force_speed_duplex = 260 e1000_phy_force_speed_duplex_82577; 261 phy->ops.get_cable_length = e1000_get_cable_length_82577; 262 phy->ops.get_info = e1000_get_phy_info_82577; 263 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 264 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 265 break; 266 case I210_I_PHY_ID: 267 phy->type = e1000_phy_i210; 268 phy->ops.check_polarity = e1000_check_polarity_m88; 269 phy->ops.get_info = e1000_get_phy_info_m88; 270 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 273 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 274 break; 275 default: 276 ret_val = -E1000_ERR_PHY; 277 goto out; 278 } 279 280 out: 281 return ret_val; 282 } 283 284 /** 285 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 286 * @hw: pointer to the HW structure 287 **/ 288 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 289 { 290 struct e1000_nvm_info *nvm = &hw->nvm; 291 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 292 u16 size; 293 294 DEBUGFUNC("e1000_init_nvm_params_82575"); 295 296 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 297 E1000_EECD_SIZE_EX_SHIFT); 298 /* 299 * Added to a constant, "size" becomes the left-shift value 300 * for setting word_size. 301 */ 302 size += NVM_WORD_SIZE_BASE_SHIFT; 303 304 /* Just in case size is out of range, cap it to the largest 305 * EEPROM size supported 306 */ 307 if (size > 15) 308 size = 15; 309 310 nvm->word_size = 1 << size; 311 if (hw->mac.type < e1000_i210) { 312 nvm->opcode_bits = 8; 313 nvm->delay_usec = 1; 314 315 switch (nvm->override) { 316 case e1000_nvm_override_spi_large: 317 nvm->page_size = 32; 318 nvm->address_bits = 16; 319 break; 320 case e1000_nvm_override_spi_small: 321 nvm->page_size = 8; 322 nvm->address_bits = 8; 323 break; 324 default: 325 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 326 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 327 16 : 8; 328 break; 329 } 330 if (nvm->word_size == (1 << 15)) 331 nvm->page_size = 128; 332 333 nvm->type = e1000_nvm_eeprom_spi; 334 } else { 335 nvm->type = e1000_nvm_flash_hw; 336 } 337 338 /* Function Pointers */ 339 nvm->ops.acquire = e1000_acquire_nvm_82575; 340 nvm->ops.release = e1000_release_nvm_82575; 341 if (nvm->word_size < (1 << 15)) 342 nvm->ops.read = e1000_read_nvm_eerd; 343 else 344 nvm->ops.read = e1000_read_nvm_spi; 345 346 nvm->ops.write = e1000_write_nvm_spi; 347 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 348 nvm->ops.update = e1000_update_nvm_checksum_generic; 349 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 350 351 /* override generic family function pointers for specific descendants */ 352 switch (hw->mac.type) { 353 case e1000_82580: 354 nvm->ops.validate = e1000_validate_nvm_checksum_82580; 355 nvm->ops.update = e1000_update_nvm_checksum_82580; 356 break; 357 case e1000_i350: 358 nvm->ops.validate = e1000_validate_nvm_checksum_i350; 359 nvm->ops.update = e1000_update_nvm_checksum_i350; 360 break; 361 default: 362 break; 363 } 364 365 return E1000_SUCCESS; 366 } 367 368 /** 369 * e1000_init_mac_params_82575 - Init MAC func ptrs. 370 * @hw: pointer to the HW structure 371 **/ 372 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 373 { 374 struct e1000_mac_info *mac = &hw->mac; 375 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 376 377 DEBUGFUNC("e1000_init_mac_params_82575"); 378 379 /* Derives media type */ 380 e1000_get_media_type_82575(hw); 381 /* Set mta register count */ 382 mac->mta_reg_count = 128; 383 /* Set uta register count */ 384 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 385 /* Set rar entry count */ 386 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 387 if (mac->type == e1000_82576) 388 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 389 if (mac->type == e1000_82580) 390 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 391 if (mac->type == e1000_i350) 392 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 393 394 /* Enable EEE default settings for EEE supported devices */ 395 if (mac->type >= e1000_i350) 396 dev_spec->eee_disable = TRUE; 397 398 /* Allow a single clear of the SW semaphore on I210 and newer */ 399 if (mac->type >= e1000_i210) 400 dev_spec->clear_semaphore_once = TRUE; 401 402 /* Set if part includes ASF firmware */ 403 mac->asf_firmware_present = TRUE; 404 /* FWSM register */ 405 mac->has_fwsm = TRUE; 406 /* ARC supported; valid only if manageability features are enabled. */ 407 mac->arc_subsystem_valid = 408 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 409 410 /* Function pointers */ 411 412 /* bus type/speed/width */ 413 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 414 /* reset */ 415 if (mac->type >= e1000_82580) 416 mac->ops.reset_hw = e1000_reset_hw_82580; 417 else 418 mac->ops.reset_hw = e1000_reset_hw_82575; 419 /* hw initialization */ 420 mac->ops.init_hw = e1000_init_hw_82575; 421 /* link setup */ 422 mac->ops.setup_link = e1000_setup_link_generic; 423 /* physical interface link setup */ 424 mac->ops.setup_physical_interface = 425 (hw->phy.media_type == e1000_media_type_copper) 426 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 427 /* physical interface shutdown */ 428 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 429 /* physical interface power up */ 430 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 431 /* check for link */ 432 mac->ops.check_for_link = e1000_check_for_link_82575; 433 /* read mac address */ 434 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 435 /* configure collision distance */ 436 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 437 /* multicast address update */ 438 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 439 if (mac->type == e1000_i350) { 440 /* writing VFTA */ 441 mac->ops.write_vfta = e1000_write_vfta_i350; 442 /* clearing VFTA */ 443 mac->ops.clear_vfta = e1000_clear_vfta_i350; 444 } else { 445 /* writing VFTA */ 446 mac->ops.write_vfta = e1000_write_vfta_generic; 447 /* clearing VFTA */ 448 mac->ops.clear_vfta = e1000_clear_vfta_generic; 449 } 450 if (hw->mac.type >= e1000_82580) 451 mac->ops.validate_mdi_setting = 452 e1000_validate_mdi_setting_crossover_generic; 453 /* ID LED init */ 454 mac->ops.id_led_init = e1000_id_led_init_generic; 455 /* blink LED */ 456 mac->ops.blink_led = e1000_blink_led_generic; 457 /* setup LED */ 458 mac->ops.setup_led = e1000_setup_led_generic; 459 /* cleanup LED */ 460 mac->ops.cleanup_led = e1000_cleanup_led_generic; 461 /* turn on/off LED */ 462 mac->ops.led_on = e1000_led_on_generic; 463 mac->ops.led_off = e1000_led_off_generic; 464 /* clear hardware counters */ 465 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 466 /* link info */ 467 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 468 /* acquire SW_FW sync */ 469 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 470 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 471 if (mac->type >= e1000_i210) { 472 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 473 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 474 } 475 476 /* set lan id for port to determine which phy lock to use */ 477 hw->mac.ops.set_lan_id(hw); 478 479 return E1000_SUCCESS; 480 } 481 482 /** 483 * e1000_init_function_pointers_82575 - Init func ptrs. 484 * @hw: pointer to the HW structure 485 * 486 * Called to initialize all function pointers and parameters. 487 **/ 488 void e1000_init_function_pointers_82575(struct e1000_hw *hw) 489 { 490 DEBUGFUNC("e1000_init_function_pointers_82575"); 491 492 hw->mac.ops.init_params = e1000_init_mac_params_82575; 493 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 494 hw->phy.ops.init_params = e1000_init_phy_params_82575; 495 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 496 } 497 498 /** 499 * e1000_acquire_phy_82575 - Acquire rights to access PHY 500 * @hw: pointer to the HW structure 501 * 502 * Acquire access rights to the correct PHY. 503 **/ 504 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 505 { 506 u16 mask = E1000_SWFW_PHY0_SM; 507 508 DEBUGFUNC("e1000_acquire_phy_82575"); 509 510 if (hw->bus.func == E1000_FUNC_1) 511 mask = E1000_SWFW_PHY1_SM; 512 else if (hw->bus.func == E1000_FUNC_2) 513 mask = E1000_SWFW_PHY2_SM; 514 else if (hw->bus.func == E1000_FUNC_3) 515 mask = E1000_SWFW_PHY3_SM; 516 517 return hw->mac.ops.acquire_swfw_sync(hw, mask); 518 } 519 520 /** 521 * e1000_release_phy_82575 - Release rights to access PHY 522 * @hw: pointer to the HW structure 523 * 524 * A wrapper to release access rights to the correct PHY. 525 **/ 526 static void e1000_release_phy_82575(struct e1000_hw *hw) 527 { 528 u16 mask = E1000_SWFW_PHY0_SM; 529 530 DEBUGFUNC("e1000_release_phy_82575"); 531 532 if (hw->bus.func == E1000_FUNC_1) 533 mask = E1000_SWFW_PHY1_SM; 534 else if (hw->bus.func == E1000_FUNC_2) 535 mask = E1000_SWFW_PHY2_SM; 536 else if (hw->bus.func == E1000_FUNC_3) 537 mask = E1000_SWFW_PHY3_SM; 538 539 hw->mac.ops.release_swfw_sync(hw, mask); 540 } 541 542 /** 543 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 544 * @hw: pointer to the HW structure 545 * @offset: register offset to be read 546 * @data: pointer to the read data 547 * 548 * Reads the PHY register at offset using the serial gigabit media independent 549 * interface and stores the retrieved information in data. 550 **/ 551 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 552 u16 *data) 553 { 554 s32 ret_val = -E1000_ERR_PARAM; 555 556 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 557 558 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 559 DEBUGOUT1("PHY Address %u is out of range\n", offset); 560 goto out; 561 } 562 563 ret_val = hw->phy.ops.acquire(hw); 564 if (ret_val) 565 goto out; 566 567 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 568 569 hw->phy.ops.release(hw); 570 571 out: 572 return ret_val; 573 } 574 575 /** 576 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 577 * @hw: pointer to the HW structure 578 * @offset: register offset to write to 579 * @data: data to write at register offset 580 * 581 * Writes the data to PHY register at the offset using the serial gigabit 582 * media independent interface. 583 **/ 584 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 585 u16 data) 586 { 587 s32 ret_val = -E1000_ERR_PARAM; 588 589 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 590 591 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 592 DEBUGOUT1("PHY Address %d is out of range\n", offset); 593 goto out; 594 } 595 596 ret_val = hw->phy.ops.acquire(hw); 597 if (ret_val) 598 goto out; 599 600 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 601 602 hw->phy.ops.release(hw); 603 604 out: 605 return ret_val; 606 } 607 608 /** 609 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 610 * @hw: pointer to the HW structure 611 * 612 * Retrieves the PHY address and ID for both PHY's which do and do not use 613 * sgmi interface. 614 **/ 615 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 616 { 617 struct e1000_phy_info *phy = &hw->phy; 618 s32 ret_val = E1000_SUCCESS; 619 u16 phy_id; 620 u32 ctrl_ext; 621 u32 mdic; 622 623 DEBUGFUNC("e1000_get_phy_id_82575"); 624 625 /* 626 * For SGMII PHYs, we try the list of possible addresses until 627 * we find one that works. For non-SGMII PHYs 628 * (e.g. integrated copper PHYs), an address of 1 should 629 * work. The result of this function should mean phy->phy_addr 630 * and phy->id are set correctly. 631 */ 632 if (!e1000_sgmii_active_82575(hw)) { 633 phy->addr = 1; 634 ret_val = e1000_get_phy_id(hw); 635 goto out; 636 } 637 638 if (e1000_sgmii_uses_mdio_82575(hw)) { 639 switch (hw->mac.type) { 640 case e1000_82575: 641 case e1000_82576: 642 mdic = E1000_READ_REG(hw, E1000_MDIC); 643 mdic &= E1000_MDIC_PHY_MASK; 644 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 645 break; 646 case e1000_82580: 647 case e1000_i350: 648 case e1000_i210: 649 case e1000_i211: 650 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 651 mdic &= E1000_MDICNFG_PHY_MASK; 652 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 653 break; 654 default: 655 ret_val = -E1000_ERR_PHY; 656 goto out; 657 break; 658 } 659 ret_val = e1000_get_phy_id(hw); 660 goto out; 661 } 662 663 /* Power on sgmii phy if it is disabled */ 664 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 665 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 666 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 667 E1000_WRITE_FLUSH(hw); 668 msec_delay(300); 669 670 /* 671 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 672 * Therefore, we need to test 1-7 673 */ 674 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 675 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 676 if (ret_val == E1000_SUCCESS) { 677 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 678 phy_id, phy->addr); 679 /* 680 * At the time of this writing, The M88 part is 681 * the only supported SGMII PHY product. 682 */ 683 if (phy_id == M88_VENDOR) 684 break; 685 } else { 686 DEBUGOUT1("PHY address %u was unreadable\n", 687 phy->addr); 688 } 689 } 690 691 /* A valid PHY type couldn't be found. */ 692 if (phy->addr == 8) { 693 phy->addr = 0; 694 ret_val = -E1000_ERR_PHY; 695 } else { 696 ret_val = e1000_get_phy_id(hw); 697 } 698 699 /* restore previous sfp cage power state */ 700 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 701 702 out: 703 return ret_val; 704 } 705 706 /** 707 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 708 * @hw: pointer to the HW structure 709 * 710 * Resets the PHY using the serial gigabit media independent interface. 711 **/ 712 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 713 { 714 s32 ret_val = E1000_SUCCESS; 715 716 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 717 718 /* 719 * This isn't a TRUE "hard" reset, but is the only reset 720 * available to us at this time. 721 */ 722 723 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 724 725 if (!(hw->phy.ops.write_reg)) 726 goto out; 727 728 /* 729 * SFP documentation requires the following to configure the SPF module 730 * to work on SGMII. No further documentation is given. 731 */ 732 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 733 if (ret_val) 734 goto out; 735 736 ret_val = hw->phy.ops.commit(hw); 737 738 out: 739 return ret_val; 740 } 741 742 /** 743 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 744 * @hw: pointer to the HW structure 745 * @active: TRUE to enable LPLU, FALSE to disable 746 * 747 * Sets the LPLU D0 state according to the active flag. When 748 * activating LPLU this function also disables smart speed 749 * and vice versa. LPLU will not be activated unless the 750 * device autonegotiation advertisement meets standards of 751 * either 10 or 10/100 or 10/100/1000 at all duplexes. 752 * This is a function pointer entry point only called by 753 * PHY setup routines. 754 **/ 755 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 756 { 757 struct e1000_phy_info *phy = &hw->phy; 758 s32 ret_val = E1000_SUCCESS; 759 u16 data; 760 761 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 762 763 if (!(hw->phy.ops.read_reg)) 764 goto out; 765 766 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 767 if (ret_val) 768 goto out; 769 770 if (active) { 771 data |= IGP02E1000_PM_D0_LPLU; 772 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 773 data); 774 if (ret_val) 775 goto out; 776 777 /* When LPLU is enabled, we should disable SmartSpeed */ 778 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 779 &data); 780 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 782 data); 783 if (ret_val) 784 goto out; 785 } else { 786 data &= ~IGP02E1000_PM_D0_LPLU; 787 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 788 data); 789 /* 790 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 791 * during Dx states where the power conservation is most 792 * important. During driver activity we should enable 793 * SmartSpeed, so performance is maintained. 794 */ 795 if (phy->smart_speed == e1000_smart_speed_on) { 796 ret_val = phy->ops.read_reg(hw, 797 IGP01E1000_PHY_PORT_CONFIG, 798 &data); 799 if (ret_val) 800 goto out; 801 802 data |= IGP01E1000_PSCFR_SMART_SPEED; 803 ret_val = phy->ops.write_reg(hw, 804 IGP01E1000_PHY_PORT_CONFIG, 805 data); 806 if (ret_val) 807 goto out; 808 } else if (phy->smart_speed == e1000_smart_speed_off) { 809 ret_val = phy->ops.read_reg(hw, 810 IGP01E1000_PHY_PORT_CONFIG, 811 &data); 812 if (ret_val) 813 goto out; 814 815 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 816 ret_val = phy->ops.write_reg(hw, 817 IGP01E1000_PHY_PORT_CONFIG, 818 data); 819 if (ret_val) 820 goto out; 821 } 822 } 823 824 out: 825 return ret_val; 826 } 827 828 /** 829 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 830 * @hw: pointer to the HW structure 831 * @active: TRUE to enable LPLU, FALSE to disable 832 * 833 * Sets the LPLU D0 state according to the active flag. When 834 * activating LPLU this function also disables smart speed 835 * and vice versa. LPLU will not be activated unless the 836 * device autonegotiation advertisement meets standards of 837 * either 10 or 10/100 or 10/100/1000 at all duplexes. 838 * This is a function pointer entry point only called by 839 * PHY setup routines. 840 **/ 841 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 842 { 843 struct e1000_phy_info *phy = &hw->phy; 844 s32 ret_val = E1000_SUCCESS; 845 u32 data; 846 847 DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 848 849 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 850 851 if (active) { 852 data |= E1000_82580_PM_D0_LPLU; 853 854 /* When LPLU is enabled, we should disable SmartSpeed */ 855 data &= ~E1000_82580_PM_SPD; 856 } else { 857 data &= ~E1000_82580_PM_D0_LPLU; 858 859 /* 860 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 861 * during Dx states where the power conservation is most 862 * important. During driver activity we should enable 863 * SmartSpeed, so performance is maintained. 864 */ 865 if (phy->smart_speed == e1000_smart_speed_on) 866 data |= E1000_82580_PM_SPD; 867 else if (phy->smart_speed == e1000_smart_speed_off) 868 data &= ~E1000_82580_PM_SPD; 869 } 870 871 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 872 return ret_val; 873 } 874 875 /** 876 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 877 * @hw: pointer to the HW structure 878 * @active: boolean used to enable/disable lplu 879 * 880 * Success returns 0, Failure returns 1 881 * 882 * The low power link up (lplu) state is set to the power management level D3 883 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 884 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 885 * is used during Dx states where the power conservation is most important. 886 * During driver activity, SmartSpeed should be enabled so performance is 887 * maintained. 888 **/ 889 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 890 { 891 struct e1000_phy_info *phy = &hw->phy; 892 s32 ret_val = E1000_SUCCESS; 893 u32 data; 894 895 DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 896 897 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 898 899 if (!active) { 900 data &= ~E1000_82580_PM_D3_LPLU; 901 /* 902 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 903 * during Dx states where the power conservation is most 904 * important. During driver activity we should enable 905 * SmartSpeed, so performance is maintained. 906 */ 907 if (phy->smart_speed == e1000_smart_speed_on) 908 data |= E1000_82580_PM_SPD; 909 else if (phy->smart_speed == e1000_smart_speed_off) 910 data &= ~E1000_82580_PM_SPD; 911 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 912 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 913 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 914 data |= E1000_82580_PM_D3_LPLU; 915 /* When LPLU is enabled, we should disable SmartSpeed */ 916 data &= ~E1000_82580_PM_SPD; 917 } 918 919 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 920 return ret_val; 921 } 922 923 /** 924 * e1000_acquire_nvm_82575 - Request for access to EEPROM 925 * @hw: pointer to the HW structure 926 * 927 * Acquire the necessary semaphores for exclusive access to the EEPROM. 928 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 929 * Return successful if access grant bit set, else clear the request for 930 * EEPROM access and return -E1000_ERR_NVM (-1). 931 **/ 932 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 933 { 934 s32 ret_val; 935 936 DEBUGFUNC("e1000_acquire_nvm_82575"); 937 938 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 939 if (ret_val) 940 goto out; 941 942 /* 943 * Check if there is some access 944 * error this access may hook on 945 */ 946 if (hw->mac.type == e1000_i350) { 947 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 948 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 949 E1000_EECD_TIMEOUT)) { 950 /* Clear all access error flags */ 951 E1000_WRITE_REG(hw, E1000_EECD, eecd | 952 E1000_EECD_ERROR_CLR); 953 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 954 } 955 } 956 if (hw->mac.type == e1000_82580) { 957 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 958 if (eecd & E1000_EECD_BLOCKED) { 959 /* Clear access error flag */ 960 E1000_WRITE_REG(hw, E1000_EECD, eecd | 961 E1000_EECD_BLOCKED); 962 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 963 } 964 } 965 966 967 ret_val = e1000_acquire_nvm_generic(hw); 968 if (ret_val) 969 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 970 971 out: 972 return ret_val; 973 } 974 975 /** 976 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 977 * @hw: pointer to the HW structure 978 * 979 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 980 * then release the semaphores acquired. 981 **/ 982 static void e1000_release_nvm_82575(struct e1000_hw *hw) 983 { 984 DEBUGFUNC("e1000_release_nvm_82575"); 985 986 e1000_release_nvm_generic(hw); 987 988 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 989 } 990 991 /** 992 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 993 * @hw: pointer to the HW structure 994 * @mask: specifies which semaphore to acquire 995 * 996 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 997 * will also specify which port we're acquiring the lock for. 998 **/ 999 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1000 { 1001 u32 swfw_sync; 1002 u32 swmask = mask; 1003 u32 fwmask = mask << 16; 1004 s32 ret_val = E1000_SUCCESS; 1005 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 1006 1007 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 1008 1009 while (i < timeout) { 1010 if (e1000_get_hw_semaphore_generic(hw)) { 1011 ret_val = -E1000_ERR_SWFW_SYNC; 1012 goto out; 1013 } 1014 1015 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1016 if (!(swfw_sync & (fwmask | swmask))) 1017 break; 1018 1019 /* 1020 * Firmware currently using resource (fwmask) 1021 * or other software thread using resource (swmask) 1022 */ 1023 e1000_put_hw_semaphore_generic(hw); 1024 msec_delay_irq(5); 1025 i++; 1026 } 1027 1028 if (i == timeout) { 1029 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1030 ret_val = -E1000_ERR_SWFW_SYNC; 1031 goto out; 1032 } 1033 1034 swfw_sync |= swmask; 1035 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1036 1037 e1000_put_hw_semaphore_generic(hw); 1038 1039 out: 1040 return ret_val; 1041 } 1042 1043 /** 1044 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1045 * @hw: pointer to the HW structure 1046 * @mask: specifies which semaphore to acquire 1047 * 1048 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1049 * will also specify which port we're releasing the lock for. 1050 **/ 1051 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1052 { 1053 u32 swfw_sync; 1054 1055 DEBUGFUNC("e1000_release_swfw_sync_82575"); 1056 1057 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1058 ; /* Empty */ 1059 1060 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1061 swfw_sync &= ~mask; 1062 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1063 1064 e1000_put_hw_semaphore_generic(hw); 1065 } 1066 1067 /** 1068 * e1000_get_cfg_done_82575 - Read config done bit 1069 * @hw: pointer to the HW structure 1070 * 1071 * Read the management control register for the config done bit for 1072 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1073 * to read the config done bit, so an error is *ONLY* logged and returns 1074 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1075 * would not be able to be reset or change link. 1076 **/ 1077 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1078 { 1079 s32 timeout = PHY_CFG_TIMEOUT; 1080 s32 ret_val = E1000_SUCCESS; 1081 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1082 1083 DEBUGFUNC("e1000_get_cfg_done_82575"); 1084 1085 if (hw->bus.func == E1000_FUNC_1) 1086 mask = E1000_NVM_CFG_DONE_PORT_1; 1087 else if (hw->bus.func == E1000_FUNC_2) 1088 mask = E1000_NVM_CFG_DONE_PORT_2; 1089 else if (hw->bus.func == E1000_FUNC_3) 1090 mask = E1000_NVM_CFG_DONE_PORT_3; 1091 while (timeout) { 1092 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1093 break; 1094 msec_delay(1); 1095 timeout--; 1096 } 1097 if (!timeout) 1098 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1099 1100 /* If EEPROM is not marked present, init the PHY manually */ 1101 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1102 (hw->phy.type == e1000_phy_igp_3)) 1103 e1000_phy_init_script_igp3(hw); 1104 1105 return ret_val; 1106 } 1107 1108 /** 1109 * e1000_get_link_up_info_82575 - Get link speed/duplex info 1110 * @hw: pointer to the HW structure 1111 * @speed: stores the current speed 1112 * @duplex: stores the current duplex 1113 * 1114 * This is a wrapper function, if using the serial gigabit media independent 1115 * interface, use PCS to retrieve the link speed and duplex information. 1116 * Otherwise, use the generic function to get the link speed and duplex info. 1117 **/ 1118 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1119 u16 *duplex) 1120 { 1121 s32 ret_val; 1122 1123 DEBUGFUNC("e1000_get_link_up_info_82575"); 1124 1125 if (hw->phy.media_type != e1000_media_type_copper) 1126 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1127 duplex); 1128 else 1129 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1130 duplex); 1131 1132 return ret_val; 1133 } 1134 1135 /** 1136 * e1000_check_for_link_82575 - Check for link 1137 * @hw: pointer to the HW structure 1138 * 1139 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1140 * use the generic interface for determining link. 1141 **/ 1142 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1143 { 1144 s32 ret_val; 1145 u16 speed, duplex; 1146 1147 DEBUGFUNC("e1000_check_for_link_82575"); 1148 1149 if (hw->phy.media_type != e1000_media_type_copper) { 1150 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1151 &duplex); 1152 /* 1153 * Use this flag to determine if link needs to be checked or 1154 * not. If we have link clear the flag so that we do not 1155 * continue to check for link. 1156 */ 1157 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1158 1159 /* 1160 * Configure Flow Control now that Auto-Neg has completed. 1161 * First, we need to restore the desired flow control 1162 * settings because we may have had to re-autoneg with a 1163 * different link partner. 1164 */ 1165 ret_val = e1000_config_fc_after_link_up_generic(hw); 1166 if (ret_val) 1167 DEBUGOUT("Error configuring flow control\n"); 1168 } else { 1169 ret_val = e1000_check_for_copper_link_generic(hw); 1170 } 1171 1172 return ret_val; 1173 } 1174 1175 /** 1176 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1177 * @hw: pointer to the HW structure 1178 **/ 1179 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1180 { 1181 u32 reg; 1182 1183 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1184 1185 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1186 !e1000_sgmii_active_82575(hw)) 1187 return; 1188 1189 /* Enable PCS to turn on link */ 1190 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1191 reg |= E1000_PCS_CFG_PCS_EN; 1192 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1193 1194 /* Power up the laser */ 1195 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1196 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1197 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1198 1199 /* flush the write to verify completion */ 1200 E1000_WRITE_FLUSH(hw); 1201 msec_delay(1); 1202 } 1203 1204 /** 1205 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1206 * @hw: pointer to the HW structure 1207 * @speed: stores the current speed 1208 * @duplex: stores the current duplex 1209 * 1210 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1211 * duplex, then store the values in the pointers provided. 1212 **/ 1213 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1214 u16 *speed, u16 *duplex) 1215 { 1216 struct e1000_mac_info *mac = &hw->mac; 1217 u32 pcs; 1218 1219 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1220 1221 /* 1222 * Read the PCS Status register for link state. For non-copper mode, 1223 * the status register is not accurate. The PCS status register is 1224 * used instead. 1225 */ 1226 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1227 1228 /* 1229 * The link up bit determines when link is up on autoneg. 1230 */ 1231 if (pcs & E1000_PCS_LSTS_LINK_OK) { 1232 mac->serdes_has_link = TRUE; 1233 1234 /* Detect and store PCS speed */ 1235 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1236 *speed = SPEED_1000; 1237 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1238 *speed = SPEED_100; 1239 else 1240 *speed = SPEED_10; 1241 1242 /* Detect and store PCS duplex */ 1243 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1244 *duplex = FULL_DUPLEX; 1245 else 1246 *duplex = HALF_DUPLEX; 1247 1248 } else { 1249 mac->serdes_has_link = FALSE; 1250 *speed = 0; 1251 *duplex = 0; 1252 } 1253 1254 return E1000_SUCCESS; 1255 } 1256 1257 /** 1258 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1259 * @hw: pointer to the HW structure 1260 * 1261 * In the case of serdes shut down sfp and PCS on driver unload 1262 * when management pass thru is not enabled. 1263 **/ 1264 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1265 { 1266 u32 reg; 1267 1268 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1269 1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1271 !e1000_sgmii_active_82575(hw)) 1272 return; 1273 1274 if (!e1000_enable_mng_pass_thru(hw)) { 1275 /* Disable PCS to turn off link */ 1276 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1277 reg &= ~E1000_PCS_CFG_PCS_EN; 1278 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1279 1280 /* shutdown the laser */ 1281 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1282 reg |= E1000_CTRL_EXT_SDP3_DATA; 1283 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1284 1285 /* flush the write to verify completion */ 1286 E1000_WRITE_FLUSH(hw); 1287 msec_delay(1); 1288 } 1289 1290 return; 1291 } 1292 1293 /** 1294 * e1000_reset_hw_82575 - Reset hardware 1295 * @hw: pointer to the HW structure 1296 * 1297 * This resets the hardware into a known state. 1298 **/ 1299 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1300 { 1301 u32 ctrl; 1302 s32 ret_val; 1303 1304 DEBUGFUNC("e1000_reset_hw_82575"); 1305 1306 /* 1307 * Prevent the PCI-E bus from sticking if there is no TLP connection 1308 * on the last TLP read/write transaction when MAC is reset. 1309 */ 1310 ret_val = e1000_disable_pcie_master_generic(hw); 1311 if (ret_val) 1312 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1313 1314 /* set the completion timeout for interface */ 1315 ret_val = e1000_set_pcie_completion_timeout(hw); 1316 if (ret_val) 1317 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1318 1319 DEBUGOUT("Masking off all interrupts\n"); 1320 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1321 1322 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1323 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1324 E1000_WRITE_FLUSH(hw); 1325 1326 msec_delay(10); 1327 1328 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1329 1330 DEBUGOUT("Issuing a global reset to MAC\n"); 1331 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1332 1333 ret_val = e1000_get_auto_rd_done_generic(hw); 1334 if (ret_val) { 1335 /* 1336 * When auto config read does not complete, do not 1337 * return with an error. This can happen in situations 1338 * where there is no eeprom and prevents getting link. 1339 */ 1340 DEBUGOUT("Auto Read Done did not complete\n"); 1341 } 1342 1343 /* If EEPROM is not present, run manual init scripts */ 1344 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1345 e1000_reset_init_script_82575(hw); 1346 1347 /* Clear any pending interrupt events. */ 1348 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1349 E1000_READ_REG(hw, E1000_ICR); 1350 1351 /* Install any alternate MAC address into RAR0 */ 1352 ret_val = e1000_check_alt_mac_addr_generic(hw); 1353 1354 return ret_val; 1355 } 1356 1357 /** 1358 * e1000_init_hw_82575 - Initialize hardware 1359 * @hw: pointer to the HW structure 1360 * 1361 * This inits the hardware readying it for operation. 1362 **/ 1363 static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1364 { 1365 struct e1000_mac_info *mac = &hw->mac; 1366 s32 ret_val; 1367 u16 i, rar_count = mac->rar_entry_count; 1368 1369 DEBUGFUNC("e1000_init_hw_82575"); 1370 1371 /* Initialize identification LED */ 1372 ret_val = mac->ops.id_led_init(hw); 1373 if (ret_val) { 1374 DEBUGOUT("Error initializing identification LED\n"); 1375 /* This is not fatal and we should not stop init due to this */ 1376 } 1377 1378 /* Disabling VLAN filtering */ 1379 DEBUGOUT("Initializing the IEEE VLAN\n"); 1380 mac->ops.clear_vfta(hw); 1381 1382 /* Setup the receive address */ 1383 e1000_init_rx_addrs_generic(hw, rar_count); 1384 1385 /* Zero out the Multicast HASH table */ 1386 DEBUGOUT("Zeroing the MTA\n"); 1387 for (i = 0; i < mac->mta_reg_count; i++) 1388 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1389 1390 /* Zero out the Unicast HASH table */ 1391 DEBUGOUT("Zeroing the UTA\n"); 1392 for (i = 0; i < mac->uta_reg_count; i++) 1393 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1394 1395 /* Setup link and flow control */ 1396 ret_val = mac->ops.setup_link(hw); 1397 1398 /* Set the default MTU size */ 1399 hw->dev_spec._82575.mtu = 1500; 1400 1401 /* 1402 * Clear all of the statistics registers (clear on read). It is 1403 * important that we do this after we have tried to establish link 1404 * because the symbol error count will increment wildly if there 1405 * is no link. 1406 */ 1407 e1000_clear_hw_cntrs_82575(hw); 1408 1409 return ret_val; 1410 } 1411 1412 /** 1413 * e1000_setup_copper_link_82575 - Configure copper link settings 1414 * @hw: pointer to the HW structure 1415 * 1416 * Configures the link for auto-neg or forced speed and duplex. Then we check 1417 * for link, once link is established calls to configure collision distance 1418 * and flow control are called. 1419 **/ 1420 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1421 { 1422 u32 ctrl; 1423 s32 ret_val; 1424 u32 phpm_reg; 1425 1426 DEBUGFUNC("e1000_setup_copper_link_82575"); 1427 1428 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1429 ctrl |= E1000_CTRL_SLU; 1430 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1431 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1432 1433 /* Clear Go Link Disconnect bit */ 1434 if (hw->mac.type >= e1000_82580) { 1435 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1436 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1437 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1438 } 1439 1440 ret_val = e1000_setup_serdes_link_82575(hw); 1441 if (ret_val) 1442 goto out; 1443 1444 if (e1000_sgmii_active_82575(hw)) { 1445 /* allow time for SFP cage time to power up phy */ 1446 msec_delay(300); 1447 1448 ret_val = hw->phy.ops.reset(hw); 1449 if (ret_val) { 1450 DEBUGOUT("Error resetting the PHY.\n"); 1451 goto out; 1452 } 1453 } 1454 switch (hw->phy.type) { 1455 case e1000_phy_i210: 1456 case e1000_phy_m88: 1457 switch (hw->phy.id) { 1458 case I347AT4_E_PHY_ID: 1459 case M88E1112_E_PHY_ID: 1460 case M88E1340M_E_PHY_ID: 1461 case I210_I_PHY_ID: 1462 ret_val = e1000_copper_link_setup_m88_gen2(hw); 1463 break; 1464 default: 1465 ret_val = e1000_copper_link_setup_m88(hw); 1466 break; 1467 } 1468 break; 1469 case e1000_phy_igp_3: 1470 ret_val = e1000_copper_link_setup_igp(hw); 1471 break; 1472 case e1000_phy_82580: 1473 ret_val = e1000_copper_link_setup_82577(hw); 1474 break; 1475 default: 1476 ret_val = -E1000_ERR_PHY; 1477 break; 1478 } 1479 1480 if (ret_val) 1481 goto out; 1482 1483 ret_val = e1000_setup_copper_link_generic(hw); 1484 out: 1485 return ret_val; 1486 } 1487 1488 /** 1489 * e1000_setup_serdes_link_82575 - Setup link for serdes 1490 * @hw: pointer to the HW structure 1491 * 1492 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1493 * used on copper connections where the serialized gigabit media independent 1494 * interface (sgmii), or serdes fiber is being used. Configures the link 1495 * for auto-negotiation or forces speed/duplex. 1496 **/ 1497 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1498 { 1499 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1500 bool pcs_autoneg; 1501 s32 ret_val = E1000_SUCCESS; 1502 u16 data; 1503 1504 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1505 1506 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1507 !e1000_sgmii_active_82575(hw)) 1508 return ret_val; 1509 1510 /* 1511 * On the 82575, SerDes loopback mode persists until it is 1512 * explicitly turned off or a power cycle is performed. A read to 1513 * the register does not indicate its status. Therefore, we ensure 1514 * loopback mode is disabled during initialization. 1515 */ 1516 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1517 1518 /* power on the sfp cage if present */ 1519 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1520 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1521 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1522 1523 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1524 ctrl_reg |= E1000_CTRL_SLU; 1525 1526 /* set both sw defined pins on 82575/82576*/ 1527 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1528 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1529 1530 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1531 1532 /* default pcs_autoneg to the same setting as mac autoneg */ 1533 pcs_autoneg = hw->mac.autoneg; 1534 1535 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1536 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1537 /* sgmii mode lets the phy handle forcing speed/duplex */ 1538 pcs_autoneg = TRUE; 1539 /* autoneg time out should be disabled for SGMII mode */ 1540 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1541 break; 1542 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1543 /* disable PCS autoneg and support parallel detect only */ 1544 pcs_autoneg = FALSE; 1545 /* fall through to default case */ 1546 default: 1547 if (hw->mac.type == e1000_82575 || 1548 hw->mac.type == e1000_82576) { 1549 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1550 if (ret_val) { 1551 DEBUGOUT("NVM Read Error\n"); 1552 return ret_val; 1553 } 1554 1555 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1556 pcs_autoneg = FALSE; 1557 } 1558 1559 /* 1560 * non-SGMII modes only supports a speed of 1000/Full for the 1561 * link so it is best to just force the MAC and let the pcs 1562 * link either autoneg or be forced to 1000/Full 1563 */ 1564 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1565 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1566 1567 /* set speed of 1000/Full if speed/duplex is forced */ 1568 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1569 break; 1570 } 1571 1572 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1573 1574 /* 1575 * New SerDes mode allows for forcing speed or autonegotiating speed 1576 * at 1gb. Autoneg should be default set by most drivers. This is the 1577 * mode that will be compatible with older link partners and switches. 1578 * However, both are supported by the hardware and some drivers/tools. 1579 */ 1580 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1581 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1582 1583 if (pcs_autoneg) { 1584 /* Set PCS register for autoneg */ 1585 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1586 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1587 1588 /* Disable force flow control for autoneg */ 1589 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1590 1591 /* Configure flow control advertisement for autoneg */ 1592 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1593 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1594 1595 switch (hw->fc.requested_mode) { 1596 case e1000_fc_full: 1597 case e1000_fc_rx_pause: 1598 anadv_reg |= E1000_TXCW_ASM_DIR; 1599 anadv_reg |= E1000_TXCW_PAUSE; 1600 break; 1601 case e1000_fc_tx_pause: 1602 anadv_reg |= E1000_TXCW_ASM_DIR; 1603 break; 1604 default: 1605 break; 1606 } 1607 1608 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1609 1610 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1611 } else { 1612 /* Set PCS register for forced link */ 1613 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1614 1615 /* Force flow control for forced link */ 1616 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1617 1618 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1619 } 1620 1621 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1622 1623 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1624 e1000_force_mac_fc_generic(hw); 1625 1626 return ret_val; 1627 } 1628 1629 /** 1630 * e1000_get_media_type_82575 - derives current media type. 1631 * @hw: pointer to the HW structure 1632 * 1633 * The media type is chosen reflecting few settings. 1634 * The following are taken into account: 1635 * - link mode set in the current port Init Control Word #3 1636 * - current link mode settings in CSR register 1637 * - MDIO vs. I2C PHY control interface chosen 1638 * - SFP module media type 1639 **/ 1640 static s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1641 { 1642 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1643 s32 ret_val = E1000_SUCCESS; 1644 u32 ctrl_ext = 0; 1645 u32 link_mode = 0; 1646 1647 /* Set internal phy as default */ 1648 dev_spec->sgmii_active = FALSE; 1649 dev_spec->module_plugged = FALSE; 1650 1651 /* Get CSR setting */ 1652 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1653 1654 /* extract link mode setting */ 1655 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1656 1657 switch (link_mode) { 1658 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1659 hw->phy.media_type = e1000_media_type_internal_serdes; 1660 break; 1661 case E1000_CTRL_EXT_LINK_MODE_GMII: 1662 hw->phy.media_type = e1000_media_type_copper; 1663 break; 1664 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1665 /* Get phy control interface type set (MDIO vs. I2C)*/ 1666 if (e1000_sgmii_uses_mdio_82575(hw)) { 1667 hw->phy.media_type = e1000_media_type_copper; 1668 dev_spec->sgmii_active = TRUE; 1669 break; 1670 } 1671 /* fall through for I2C based SGMII */ 1672 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1673 /* read media type from SFP EEPROM */ 1674 ret_val = e1000_set_sfp_media_type_82575(hw); 1675 if ((ret_val != E1000_SUCCESS) || 1676 (hw->phy.media_type == e1000_media_type_unknown)) { 1677 /* 1678 * If media type was not identified then return media 1679 * type defined by the CTRL_EXT settings. 1680 */ 1681 hw->phy.media_type = e1000_media_type_internal_serdes; 1682 1683 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 1684 hw->phy.media_type = e1000_media_type_copper; 1685 dev_spec->sgmii_active = TRUE; 1686 } 1687 1688 break; 1689 } 1690 1691 /* do not change link mode for 100BaseFX */ 1692 if (dev_spec->eth_flags.e100_base_fx) 1693 break; 1694 1695 /* change current link mode setting */ 1696 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1697 1698 if (hw->phy.media_type == e1000_media_type_copper) 1699 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 1700 else 1701 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1702 1703 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1704 1705 break; 1706 } 1707 1708 return ret_val; 1709 } 1710 1711 /** 1712 * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1713 * @hw: pointer to the HW structure 1714 * 1715 * The media type is chosen based on SFP module. 1716 * compatibility flags retrieved from SFP ID EEPROM. 1717 **/ 1718 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1719 { 1720 s32 ret_val = E1000_ERR_CONFIG; 1721 u32 ctrl_ext = 0; 1722 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1723 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1724 u8 tranceiver_type = 0; 1725 s32 timeout = 3; 1726 1727 /* Turn I2C interface ON and power on sfp cage */ 1728 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1729 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1730 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1731 1732 E1000_WRITE_FLUSH(hw); 1733 1734 /* Read SFP module data */ 1735 while (timeout) { 1736 ret_val = e1000_read_sfp_data_byte(hw, 1737 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1738 &tranceiver_type); 1739 if (ret_val == E1000_SUCCESS) 1740 break; 1741 msec_delay(100); 1742 timeout--; 1743 } 1744 if (ret_val != E1000_SUCCESS) 1745 goto out; 1746 1747 ret_val = e1000_read_sfp_data_byte(hw, 1748 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1749 (u8 *)eth_flags); 1750 if (ret_val != E1000_SUCCESS) 1751 goto out; 1752 1753 /* Check if there is some SFP module plugged and powered */ 1754 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1755 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1756 dev_spec->module_plugged = TRUE; 1757 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1758 hw->phy.media_type = e1000_media_type_internal_serdes; 1759 } else if (eth_flags->e100_base_fx) { 1760 dev_spec->sgmii_active = TRUE; 1761 hw->phy.media_type = e1000_media_type_internal_serdes; 1762 } else if (eth_flags->e1000_base_t) { 1763 dev_spec->sgmii_active = TRUE; 1764 hw->phy.media_type = e1000_media_type_copper; 1765 } else { 1766 hw->phy.media_type = e1000_media_type_unknown; 1767 DEBUGOUT("PHY module has not been recognized\n"); 1768 goto out; 1769 } 1770 } else { 1771 hw->phy.media_type = e1000_media_type_unknown; 1772 } 1773 ret_val = E1000_SUCCESS; 1774 out: 1775 /* Restore I2C interface setting */ 1776 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1777 return ret_val; 1778 } 1779 1780 /** 1781 * e1000_valid_led_default_82575 - Verify a valid default LED config 1782 * @hw: pointer to the HW structure 1783 * @data: pointer to the NVM (EEPROM) 1784 * 1785 * Read the EEPROM for the current default LED configuration. If the 1786 * LED configuration is not valid, set to a valid LED configuration. 1787 **/ 1788 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1789 { 1790 s32 ret_val; 1791 1792 DEBUGFUNC("e1000_valid_led_default_82575"); 1793 1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1795 if (ret_val) { 1796 DEBUGOUT("NVM Read Error\n"); 1797 goto out; 1798 } 1799 1800 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1801 switch (hw->phy.media_type) { 1802 case e1000_media_type_internal_serdes: 1803 *data = ID_LED_DEFAULT_82575_SERDES; 1804 break; 1805 case e1000_media_type_copper: 1806 default: 1807 *data = ID_LED_DEFAULT; 1808 break; 1809 } 1810 } 1811 out: 1812 return ret_val; 1813 } 1814 1815 /** 1816 * e1000_sgmii_active_82575 - Return sgmii state 1817 * @hw: pointer to the HW structure 1818 * 1819 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1820 * which can be enabled for use in the embedded applications. Simply 1821 * return the current state of the sgmii interface. 1822 **/ 1823 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1824 { 1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1826 return dev_spec->sgmii_active; 1827 } 1828 1829 /** 1830 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1831 * @hw: pointer to the HW structure 1832 * 1833 * Inits recommended HW defaults after a reset when there is no EEPROM 1834 * detected. This is only for the 82575. 1835 **/ 1836 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1837 { 1838 DEBUGFUNC("e1000_reset_init_script_82575"); 1839 1840 if (hw->mac.type == e1000_82575) { 1841 DEBUGOUT("Running reset init script for 82575\n"); 1842 /* SerDes configuration via SERDESCTRL */ 1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1845 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1846 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1847 1848 /* CCM configuration via CCMCTL register */ 1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1850 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1851 1852 /* PCIe lanes configuration */ 1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1855 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1856 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1857 1858 /* PCIe PLL Configuration */ 1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1861 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1862 } 1863 1864 return E1000_SUCCESS; 1865 } 1866 1867 /** 1868 * e1000_read_mac_addr_82575 - Read device MAC address 1869 * @hw: pointer to the HW structure 1870 **/ 1871 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1872 { 1873 s32 ret_val = E1000_SUCCESS; 1874 1875 DEBUGFUNC("e1000_read_mac_addr_82575"); 1876 1877 /* 1878 * If there's an alternate MAC address place it in RAR0 1879 * so that it will override the Si installed default perm 1880 * address. 1881 */ 1882 ret_val = e1000_check_alt_mac_addr_generic(hw); 1883 if (ret_val) 1884 goto out; 1885 1886 ret_val = e1000_read_mac_addr_generic(hw); 1887 1888 out: 1889 return ret_val; 1890 } 1891 1892 /** 1893 * e1000_config_collision_dist_82575 - Configure collision distance 1894 * @hw: pointer to the HW structure 1895 * 1896 * Configures the collision distance to the default value and is used 1897 * during link setup. 1898 **/ 1899 static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1900 { 1901 u32 tctl_ext; 1902 1903 DEBUGFUNC("e1000_config_collision_dist_82575"); 1904 1905 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1906 1907 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1908 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1909 1910 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1911 E1000_WRITE_FLUSH(hw); 1912 } 1913 1914 /** 1915 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1916 * @hw: pointer to the HW structure 1917 * 1918 * In the case of a PHY power down to save power, or to turn off link during a 1919 * driver unload, or wake on lan is not enabled, remove the link. 1920 **/ 1921 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1922 { 1923 struct e1000_phy_info *phy = &hw->phy; 1924 1925 if (!(phy->ops.check_reset_block)) 1926 return; 1927 1928 /* If the management interface is not enabled, then power down */ 1929 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1930 e1000_power_down_phy_copper(hw); 1931 1932 return; 1933 } 1934 1935 /** 1936 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1937 * @hw: pointer to the HW structure 1938 * 1939 * Clears the hardware counters by reading the counter registers. 1940 **/ 1941 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1942 { 1943 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1944 1945 e1000_clear_hw_cntrs_base_generic(hw); 1946 1947 E1000_READ_REG(hw, E1000_PRC64); 1948 E1000_READ_REG(hw, E1000_PRC127); 1949 E1000_READ_REG(hw, E1000_PRC255); 1950 E1000_READ_REG(hw, E1000_PRC511); 1951 E1000_READ_REG(hw, E1000_PRC1023); 1952 E1000_READ_REG(hw, E1000_PRC1522); 1953 E1000_READ_REG(hw, E1000_PTC64); 1954 E1000_READ_REG(hw, E1000_PTC127); 1955 E1000_READ_REG(hw, E1000_PTC255); 1956 E1000_READ_REG(hw, E1000_PTC511); 1957 E1000_READ_REG(hw, E1000_PTC1023); 1958 E1000_READ_REG(hw, E1000_PTC1522); 1959 1960 E1000_READ_REG(hw, E1000_ALGNERRC); 1961 E1000_READ_REG(hw, E1000_RXERRC); 1962 E1000_READ_REG(hw, E1000_TNCRS); 1963 E1000_READ_REG(hw, E1000_CEXTERR); 1964 E1000_READ_REG(hw, E1000_TSCTC); 1965 E1000_READ_REG(hw, E1000_TSCTFC); 1966 1967 E1000_READ_REG(hw, E1000_MGTPRC); 1968 E1000_READ_REG(hw, E1000_MGTPDC); 1969 E1000_READ_REG(hw, E1000_MGTPTC); 1970 1971 E1000_READ_REG(hw, E1000_IAC); 1972 E1000_READ_REG(hw, E1000_ICRXOC); 1973 1974 E1000_READ_REG(hw, E1000_ICRXPTC); 1975 E1000_READ_REG(hw, E1000_ICRXATC); 1976 E1000_READ_REG(hw, E1000_ICTXPTC); 1977 E1000_READ_REG(hw, E1000_ICTXATC); 1978 E1000_READ_REG(hw, E1000_ICTXQEC); 1979 E1000_READ_REG(hw, E1000_ICTXQMTC); 1980 E1000_READ_REG(hw, E1000_ICRXDMTC); 1981 1982 E1000_READ_REG(hw, E1000_CBTMPC); 1983 E1000_READ_REG(hw, E1000_HTDPMC); 1984 E1000_READ_REG(hw, E1000_CBRMPC); 1985 E1000_READ_REG(hw, E1000_RPTHC); 1986 E1000_READ_REG(hw, E1000_HGPTC); 1987 E1000_READ_REG(hw, E1000_HTCBDPC); 1988 E1000_READ_REG(hw, E1000_HGORCL); 1989 E1000_READ_REG(hw, E1000_HGORCH); 1990 E1000_READ_REG(hw, E1000_HGOTCL); 1991 E1000_READ_REG(hw, E1000_HGOTCH); 1992 E1000_READ_REG(hw, E1000_LENERRS); 1993 1994 /* This register should not be read in copper configurations */ 1995 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1996 e1000_sgmii_active_82575(hw)) 1997 E1000_READ_REG(hw, E1000_SCVPC); 1998 } 1999 2000 /** 2001 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2002 * @hw: pointer to the HW structure 2003 * 2004 * After rx enable if managability is enabled then there is likely some 2005 * bad data at the start of the fifo and possibly in the DMA fifo. This 2006 * function clears the fifos and flushes any packets that came in as rx was 2007 * being enabled. 2008 **/ 2009 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2010 { 2011 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2012 int i, ms_wait; 2013 2014 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 2015 if (hw->mac.type != e1000_82575 || 2016 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2017 return; 2018 2019 /* Disable all Rx queues */ 2020 for (i = 0; i < 4; i++) { 2021 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2022 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2023 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2024 } 2025 /* Poll all queues to verify they have shut down */ 2026 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2027 msec_delay(1); 2028 rx_enabled = 0; 2029 for (i = 0; i < 4; i++) 2030 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2031 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2032 break; 2033 } 2034 2035 if (ms_wait == 10) 2036 DEBUGOUT("Queue disable timed out after 10ms\n"); 2037 2038 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2039 * incoming packets are rejected. Set enable and wait 2ms so that 2040 * any packet that was coming in as RCTL.EN was set is flushed 2041 */ 2042 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2043 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2044 2045 rlpml = E1000_READ_REG(hw, E1000_RLPML); 2046 E1000_WRITE_REG(hw, E1000_RLPML, 0); 2047 2048 rctl = E1000_READ_REG(hw, E1000_RCTL); 2049 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2050 temp_rctl |= E1000_RCTL_LPE; 2051 2052 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2053 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2054 E1000_WRITE_FLUSH(hw); 2055 msec_delay(2); 2056 2057 /* Enable Rx queues that were previously enabled and restore our 2058 * previous state 2059 */ 2060 for (i = 0; i < 4; i++) 2061 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2062 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2063 E1000_WRITE_FLUSH(hw); 2064 2065 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2066 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2067 2068 /* Flush receive errors generated by workaround */ 2069 E1000_READ_REG(hw, E1000_ROC); 2070 E1000_READ_REG(hw, E1000_RNBC); 2071 E1000_READ_REG(hw, E1000_MPC); 2072 } 2073 2074 /** 2075 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2076 * @hw: pointer to the HW structure 2077 * 2078 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2079 * however the hardware default for these parts is 500us to 1ms which is less 2080 * than the 10ms recommended by the pci-e spec. To address this we need to 2081 * increase the value to either 10ms to 200ms for capability version 1 config, 2082 * or 16ms to 55ms for version 2. 2083 **/ 2084 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2085 { 2086 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2087 s32 ret_val = E1000_SUCCESS; 2088 u16 pcie_devctl2; 2089 2090 /* only take action if timeout value is defaulted to 0 */ 2091 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2092 goto out; 2093 2094 /* 2095 * if capababilities version is type 1 we can write the 2096 * timeout of 10ms to 200ms through the GCR register 2097 */ 2098 if (!(gcr & E1000_GCR_CAP_VER2)) { 2099 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2100 goto out; 2101 } 2102 2103 /* 2104 * for version 2 capabilities we need to write the config space 2105 * directly in order to set the completion timeout value for 2106 * 16ms to 55ms 2107 */ 2108 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2109 &pcie_devctl2); 2110 if (ret_val) 2111 goto out; 2112 2113 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2114 2115 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2116 &pcie_devctl2); 2117 out: 2118 /* disable completion timeout resend */ 2119 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2120 2121 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2122 return ret_val; 2123 } 2124 2125 /** 2126 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2127 * @hw: pointer to the hardware struct 2128 * @enable: state to enter, either enabled or disabled 2129 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2130 * 2131 * enables/disables L2 switch anti-spoofing functionality. 2132 **/ 2133 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2134 { 2135 u32 dtxswc; 2136 2137 switch (hw->mac.type) { 2138 case e1000_82576: 2139 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2140 if (enable) { 2141 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2142 E1000_DTXSWC_VLAN_SPOOF_MASK); 2143 /* The PF can spoof - it has to in order to 2144 * support emulation mode NICs */ 2145 dtxswc ^= (1 << pf | 1 << (pf + 2146 E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 2147 } else { 2148 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2149 E1000_DTXSWC_VLAN_SPOOF_MASK); 2150 } 2151 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2152 break; 2153 case e1000_i350: 2154 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2155 if (enable) { 2156 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2157 E1000_DTXSWC_VLAN_SPOOF_MASK); 2158 /* The PF can spoof - it has to in order to 2159 * support emulation mode NICs 2160 */ 2161 dtxswc ^= (1 << pf | 1 << (pf + 2162 E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 2163 } else { 2164 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2165 E1000_DTXSWC_VLAN_SPOOF_MASK); 2166 } 2167 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2168 default: 2169 break; 2170 } 2171 } 2172 2173 /** 2174 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2175 * @hw: pointer to the hardware struct 2176 * @enable: state to enter, either enabled or disabled 2177 * 2178 * enables/disables L2 switch loopback functionality. 2179 **/ 2180 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2181 { 2182 u32 dtxswc; 2183 2184 switch (hw->mac.type) { 2185 case e1000_82576: 2186 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2187 if (enable) 2188 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2189 else 2190 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2191 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2192 break; 2193 case e1000_i350: 2194 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2195 if (enable) 2196 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2197 else 2198 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2199 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2200 break; 2201 default: 2202 /* Currently no other hardware supports loopback */ 2203 break; 2204 } 2205 2206 2207 } 2208 2209 /** 2210 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2211 * @hw: pointer to the hardware struct 2212 * @enable: state to enter, either enabled or disabled 2213 * 2214 * enables/disables replication of packets across multiple pools. 2215 **/ 2216 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2217 { 2218 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2219 2220 if (enable) 2221 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2222 else 2223 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2224 2225 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2226 } 2227 2228 /** 2229 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2230 * @hw: pointer to the HW structure 2231 * @offset: register offset to be read 2232 * @data: pointer to the read data 2233 * 2234 * Reads the MDI control register in the PHY at offset and stores the 2235 * information read to data. 2236 **/ 2237 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2238 { 2239 s32 ret_val; 2240 2241 DEBUGFUNC("e1000_read_phy_reg_82580"); 2242 2243 ret_val = hw->phy.ops.acquire(hw); 2244 if (ret_val) 2245 goto out; 2246 2247 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2248 2249 hw->phy.ops.release(hw); 2250 2251 out: 2252 return ret_val; 2253 } 2254 2255 /** 2256 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2257 * @hw: pointer to the HW structure 2258 * @offset: register offset to write to 2259 * @data: data to write to register at offset 2260 * 2261 * Writes data to MDI control register in the PHY at offset. 2262 **/ 2263 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2264 { 2265 s32 ret_val; 2266 2267 DEBUGFUNC("e1000_write_phy_reg_82580"); 2268 2269 ret_val = hw->phy.ops.acquire(hw); 2270 if (ret_val) 2271 goto out; 2272 2273 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2274 2275 hw->phy.ops.release(hw); 2276 2277 out: 2278 return ret_val; 2279 } 2280 2281 /** 2282 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2283 * @hw: pointer to the HW structure 2284 * 2285 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2286 * the values found in the EEPROM. This addresses an issue in which these 2287 * bits are not restored from EEPROM after reset. 2288 **/ 2289 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2290 { 2291 s32 ret_val = E1000_SUCCESS; 2292 u32 mdicnfg; 2293 u16 nvm_data = 0; 2294 2295 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2296 2297 if (hw->mac.type != e1000_82580) 2298 goto out; 2299 if (!e1000_sgmii_active_82575(hw)) 2300 goto out; 2301 2302 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2303 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2304 &nvm_data); 2305 if (ret_val) { 2306 DEBUGOUT("NVM Read Error\n"); 2307 goto out; 2308 } 2309 2310 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2311 if (nvm_data & NVM_WORD24_EXT_MDIO) 2312 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2313 if (nvm_data & NVM_WORD24_COM_MDIO) 2314 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2315 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2316 out: 2317 return ret_val; 2318 } 2319 2320 /** 2321 * e1000_reset_hw_82580 - Reset hardware 2322 * @hw: pointer to the HW structure 2323 * 2324 * This resets function or entire device (all ports, etc.) 2325 * to a known state. 2326 **/ 2327 static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2328 { 2329 s32 ret_val = E1000_SUCCESS; 2330 /* BH SW mailbox bit in SW_FW_SYNC */ 2331 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2332 u32 ctrl; 2333 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2334 2335 DEBUGFUNC("e1000_reset_hw_82580"); 2336 2337 hw->dev_spec._82575.global_device_reset = FALSE; 2338 2339 /* 82580 does not reliably do global_device_reset due to hw errata */ 2340 if (hw->mac.type == e1000_82580) 2341 global_device_reset = FALSE; 2342 2343 /* Get current control state. */ 2344 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2345 2346 /* 2347 * Prevent the PCI-E bus from sticking if there is no TLP connection 2348 * on the last TLP read/write transaction when MAC is reset. 2349 */ 2350 ret_val = e1000_disable_pcie_master_generic(hw); 2351 if (ret_val) 2352 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2353 2354 DEBUGOUT("Masking off all interrupts\n"); 2355 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2356 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2357 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2358 E1000_WRITE_FLUSH(hw); 2359 2360 msec_delay(10); 2361 2362 /* Determine whether or not a global dev reset is requested */ 2363 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2364 swmbsw_mask)) 2365 global_device_reset = FALSE; 2366 2367 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2368 E1000_STAT_DEV_RST_SET)) 2369 ctrl |= E1000_CTRL_DEV_RST; 2370 else 2371 ctrl |= E1000_CTRL_RST; 2372 2373 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2374 E1000_WRITE_FLUSH(hw); 2375 2376 /* Add delay to insure DEV_RST has time to complete */ 2377 if (global_device_reset) 2378 msec_delay(5); 2379 2380 ret_val = e1000_get_auto_rd_done_generic(hw); 2381 if (ret_val) { 2382 /* 2383 * When auto config read does not complete, do not 2384 * return with an error. This can happen in situations 2385 * where there is no eeprom and prevents getting link. 2386 */ 2387 DEBUGOUT("Auto Read Done did not complete\n"); 2388 } 2389 2390 /* If EEPROM is not present, run manual init scripts */ 2391 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 2392 e1000_reset_init_script_82575(hw); 2393 2394 /* clear global device reset status bit */ 2395 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2396 2397 /* Clear any pending interrupt events. */ 2398 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2399 E1000_READ_REG(hw, E1000_ICR); 2400 2401 ret_val = e1000_reset_mdicnfg_82580(hw); 2402 if (ret_val) 2403 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2404 2405 /* Install any alternate MAC address into RAR0 */ 2406 ret_val = e1000_check_alt_mac_addr_generic(hw); 2407 2408 /* Release semaphore */ 2409 if (global_device_reset) 2410 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2411 2412 return ret_val; 2413 } 2414 2415 /** 2416 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2417 * @data: data received by reading RXPBS register 2418 * 2419 * The 82580 uses a table based approach for packet buffer allocation sizes. 2420 * This function converts the retrieved value into the correct table value 2421 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2422 * 0x0 36 72 144 1 2 4 8 16 2423 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2424 */ 2425 u16 e1000_rxpbs_adjust_82580(u32 data) 2426 { 2427 u16 ret_val = 0; 2428 2429 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2430 ret_val = e1000_82580_rxpbs_table[data]; 2431 2432 return ret_val; 2433 } 2434 2435 /** 2436 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2437 * checksum 2438 * @hw: pointer to the HW structure 2439 * @offset: offset in words of the checksum protected region 2440 * 2441 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2442 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2443 **/ 2444 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2445 { 2446 s32 ret_val = E1000_SUCCESS; 2447 u16 checksum = 0; 2448 u16 i, nvm_data; 2449 2450 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2451 2452 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2453 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2454 if (ret_val) { 2455 DEBUGOUT("NVM Read Error\n"); 2456 goto out; 2457 } 2458 checksum += nvm_data; 2459 } 2460 2461 if (checksum != (u16) NVM_SUM) { 2462 DEBUGOUT("NVM Checksum Invalid\n"); 2463 ret_val = -E1000_ERR_NVM; 2464 goto out; 2465 } 2466 2467 out: 2468 return ret_val; 2469 } 2470 2471 /** 2472 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2473 * checksum 2474 * @hw: pointer to the HW structure 2475 * @offset: offset in words of the checksum protected region 2476 * 2477 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2478 * up to the checksum. Then calculates the EEPROM checksum and writes the 2479 * value to the EEPROM. 2480 **/ 2481 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2482 { 2483 s32 ret_val; 2484 u16 checksum = 0; 2485 u16 i, nvm_data; 2486 2487 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2488 2489 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2490 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2491 if (ret_val) { 2492 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2493 goto out; 2494 } 2495 checksum += nvm_data; 2496 } 2497 checksum = (u16) NVM_SUM - checksum; 2498 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2499 &checksum); 2500 if (ret_val) 2501 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2502 2503 out: 2504 return ret_val; 2505 } 2506 2507 /** 2508 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2509 * @hw: pointer to the HW structure 2510 * 2511 * Calculates the EEPROM section checksum by reading/adding each word of 2512 * the EEPROM and then verifies that the sum of the EEPROM is 2513 * equal to 0xBABA. 2514 **/ 2515 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2516 { 2517 s32 ret_val = E1000_SUCCESS; 2518 u16 eeprom_regions_count = 1; 2519 u16 j, nvm_data; 2520 u16 nvm_offset; 2521 2522 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2523 2524 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2525 if (ret_val) { 2526 DEBUGOUT("NVM Read Error\n"); 2527 goto out; 2528 } 2529 2530 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2531 /* if chekcsums compatibility bit is set validate checksums 2532 * for all 4 ports. */ 2533 eeprom_regions_count = 4; 2534 } 2535 2536 for (j = 0; j < eeprom_regions_count; j++) { 2537 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2538 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2539 nvm_offset); 2540 if (ret_val != E1000_SUCCESS) 2541 goto out; 2542 } 2543 2544 out: 2545 return ret_val; 2546 } 2547 2548 /** 2549 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2550 * @hw: pointer to the HW structure 2551 * 2552 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2553 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2554 * checksum and writes the value to the EEPROM. 2555 **/ 2556 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2557 { 2558 s32 ret_val; 2559 u16 j, nvm_data; 2560 u16 nvm_offset; 2561 2562 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2563 2564 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2565 if (ret_val) { 2566 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2567 goto out; 2568 } 2569 2570 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2571 /* set compatibility bit to validate checksums appropriately */ 2572 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2573 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2574 &nvm_data); 2575 if (ret_val) { 2576 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2577 goto out; 2578 } 2579 } 2580 2581 for (j = 0; j < 4; j++) { 2582 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2583 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2584 if (ret_val) 2585 goto out; 2586 } 2587 2588 out: 2589 return ret_val; 2590 } 2591 2592 /** 2593 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2594 * @hw: pointer to the HW structure 2595 * 2596 * Calculates the EEPROM section checksum by reading/adding each word of 2597 * the EEPROM and then verifies that the sum of the EEPROM is 2598 * equal to 0xBABA. 2599 **/ 2600 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2601 { 2602 s32 ret_val = E1000_SUCCESS; 2603 u16 j; 2604 u16 nvm_offset; 2605 2606 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2607 2608 for (j = 0; j < 4; j++) { 2609 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2610 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2611 nvm_offset); 2612 if (ret_val != E1000_SUCCESS) 2613 goto out; 2614 } 2615 2616 out: 2617 return ret_val; 2618 } 2619 2620 /** 2621 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2622 * @hw: pointer to the HW structure 2623 * 2624 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2625 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2626 * checksum and writes the value to the EEPROM. 2627 **/ 2628 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2629 { 2630 s32 ret_val = E1000_SUCCESS; 2631 u16 j; 2632 u16 nvm_offset; 2633 2634 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2635 2636 for (j = 0; j < 4; j++) { 2637 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2638 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2639 if (ret_val != E1000_SUCCESS) 2640 goto out; 2641 } 2642 2643 out: 2644 return ret_val; 2645 } 2646 2647 /** 2648 * e1000_set_eee_i350 - Enable/disable EEE support 2649 * @hw: pointer to the HW structure 2650 * 2651 * Enable/disable EEE based on setting in dev_spec structure. 2652 * 2653 **/ 2654 s32 e1000_set_eee_i350(struct e1000_hw *hw) 2655 { 2656 s32 ret_val = E1000_SUCCESS; 2657 u32 ipcnfg, eeer; 2658 2659 DEBUGFUNC("e1000_set_eee_i350"); 2660 2661 if ((hw->mac.type < e1000_i350) || 2662 (hw->phy.media_type != e1000_media_type_copper)) 2663 goto out; 2664 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2665 eeer = E1000_READ_REG(hw, E1000_EEER); 2666 2667 /* enable or disable per user setting */ 2668 if (!(hw->dev_spec._82575.eee_disable)) { 2669 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 2670 2671 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2672 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2673 E1000_EEER_LPI_FC); 2674 2675 /* This bit should not be set in normal operation. */ 2676 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2677 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 2678 } else { 2679 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2680 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2681 E1000_EEER_LPI_FC); 2682 } 2683 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2684 E1000_WRITE_REG(hw, E1000_EEER, eeer); 2685 E1000_READ_REG(hw, E1000_IPCNFG); 2686 E1000_READ_REG(hw, E1000_EEER); 2687 out: 2688 2689 return ret_val; 2690 } 2691 2692 /* Due to a hw errata, if the host tries to configure the VFTA register 2693 * while performing queries from the BMC or DMA, then the VFTA in some 2694 * cases won't be written. 2695 */ 2696 2697 /** 2698 * e1000_clear_vfta_i350 - Clear VLAN filter table 2699 * @hw: pointer to the HW structure 2700 * 2701 * Clears the register array which contains the VLAN filter table by 2702 * setting all the values to 0. 2703 **/ 2704 void e1000_clear_vfta_i350(struct e1000_hw *hw) 2705 { 2706 u32 offset; 2707 int i; 2708 2709 DEBUGFUNC("e1000_clear_vfta_350"); 2710 2711 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 2712 for (i = 0; i < 10; i++) 2713 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 2714 2715 E1000_WRITE_FLUSH(hw); 2716 } 2717 } 2718 2719 /** 2720 * e1000_write_vfta_i350 - Write value to VLAN filter table 2721 * @hw: pointer to the HW structure 2722 * @offset: register offset in VLAN filter table 2723 * @value: register value written to VLAN filter table 2724 * 2725 * Writes value at the given offset in the register array which stores 2726 * the VLAN filter table. 2727 **/ 2728 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 2729 { 2730 int i; 2731 2732 DEBUGFUNC("e1000_write_vfta_350"); 2733 2734 for (i = 0; i < 10; i++) 2735 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 2736 2737 E1000_WRITE_FLUSH(hw); 2738 } 2739 2740 2741 /** 2742 * e1000_set_i2c_bb - Enable I2C bit-bang 2743 * @hw: pointer to the HW structure 2744 * 2745 * Enable I2C bit-bang interface 2746 * 2747 **/ 2748 s32 e1000_set_i2c_bb(struct e1000_hw *hw) 2749 { 2750 s32 ret_val = E1000_SUCCESS; 2751 u32 ctrl_ext, i2cparams; 2752 2753 DEBUGFUNC("e1000_set_i2c_bb"); 2754 2755 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2756 ctrl_ext |= E1000_CTRL_I2C_ENA; 2757 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2758 E1000_WRITE_FLUSH(hw); 2759 2760 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 2761 i2cparams |= E1000_I2CBB_EN; 2762 i2cparams |= E1000_I2C_DATA_OE_N; 2763 i2cparams |= E1000_I2C_CLK_OE_N; 2764 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 2765 E1000_WRITE_FLUSH(hw); 2766 2767 return ret_val; 2768 } 2769 2770 /** 2771 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 2772 * @hw: pointer to hardware structure 2773 * @byte_offset: byte offset to read 2774 * @dev_addr: device address 2775 * @data: value read 2776 * 2777 * Performs byte read operation over I2C interface at 2778 * a specified device address. 2779 **/ 2780 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2781 u8 dev_addr, u8 *data) 2782 { 2783 s32 status = E1000_SUCCESS; 2784 u32 max_retry = 10; 2785 u32 retry = 1; 2786 u16 swfw_mask = 0; 2787 2788 bool nack = TRUE; 2789 2790 DEBUGFUNC("e1000_read_i2c_byte_generic"); 2791 2792 swfw_mask = E1000_SWFW_PHY0_SM; 2793 2794 do { 2795 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 2796 != E1000_SUCCESS) { 2797 status = E1000_ERR_SWFW_SYNC; 2798 goto read_byte_out; 2799 } 2800 2801 e1000_i2c_start(hw); 2802 2803 /* Device Address and write indication */ 2804 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2805 if (status != E1000_SUCCESS) 2806 goto fail; 2807 2808 status = e1000_get_i2c_ack(hw); 2809 if (status != E1000_SUCCESS) 2810 goto fail; 2811 2812 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2813 if (status != E1000_SUCCESS) 2814 goto fail; 2815 2816 status = e1000_get_i2c_ack(hw); 2817 if (status != E1000_SUCCESS) 2818 goto fail; 2819 2820 e1000_i2c_start(hw); 2821 2822 /* Device Address and read indication */ 2823 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2824 if (status != E1000_SUCCESS) 2825 goto fail; 2826 2827 status = e1000_get_i2c_ack(hw); 2828 if (status != E1000_SUCCESS) 2829 goto fail; 2830 2831 status = e1000_clock_in_i2c_byte(hw, data); 2832 if (status != E1000_SUCCESS) 2833 goto fail; 2834 2835 status = e1000_clock_out_i2c_bit(hw, nack); 2836 if (status != E1000_SUCCESS) 2837 goto fail; 2838 2839 e1000_i2c_stop(hw); 2840 break; 2841 2842 fail: 2843 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2844 msec_delay(100); 2845 e1000_i2c_bus_clear(hw); 2846 retry++; 2847 if (retry < max_retry) 2848 DEBUGOUT("I2C byte read error - Retrying.\n"); 2849 else 2850 DEBUGOUT("I2C byte read error.\n"); 2851 2852 } while (retry < max_retry); 2853 2854 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2855 2856 read_byte_out: 2857 2858 return status; 2859 } 2860 2861 /** 2862 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 2863 * @hw: pointer to hardware structure 2864 * @byte_offset: byte offset to write 2865 * @dev_addr: device address 2866 * @data: value to write 2867 * 2868 * Performs byte write operation over I2C interface at 2869 * a specified device address. 2870 **/ 2871 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2872 u8 dev_addr, u8 data) 2873 { 2874 s32 status = E1000_SUCCESS; 2875 u32 max_retry = 1; 2876 u32 retry = 0; 2877 u16 swfw_mask = 0; 2878 2879 DEBUGFUNC("e1000_write_i2c_byte_generic"); 2880 2881 swfw_mask = E1000_SWFW_PHY0_SM; 2882 2883 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 2884 status = E1000_ERR_SWFW_SYNC; 2885 goto write_byte_out; 2886 } 2887 2888 do { 2889 e1000_i2c_start(hw); 2890 2891 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2892 if (status != E1000_SUCCESS) 2893 goto fail; 2894 2895 status = e1000_get_i2c_ack(hw); 2896 if (status != E1000_SUCCESS) 2897 goto fail; 2898 2899 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2900 if (status != E1000_SUCCESS) 2901 goto fail; 2902 2903 status = e1000_get_i2c_ack(hw); 2904 if (status != E1000_SUCCESS) 2905 goto fail; 2906 2907 status = e1000_clock_out_i2c_byte(hw, data); 2908 if (status != E1000_SUCCESS) 2909 goto fail; 2910 2911 status = e1000_get_i2c_ack(hw); 2912 if (status != E1000_SUCCESS) 2913 goto fail; 2914 2915 e1000_i2c_stop(hw); 2916 break; 2917 2918 fail: 2919 e1000_i2c_bus_clear(hw); 2920 retry++; 2921 if (retry < max_retry) 2922 DEBUGOUT("I2C byte write error - Retrying.\n"); 2923 else 2924 DEBUGOUT("I2C byte write error.\n"); 2925 } while (retry < max_retry); 2926 2927 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2928 2929 write_byte_out: 2930 2931 return status; 2932 } 2933 2934 /** 2935 * e1000_i2c_start - Sets I2C start condition 2936 * @hw: pointer to hardware structure 2937 * 2938 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2939 **/ 2940 static void e1000_i2c_start(struct e1000_hw *hw) 2941 { 2942 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 2943 2944 DEBUGFUNC("e1000_i2c_start"); 2945 2946 /* Start condition must begin with data and clock high */ 2947 e1000_set_i2c_data(hw, &i2cctl, 1); 2948 e1000_raise_i2c_clk(hw, &i2cctl); 2949 2950 /* Setup time for start condition (4.7us) */ 2951 usec_delay(E1000_I2C_T_SU_STA); 2952 2953 e1000_set_i2c_data(hw, &i2cctl, 0); 2954 2955 /* Hold time for start condition (4us) */ 2956 usec_delay(E1000_I2C_T_HD_STA); 2957 2958 e1000_lower_i2c_clk(hw, &i2cctl); 2959 2960 /* Minimum low period of clock is 4.7 us */ 2961 usec_delay(E1000_I2C_T_LOW); 2962 2963 } 2964 2965 /** 2966 * e1000_i2c_stop - Sets I2C stop condition 2967 * @hw: pointer to hardware structure 2968 * 2969 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2970 **/ 2971 static void e1000_i2c_stop(struct e1000_hw *hw) 2972 { 2973 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 2974 2975 DEBUGFUNC("e1000_i2c_stop"); 2976 2977 /* Stop condition must begin with data low and clock high */ 2978 e1000_set_i2c_data(hw, &i2cctl, 0); 2979 e1000_raise_i2c_clk(hw, &i2cctl); 2980 2981 /* Setup time for stop condition (4us) */ 2982 usec_delay(E1000_I2C_T_SU_STO); 2983 2984 e1000_set_i2c_data(hw, &i2cctl, 1); 2985 2986 /* bus free time between stop and start (4.7us)*/ 2987 usec_delay(E1000_I2C_T_BUF); 2988 } 2989 2990 /** 2991 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 2992 * @hw: pointer to hardware structure 2993 * @data: data byte to clock in 2994 * 2995 * Clocks in one byte data via I2C data/clock 2996 **/ 2997 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 2998 { 2999 s32 i; 3000 bool bit = 0; 3001 3002 DEBUGFUNC("e1000_clock_in_i2c_byte"); 3003 3004 *data = 0; 3005 for (i = 7; i >= 0; i--) { 3006 e1000_clock_in_i2c_bit(hw, &bit); 3007 *data |= bit << i; 3008 } 3009 3010 return E1000_SUCCESS; 3011 } 3012 3013 /** 3014 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3015 * @hw: pointer to hardware structure 3016 * @data: data byte clocked out 3017 * 3018 * Clocks out one byte data via I2C data/clock 3019 **/ 3020 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3021 { 3022 s32 status = E1000_SUCCESS; 3023 s32 i; 3024 u32 i2cctl; 3025 bool bit = 0; 3026 3027 DEBUGFUNC("e1000_clock_out_i2c_byte"); 3028 3029 for (i = 7; i >= 0; i--) { 3030 bit = (data >> i) & 0x1; 3031 status = e1000_clock_out_i2c_bit(hw, bit); 3032 3033 if (status != E1000_SUCCESS) 3034 break; 3035 } 3036 3037 /* Release SDA line (set high) */ 3038 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3039 3040 i2cctl |= E1000_I2C_DATA_OE_N; 3041 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3042 E1000_WRITE_FLUSH(hw); 3043 3044 return status; 3045 } 3046 3047 /** 3048 * e1000_get_i2c_ack - Polls for I2C ACK 3049 * @hw: pointer to hardware structure 3050 * 3051 * Clocks in/out one bit via I2C data/clock 3052 **/ 3053 static s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3054 { 3055 s32 status = E1000_SUCCESS; 3056 u32 i = 0; 3057 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3058 u32 timeout = 10; 3059 bool ack = TRUE; 3060 3061 DEBUGFUNC("e1000_get_i2c_ack"); 3062 3063 e1000_raise_i2c_clk(hw, &i2cctl); 3064 3065 /* Minimum high period of clock is 4us */ 3066 usec_delay(E1000_I2C_T_HIGH); 3067 3068 /* Wait until SCL returns high */ 3069 for (i = 0; i < timeout; i++) { 3070 usec_delay(1); 3071 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3072 if (i2cctl & E1000_I2C_CLK_IN) 3073 break; 3074 } 3075 if (!(i2cctl & E1000_I2C_CLK_IN)) 3076 return E1000_ERR_I2C; 3077 3078 ack = e1000_get_i2c_data(&i2cctl); 3079 if (ack) { 3080 DEBUGOUT("I2C ack was not received.\n"); 3081 status = E1000_ERR_I2C; 3082 } 3083 3084 e1000_lower_i2c_clk(hw, &i2cctl); 3085 3086 /* Minimum low period of clock is 4.7 us */ 3087 usec_delay(E1000_I2C_T_LOW); 3088 3089 return status; 3090 } 3091 3092 /** 3093 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3094 * @hw: pointer to hardware structure 3095 * @data: read data value 3096 * 3097 * Clocks in one bit via I2C data/clock 3098 **/ 3099 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3100 { 3101 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3102 3103 DEBUGFUNC("e1000_clock_in_i2c_bit"); 3104 3105 e1000_raise_i2c_clk(hw, &i2cctl); 3106 3107 /* Minimum high period of clock is 4us */ 3108 usec_delay(E1000_I2C_T_HIGH); 3109 3110 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3111 *data = e1000_get_i2c_data(&i2cctl); 3112 3113 e1000_lower_i2c_clk(hw, &i2cctl); 3114 3115 /* Minimum low period of clock is 4.7 us */ 3116 usec_delay(E1000_I2C_T_LOW); 3117 3118 return E1000_SUCCESS; 3119 } 3120 3121 /** 3122 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3123 * @hw: pointer to hardware structure 3124 * @data: data value to write 3125 * 3126 * Clocks out one bit via I2C data/clock 3127 **/ 3128 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3129 { 3130 s32 status; 3131 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3132 3133 DEBUGFUNC("e1000_clock_out_i2c_bit"); 3134 3135 status = e1000_set_i2c_data(hw, &i2cctl, data); 3136 if (status == E1000_SUCCESS) { 3137 e1000_raise_i2c_clk(hw, &i2cctl); 3138 3139 /* Minimum high period of clock is 4us */ 3140 usec_delay(E1000_I2C_T_HIGH); 3141 3142 e1000_lower_i2c_clk(hw, &i2cctl); 3143 3144 /* Minimum low period of clock is 4.7 us. 3145 * This also takes care of the data hold time. 3146 */ 3147 usec_delay(E1000_I2C_T_LOW); 3148 } else { 3149 status = E1000_ERR_I2C; 3150 DEBUGOUT1("I2C data was not set to %X\n", data); 3151 } 3152 3153 return status; 3154 } 3155 /** 3156 * e1000_raise_i2c_clk - Raises the I2C SCL clock 3157 * @hw: pointer to hardware structure 3158 * @i2cctl: Current value of I2CCTL register 3159 * 3160 * Raises the I2C clock line '0'->'1' 3161 **/ 3162 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3163 { 3164 DEBUGFUNC("e1000_raise_i2c_clk"); 3165 3166 *i2cctl |= E1000_I2C_CLK_OUT; 3167 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3168 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3169 E1000_WRITE_FLUSH(hw); 3170 3171 /* SCL rise time (1000ns) */ 3172 usec_delay(E1000_I2C_T_RISE); 3173 } 3174 3175 /** 3176 * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3177 * @hw: pointer to hardware structure 3178 * @i2cctl: Current value of I2CCTL register 3179 * 3180 * Lowers the I2C clock line '1'->'0' 3181 **/ 3182 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3183 { 3184 3185 DEBUGFUNC("e1000_lower_i2c_clk"); 3186 3187 *i2cctl &= ~E1000_I2C_CLK_OUT; 3188 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3189 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3190 E1000_WRITE_FLUSH(hw); 3191 3192 /* SCL fall time (300ns) */ 3193 usec_delay(E1000_I2C_T_FALL); 3194 } 3195 3196 /** 3197 * e1000_set_i2c_data - Sets the I2C data bit 3198 * @hw: pointer to hardware structure 3199 * @i2cctl: Current value of I2CCTL register 3200 * @data: I2C data value (0 or 1) to set 3201 * 3202 * Sets the I2C data bit 3203 **/ 3204 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3205 { 3206 s32 status = E1000_SUCCESS; 3207 3208 DEBUGFUNC("e1000_set_i2c_data"); 3209 3210 if (data) 3211 *i2cctl |= E1000_I2C_DATA_OUT; 3212 else 3213 *i2cctl &= ~E1000_I2C_DATA_OUT; 3214 3215 *i2cctl &= ~E1000_I2C_DATA_OE_N; 3216 *i2cctl |= E1000_I2C_CLK_OE_N; 3217 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3218 E1000_WRITE_FLUSH(hw); 3219 3220 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3221 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3222 3223 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3224 if (data != e1000_get_i2c_data(i2cctl)) { 3225 status = E1000_ERR_I2C; 3226 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3227 } 3228 3229 return status; 3230 } 3231 3232 /** 3233 * e1000_get_i2c_data - Reads the I2C SDA data bit 3234 * @hw: pointer to hardware structure 3235 * @i2cctl: Current value of I2CCTL register 3236 * 3237 * Returns the I2C data bit value 3238 **/ 3239 static bool e1000_get_i2c_data(u32 *i2cctl) 3240 { 3241 bool data; 3242 3243 DEBUGFUNC("e1000_get_i2c_data"); 3244 3245 if (*i2cctl & E1000_I2C_DATA_IN) 3246 data = 1; 3247 else 3248 data = 0; 3249 3250 return data; 3251 } 3252 3253 /** 3254 * e1000_i2c_bus_clear - Clears the I2C bus 3255 * @hw: pointer to hardware structure 3256 * 3257 * Clears the I2C bus by sending nine clock pulses. 3258 * Used when data line is stuck low. 3259 **/ 3260 void e1000_i2c_bus_clear(struct e1000_hw *hw) 3261 { 3262 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3263 u32 i; 3264 3265 DEBUGFUNC("e1000_i2c_bus_clear"); 3266 3267 e1000_i2c_start(hw); 3268 3269 e1000_set_i2c_data(hw, &i2cctl, 1); 3270 3271 for (i = 0; i < 9; i++) { 3272 e1000_raise_i2c_clk(hw, &i2cctl); 3273 3274 /* Min high period of clock is 4us */ 3275 usec_delay(E1000_I2C_T_HIGH); 3276 3277 e1000_lower_i2c_clk(hw, &i2cctl); 3278 3279 /* Min low period of clock is 4.7us*/ 3280 usec_delay(E1000_I2C_T_LOW); 3281 } 3282 3283 e1000_i2c_start(hw); 3284 3285 /* Put the i2c bus back to default state */ 3286 e1000_i2c_stop(hw); 3287 } 3288 3289 3290