1*56b2bdd1SGireesh Nagabhushana /* 2*56b2bdd1SGireesh Nagabhushana * This file and its contents are supplied under the terms of the 3*56b2bdd1SGireesh Nagabhushana * Common Development and Distribution License ("CDDL"), version 1.0. 4*56b2bdd1SGireesh Nagabhushana * You may only use this file in accordance with the terms of version 5*56b2bdd1SGireesh Nagabhushana * 1.0 of the CDDL. 6*56b2bdd1SGireesh Nagabhushana * 7*56b2bdd1SGireesh Nagabhushana * A full copy of the text of the CDDL should have accompanied this 8*56b2bdd1SGireesh Nagabhushana * source. A copy of the CDDL is also available via the Internet at 9*56b2bdd1SGireesh Nagabhushana * http://www.illumos.org/license/CDDL. 10*56b2bdd1SGireesh Nagabhushana */ 11*56b2bdd1SGireesh Nagabhushana 12*56b2bdd1SGireesh Nagabhushana /* 13*56b2bdd1SGireesh Nagabhushana * This file is part of the Chelsio T4 support code. 14*56b2bdd1SGireesh Nagabhushana * 15*56b2bdd1SGireesh Nagabhushana * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved. 16*56b2bdd1SGireesh Nagabhushana * 17*56b2bdd1SGireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT 18*56b2bdd1SGireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19*56b2bdd1SGireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20*56b2bdd1SGireesh Nagabhushana * release for licensing terms and conditions. 21*56b2bdd1SGireesh Nagabhushana */ 22*56b2bdd1SGireesh Nagabhushana 23*56b2bdd1SGireesh Nagabhushana #ifndef __CXGBE_OFFLOAD_H 24*56b2bdd1SGireesh Nagabhushana #define __CXGBE_OFFLOAD_H 25*56b2bdd1SGireesh Nagabhushana 26*56b2bdd1SGireesh Nagabhushana /* 27*56b2bdd1SGireesh Nagabhushana * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 28*56b2bdd1SGireesh Nagabhushana */ 29*56b2bdd1SGireesh Nagabhushana #define MAX_ATIDS 8192U 30*56b2bdd1SGireesh Nagabhushana 31*56b2bdd1SGireesh Nagabhushana #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \ 32*56b2bdd1SGireesh Nagabhushana (w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_ULPTX_WR) | \ 33*56b2bdd1SGireesh Nagabhushana V_FW_WR_ATOMIC(atomic)); \ 34*56b2bdd1SGireesh Nagabhushana (w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \ 35*56b2bdd1SGireesh Nagabhushana V_FW_WR_FLOWID(tid)); \ 36*56b2bdd1SGireesh Nagabhushana (w)->wr.wr_lo = cpu_to_be64(0); \ 37*56b2bdd1SGireesh Nagabhushana } while (0) 38*56b2bdd1SGireesh Nagabhushana 39*56b2bdd1SGireesh Nagabhushana #define INIT_TP_WR(w, tid) do { \ 40*56b2bdd1SGireesh Nagabhushana (w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_TP_WR) | \ 41*56b2bdd1SGireesh Nagabhushana V_FW_WR_IMMDLEN(sizeof (*w) - sizeof (w->wr))); \ 42*56b2bdd1SGireesh Nagabhushana (w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(sizeof (*w), 16)) | \ 43*56b2bdd1SGireesh Nagabhushana V_FW_WR_FLOWID(tid)); \ 44*56b2bdd1SGireesh Nagabhushana (w)->wr.wr_lo = cpu_to_be64(0); \ 45*56b2bdd1SGireesh Nagabhushana } while (0) 46*56b2bdd1SGireesh Nagabhushana 47*56b2bdd1SGireesh Nagabhushana #define INIT_TP_WR_MIT_CPL(w, cpl, tid) do { \ 48*56b2bdd1SGireesh Nagabhushana INIT_TP_WR(w, tid); \ 49*56b2bdd1SGireesh Nagabhushana OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \ 50*56b2bdd1SGireesh Nagabhushana } while (0) 51*56b2bdd1SGireesh Nagabhushana 52*56b2bdd1SGireesh Nagabhushana union serv_entry { 53*56b2bdd1SGireesh Nagabhushana void *data; 54*56b2bdd1SGireesh Nagabhushana union serv_entry *next; 55*56b2bdd1SGireesh Nagabhushana }; 56*56b2bdd1SGireesh Nagabhushana 57*56b2bdd1SGireesh Nagabhushana union aopen_entry { 58*56b2bdd1SGireesh Nagabhushana void *data; 59*56b2bdd1SGireesh Nagabhushana union aopen_entry *next; 60*56b2bdd1SGireesh Nagabhushana }; 61*56b2bdd1SGireesh Nagabhushana 62*56b2bdd1SGireesh Nagabhushana /* 63*56b2bdd1SGireesh Nagabhushana * Holds the size, base address, free list start, etc of the TID, server TID, 64*56b2bdd1SGireesh Nagabhushana * and active-open TID tables. The tables themselves are allocated dynamically. 65*56b2bdd1SGireesh Nagabhushana */ 66*56b2bdd1SGireesh Nagabhushana struct tid_info { 67*56b2bdd1SGireesh Nagabhushana void **tid_tab; 68*56b2bdd1SGireesh Nagabhushana unsigned int ntids; 69*56b2bdd1SGireesh Nagabhushana 70*56b2bdd1SGireesh Nagabhushana union serv_entry *stid_tab; 71*56b2bdd1SGireesh Nagabhushana unsigned int nstids; 72*56b2bdd1SGireesh Nagabhushana unsigned int stid_base; 73*56b2bdd1SGireesh Nagabhushana 74*56b2bdd1SGireesh Nagabhushana union aopen_entry *atid_tab; 75*56b2bdd1SGireesh Nagabhushana unsigned int natids; 76*56b2bdd1SGireesh Nagabhushana 77*56b2bdd1SGireesh Nagabhushana struct filter_entry *ftid_tab; 78*56b2bdd1SGireesh Nagabhushana unsigned int nftids; 79*56b2bdd1SGireesh Nagabhushana unsigned int ftid_base; 80*56b2bdd1SGireesh Nagabhushana unsigned int ftids_in_use; 81*56b2bdd1SGireesh Nagabhushana 82*56b2bdd1SGireesh Nagabhushana kmutex_t atid_lock; 83*56b2bdd1SGireesh Nagabhushana union aopen_entry *afree; 84*56b2bdd1SGireesh Nagabhushana unsigned int atids_in_use; 85*56b2bdd1SGireesh Nagabhushana 86*56b2bdd1SGireesh Nagabhushana kmutex_t stid_lock; 87*56b2bdd1SGireesh Nagabhushana union serv_entry *sfree; 88*56b2bdd1SGireesh Nagabhushana unsigned int stids_in_use; 89*56b2bdd1SGireesh Nagabhushana 90*56b2bdd1SGireesh Nagabhushana unsigned int tids_in_use; 91*56b2bdd1SGireesh Nagabhushana }; 92*56b2bdd1SGireesh Nagabhushana 93*56b2bdd1SGireesh Nagabhushana struct t4_range { 94*56b2bdd1SGireesh Nagabhushana unsigned int start; 95*56b2bdd1SGireesh Nagabhushana unsigned int size; 96*56b2bdd1SGireesh Nagabhushana }; 97*56b2bdd1SGireesh Nagabhushana 98*56b2bdd1SGireesh Nagabhushana struct t4_virt_res { /* virtualized HW resources */ 99*56b2bdd1SGireesh Nagabhushana struct t4_range ddp; 100*56b2bdd1SGireesh Nagabhushana struct t4_range iscsi; 101*56b2bdd1SGireesh Nagabhushana struct t4_range stag; 102*56b2bdd1SGireesh Nagabhushana struct t4_range rq; 103*56b2bdd1SGireesh Nagabhushana struct t4_range pbl; 104*56b2bdd1SGireesh Nagabhushana }; 105*56b2bdd1SGireesh Nagabhushana 106*56b2bdd1SGireesh Nagabhushana struct adapter; 107*56b2bdd1SGireesh Nagabhushana struct port_info; 108*56b2bdd1SGireesh Nagabhushana 109*56b2bdd1SGireesh Nagabhushana enum { 110*56b2bdd1SGireesh Nagabhushana ULD_TOM = 1, 111*56b2bdd1SGireesh Nagabhushana }; 112*56b2bdd1SGireesh Nagabhushana 113*56b2bdd1SGireesh Nagabhushana enum cxgb4_control { 114*56b2bdd1SGireesh Nagabhushana CXGB4_CONTROL_SET_OFFLOAD_POLICY, 115*56b2bdd1SGireesh Nagabhushana }; 116*56b2bdd1SGireesh Nagabhushana 117*56b2bdd1SGireesh Nagabhushana struct uld_info { 118*56b2bdd1SGireesh Nagabhushana SLIST_ENTRY(uld_info) link; 119*56b2bdd1SGireesh Nagabhushana int refcount; 120*56b2bdd1SGireesh Nagabhushana int uld_id; 121*56b2bdd1SGireesh Nagabhushana int (*attach)(struct adapter *, void **); 122*56b2bdd1SGireesh Nagabhushana int (*detach)(void *); 123*56b2bdd1SGireesh Nagabhushana int (*rx)(void *, const void *, mblk_t *); 124*56b2bdd1SGireesh Nagabhushana int (*control)(void *handle, enum cxgb4_control control, ...); 125*56b2bdd1SGireesh Nagabhushana }; 126*56b2bdd1SGireesh Nagabhushana 127*56b2bdd1SGireesh Nagabhushana struct uld_softc { 128*56b2bdd1SGireesh Nagabhushana struct uld_info *uld; 129*56b2bdd1SGireesh Nagabhushana void *softc; 130*56b2bdd1SGireesh Nagabhushana }; 131*56b2bdd1SGireesh Nagabhushana 132*56b2bdd1SGireesh Nagabhushana struct tom_tunables { 133*56b2bdd1SGireesh Nagabhushana int sndbuf; 134*56b2bdd1SGireesh Nagabhushana int ddp; 135*56b2bdd1SGireesh Nagabhushana int indsz; 136*56b2bdd1SGireesh Nagabhushana int ddp_thres; 137*56b2bdd1SGireesh Nagabhushana }; 138*56b2bdd1SGireesh Nagabhushana 139*56b2bdd1SGireesh Nagabhushana #ifndef TCP_OFFLOAD_DISABLE 140*56b2bdd1SGireesh Nagabhushana struct offload_req { 141*56b2bdd1SGireesh Nagabhushana __be32 sip[4]; 142*56b2bdd1SGireesh Nagabhushana __be32 dip[4]; 143*56b2bdd1SGireesh Nagabhushana __be16 sport; 144*56b2bdd1SGireesh Nagabhushana __be16 dport; 145*56b2bdd1SGireesh Nagabhushana __u8 ipvers_opentype; 146*56b2bdd1SGireesh Nagabhushana __u8 tos; 147*56b2bdd1SGireesh Nagabhushana __be16 vlan; 148*56b2bdd1SGireesh Nagabhushana __u32 mark; 149*56b2bdd1SGireesh Nagabhushana }; 150*56b2bdd1SGireesh Nagabhushana 151*56b2bdd1SGireesh Nagabhushana enum { OPEN_TYPE_LISTEN, OPEN_TYPE_ACTIVE, OPEN_TYPE_PASSIVE }; 152*56b2bdd1SGireesh Nagabhushana 153*56b2bdd1SGireesh Nagabhushana struct offload_settings { 154*56b2bdd1SGireesh Nagabhushana __u8 offload; 155*56b2bdd1SGireesh Nagabhushana int8_t ddp; 156*56b2bdd1SGireesh Nagabhushana int8_t rx_coalesce; 157*56b2bdd1SGireesh Nagabhushana int8_t cong_algo; 158*56b2bdd1SGireesh Nagabhushana int32_t rssq; 159*56b2bdd1SGireesh Nagabhushana int16_t sched_class; 160*56b2bdd1SGireesh Nagabhushana int8_t tstamp; 161*56b2bdd1SGireesh Nagabhushana int8_t sack; 162*56b2bdd1SGireesh Nagabhushana 163*56b2bdd1SGireesh Nagabhushana }; 164*56b2bdd1SGireesh Nagabhushana #endif 165*56b2bdd1SGireesh Nagabhushana 166*56b2bdd1SGireesh Nagabhushana extern int t4_register_uld(struct uld_info *ui); 167*56b2bdd1SGireesh Nagabhushana extern int t4_unregister_uld(struct uld_info *ui); 168*56b2bdd1SGireesh Nagabhushana 169*56b2bdd1SGireesh Nagabhushana #endif /* __CXGBE_OFFLOAD_H */ 170