xref: /titanic_50/usr/src/uts/common/io/bnxe/bnxe.conf (revision d14abf155341d55053c76eeec58b787a456b753b)
1*d14abf15SRobert Mustacchi#
2*d14abf15SRobert Mustacchi# CDDL HEADER START
3*d14abf15SRobert Mustacchi#
4*d14abf15SRobert Mustacchi# The contents of this file are subject to the terms of the
5*d14abf15SRobert Mustacchi# Common Development and Distribution License (the "License").
6*d14abf15SRobert Mustacchi# You may not use this file except in compliance with the License.
7*d14abf15SRobert Mustacchi#
8*d14abf15SRobert Mustacchi# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*d14abf15SRobert Mustacchi# or http://www.opensolaris.org/os/licensing.
10*d14abf15SRobert Mustacchi# See the License for the specific language governing permissions
11*d14abf15SRobert Mustacchi# and limitations under the License.
12*d14abf15SRobert Mustacchi#
13*d14abf15SRobert Mustacchi# When distributing Covered Code, include this CDDL HEADER in each
14*d14abf15SRobert Mustacchi# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*d14abf15SRobert Mustacchi# If applicable, add the following below this CDDL HEADER, with the
16*d14abf15SRobert Mustacchi# fields enclosed by brackets "[]" replaced with your own identifying
17*d14abf15SRobert Mustacchi# information: Portions Copyright [yyyy] [name of copyright owner]
18*d14abf15SRobert Mustacchi#
19*d14abf15SRobert Mustacchi# CDDL HEADER END
20*d14abf15SRobert Mustacchi#
21*d14abf15SRobert Mustacchi
22*d14abf15SRobert Mustacchi#
23*d14abf15SRobert Mustacchi# Copyright 2014 QLogic Corporation
24*d14abf15SRobert Mustacchi# The contents of this file are subject to the terms of the
25*d14abf15SRobert Mustacchi# QLogic End User License (the "License").
26*d14abf15SRobert Mustacchi# You may not use this file except in compliance with the License.
27*d14abf15SRobert Mustacchi#
28*d14abf15SRobert Mustacchi# You can obtain a copy of the License at
29*d14abf15SRobert Mustacchi# http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
30*d14abf15SRobert Mustacchi# QLogic_End_User_Software_License.txt
31*d14abf15SRobert Mustacchi# See the License for the specific language governing permissions
32*d14abf15SRobert Mustacchi# and limitations under the License.
33*d14abf15SRobert Mustacchi#
34*d14abf15SRobert Mustacchi#
35*d14abf15SRobert Mustacchi# All configuration can be specified per-instance.  The format used is as
36*d14abf15SRobert Mustacchi# follows and each line must end with a semicolon:
37*d14abf15SRobert Mustacchi#
38*d14abf15SRobert Mustacchi#   bnxe<#>_<config_item>=X;
39*d14abf15SRobert Mustacchi#
40*d14abf15SRobert Mustacchi# So for "adv_autoneg_cap" you would use the following:
41*d14abf15SRobert Mustacchi#
42*d14abf15SRobert Mustacchi#   bnxe0_adv_autoneg_cap=1;
43*d14abf15SRobert Mustacchi#   bnxe1_adv_autoneg_cap=0;
44*d14abf15SRobert Mustacchi#   bnxe2_adv_autoneg_cap=1;
45*d14abf15SRobert Mustacchi#   bnxe3_adv_autoneg_cap=1;
46*d14abf15SRobert Mustacchi#
47*d14abf15SRobert Mustacchi# If a configuration item is not specified for a specific instance then the
48*d14abf15SRobert Mustacchi# default value will be used.  The default value used by all instances can be
49*d14abf15SRobert Mustacchi# overridden using:
50*d14abf15SRobert Mustacchi#
51*d14abf15SRobert Mustacchi#   default_<config_item>=X;
52*d14abf15SRobert Mustacchi#
53*d14abf15SRobert Mustacchi# For boolean values 1 = TRUE and 0 = FALSE.
54*d14abf15SRobert Mustacchi#
55*d14abf15SRobert Mustacchi
56*d14abf15SRobert Mustacchi# adv_autoneg_cap - advertise autonegotiation mode
57*d14abf15SRobert Mustacchi#                 - default enabled
58*d14abf15SRobert Mustacchi#                 - 0 = disabled / 1 = enabled
59*d14abf15SRobert Mustacchi#default_adv_autoneg_cap=1;
60*d14abf15SRobert Mustacchi#bnxe0_adv_autoneg_cap=1;
61*d14abf15SRobert Mustacchi#bnxe1_adv_autoneg_cap=1;
62*d14abf15SRobert Mustacchi
63*d14abf15SRobert Mustacchi# adv_20000fdx_cap - advertise 20Gbps full duplex
64*d14abf15SRobert Mustacchi#                  - ignored for serdes devices
65*d14abf15SRobert Mustacchi#                  - default enabled
66*d14abf15SRobert Mustacchi#                  - 0 = disable / 1 = enable
67*d14abf15SRobert Mustacchi#default_adv_20000fdx_cap=1;
68*d14abf15SRobert Mustacchi#bnxe0_adv_20000fdx_cap=1;
69*d14abf15SRobert Mustacchi#bnxe1_adv_20000fdx_cap=1;
70*d14abf15SRobert Mustacchi
71*d14abf15SRobert Mustacchi# adv_10000fdx_cap - advertise 10Gbps full duplex
72*d14abf15SRobert Mustacchi#                  - ignored for serdes devices
73*d14abf15SRobert Mustacchi#                  - default enabled
74*d14abf15SRobert Mustacchi#                  - 0 = disable / 1 = enable
75*d14abf15SRobert Mustacchi#default_adv_10000fdx_cap=1;
76*d14abf15SRobert Mustacchi#bnxe0_adv_10000fdx_cap=1;
77*d14abf15SRobert Mustacchi#bnxe1_adv_10000fdx_cap=1;
78*d14abf15SRobert Mustacchi
79*d14abf15SRobert Mustacchi# adv_2500fdx_cap - advertise 2500Mbps full duplex
80*d14abf15SRobert Mustacchi#                 - ignored for copper devices
81*d14abf15SRobert Mustacchi#                 - default enabled
82*d14abf15SRobert Mustacchi#                 - 0 = disable / 1 = enable
83*d14abf15SRobert Mustacchi#default_adv_2500fdx_cap=1;
84*d14abf15SRobert Mustacchi#bnxe0_adv_2500fdx_cap=1;
85*d14abf15SRobert Mustacchi#bnxe1_adv_2500fdx_cap=1;
86*d14abf15SRobert Mustacchi
87*d14abf15SRobert Mustacchi# adv_1000fdx_cap - advertise 1000Mbps full duplex
88*d14abf15SRobert Mustacchi#                 - default enabled
89*d14abf15SRobert Mustacchi#                 - 0 = disable / 1 = enable
90*d14abf15SRobert Mustacchi#default_adv_1000fdx_cap=1;
91*d14abf15SRobert Mustacchi#bnxe0_adv_1000fdx_cap=1;
92*d14abf15SRobert Mustacchi#bnxe1_adv_1000fdx_cap=1;
93*d14abf15SRobert Mustacchi
94*d14abf15SRobert Mustacchi# adv_100fdx_cap - advertise 100Mbps full duplex
95*d14abf15SRobert Mustacchi#                - ignored for serdes devices
96*d14abf15SRobert Mustacchi#                - default disabled
97*d14abf15SRobert Mustacchi#                - 0 = disable / 1 = enable
98*d14abf15SRobert Mustacchi#default_adv_100fdx_cap=0;
99*d14abf15SRobert Mustacchi#bnxe0_adv_100fdx_cap=0;
100*d14abf15SRobert Mustacchi#bnxe1_adv_100fdx_cap=0;
101*d14abf15SRobert Mustacchi
102*d14abf15SRobert Mustacchi# adv_100hdx_cap - advertise 100Mbps half duplex
103*d14abf15SRobert Mustacchi#                - ignored for serdes devices
104*d14abf15SRobert Mustacchi#                - default disabled
105*d14abf15SRobert Mustacchi#                - 0 = disable / 1 = enable
106*d14abf15SRobert Mustacchi#default_adv_100hdx_cap=0;
107*d14abf15SRobert Mustacchi#bnxe0_adv_100hdx_cap=0;
108*d14abf15SRobert Mustacchi#bnxe1_adv_100hdx_cap=0;
109*d14abf15SRobert Mustacchi
110*d14abf15SRobert Mustacchi# adv_10fdx_cap - advertise 10Mbps full duplex
111*d14abf15SRobert Mustacchi#               - ignored for serdes devices
112*d14abf15SRobert Mustacchi#               - default disabled
113*d14abf15SRobert Mustacchi#               - 0 = disable / 1 = enable
114*d14abf15SRobert Mustacchi#default_adv_10fdx_cap=0;
115*d14abf15SRobert Mustacchi#bnxe0_adv_10fdx_cap=0;
116*d14abf15SRobert Mustacchi#bnxe1_adv_10fdx_cap=0;
117*d14abf15SRobert Mustacchi
118*d14abf15SRobert Mustacchi# adv_10hdx_cap - advertise 10Mbps half duplex
119*d14abf15SRobert Mustacchi#               - ignored for serdes devices
120*d14abf15SRobert Mustacchi#               - default disabled
121*d14abf15SRobert Mustacchi#               - 0 = disable / 1 = enable
122*d14abf15SRobert Mustacchi#default_adv_10hdx_cap=0;
123*d14abf15SRobert Mustacchi#bnxe0_adv_10hdx_cap=0;
124*d14abf15SRobert Mustacchi#bnxe1_adv_10hdx_cap=0;
125*d14abf15SRobert Mustacchi
126*d14abf15SRobert Mustacchi# txpause_cap - controls whether or not tx flow control is enabled
127*d14abf15SRobert Mustacchi#             - default enabled
128*d14abf15SRobert Mustacchi#             - 0 = disable / 1 = enable
129*d14abf15SRobert Mustacchi#default_txpause_cap=1;
130*d14abf15SRobert Mustacchi#bnxe0_txpause_cap=1;
131*d14abf15SRobert Mustacchi#bnxe1_txpause_cap=1;
132*d14abf15SRobert Mustacchi
133*d14abf15SRobert Mustacchi# rxpause_cap - controls whether or not rx flow control is enabled
134*d14abf15SRobert Mustacchi#             - default enabled
135*d14abf15SRobert Mustacchi#             - 0 = disable / 1 = enable
136*d14abf15SRobert Mustacchi#default_rxpause_cap=1;
137*d14abf15SRobert Mustacchi#bnxe0_rxpause_cap=1;
138*d14abf15SRobert Mustacchi#bnxe1_rxpause_cap=1;
139*d14abf15SRobert Mustacchi
140*d14abf15SRobert Mustacchi# autoneg_flow - advertise flow autonegotiation mode
141*d14abf15SRobert Mustacchi#              - for MTUs greater than 5000 flow control is automatically
142*d14abf15SRobert Mustacchi#                forced off no matter what the configuration is set to
143*d14abf15SRobert Mustacchi#              - default enabled
144*d14abf15SRobert Mustacchi#              - 0 = disable / 1 = enable
145*d14abf15SRobert Mustacchi#default_autoneg_flow=1;
146*d14abf15SRobert Mustacchi#bnxe0_autoneg_flow=1;
147*d14abf15SRobert Mustacchi#bnxe1_autoneg_flow=1;
148*d14abf15SRobert Mustacchi
149*d14abf15SRobert Mustacchi# checksum - configures checksum tasks to be offloaded to the card
150*d14abf15SRobert Mustacchi#          - default is TCP/UDP/IPv4 checksum offload for rx/tx
151*d14abf15SRobert Mustacchi#          - 0 = no checksum offload
152*d14abf15SRobert Mustacchi#          - 1 = IPv4 checksum offload for rx/tx
153*d14abf15SRobert Mustacchi#          - 2 = TCP/UDP/IPv4 checksum offload for rx/tx
154*d14abf15SRobert Mustacchi#default_checksum=2;
155*d14abf15SRobert Mustacchi#bnxe0_checksum=2;
156*d14abf15SRobert Mustacchi#bnxe1_checksum=2;
157*d14abf15SRobert Mustacchi
158*d14abf15SRobert Mustacchi# mtu - hardware MTU size
159*d14abf15SRobert Mustacchi#     - valid range is 60 to 9216
160*d14abf15SRobert Mustacchi#     - default is 1500
161*d14abf15SRobert Mustacchi#default_mtu=1500;
162*d14abf15SRobert Mustacchi#bnxe0_mtu=1500;
163*d14abf15SRobert Mustacchi#bnxe1_mtu=1500;
164*d14abf15SRobert Mustacchi
165*d14abf15SRobert Mustacchi# route_tx_ring_policy - policy used to route outgoing packets on rings
166*d14abf15SRobert Mustacchi#                      - default is 1 for TCP/UDP port hash
167*d14abf15SRobert Mustacchi#                      - 0 = NONE, all packets sent on ring 0
168*d14abf15SRobert Mustacchi#                      - 1 = TCP/UDP port hash
169*d14abf15SRobert Mustacchi#                      - 2 = Destination MAC address hash
170*d14abf15SRobert Mustacchi#                      - 3 = packet message priority (set in mblk)
171*d14abf15SRobert Mustacchi#default_route_tx_ring_policy=1;
172*d14abf15SRobert Mustacchi#bnxe0_route_tx_ring_policy=1;
173*d14abf15SRobert Mustacchi#bnxe1_route_tx_ring_policy=1;
174*d14abf15SRobert Mustacchi
175*d14abf15SRobert Mustacchi# num_rings - configures the number of rings to allocate
176*d14abf15SRobert Mustacchi#           - valid values are 0,1,2,4,8,16
177*d14abf15SRobert Mustacchi#           - a non-zero value overrides the default
178*d14abf15SRobert Mustacchi#           - default is 0 which implies:
179*d14abf15SRobert Mustacchi#               - 4 rings for single function mode
180*d14abf15SRobert Mustacchi#               - 1 ring for multi-function mode to keep the number
181*d14abf15SRobert Mustacchi#                 of interrupt allocations at a minimum.
182*d14abf15SRobert Mustacchi#default_num_rings=0;
183*d14abf15SRobert Mustacchi#bnxe0_num_rings=0;
184*d14abf15SRobert Mustacchi#bnxe1_num_rings=0;
185*d14abf15SRobert Mustacchi
186*d14abf15SRobert Mustacchi# rx_descs - configures the number of RX packet descriptors to allocate per ring
187*d14abf15SRobert Mustacchi#          - to keep the number of DMA allocations at a minimum, on 57711 in
188*d14abf15SRobert Mustacchi#            multi-function mode this config value is divided by four(4) and the
189*d14abf15SRobert Mustacchi#            resulting value is used as the descriptor count for each virtual
190*d14abf15SRobert Mustacchi#            interface
191*d14abf15SRobert Mustacchi#          - valid range is 1 to 32767
192*d14abf15SRobert Mustacchi#          - default is 1024
193*d14abf15SRobert Mustacchi#default_rx_descs=1024;
194*d14abf15SRobert Mustacchi#bnxe0_rx_descs=1024;
195*d14abf15SRobert Mustacchi#bnxe1_rx_descs=1024;
196*d14abf15SRobert Mustacchi
197*d14abf15SRobert Mustacchi# tx_descs - configures the number of TX packet descriptors to allocate per ring
198*d14abf15SRobert Mustacchi#          - to keep the number of DMA allocations at a minimum, on 57711 in
199*d14abf15SRobert Mustacchi#            multi-function mode this config value is divided by four(4) and the
200*d14abf15SRobert Mustacchi#            resulting value is used as the descriptor count for each virtual
201*d14abf15SRobert Mustacchi#            interface
202*d14abf15SRobert Mustacchi#          - valid range is 1 to 32767
203*d14abf15SRobert Mustacchi#          - default is 1024
204*d14abf15SRobert Mustacchi#default_tx_descs=1024;
205*d14abf15SRobert Mustacchi#bnxe0_tx_descs=1024;
206*d14abf15SRobert Mustacchi#bnxe1_tx_descs=1024;
207*d14abf15SRobert Mustacchi
208*d14abf15SRobert Mustacchi# rx_free_reclaim - configures the number of outstanding already processed
209*d14abf15SRobert Mustacchi#                   RX packet descriptors allowed before posting back for reuse
210*d14abf15SRobert Mustacchi#                 - valid range is 0 to value of 'rx_descs'
211*d14abf15SRobert Mustacchi#                 - default is 32
212*d14abf15SRobert Mustacchi#default_rx_free_reclaim=32;
213*d14abf15SRobert Mustacchi#bnxe0_rx_free_reclaim=32;
214*d14abf15SRobert Mustacchi#bnxe1_rx_free_reclaim=32;
215*d14abf15SRobert Mustacchi
216*d14abf15SRobert Mustacchi# tx_free_reclaim - configures the number of outstanding already processed
217*d14abf15SRobert Mustacchi#                   TX packet descriptors allowed before posting back for reuse
218*d14abf15SRobert Mustacchi#                 - valid range is 0 to value of 'tx_descs'
219*d14abf15SRobert Mustacchi#                 - default is 32
220*d14abf15SRobert Mustacchi#default_tx_free_reclaim=32;
221*d14abf15SRobert Mustacchi#bnxe0_tx_free_reclaim=32;
222*d14abf15SRobert Mustacchi#bnxe1_tx_free_reclaim=32;
223*d14abf15SRobert Mustacchi
224*d14abf15SRobert Mustacchi# rx_copy_threshold - packets smaller than this threshold (number of bytes) will
225*d14abf15SRobert Mustacchi#                     be copied into a new buffer before sending up the stack
226*d14abf15SRobert Mustacchi#                   - default is all rx packets less then 128 bytes are copied
227*d14abf15SRobert Mustacchi#default_rx_copy_threshold=128;
228*d14abf15SRobert Mustacchi#bnxe0_rx_copy_threshold=128;
229*d14abf15SRobert Mustacchi#bnxe1_rx_copy_threshold=128;
230*d14abf15SRobert Mustacchi
231*d14abf15SRobert Mustacchi# tx_copy_threshold - packets smaller than this threshold (number of bytes) will
232*d14abf15SRobert Mustacchi#                     be copied into a new buffer before sending to the hardware
233*d14abf15SRobert Mustacchi#                   - default is all tx packets less then 512 bytes are copied
234*d14abf15SRobert Mustacchi#default_tx_copy_threshold=512;
235*d14abf15SRobert Mustacchi#bnxe0_tx_copy_threshold=512;
236*d14abf15SRobert Mustacchi#bnxe1_tx_copy_threshold=512;
237*d14abf15SRobert Mustacchi
238*d14abf15SRobert Mustacchi# interrupt_coalesce - enable interrupt/packet coalescing
239*d14abf15SRobert Mustacchi#                      on  = great sustained/burst / decent interactive
240*d14abf15SRobert Mustacchi#                      off = great interactive / decent systained/burst
241*d14abf15SRobert Mustacchi#                    - default enabled
242*d14abf15SRobert Mustacchi#                    - 0 = disabled / 1 = enabled
243*d14abf15SRobert Mustacchi#default_interrupt_coalesce=1;
244*d14abf15SRobert Mustacchi#bnxe0_interrupt_coalesce=1;
245*d14abf15SRobert Mustacchi#bnxe1_interrupt_coalesce=1;
246*d14abf15SRobert Mustacchi
247*d14abf15SRobert Mustacchi# rx_interrupt_coalesce_usec - time between rx interrupts in usecs
248*d14abf15SRobert Mustacchi#                            - only valid if interrupt_coalesce turned on
249*d14abf15SRobert Mustacchi#                            - valid range is 10 to 1000
250*d14abf15SRobert Mustacchi#                            - default 20
251*d14abf15SRobert Mustacchi#default_rx_interrupt_coalesce_usec=20;
252*d14abf15SRobert Mustacchi#bnxe0_rx_interrupt_coalesce_usec=20;
253*d14abf15SRobert Mustacchi#bnxe1_rx_interrupt_coalesce_usec=20;
254*d14abf15SRobert Mustacchi
255*d14abf15SRobert Mustacchi# tx_interrupt_coalesce_usec - time between tx interrupts in usecs
256*d14abf15SRobert Mustacchi#                            - only valid if interrupt_coalesce turned on
257*d14abf15SRobert Mustacchi#                            - valid range is 10 to 1000
258*d14abf15SRobert Mustacchi#                            - default 40
259*d14abf15SRobert Mustacchi#default_tx_interrupt_coalesce_usec=40;
260*d14abf15SRobert Mustacchi#bnxe0_tx_interrupt_coalesce_usec=40;
261*d14abf15SRobert Mustacchi#bnxe1_tx_interrupt_coalesce_usec=40;
262*d14abf15SRobert Mustacchi
263*d14abf15SRobert Mustacchi# disable_msix - turn off MSI-X and use Fixed level interrupts
264*d14abf15SRobert Mustacchi#              - default is FALSE, use MSI-X
265*d14abf15SRobert Mustacchi#              - 0 = MSI-X enabled / 1 = Fixed enabled
266*d14abf15SRobert Mustacchi#default_disable_msix=0;
267*d14abf15SRobert Mustacchi#bnxe0_disable_msix=0;
268*d14abf15SRobert Mustacchi#bnxe1_disable_msix=0;
269*d14abf15SRobert Mustacchi
270*d14abf15SRobert Mustacchi# l2_fw_flow_ctrl - enable flow control when rx ring is low on buffers
271*d14abf15SRobert Mustacchi#                   NOTE: This parameter is NOT used in multifunction mode
272*d14abf15SRobert Mustacchi#                   as the config is driven via nvram and device shared
273*d14abf15SRobert Mustacchi#                   memory in that case.
274*d14abf15SRobert Mustacchi#                 - default disabled
275*d14abf15SRobert Mustacchi#                 - 0 = disabled / 1 = enabled
276*d14abf15SRobert Mustacchi#default_l2_fw_flow_ctrl=0;
277*d14abf15SRobert Mustacchi#bnxe0_l2_fw_flow_ctrl=0;
278*d14abf15SRobert Mustacchi#bnxe1_l2_fw_flow_ctrl=0;
279*d14abf15SRobert Mustacchi
280*d14abf15SRobert Mustacchi# autogreeen_enable - enable AutogrEEEn for devices that support it
281*d14abf15SRobert Mustacchi#                   - default enabled
282*d14abf15SRobert Mustacchi#                   - 0 = disabled / 1 = enabled
283*d14abf15SRobert Mustacchi#default_autogreeen_enable=1;
284*d14abf15SRobert Mustacchi#bnxe0_autogreeen_enable=1;
285*d14abf15SRobert Mustacchi#bnxe1_autogreeen_enable=1;
286*d14abf15SRobert Mustacchi
287*d14abf15SRobert Mustacchi# lso_enable - enable TCP Large Segment Offload (LSO)
288*d14abf15SRobert Mustacchi#            - default enabled
289*d14abf15SRobert Mustacchi#            - 0 = disabled / 1 = enabled
290*d14abf15SRobert Mustacchi#default_lso_enable=1;
291*d14abf15SRobert Mustacchi#bnxe0_lso_enable=1;
292*d14abf15SRobert Mustacchi#bnxe1_lso_enable=1;
293*d14abf15SRobert Mustacchi
294*d14abf15SRobert Mustacchi# log_enable - enable syslog logging of vital information
295*d14abf15SRobert Mustacchi#            - default enabled
296*d14abf15SRobert Mustacchi#            - 0 = disabled / 1 = enabled
297*d14abf15SRobert Mustacchi#default_log_enable=1;
298*d14abf15SRobert Mustacchi#bnxe0_log_enable=1;
299*d14abf15SRobert Mustacchi#bnxe1_log_enable=1;
300*d14abf15SRobert Mustacchi
301*d14abf15SRobert Mustacchi# link_remote_fault_detect - enable/disable phy LSS remote fault detection
302*d14abf15SRobert Mustacchi#                          - default enabled
303*d14abf15SRobert Mustacchi#                          - 0 = disabled / 1 = enabled
304*d14abf15SRobert Mustacchi#default_link_remote_fault_detect=1;
305*d14abf15SRobert Mustacchi#bnxe0_link_remote_fault_detect=1;
306*d14abf15SRobert Mustacchi#bnxe1_link_remote_fault_detect=1;
307*d14abf15SRobert Mustacchi
308*d14abf15SRobert Mustacchi# LLDP - prefixed with "default_" or override with "bnxe#_"
309*d14abf15SRobert Mustacchi#default_lldp_overwrite_settings=0;
310*d14abf15SRobert Mustacchi#default_lldp_msg_tx_hold=4;
311*d14abf15SRobert Mustacchi#default_lldp_msg_fast_tx=1;
312*d14abf15SRobert Mustacchi#default_lldp_tx_credit_max=5;
313*d14abf15SRobert Mustacchi#default_lldp_msg_tx_interval=30;
314*d14abf15SRobert Mustacchi#default_lldp_tx_fast=4;
315*d14abf15SRobert Mustacchi
316*d14abf15SRobert Mustacchi# DCBX - prefixed with "default_" or override with "bnxe#_"
317*d14abf15SRobert Mustacchi#default_dcbx_dcb_enable=1;
318*d14abf15SRobert Mustacchi#default_dcbx_admin_dcbx_enable=1;
319*d14abf15SRobert Mustacchi#default_dcbx_overwrite_settings=0;
320*d14abf15SRobert Mustacchi#default_dcbx_admin_dcbx_version=0;
321*d14abf15SRobert Mustacchi#default_dcbx_admin_ets_enable=1;
322*d14abf15SRobert Mustacchi#default_dcbx_admin_pfc_enable=1;
323*d14abf15SRobert Mustacchi#default_dcbx_admin_tc_supported_tx_enable=1;
324*d14abf15SRobert Mustacchi#default_dcbx_admin_ets_configuration_tx_enable=1;
325*d14abf15SRobert Mustacchi#default_dcbx_admin_ets_recommendation_tx_enable=0;
326*d14abf15SRobert Mustacchi#default_dcbx_admin_pfc_tx_enable=0;
327*d14abf15SRobert Mustacchi#default_dcbx_admin_application_priority_tx_enable=1;
328*d14abf15SRobert Mustacchi#default_dcbx_admin_ets_willing=1;
329*d14abf15SRobert Mustacchi#default_dcbx_admin_pfc_willing=1;
330*d14abf15SRobert Mustacchi#default_dcbx_admin_ets_reco_valid=0;
331*d14abf15SRobert Mustacchi#default_dcbx_admin_app_priority_willing=1;
332*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_0=0;
333*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_1=50;
334*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_2=50;
335*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_3=0;
336*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_4=0;
337*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_5=0;
338*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_6=0;
339*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_bw_percentage_7=0;
340*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_0=0;
341*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_1=1;
342*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_2=0;
343*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_3=2;
344*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_4=1;
345*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_5=0;
346*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_6=0;
347*d14abf15SRobert Mustacchi#default_dcbx_admin_configuration_ets_pg_7=0;
348*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_0=0;
349*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_1=0;
350*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_2=0;
351*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_3=0;
352*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_4=0;
353*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_5=0;
354*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_6=0;
355*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_bw_percentage_7=0;
356*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_0=0;
357*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_1=0;
358*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_2=0;
359*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_3=0;
360*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_4=0;
361*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_5=0;
362*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_6=0;
363*d14abf15SRobert Mustacchi#default_dcbx_admin_recommendation_ets_pg_7=0;
364*d14abf15SRobert Mustacchi#default_dcbx_admin_pfc_bitmap=16;
365*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_0_valid=1;
366*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_0_priority=3;
367*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_0_traffic_type=0;
368*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_0_app_id=35078;
369*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_1_valid=1;
370*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_1_priority=4;
371*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_1_traffic_type=1;
372*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_1_app_id=3260;
373*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_2_valid=0;
374*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_2_priority=0;
375*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_2_traffic_type=0;
376*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_2_app_id=0;
377*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_3_valid=0;
378*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_3_priority=0;
379*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_3_traffic_type=0;
380*d14abf15SRobert Mustacchi#default_dcbx_admin_priority_app_table_3_app_id=0;
381*d14abf15SRobert Mustacchi#default_dcbx_admin_default_priority=1;
382*d14abf15SRobert Mustacchi
383*d14abf15SRobert Mustacchi# debug_level - mask for various debug logs
384*d14abf15SRobert Mustacchi#             - this config only affects the debug driver
385*d14abf15SRobert Mustacchi#             - (example) if you want to only see L2 receive warnings
386*d14abf15SRobert Mustacchi#               and fatals then set this to: 0x00004002
387*d14abf15SRobert Mustacchi#             - note that log levels are inclusive so specifying
388*d14abf15SRobert Mustacchi#               verbose includes inform, warn, and fatal
389*d14abf15SRobert Mustacchi#             - default is to dump everything(!): 0xffffffff
390*d14abf15SRobert Mustacchi#
391*d14abf15SRobert Mustacchi# DEBUG LOG LEVELS:
392*d14abf15SRobert Mustacchi#
393*d14abf15SRobert Mustacchi#   0x00000001  Fatal
394*d14abf15SRobert Mustacchi#   0x00000002  Warn
395*d14abf15SRobert Mustacchi#   0x00000003  Inform
396*d14abf15SRobert Mustacchi#   0x00000004  Verbose
397*d14abf15SRobert Mustacchi#   0x000000ff  All
398*d14abf15SRobert Mustacchi#
399*d14abf15SRobert Mustacchi# DEBUG LOG CODE PATHS:
400*d14abf15SRobert Mustacchi#
401*d14abf15SRobert Mustacchi#   0x00000100  Initialization
402*d14abf15SRobert Mustacchi#   0x00000200  nvram
403*d14abf15SRobert Mustacchi#   0x00001000  L2 Slow Path
404*d14abf15SRobert Mustacchi#   0x00002000  L2 Transmit
405*d14abf15SRobert Mustacchi#   0x00004000  L2 Receive
406*d14abf15SRobert Mustacchi#   0x00008000  L2 Interrupt
407*d14abf15SRobert Mustacchi#   0x0000f000  L2 all
408*d14abf15SRobert Mustacchi#   0x00010000  L4 Slow Path
409*d14abf15SRobert Mustacchi#   0x00020000  L4 Transmit
410*d14abf15SRobert Mustacchi#   0x00040000  L4 Receive
411*d14abf15SRobert Mustacchi#   0x00080000  L4 Interrupt
412*d14abf15SRobert Mustacchi#   0x000f0000  L4 all
413*d14abf15SRobert Mustacchi#   0x00100000  L5 Slow Path
414*d14abf15SRobert Mustacchi#   0x00200000  L5 Transmit
415*d14abf15SRobert Mustacchi#   0x00400000  L5 Receive
416*d14abf15SRobert Mustacchi#   0x00f00000  L5 all
417*d14abf15SRobert Mustacchi#   0x01000000  VF all
418*d14abf15SRobert Mustacchi#   0x02000000  Event Queue
419*d14abf15SRobert Mustacchi#   0x04000000  Statistics
420*d14abf15SRobert Mustacchi#   0x08000000  Event Queue
421*d14abf15SRobert Mustacchi#   0x10000000  OOO Manager
422*d14abf15SRobert Mustacchi#   0x40000000  Diagnostics
423*d14abf15SRobert Mustacchi#   0x80000000  Miscellaneous
424*d14abf15SRobert Mustacchi#
425*d14abf15SRobert Mustacchi#default_debug_level=0xffffffff;
426*d14abf15SRobert Mustacchi#bnxe0_debug_level=0xffffffff;
427*d14abf15SRobert Mustacchi#bnxe1_debug_level=0xffffffff;
428*d14abf15SRobert Mustacchi
429*d14abf15SRobert Mustacchi# If you have a system with *many* interfaces it is possible to reach the
430*d14abf15SRobert Mustacchi# allocation limit of MSIX interrupts.  By default, Solaris limits each driver
431*d14abf15SRobert Mustacchi# to 2 MSIX allocations and there is an issue with the pcplusmp module where
432*d14abf15SRobert Mustacchi# only a maximum of 31 MSIX interrupts are available per interrupt priority
433*d14abf15SRobert Mustacchi# level.
434*d14abf15SRobert Mustacchi#
435*d14abf15SRobert Mustacchi# If your system has four 57711 ports each running in multi-function mode
436*d14abf15SRobert Mustacchi# Solaris will enumerate 16 bnxe interfaces.  The last interface attached will
437*d14abf15SRobert Mustacchi# fail to allocate its second MSIX interrupt and revert to Fixed.  This in turn
438*d14abf15SRobert Mustacchi# can eventually expose an issue in the system regarding interrupt management
439*d14abf15SRobert Mustacchi# resulting in interrupts never being received on the interface which reverted
440*d14abf15SRobert Mustacchi# back to Fixed.
441*d14abf15SRobert Mustacchi#
442*d14abf15SRobert Mustacchi# To ensure all interfaces are able to allocate their two MSIX interrupts, the
443*d14abf15SRobert Mustacchi# workaround is to change the priority levels of specific interfaces.  Network
444*d14abf15SRobert Mustacchi# drivers are automatically assigned an interrupt priority level of 6 so
445*d14abf15SRobert Mustacchi# changing an interface's priority level to 5 is common.
446*d14abf15SRobert Mustacchi#
447*d14abf15SRobert Mustacchi# 0. First read the driver.conf man page for a background primer.
448*d14abf15SRobert Mustacchi#
449*d14abf15SRobert Mustacchi# 1. Find out the driver instance paths assigned on your system.
450*d14abf15SRobert Mustacchi#
451*d14abf15SRobert Mustacchi#  % grep bnxe /etc/path_to_inst
452*d14abf15SRobert Mustacchi#  "/pci@0,0/pci8086,2779@1/pci14e4,1650@0" 0 "bnxe"
453*d14abf15SRobert Mustacchi#  "/pci@0,0/pci8086,2779@1/pci14e4,1650@0,1" 1 "bnxe"
454*d14abf15SRobert Mustacchi#
455*d14abf15SRobert Mustacchi# 2. The name of the driver is the last portion of the path but you should
456*d14abf15SRobert Mustacchi#    probably use the most appropriate PCI ID found in /etc/driver_aliases.
457*d14abf15SRobert Mustacchi#    Depending on how the hardware is layered we've seen cases where the name
458*d14abf15SRobert Mustacchi#    identified in path_to_inst won't work.  To figure out which name to use
459*d14abf15SRobert Mustacchi#    examine the output from 'prtconf -v'.
460*d14abf15SRobert Mustacchi#
461*d14abf15SRobert Mustacchi#  % grep bnxe /etc/driver_aliases
462*d14abf15SRobert Mustacchi#  bnxe "pci14e4,164e"
463*d14abf15SRobert Mustacchi#  bnxe "pci14e4,164f"
464*d14abf15SRobert Mustacchi#  bnxe "pci14e4,1650"
465*d14abf15SRobert Mustacchi#  bnxe "pciex14e4,164e"
466*d14abf15SRobert Mustacchi#  bnxe "pciex14e4,164f"
467*d14abf15SRobert Mustacchi#  bnxe "pciex14e4,1650"
468*d14abf15SRobert Mustacchi#
469*d14abf15SRobert Mustacchi# 3. The parent of the driver is the entire path leading up to the name.
470*d14abf15SRobert Mustacchi#
471*d14abf15SRobert Mustacchi# 4. The unit-address is located after the final '@' in the path.
472*d14abf15SRobert Mustacchi#
473*d14abf15SRobert Mustacchi# 5. Therefore, changing both of the bnxe interfaces found in path_to_inst to
474*d14abf15SRobert Mustacchi#    interrupt priority 5 we would use the following config lines to bnxe.conf:
475*d14abf15SRobert Mustacchi#
476*d14abf15SRobert Mustacchi# name = "pciex14e4,1650" parent = "/pci@0,0/pci8086,2779@1" unit-address = "0" interrupt-priorities = 5;
477*d14abf15SRobert Mustacchi# name = "pciex14e4,1650" parent = "/pci@0,0/pci8086,2779@1" unit-address = "0,1" interrupt-priorities = 5;
478*d14abf15SRobert Mustacchi#
479*d14abf15SRobert Mustacchi# 6. After modifying the config either reboot the system or unplumb all
480*d14abf15SRobert Mustacchi#    interfaces and run the update_drv command.
481*d14abf15SRobert Mustacchi#
482*d14abf15SRobert Mustacchi# 7. When the system has been reconfigured and the interfaces plumbed back up
483*d14abf15SRobert Mustacchi#    you can verify the new interrupt priority settings by running the
484*d14abf15SRobert Mustacchi#    following command as root:
485*d14abf15SRobert Mustacchi#
486*d14abf15SRobert Mustacchi#  % echo "::interrupts -d" | mdb -k
487*d14abf15SRobert Mustacchi
488