1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Broadcom chips 42 * 43 * Note: the various ID values are *not* all unique ;-( 44 * 45 * Note: the presence of an ID here does *not* imply that the chip is 46 * supported. At this time, only the 5703C, 5704C, and 5704S devices 47 * used on the motherboards of certain Sun products are supported. 48 * 49 * Note: the revision-id values in the PCI revision ID register are 50 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 51 */ 52 53 #define VENDOR_ID_BROADCOM 0x14e4 54 #define VENDOR_ID_SUN 0x108e 55 56 #define DEVICE_ID_5700 0x1644 57 #define DEVICE_ID_5700x 0x0003 58 #define DEVICE_ID_5701 0x1645 59 #define DEVICE_ID_5702 0x16a6 60 #define DEVICE_ID_5702fe 0x164d 61 #define DEVICE_ID_5703C 0x1647 62 #define DEVICE_ID_5703S 0x16a7 63 #define DEVICE_ID_5703 0x16c7 64 #define DEVICE_ID_5704C 0x1648 65 #define DEVICE_ID_5704S 0x16a8 66 #define DEVICE_ID_5704 0x1649 67 #define DEVICE_ID_5705C 0x1653 68 #define DEVICE_ID_5705_2 0x1654 69 #define DEVICE_ID_5705M 0x165d 70 #define DEVICE_ID_5705MA3 0x165e 71 #define DEVICE_ID_5705F 0x166e 72 #define DEVICE_ID_5706 0x164a 73 #define DEVICE_ID_5782 0x1696 74 #define DEVICE_ID_5787 0x169b 75 #define DEVICE_ID_5787M 0x1693 76 #define DEVICE_ID_5788 0x169c 77 #define DEVICE_ID_5789 0x169d 78 #define DEVICE_ID_5751 0x1677 79 #define DEVICE_ID_5751M 0x167d 80 #define DEVICE_ID_5752 0x1600 81 #define DEVICE_ID_5752M 0x1601 82 #define DEVICE_ID_5753 0x16fd 83 #define DEVICE_ID_5754 0x167a 84 #define DEVICE_ID_5755 0x167b 85 #define DEVICE_ID_5755M 0x1673 86 #define DEVICE_ID_5721 0x1659 87 #define DEVICE_ID_5714C 0x1668 88 #define DEVICE_ID_5714S 0x1669 89 #define DEVICE_ID_5715C 0x1678 90 #define DEVICE_ID_5715S 0x1679 91 92 #define REVISION_ID_5700_B0 0x10 93 #define REVISION_ID_5700_B2 0x12 94 #define REVISION_ID_5700_B3 0x13 95 #define REVISION_ID_5700_C0 0x20 96 #define REVISION_ID_5700_C1 0x21 97 #define REVISION_ID_5700_C2 0x22 98 99 #define REVISION_ID_5701_A0 0x08 100 #define REVISION_ID_5701_A2 0x12 101 #define REVISION_ID_5701_A3 0x15 102 103 #define REVISION_ID_5702_A0 0x00 104 105 #define REVISION_ID_5703_A0 0x00 106 #define REVISION_ID_5703_A1 0x01 107 #define REVISION_ID_5703_A2 0x02 108 109 #define REVISION_ID_5704_A0 0x00 110 #define REVISION_ID_5704_A1 0x01 111 #define REVISION_ID_5704_A2 0x02 112 #define REVISION_ID_5704_A3 0x03 113 #define REVISION_ID_5704_B0 0x10 114 115 #define REVISION_ID_5705_A0 0x00 116 #define REVISION_ID_5705_A1 0x01 117 #define REVISION_ID_5705_A2 0x02 118 #define REVISION_ID_5705_A3 0x03 119 120 #define REVISION_ID_5721_A0 0x00 121 #define REVISION_ID_5721_A1 0x01 122 123 #define REVISION_ID_5751_A0 0x00 124 #define REVISION_ID_5751_A1 0x01 125 126 #define REVISION_ID_5714_A0 0x00 127 #define REVISION_ID_5714_A1 0x01 128 #define REVISION_ID_5714_A2 0xA2 129 #define REVISION_ID_5714_A3 0xA3 130 131 #define REVISION_ID_5715_A0 0x00 132 #define REVISION_ID_5715_A1 0x01 133 #define REVISION_ID_5715_A2 0xA2 134 135 #define REVISION_ID_5715S_A0 0x00 136 #define REVISION_ID_5715S_A1 0x01 137 138 #define REVISION_ID_5754_A0 0x00 139 #define REVISION_ID_5754_A1 0x01 140 141 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 142 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 143 (bgep->chipid.device == DEVICE_ID_5701) ||\ 144 (bgep->chipid.device == DEVICE_ID_5702) ||\ 145 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 146 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 147 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 148 (bgep->chipid.device == DEVICE_ID_5703) ||\ 149 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 150 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 151 (bgep->chipid.device == DEVICE_ID_5704)) 152 153 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 154 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 155 (bgep->chipid.device == DEVICE_ID_5702fe)) 156 157 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 158 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 159 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 160 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 161 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 162 (bgep->chipid.device == DEVICE_ID_5782) ||\ 163 (bgep->chipid.device == DEVICE_ID_5788) ||\ 164 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 165 (bgep->chipid.device == DEVICE_ID_5754) ||\ 166 (bgep->chipid.device == DEVICE_ID_5755) ||\ 167 (bgep->chipid.device == DEVICE_ID_5753)) 168 169 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 170 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 171 (bgep->chipid.device == DEVICE_ID_5751) ||\ 172 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 173 (bgep->chipid.device == DEVICE_ID_5752) ||\ 174 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 175 (bgep->chipid.device == DEVICE_ID_5789)) 176 177 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 178 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 179 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 180 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 181 (bgep->chipid.device == DEVICE_ID_5715S)) 182 183 /* 184 * Second section: 185 * Offsets of important registers & definitions for bits therein 186 */ 187 188 /* 189 * PCI-X registers & bits 190 */ 191 #define PCIX_CONF_COMM 0x42 192 #define PCIX_COMM_RELAXED 0x0002 193 194 /* 195 * Miscellaneous Host Control Register, in PCI config space 196 */ 197 #define PCI_CONF_BGE_MHCR 0x68 198 #define MHCR_CHIP_REV_MASK 0xffff0000 199 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 200 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 201 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 202 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 203 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 204 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 205 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 206 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 207 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 208 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 209 210 #define MHCR_CHIP_REV_5700_B0 0x71000000 211 #define MHCR_CHIP_REV_5700_B2 0x71020000 212 #define MHCR_CHIP_REV_5700_B3 0x71030000 213 #define MHCR_CHIP_REV_5700_C0 0x72000000 214 #define MHCR_CHIP_REV_5700_C1 0x72010000 215 #define MHCR_CHIP_REV_5700_C2 0x72020000 216 217 #define MHCR_CHIP_REV_5701_A0 0x00000000 218 #define MHCR_CHIP_REV_5701_A2 0x00020000 219 #define MHCR_CHIP_REV_5701_A3 0x00030000 220 #define MHCR_CHIP_REV_5701_A5 0x01050000 221 222 #define MHCR_CHIP_REV_5702_A0 0x10000000 223 #define MHCR_CHIP_REV_5702_A1 0x10010000 224 #define MHCR_CHIP_REV_5702_A2 0x10020000 225 226 #define MHCR_CHIP_REV_5703_A0 0x10000000 227 #define MHCR_CHIP_REV_5703_A1 0x10010000 228 #define MHCR_CHIP_REV_5703_A2 0x10020000 229 #define MHCR_CHIP_REV_5703_B0 0x11000000 230 #define MHCR_CHIP_REV_5703_B1 0x11010000 231 232 #define MHCR_CHIP_REV_5704_A0 0x20000000 233 #define MHCR_CHIP_REV_5704_A1 0x20010000 234 #define MHCR_CHIP_REV_5704_A2 0x20020000 235 #define MHCR_CHIP_REV_5704_A3 0x20030000 236 #define MHCR_CHIP_REV_5704_B0 0x21000000 237 238 #define MHCR_CHIP_REV_5705_A0 0x30000000 239 #define MHCR_CHIP_REV_5705_A1 0x30010000 240 #define MHCR_CHIP_REV_5705_A2 0x30020000 241 #define MHCR_CHIP_REV_5705_A3 0x30030000 242 #define MHCR_CHIP_REV_5705_A5 0x30050000 243 244 #define MHCR_CHIP_REV_5782_A0 0x30030000 245 #define MHCR_CHIP_REV_5782_A1 0x30030088 246 247 #define MHCR_CHIP_REV_5788_A1 0x30050000 248 249 #define MHCR_CHIP_REV_5751_A0 0x40000000 250 #define MHCR_CHIP_REV_5751_A1 0x40010000 251 252 #define MHCR_CHIP_REV_5721_A0 0x41000000 253 #define MHCR_CHIP_REV_5721_A1 0x41010000 254 255 #define MHCR_CHIP_REV_5714_A0 0x50000000 256 #define MHCR_CHIP_REV_5714_A1 0x90010000 257 258 #define MHCR_CHIP_REV_5715_A0 0x50000000 259 #define MHCR_CHIP_REV_5715_A1 0x90010000 260 261 #define MHCR_CHIP_REV_5715S_A0 0x50000000 262 #define MHCR_CHIP_REV_5715S_A1 0x90010000 263 264 #define MHCR_CHIP_REV_5754_A0 0xb0000000 265 #define MHCR_CHIP_REV_5754_A1 0xb0010000 266 267 #define MHCR_CHIP_REV_5787_A0 0xb0000000 268 #define MHCR_CHIP_REV_5787_A1 0xb0010000 269 #define MHCR_CHIP_REV_5787_A2 0xb0020000 270 271 #define MHCR_CHIP_REV_5755_A0 0xa0000000 272 #define MHCR_CHIP_REV_5755_A1 0xa0010000 273 274 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 275 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 276 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 277 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 278 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 279 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 280 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 281 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 282 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 283 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 284 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 285 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 286 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 287 288 289 /* 290 * PCI DMA read/write Control Register, in PCI config space 291 * 292 * Note that several fields previously defined here have been deleted 293 * as they are not implemented in the 5703/4. 294 * 295 * Note: the value of this register is critical. It is possible to 296 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 297 * by programming the wrong value. The value #defined below has been 298 * tested and shown to avoid all known problems. If it is to be changed, 299 * correct operation must be reverified on all supported platforms. 300 * 301 * In particular, we set both watermark fields to 2xCacheLineSize (128) 302 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 303 * with Tomatillo's internal pipelines, that otherwise result in stalls, 304 * repeated retries, and DTOs. 305 */ 306 #define PCI_CONF_BGE_PDRWCR 0x6c 307 #define PDRWCR_RWCMD_MASK 0xFF000000 308 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 309 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 310 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 311 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 312 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 313 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 314 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 315 316 /* 317 * These are the actual values to be put into the fields shown above 318 */ 319 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 320 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 321 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 322 #define PDRWCR_MIN_BEATS 0x00000000 323 324 #define PDRWCR_VAR_DEFAULT 0x761b0000 325 #define PDRWCR_VAR_5721 0x76180000 326 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 327 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 328 329 /* 330 * PCI State Register, in PCI config space 331 * 332 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 333 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 334 */ 335 #define PCI_CONF_BGE_PCISTATE 0x70 336 #define PCISTATE_RETRY_SAME_DMA 0x00002000 337 #define PCISTATE_FLAT_VIEW 0x00000100 338 #define PCISTATE_EXT_ROM_RETRY 0x00000040 339 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 340 #define PCISTATE_BUS_IS_32_BIT 0x00000010 341 #define PCISTATE_BUS_IS_FAST 0x00000008 342 #define PCISTATE_BUS_IS_PCI 0x00000004 343 #define PCISTATE_INTA_STATE 0x00000002 344 #define PCISTATE_FORCE_RESET 0x00000001 345 346 /* 347 * PCI Clock Control Register, in PCI config space 348 */ 349 #define PCI_CONF_BGE_CLKCTL 0x74 350 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 351 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 352 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 353 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 354 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 355 #define CLKCTL_PCIE_A0_FIX 0x00101000 356 357 /* 358 * Dual MAC Control Register, in PCI config space 359 */ 360 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 361 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 362 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 363 364 /* 365 * Register Indirect Access Address Register, 0x78 in PCI config 366 * space. Once this is set, accesses to the Register Indirect 367 * Access Data Register (0x80) refer to the register whose address 368 * is given by *this* register. This allows access to all the 369 * operating registers, while using only config space accesses. 370 * 371 * Note that the address written to the RIIAR should lie in one 372 * of the following ranges: 373 * 0x00000000 <= address < 0x00008000 (regular registers) 374 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 375 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 376 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 377 */ 378 #define PCI_CONF_BGE_RIAAR 0x78 379 #define PCI_CONF_BGE_RIADR 0x80 380 381 #define RIAAR_REGISTER_MIN 0x00000000 382 #define RIAAR_REGISTER_MAX 0x00008000 383 #define RIAAR_RX_SCRATCH_MIN 0x00030000 384 #define RIAAR_RX_SCRATCH_MAX 0x00034000 385 #define RIAAR_TX_SCRATCH_MIN 0x00034000 386 #define RIAAR_TX_SCRATCH_MAX 0x00038000 387 #define RIAAR_RXROM_MIN 0x00038000 388 #define RIAAR_RXROM_MAX 0x00038800 389 390 /* 391 * Memory Window Base Address Register, 0x7c in PCI config space 392 * Once this is set, accesses to the Memory Window Data Access Register 393 * (0x84) refer to the word of NIC-local memory whose address is given 394 * by this register. When used in this way, the whole of the address 395 * written to this register is significant. 396 * 397 * This register also provides the 32K-aligned base address for a 32K 398 * region of NIC-local memory that the host can directly address in 399 * the upper 32K of the 64K of PCI memory space allocated to the chip. 400 * In this case, the bottom 15 bits of the register are ignored. 401 * 402 * Note that the address written to the MWBAR should lie in the range 403 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 404 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 405 * memory were present, but it's only supported on the 5700, not the 406 * 5701/5703/5704. 407 */ 408 #define PCI_CONF_BGE_MWBAR 0x7c 409 #define PCI_CONF_BGE_MWDAR 0x84 410 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 411 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 412 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 413 414 /* 415 * The PCI express device control register and device status register 416 * which are only applicable on BCM5751 and BCM5721. 417 */ 418 #define PCI_CONF_DEV_CTRL 0xd8 419 #define READ_REQ_SIZE_MAX 0x5000 420 #define DEV_CTRL_NO_SNOOP 0x0800 421 #define DEV_CTRL_RELAXED 0x0010 422 423 #define PCI_CONF_DEV_STUS 0xda 424 #define DEVICE_ERROR_STUS 0xf 425 426 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 427 428 /* 429 * Where to find things in NIC-local (on-chip) memory 430 */ 431 #define NIC_MEM_SEND_RINGS 0x0100 432 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 433 #define NIC_MEM_RECV_RINGS 0x0200 434 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 435 #define NIC_MEM_STATISTICS 0x0300 436 #define NIC_MEM_STATISTICS_SIZE 0x0800 437 #define NIC_MEM_STATUS_BLOCK 0x0b00 438 #define NIC_MEM_STATUS_SIZE 0x0050 439 #define NIC_MEM_GENCOMM 0x0b50 440 441 442 /* 443 * Note: the (non-bogus) values below are appropriate for systems 444 * without external memory. They would be different on a 5700 with 445 * external memory. 446 * 447 * Note: The higher send ring addresses and the mini ring shadow 448 * buffer address are dummies - systems without external memory 449 * are limited to 4 send rings and no mini receive ring. 450 */ 451 #define NIC_MEM_SHADOW_DMA 0x2000 452 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 453 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 454 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 455 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 456 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 457 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 458 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 459 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 460 461 /* 462 * Put this in the GENCOMM port to tell the firmware not to run PXE 463 */ 464 #define T3_MAGIC_NUMBER 0x4b657654u 465 466 /* 467 * The remaining registers appear in the low 32K of regular 468 * PCI Memory Address Space 469 */ 470 471 /* 472 * All the state machine control registers below have at least a 473 * <RESET> bit and an <ENABLE> bit as defined below. Some also 474 * have an <ATTN_ENABLE> bit. 475 */ 476 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 477 #define STATE_MACHINE_ENABLE_BIT 0x00000002 478 #define STATE_MACHINE_RESET_BIT 0x00000001 479 480 #define TRANSMIT_MAC_MODE_REG 0x045c 481 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 482 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 483 #define SEND_BD_SELECTOR_MODE_REG 0x1400 484 #define SEND_BD_INITIATOR_MODE_REG 0x1800 485 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 486 487 #define RECEIVE_MAC_MODE_REG 0x0468 488 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 489 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 490 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 491 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 492 #define RCV_BD_COMPLETION_MODE_REG 0x3000 493 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 494 495 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 496 #define HOST_COALESCE_MODE_REG 0x3c00 497 #define MEMORY_ARBITER_MODE_REG 0x4000 498 #define BUFFER_MANAGER_MODE_REG 0x4400 499 #define READ_DMA_MODE_REG 0x4800 500 #define WRITE_DMA_MODE_REG 0x4c00 501 #define DMA_COMPLETION_MODE_REG 0x6400 502 503 /* 504 * Other bits in some of the above state machine control registers 505 */ 506 507 /* 508 * Transmit MAC Mode Register 509 * (TRANSMIT_MAC_MODE_REG, 0x045c) 510 */ 511 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 512 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 513 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 514 515 /* 516 * Receive MAC Mode Register 517 * (RECEIVE_MAC_MODE_REG, 0x0468) 518 */ 519 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 520 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 521 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 522 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 523 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 524 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 525 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 526 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 527 528 /* 529 * Receive BD Initiator Mode Register 530 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 531 * 532 * Each of these bits controls whether ATTN is asserted 533 * on a particular condition 534 */ 535 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 536 537 /* 538 * Receive Data & Receive BD Initiator Mode Register 539 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 540 * 541 * Each of these bits controls whether ATTN is asserted 542 * on a particular condition 543 */ 544 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 545 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 546 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 547 548 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 549 550 /* 551 * Host Coalescing Mode Control Register 552 * (HOST_COALESCE_MODE_REG, 0x3c00) 553 */ 554 #define COALESCE_64_BYTE_RINGS 12 555 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 556 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 557 #define COALESCE_CLR_TICKS_TX 0x00000400 558 #define COALESCE_CLR_TICKS_RX 0x00000200 559 #define COALESCE_32_BYTE_STATUS 0x00000100 560 #define COALESCE_64_BYTE_STATUS 0x00000080 561 #define COALESCE_NOW 0x00000008 562 563 /* 564 * Memory Arbiter Mode Register 565 * (MEMORY_ARBITER_MODE_REG, 0x4000) 566 */ 567 #define MEMORY_ARBITER_ENABLE 0x00000002 568 569 /* 570 * Buffer Manager Mode Register 571 * (BUFFER_MANAGER_MODE_REG, 0x4400) 572 * 573 * In addition to the usual error-attn common to most state machines 574 * this register has a separate bit for attn on running-low-on-mbufs 575 */ 576 #define BUFF_MGR_TEST_MODE 0x00000008 577 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 578 579 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 580 581 /* 582 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 583 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 584 * 585 * These registers each contain a 2-bit priority field, which controls 586 * the relative priority of that type of DMA (read vs. write vs. MSI), 587 * and a set of bits that control whether ATTN is asserted on each 588 * particular condition 589 */ 590 #define DMA_PRIORITY_MASK 0xc0000000 591 #define DMA_PRIORITY_SHIFT 30 592 #define ALL_DMA_ATTN_BITS 0x000003fc 593 594 /* 595 * BCM5755, 5755M, 5906, 5906M only 596 * 1 - Enable Fix. Device will send out the status block before 597 * the interrupt message 598 * 0 - Disable fix. Device will send out the interrupt message 599 * before the status block 600 */ 601 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 602 603 /* 604 * End of state machine control register definitions 605 */ 606 607 608 /* 609 * Mailbox Registers (8 bytes each, but high half unused) 610 */ 611 #define INTERRUPT_MBOX_0_REG 0x0200 612 #define INTERRUPT_MBOX_1_REG 0x0208 613 #define INTERRUPT_MBOX_2_REG 0x0210 614 #define INTERRUPT_MBOX_3_REG 0x0218 615 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 616 617 /* 618 * Ring Producer/Consumer Index (Mailbox) Registers 619 */ 620 #define RECV_STD_PROD_INDEX_REG 0x0268 621 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 622 #define RECV_MINI_PROD_INDEX_REG 0x0278 623 #define RECV_RING_CONS_INDEX_REGS 0x0280 624 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 625 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 626 627 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 628 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 629 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 630 631 /* 632 * Ethernet MAC Mode Register 633 */ 634 #define ETHERNET_MAC_MODE_REG 0x0400 635 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 636 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 637 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 638 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 639 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 640 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 641 #define ETHERNET_MODE_SEND_CFGS 0x00020000 642 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 643 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 644 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 645 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 646 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 647 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 648 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 649 #define ETHERNET_MODE_MAX_DEFER 0x00000200 650 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 651 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 652 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 653 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 654 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 655 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 656 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 657 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 658 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 659 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 660 661 /* 662 * Ethernet MAC Status & Event Registers 663 */ 664 #define ETHERNET_MAC_STATUS_REG 0x0404 665 #define ETHERNET_STATUS_MI_INT 0x00800000 666 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 667 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 668 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 669 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 670 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 671 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 672 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 673 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 674 675 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 676 #define ETHERNET_EVENT_MI_INT 0x00800000 677 #define ETHERNET_EVENT_LINK_INT 0x00001000 678 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 679 680 /* 681 * Ethernet MAC LED Control Register 682 * 683 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 684 * the external LED driver circuitry is wired up to assume that this mode 685 * will always be selected. Software must not change it! 686 */ 687 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 688 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 689 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 690 #define LED_CONTROL_LED_MODE_MASK 0x00001800 691 #define LED_CONTROL_LED_MODE_5700 0x00000000 692 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 693 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 694 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 695 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 696 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 697 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 698 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 699 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 700 #define LED_CONTROL_TRAFFIC_LED 0x00000020 701 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 702 #define LED_CONTROL_10MBPS_LED 0x00000008 703 #define LED_CONTROL_100MBPS_LED 0x00000004 704 #define LED_CONTROL_1000MBPS_LED 0x00000002 705 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 706 #define LED_CONTROL_DEFAULT 0x02000800 707 708 /* 709 * MAC Address registers 710 * 711 * These four eight-byte registers each hold one unicast address 712 * (six bytes), right justified & zero-filled on the left. 713 * They will normally all be set to the same value, as a station 714 * usually only has one h/w address. The value in register 0 is 715 * used for pause packets; any of the four can be specified for 716 * substitution into other transmitted packets if required. 717 */ 718 #define MAC_ADDRESS_0_REG 0x0410 719 #define MAC_ADDRESS_1_REG 0x0418 720 #define MAC_ADDRESS_2_REG 0x0420 721 #define MAC_ADDRESS_3_REG 0x0428 722 723 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 724 #define MAC_ADDRESS_REGS_MAX 4 725 726 /* 727 * More MAC Registers ... 728 */ 729 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 730 #define MAC_RX_MTU_SIZE_REG 0x043c 731 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 732 #define MAC_TX_LENGTHS_REG 0x0464 733 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 734 735 /* 736 * MII access registers 737 */ 738 #define MI_COMMS_REG 0x044c 739 #define MI_COMMS_START 0x20000000 740 #define MI_COMMS_READ_FAILED 0x10000000 741 #define MI_COMMS_COMMAND_MASK 0x0c000000 742 #define MI_COMMS_COMMAND_READ 0x08000000 743 #define MI_COMMS_COMMAND_WRITE 0x04000000 744 #define MI_COMMS_ADDRESS_MASK 0x03e00000 745 #define MI_COMMS_ADDRESS_SHIFT 21 746 #define MI_COMMS_REGISTER_MASK 0x001f0000 747 #define MI_COMMS_REGISTER_SHIFT 16 748 #define MI_COMMS_DATA_MASK 0x0000ffff 749 #define MI_COMMS_DATA_SHIFT 0 750 751 #define MI_STATUS_REG 0x0450 752 #define MI_STATUS_10MBPS 0x00000002 753 #define MI_STATUS_LINK 0x00000001 754 755 #define MI_MODE_REG 0x0454 756 #define MI_MODE_CLOCK_MASK 0x001f0000 757 #define MI_MODE_AUTOPOLL 0x00000010 758 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 759 #define MI_MODE_DEFAULT 0x000c0000 760 761 #define MI_AUTOPOLL_STATUS_REG 0x0458 762 #define MI_AUTOPOLL_ERROR 0x00000001 763 764 #define TRANSMIT_MAC_STATUS_REG 0x0460 765 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 766 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 767 #define TRANSMIT_STATUS_LINK_UP 0x00000008 768 #define TRANSMIT_STATUS_SENT_XON 0x00000004 769 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 770 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 771 772 #define RECEIVE_MAC_STATUS_REG 0x046c 773 #define RECEIVE_STATUS_RCVD_XON 0x00000004 774 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 775 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 776 777 /* 778 * These four-byte registers constitute a hash table for deciding 779 * whether to accept incoming multicast packets. The bits are 780 * numbered in big-endian fashion, from hash 0 => the MSB of 781 * register 0 to hash 127 => the LSB of the highest-numbered 782 * register. 783 * 784 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 785 * enabled by setting the appropriate bit in the Rx MAC mode 786 * register. Otherwise, and on all earlier chips, the table 787 * is only 128 bits (registers 0-3). 788 */ 789 #define MAC_HASH_0_REG 0x0470 790 #define MAC_HASH_1_REG 0x0474 791 #define MAC_HASH_2_REG 0x0478 792 #define MAC_HASH_3_REG 0x047c 793 #define MAC_HASH_4_REG 0x???? 794 #define MAC_HASH_5_REG 0x???? 795 #define MAC_HASH_6_REG 0x???? 796 #define MAC_HASH_7_REG 0x???? 797 #define MAC_HASH_REG(n) (0x470+4*(n)) 798 799 /* 800 * Receive Rules Registers: 16 pairs of control+mask/value pairs 801 */ 802 #define RCV_RULES_CONTROL_0_REG 0x0480 803 #define RCV_RULES_MASK_0_REG 0x0484 804 #define RCV_RULES_CONTROL_15_REG 0x04f8 805 #define RCV_RULES_MASK_15_REG 0x04fc 806 #define RCV_RULES_CONFIG_REG 0x0500 807 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 808 809 #define RECV_RULES_NUM_MAX 16 810 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 811 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 812 813 #define RECV_RULE_CTL_ENABLE 0x80000000 814 #define RECV_RULE_CTL_AND 0x40000000 815 #define RECV_RULE_CTL_P1 0x20000000 816 #define RECV_RULE_CTL_P2 0x10000000 817 #define RECV_RULE_CTL_P3 0x08000000 818 #define RECV_RULE_CTL_MASK 0x04000000 819 #define RECV_RULE_CTL_DISCARD 0x02000000 820 #define RECV_RULE_CTL_MAP 0x01000000 821 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 822 #define RECV_RULE_CTL_OP 0x00030000 823 #define RECV_RULE_CTL_OP_EQ 0x00000000 824 #define RECV_RULE_CTL_OP_NEQ 0x00010000 825 #define RECV_RULE_CTL_OP_GREAT 0x00020000 826 #define RECV_RULE_CTL_OP_LESS 0x00030000 827 #define RECV_RULE_CTL_HEADER 0x0000e000 828 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 829 #define RECV_RULE_CTL_HEADER_IP 0x00002000 830 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 831 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 832 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 833 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 834 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 835 RECV_RULE_CTL_CLASS_BITS) 836 #define RECV_RULE_CTL_OFFSET 0x000000ff 837 838 /* 839 * Receive Rules definition 840 */ 841 #define RULE_MATCH_TO_RING 2 842 /* ring that traffic will go into when recv rule matches. */ 843 /* value is between 1 and 16, not 0 and 15 */ 844 845 #define IPHEADER_PROTO_OFFSET 0x08 846 #define IPHEADER_SIP_OFFSET 0x0c 847 848 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 849 RECV_RULE_CTL_OP_EQ | \ 850 RECV_RULE_CTL_HEADER_IP | \ 851 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 852 IPHEADER_PROTO_OFFSET) 853 #define RULE_TCP_MASK_VALUE 0x00ff0006 854 #define RULE_UDP_MASK_VALUE 0x00ff0011 855 #define RULE_ICMP_MASK_VALUE 0x00ff0001 856 857 #define RULE_SIP_ADDR 0x0a000001 858 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 859 860 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 861 RECV_RULE_CTL_HEADER_IP | \ 862 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 863 IPHEADER_SIP_OFFSET) 864 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 865 866 /* 867 * 1000BaseX low-level access registers 868 */ 869 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 870 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 871 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 872 #define TX_1000BASEX_AUTONEG_REG 0x0444 873 #define RX_1000BASEX_AUTONEG_REG 0x0448 874 875 /* 876 * Autoneg code bits for the 1000BASE-X AUTONEG registers 877 */ 878 #define AUTONEG_CODE_PAUSE 0x00008000 879 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 880 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 881 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 882 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 883 #define AUTONEG_CODE_FAULT_MASK 0x00000030 884 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 885 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 886 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 887 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 888 889 /* 890 * SerDes Registers (5703S/5704S only) 891 */ 892 #define SERDES_CONTROL_REG 0x0590 893 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 894 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 895 #define SERDES_CONTROL_TX_DISABLE 0x00004000 896 #define SERDES_STATUS_REG 0x0594 897 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 898 #define SERDES_STATUS_RXSTAT 0x000000ff 899 900 /* 901 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 902 */ 903 #define STAT_IFHCOUT_OCTETS_REG 0x0800 904 #define STAT_ETHER_COLLIS_REG 0x0808 905 #define STAT_OUTXON_SENT_REG 0x080c 906 #define STAT_OUTXOFF_SENT_REG 0x0810 907 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 908 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 909 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 910 #define STAT_DOT3_DEFERED_TX_REG 0x0824 911 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 912 #define STAT_DOT3_LATE_COLLI_REG 0x0830 913 #define STAT_IFHCOUT_UPKGS_REG 0x086c 914 #define STAT_IFHCOUT_MPKGS_REG 0x0870 915 #define STAT_IFHCOUT_BPKGS_REG 0x0874 916 917 #define STAT_IFHCIN_OCTETS_REG 0x0880 918 #define STAT_ETHER_FRAGMENT_REG 0x0888 919 #define STAT_IFHCIN_UPKGS_REG 0x088c 920 #define STAT_IFHCIN_MPKGS_REG 0x0890 921 #define STAT_IFHCIN_BPKGS_REG 0x0894 922 923 #define STAT_DOT3_FCS_ERR_REG 0x0898 924 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 925 #define STAT_XON_PAUSE_RX_REG 0x08a0 926 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 927 #define STAT_MAC_CTRL_RX_REG 0x08a8 928 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 929 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 930 #define STAT_ETHER_JABBERS_REG 0x08b4 931 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 932 #define SIZE_OF_STATISTIC_REG 0x1B 933 /* 934 * Send Data Initiator Registers 935 */ 936 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 937 #define SEND_INIT_STATS_ZERO 0x00000010 938 #define SEND_INIT_STATS_FLUSH 0x00000008 939 #define SEND_INIT_STATS_CLEAR 0x00000004 940 #define SEND_INIT_STATS_FASTER 0x00000002 941 #define SEND_INIT_STATS_ENABLE 0x00000001 942 943 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 944 945 /* 946 * Send Buffer Descriptor Selector Control Registers 947 */ 948 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 949 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 950 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 951 952 /* 953 * Receive List Placement Registers 954 */ 955 #define RCV_LP_CONFIG_REG 0x2010 956 #define RCV_LP_CONFIG_DEFAULT 0x00000009 957 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 958 959 #define RCV_LP_STATS_CONTROL_REG 0x2014 960 #define RCV_LP_STATS_ZERO 0x00000010 961 #define RCV_LP_STATS_FLUSH 0x00000008 962 #define RCV_LP_STATS_CLEAR 0x00000004 963 #define RCV_LP_STATS_FASTER 0x00000002 964 #define RCV_LP_STATS_ENABLE 0x00000001 965 966 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 967 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 968 969 /* 970 * Receive Data & BD Initiator Registers 971 */ 972 #define RCV_INITIATOR_STATUS_REG 0x2404 973 974 /* 975 * Receive Buffer Descriptor Ring Control Block Registers 976 * NB: sixteen bytes (128 bits) each 977 */ 978 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 979 #define STD_RCV_BD_RING_RCB_REG 0x2450 980 #define MINI_RCV_BD_RING_RCB_REG 0x2460 981 982 /* 983 * Receive Buffer Descriptor Ring Replenish Threshold Registers 984 */ 985 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 986 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 987 #define STD_RCV_BD_REPLENISH_REG 0x2c18 988 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 989 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 990 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 991 992 /* 993 * Host Coalescing Engine Control Registers 994 */ 995 #define RCV_COALESCE_TICKS_REG 0x3c08 996 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 997 #define SEND_COALESCE_TICKS_REG 0x3c0c 998 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 999 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1000 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1001 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1002 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1003 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1004 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1005 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1006 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1007 #define RCV_COALESCE_INT_BD_REG 0x3c20 1008 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1009 #define SEND_COALESCE_INT_BD_REG 0x3c24 1010 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1011 #define STATISTICS_TICKS_REG 0x3c28 1012 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1013 #define STATISTICS_HOST_ADDR_REG 0x3c30 1014 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1015 #define STATISTICS_BASE_ADDR_REG 0x3c40 1016 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1017 #define FLOW_ATTN_REG 0x3c48 1018 1019 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1020 #define NIC_STD_RECV_INDEX_REG 0x3c54 1021 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1022 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1023 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1024 1025 /* 1026 * Mbuf Pool Initialisation & Watermark Registers 1027 * 1028 * There are some conflicts in the PRM; compare the recommendations 1029 * on pp. 115, 236, and 339. The values here were recommended by 1030 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1031 */ 1032 #define BUFFER_MANAGER_STATUS_REG 0x4404 1033 #define MBUF_POOL_BASE_REG 0x4408 1034 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1035 #define MBUF_POOL_BASE_5721 0x00010000 1036 #define MBUF_POOL_BASE_5704 0x00010000 1037 #define MBUF_POOL_BASE_5705 0x00010000 1038 #define MBUF_POOL_LENGTH_REG 0x440c 1039 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1040 #define MBUF_POOL_LENGTH_5704 0x00010000 1041 #define MBUF_POOL_LENGTH_5705 0x00008000 1042 #define MBUF_POOL_LENGTH_5721 0x00008000 1043 #define RDMA_MBUF_LOWAT_REG 0x4410 1044 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1045 #define RDMA_MBUF_LOWAT_5705 0x00000000 1046 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1047 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1048 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1049 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1050 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1051 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1052 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1053 #define MBUF_HIWAT_REG 0x4418 1054 #define MBUF_HIWAT_DEFAULT 0x00000060 1055 #define MBUF_HIWAT_5705 0x00000060 1056 #define MBUF_HIWAT_JUMBO 0x0000017c 1057 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1058 1059 /* 1060 * DMA Descriptor Pool Initialisation & Watermark Registers 1061 */ 1062 #define DMAD_POOL_BASE_REG 0x442c 1063 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1064 #define DMAD_POOL_LENGTH_REG 0x4430 1065 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1066 #define DMAD_POOL_LOWAT_REG 0x4434 1067 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1068 #define DMAD_POOL_HIWAT_REG 0x4438 1069 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1070 1071 /* 1072 * More threshold/watermark registers ... 1073 */ 1074 #define RECV_FLOW_THRESHOLD_REG 0x4458 1075 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1076 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1077 1078 /* 1079 * Read/Write DMA Status Registers 1080 */ 1081 #define READ_DMA_STATUS_REG 0x4804 1082 #define WRITE_DMA_STATUS_REG 0x4c04 1083 1084 /* 1085 * RX/TX RISC Registers 1086 */ 1087 #define RX_RISC_MODE_REG 0x5000 1088 #define RX_RISC_STATE_REG 0x5004 1089 #define RX_RISC_PC_REG 0x501c 1090 #define TX_RISC_MODE_REG 0x5400 1091 #define TX_RISC_STATE_REG 0x5404 1092 #define TX_RISC_PC_REG 0x541c 1093 1094 #define FTQ_RESET_REG 0x5c00 1095 1096 #define MSI_MODE_REG 0x6000 1097 #define MSI_PRI_HIGHEST 0xc0000000 1098 #define MSI_MSI_ENABLE 0x00000002 1099 #define MSI_ERROR_ATTENTION 0x0000001c 1100 1101 #define MSI_STATUS_REG 0x6004 1102 1103 #define MODE_CONTROL_REG 0x6800 1104 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1105 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1106 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1107 #define MODE_INT_ON_DMA_ATTN 0x08000000 1108 #define MODE_INT_ON_MAC_ATTN 0x04000000 1109 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1110 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1111 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1112 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1113 #define MODE_HOST_SEND_BDS 0x00020000 1114 #define MODE_HOST_STACK_UP 0x00010000 1115 #define MODE_FORCE_32_BIT_PCI 0x00008000 1116 #define MODE_NO_INT_ON_RECV 0x00004000 1117 #define MODE_NO_INT_ON_SEND 0x00002000 1118 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1119 #define MODE_NO_CRC 0x00000400 1120 #define MODE_NO_FRAME_CRACKING 0x00000200 1121 #define MODE_WORD_SWAP_FRAME 0x00000020 1122 #define MODE_BYTE_SWAP_FRAME 0x00000010 1123 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1124 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1125 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1126 1127 /* 1128 * Miscellaneous Configuration Register 1129 * 1130 * This contains various bits relating to power control (which differ 1131 * among different members of the chip family), but the important bits 1132 * for our purposes are the RESET bit and the Timer Prescaler field. 1133 * 1134 * The RESET bit in this register serves to reset the whole chip, even 1135 * including the PCI interface(!) Once it's set, the chip will not 1136 * respond to ANY accesses -- not even CONFIG space -- until the reset 1137 * completes internally. According to the PRM, this should take less 1138 * than 100us. Any access during this period will get a bus error. 1139 * 1140 * The Timer Prescaler field must be programmed so that the timer period 1141 * is as near as possible to 1us. The value in this field should be 1142 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1143 * the Core Clock should always be 66MHz (independently of the bus speed, 1144 * at least for PCI rather than PCI-X), so this register must be set to 1145 * the value 0x82 ((66-1) << 1). 1146 */ 1147 #define CORE_CLOCK_MHZ 66 1148 #define MISC_CONFIG_REG 0x6804 1149 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1150 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1151 #define MISC_CONFIG_POWERDOWN 0x00100000 1152 #define MISC_CONFIG_POWER_STATE 0x00060000 1153 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1154 #define MISC_CONFIG_RESET_BIT 0x00000001 1155 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1156 1157 /* 1158 * Miscellaneous Local Control Register (MLCR) 1159 */ 1160 #define MISC_LOCAL_CONTROL_REG 0x6808 1161 #define MLCR_PCI_CTRL_SELECT 0x10000000 1162 #define MLCR_LEGACY_PCI_MODE 0x08000000 1163 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1164 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1165 #define MLCR_SSRAM_TYPE 0x00400000 1166 #define MLCR_BANK_SELECT 0x00200000 1167 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1168 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1169 1170 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1171 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1172 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1173 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1174 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1175 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1176 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1177 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1178 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1179 1180 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1181 #define MLCR_SET_INT 0x00000004 /* W/O */ 1182 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1183 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1184 1185 /* 1186 * This value defines all GPIO bits as INPUTS, but sets their default 1187 * values as outputs to HIGH, on the assumption that external circuits 1188 * (if any) will probably be active-LOW with passive pullups. 1189 * 1190 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1191 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1192 * enable writing. Otherwise, the SEEPROM is protected. 1193 */ 1194 #define MLCR_DEFAULT 0x0101c000 1195 #define MLCR_DEFAULT_5714 0x1901c000 1196 1197 /* 1198 * Serial EEPROM Data/Address Registers (auto-access mode) 1199 */ 1200 #define SERIAL_EEPROM_DATA_REG 0x683c 1201 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1202 #define SEEPROM_ACCESS_READ 0x80000000 1203 #define SEEPROM_ACCESS_WRITE 0x00000000 1204 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1205 #define SEEPROM_ACCESS_RESET 0x20000000 1206 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1207 #define SEEPROM_ACCESS_START 0x02000000 1208 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1209 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1210 1211 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1212 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1213 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1214 1215 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1216 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1217 1218 /* 1219 * "Linearised" address mask, treating multiple devices as consecutive 1220 */ 1221 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1222 1223 /* 1224 * Non-Volatile Memory Interface Registers 1225 * Note: on chips that support the flash interface (5702+), flash is the 1226 * default and the legacy seeprom interface must be explicitly enabled 1227 * if required. On older chips (5700/01), SEEPROM is the default (and 1228 * only) non-volatile memory available, and these registers don't exist! 1229 */ 1230 #define NVM_FLASH_CMD_REG 0x7000 1231 #define NVM_FLASH_CMD_LAST 0x00000100 1232 #define NVM_FLASH_CMD_FIRST 0x00000080 1233 #define NVM_FLASH_CMD_RD 0x00000000 1234 #define NVM_FLASH_CMD_WR 0x00000020 1235 #define NVM_FLASH_CMD_DOIT 0x00000010 1236 #define NVM_FLASH_CMD_DONE 0x00000008 1237 1238 #define NVM_FLASH_WRITE_REG 0x7008 1239 #define NVM_FLASH_READ_REG 0x7010 1240 1241 #define NVM_FLASH_ADDR_REG 0x700c 1242 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1243 1244 #define NVM_CONFIG1_REG 0x7014 1245 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1246 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1247 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1248 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1249 #define NVM_CFG1_FLASH_MODE 0x00000001 1250 1251 #define NVM_SW_ARBITRATION_REG 0x7020 1252 #define NVM_READ_REQ3 0X00008000 1253 #define NVM_READ_REQ2 0X00004000 1254 #define NVM_READ_REQ1 0X00002000 1255 #define NVM_READ_REQ0 0X00001000 1256 #define NVM_WON_REQ3 0X00000800 1257 #define NVM_WON_REQ2 0X00000400 1258 #define NVM_WON_REQ1 0X00000200 1259 #define NVM_WON_REQ0 0X00000100 1260 #define NVM_RESET_REQ3 0X00000080 1261 #define NVM_RESET_REQ2 0X00000040 1262 #define NVM_RESET_REQ1 0X00000020 1263 #define NVM_RESET_REQ0 0X00000010 1264 #define NVM_SET_REQ3 0X00000008 1265 #define NVM_SET_REQ2 0X00000004 1266 #define NVM_SET_REQ1 0X00000002 1267 #define NVM_SET_REQ0 0X00000001 1268 1269 /* 1270 * NVM access register 1271 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1272 * and BCM5715 only. 1273 */ 1274 #define NVM_ACCESS_REG 0X7024 1275 #define NVM_WRITE_ENABLE 0X00000002 1276 #define NVM_ACCESS_ENABLE 0X00000001 1277 1278 /* 1279 * TLP Control Register 1280 * Applicable to BCM5721 and BCM5751 only 1281 */ 1282 #define TLP_CONTROL_REG 0x7c00 1283 #define TLP_DATA_FIFO_PROTECT 0x02000000 1284 1285 /* 1286 * PHY Test Control Register 1287 * Applicable to BCM5721 and BCM5751 only 1288 */ 1289 #define PHY_TEST_CTRL_REG 0x7e2c 1290 #define PHY_PCIE_SCRAM_MODE 0x20 1291 #define PHY_PCIE_LTASS_MODE 0x40 1292 1293 /* 1294 * The internal firmware expects a certain layout of the non-volatile 1295 * memory (if fitted), and will check for it during startup, and use the 1296 * contents to initialise various internal parameters if it looks good. 1297 * 1298 * The offsets and field definitions below refer to where to find some 1299 * important values, and how to interpret them ... 1300 */ 1301 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1302 1303 /* 1304 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1305 */ 1306 1307 #define MII_AN_LPNXTPG 8 1308 #define MII_1000BASE_T_CONTROL 9 1309 #define MII_1000BASE_T_STATUS 10 1310 #define MII_IEEE_EXT_STATUS 15 1311 1312 /* 1313 * New bits in the MII_CONTROL register 1314 */ 1315 #define MII_CONTROL_1000MB 0x0040 1316 1317 /* 1318 * New bits in the MII_AN_ADVERT register 1319 */ 1320 #define MII_ABILITY_ASYM_PAUSE 0x0800 1321 #define MII_ABILITY_PAUSE 0x0400 1322 1323 /* 1324 * Values for the <selector> field of the MII_AN_ADVERT register 1325 */ 1326 #define MII_AN_SELECTOR_8023 0x0001 1327 1328 /* 1329 * Bits in the MII_1000BASE_T_CONTROL register 1330 * 1331 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1332 * (otherwise, roles are automatically negotiated). When this bit is set, 1333 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1334 */ 1335 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1336 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1337 #define MII_1000BT_CTL_ADV_FDX 0x0200 1338 #define MII_1000BT_CTL_ADV_HDX 0x0100 1339 1340 /* 1341 * Bits in the MII_1000BASE_T_STATUS register 1342 */ 1343 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1344 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1345 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1346 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1347 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1348 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1349 1350 /* 1351 * Vendor-specific MII registers 1352 */ 1353 #define MII_EXT_CONTROL MII_VENDOR(0) 1354 #define MII_EXT_STATUS MII_VENDOR(1) 1355 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1356 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1357 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1358 #define MII_AUX_CONTROL MII_VENDOR(8) 1359 #define MII_AUX_STATUS MII_VENDOR(9) 1360 #define MII_INTR_STATUS MII_VENDOR(10) 1361 #define MII_INTR_MASK MII_VENDOR(11) 1362 #define MII_HCD_STATUS MII_VENDOR(13) 1363 1364 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1365 1366 /* 1367 * Bits in the MII_EXT_CONTROL register 1368 */ 1369 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1370 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1371 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1372 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1373 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1374 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1375 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1376 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1377 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1378 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1379 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1380 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1381 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1382 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1383 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1384 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1385 1386 /* 1387 * Bits in the MII_EXT_STATUS register 1388 */ 1389 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1390 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1391 #define MII_EXT_STAT_MDIX_STATE 0x2000 1392 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1393 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1394 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1395 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1396 #define MII_EXT_STAT_LINK_STATUS 0x0100 1397 #define MII_EXT_STAT_CRC_ERROR 0x0080 1398 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1399 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1400 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1401 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1402 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1403 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1404 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1405 1406 /* 1407 * The AUX CONTROL register is seriously weird! 1408 * 1409 * It hides (up to) eight 'shadow' registers. When writing, which one 1410 * of them is written is determined by the low-order bits of the data 1411 * written(!), but when reading, which one is read is determined by the 1412 * value previously written to (part of) one of the shadow registers!!! 1413 */ 1414 1415 /* 1416 * Shadow register numbers 1417 */ 1418 #define MII_AUX_CTRL_NORMAL 0 1419 #define MII_AUX_CTRL_10BASE_T 1 1420 #define MII_AUX_CTRL_POWER 2 1421 #define MII_AUX_CTRL_TEST_1 4 1422 #define MII_AUX_CTRL_MISC 7 1423 1424 /* 1425 * Selected bits in some of the shadow registers ... 1426 */ 1427 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1428 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1429 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1430 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1431 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1432 1433 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1434 1435 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1436 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1437 1438 /* 1439 * Write this value to the AUX control register 1440 * to select which shadow register will be read 1441 */ 1442 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1443 1444 /* 1445 * Bits in the MII_AUX_STATUS register 1446 */ 1447 #define MII_AUX_STATUS_MODE_MASK 0x0700 1448 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1449 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1450 #define MII_AUX_STATUS_MODE_100_F 0x0500 1451 #define MII_AUX_STATUS_MODE_100_4 0x0400 1452 #define MII_AUX_STATUS_MODE_100_H 0x0300 1453 #define MII_AUX_STATUS_MODE_10_F 0x0200 1454 #define MII_AUX_STATUS_MODE_10_H 0x0100 1455 #define MII_AUX_STATUS_MODE_NONE 0x0000 1456 #define MII_AUX_STATUS_MODE_SHIFT 8 1457 1458 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1459 #define MII_AUX_STATUS_REM_FAULT 0x0040 1460 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1461 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1462 1463 #define MII_AUX_STATUS_LINKUP 0x0004 1464 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1465 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1466 1467 /* 1468 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1469 */ 1470 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1471 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1472 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1473 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1474 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1475 1476 1477 /* 1478 * Third section: 1479 * Hardware-defined data structures 1480 * 1481 * Note that the chip is naturally BIG-endian, so, for a big-endian 1482 * host, the structures defined below match those described in the PRM. 1483 * For little-endian hosts, some structures have to be swapped around. 1484 */ 1485 1486 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1487 #error Host endianness not defined 1488 #endif 1489 1490 /* 1491 * Architectural constants: absolute maximum numbers of each type of ring 1492 */ 1493 #ifdef BGE_EXT_MEM 1494 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1495 #else 1496 #define BGE_SEND_RINGS_MAX 4 1497 #endif 1498 #define BGE_SEND_RINGS_MAX_5705 1 1499 #define BGE_RECV_RINGS_MAX 16 1500 #define BGE_RECV_RINGS_MAX_5705 1 1501 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1502 /* only with ext mem) */ 1503 1504 #define BGE_SEND_SLOTS_MAX 512 1505 #define BGE_STD_SLOTS_MAX 512 1506 #define BGE_JUMBO_SLOTS_MAX 256 1507 #define BGE_MINI_SLOTS_MAX 1024 1508 #define BGE_RECV_SLOTS_MAX 2048 1509 #define BGE_RECV_SLOTS_5705 512 1510 #define BGE_RECV_SLOTS_5782 512 1511 #define BGE_RECV_SLOTS_5721 512 1512 1513 /* 1514 * Hardware-defined Ring Control Block 1515 */ 1516 typedef struct { 1517 uint64_t host_ring_addr; 1518 #ifdef _BIG_ENDIAN 1519 uint16_t max_len; 1520 uint16_t flags; 1521 uint32_t nic_ring_addr; 1522 #else 1523 uint32_t nic_ring_addr; 1524 uint16_t flags; 1525 uint16_t max_len; 1526 #endif /* _BIG_ENDIAN */ 1527 } bge_rcb_t; 1528 1529 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1530 #define RCB_FLAG_RING_DISABLED 0x0002 1531 1532 /* 1533 * Hardware-defined Send Buffer Descriptor 1534 */ 1535 typedef struct { 1536 uint64_t host_buf_addr; 1537 #ifdef _BIG_ENDIAN 1538 uint16_t len; 1539 uint16_t flags; 1540 uint16_t reserved; 1541 uint16_t vlan_tci; 1542 #else 1543 uint16_t vlan_tci; 1544 uint16_t reserved; 1545 uint16_t flags; 1546 uint16_t len; 1547 #endif /* _BIG_ENDIAN */ 1548 } bge_sbd_t; 1549 1550 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1551 #define SBD_FLAG_IP_CKSUM 0x0002 1552 #define SBD_FLAG_PACKET_END 0x0004 1553 #define SBD_FLAG_IP_FRAG 0x0008 1554 #define SBD_FLAG_IP_FRAG_END 0x0010 1555 1556 #define SBD_FLAG_VLAN_TAG 0x0040 1557 #define SBD_FLAG_COAL_NOW 0x0080 1558 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1559 #define SBD_FLAG_CPU_POST_DMA 0x0200 1560 1561 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1562 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1563 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1564 1565 /* 1566 * Hardware-defined Receive Buffer Descriptor 1567 */ 1568 typedef struct { 1569 uint64_t host_buf_addr; 1570 #ifdef _BIG_ENDIAN 1571 uint16_t index; 1572 uint16_t len; 1573 uint16_t type; 1574 uint16_t flags; 1575 uint16_t ip_cksum; 1576 uint16_t tcp_udp_cksum; 1577 uint16_t error_flag; 1578 uint16_t vlan_tci; 1579 uint32_t reserved; 1580 uint32_t opaque; 1581 #else 1582 uint16_t flags; 1583 uint16_t type; 1584 uint16_t len; 1585 uint16_t index; 1586 uint16_t vlan_tci; 1587 uint16_t error_flag; 1588 uint16_t tcp_udp_cksum; 1589 uint16_t ip_cksum; 1590 uint32_t opaque; 1591 uint32_t reserved; 1592 #endif /* _BIG_ENDIAN */ 1593 } bge_rbd_t; 1594 1595 #define RBD_FLAG_STD_RING 0x0000 1596 #define RBD_FLAG_PACKET_END 0x0004 1597 1598 #define RBD_FLAG_JUMBO_RING 0x0020 1599 #define RBD_FLAG_VLAN_TAG 0x0040 1600 1601 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1602 #define RBD_FLAG_MINI_RING 0x0800 1603 #define RBD_FLAG_IP_CHECKSUM 0x1000 1604 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1605 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1606 1607 #define RBD_FLAG_DEFAULT 0x0000 1608 1609 #define RBD_ERROR_BAD_CRC 0x00010000 1610 #define RBD_ERROR_COLL_DETECT 0x00020000 1611 #define RBD_ERROR_LINK_LOST 0x00040000 1612 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1613 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1614 #define RBD_ERROR_MAC_ABORT 0x00200000 1615 #define RBD_ERROR_LEN_LESS_64 0x00400000 1616 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1617 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1618 1619 /* 1620 * Hardware-defined Status Block,Size of status block 1621 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1622 * alignment.For BCM5705/5788/5721/5751/5752/5714 1623 * and 5715,there is only 1 recv and send ring index,but 1624 * driver defined 16 indexs here,please pay attention only 1625 * one ring is enabled in these chipsets. 1626 */ 1627 typedef struct { 1628 uint64_t flags_n_tag; 1629 uint16_t buff_cons_index[4]; 1630 struct { 1631 #ifdef _BIG_ENDIAN 1632 uint16_t send_cons_index; 1633 uint16_t recv_prod_index; 1634 #else 1635 uint16_t recv_prod_index; 1636 uint16_t send_cons_index; 1637 #endif /* _BIG_ENDIAN */ 1638 } index[16]; 1639 } bge_status_t; 1640 1641 /* 1642 * Hardware-defined Receive BD Rule 1643 */ 1644 typedef struct { 1645 uint32_t control; 1646 uint32_t mask_value; 1647 } bge_recv_rule_t; 1648 1649 /* 1650 * Indexes into the <buff_cons_index> array 1651 */ 1652 #ifdef _BIG_ENDIAN 1653 #define STATUS_STD_BUFF_CONS_INDEX 0 1654 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1655 #define STATUS_MINI_BUFF_CONS_INDEX 3 1656 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1657 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1658 #else 1659 #define STATUS_STD_BUFF_CONS_INDEX 3 1660 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1661 #define STATUS_MINI_BUFF_CONS_INDEX 0 1662 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1663 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1664 #endif /* _BIG_ENDIAN */ 1665 1666 /* 1667 * Bits in the <flags_n_tag> word 1668 */ 1669 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1670 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1671 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1672 #define STATUS_TAG_MASK 0x00000000000000FFull 1673 1674 /* 1675 * The tag from the status block is fed back to Interrupt Mailbox 0 1676 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1677 * lets the chip know what updates have been processed, so it can 1678 * reassert its interrupt if more updates have occurred since. 1679 * 1680 * These macros extract the tag from the <flags_n_tag> word, shift 1681 * it to the proper position in the Mailbox register, and provide 1682 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1683 * or enable interrupts 1684 */ 1685 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1686 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1687 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1688 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1689 1690 /* 1691 * Hardware-defined Statistics Block Offsets 1692 * 1693 * These are given in the manual as addresses in NIC memory, starting 1694 * from the NIC statistics area base address of 0x300; but here we 1695 * convert them into indexes into an array of (uint64_t)s, so we can 1696 * use them directly for accessing the copy of the statistics block 1697 * that the chip DMAs into main memory ... 1698 */ 1699 1700 #define KS_BASE 0x300 1701 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1702 1703 typedef enum { 1704 KS_ifHCInOctets = KS_ADDR(0x400), 1705 KS_etherStatsFragments = KS_ADDR(0x410), 1706 KS_ifHCInUcastPkts, 1707 KS_ifHCInMulticastPkts, 1708 KS_ifHCInBroadcastPkts, 1709 KS_dot3StatsFCSErrors, 1710 KS_dot3StatsAlignmentErrors, 1711 KS_xonPauseFramesReceived, 1712 KS_xoffPauseFramesReceived, 1713 KS_macControlFramesReceived, 1714 KS_xoffStateEntered, 1715 KS_dot3StatsFrameTooLongs, 1716 KS_etherStatsJabbers, 1717 KS_etherStatsUndersizePkts, 1718 KS_inRangeLengthError, 1719 KS_outRangeLengthError, 1720 KS_etherStatsPkts64Octets, 1721 KS_etherStatsPkts65to127Octets, 1722 KS_etherStatsPkts128to255Octets, 1723 KS_etherStatsPkts256to511Octets, 1724 KS_etherStatsPkts512to1023Octets, 1725 KS_etherStatsPkts1024to1518Octets, 1726 KS_etherStatsPkts1519to2047Octets, 1727 KS_etherStatsPkts2048to4095Octets, 1728 KS_etherStatsPkts4096to8191Octets, 1729 KS_etherStatsPkts8192to9022Octets, 1730 1731 KS_ifHCOutOctets = KS_ADDR(0x600), 1732 KS_etherStatsCollisions = KS_ADDR(0x610), 1733 KS_outXonSent, 1734 KS_outXoffSent, 1735 KS_flowControlDone, 1736 KS_dot3StatsInternalMacTransmitErrors, 1737 KS_dot3StatsSingleCollisionFrames, 1738 KS_dot3StatsMultipleCollisionFrames, 1739 KS_dot3StatsDeferredTransmissions, 1740 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1741 KS_dot3StatsLateCollisions, 1742 KS_dot3Collided2Times, 1743 KS_dot3Collided3Times, 1744 KS_dot3Collided4Times, 1745 KS_dot3Collided5Times, 1746 KS_dot3Collided6Times, 1747 KS_dot3Collided7Times, 1748 KS_dot3Collided8Times, 1749 KS_dot3Collided9Times, 1750 KS_dot3Collided10Times, 1751 KS_dot3Collided11Times, 1752 KS_dot3Collided12Times, 1753 KS_dot3Collided13Times, 1754 KS_dot3Collided14Times, 1755 KS_dot3Collided15Times, 1756 KS_ifHCOutUcastPkts, 1757 KS_ifHCOutMulticastPkts, 1758 KS_ifHCOutBroadcastPkts, 1759 KS_dot3StatsCarrierSenseErrors, 1760 KS_ifOutDiscards, 1761 KS_ifOutErrors, 1762 1763 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1764 KS_COSIfHCInPkts_2, 1765 KS_COSIfHCInPkts_3, 1766 KS_COSIfHCInPkts_4, 1767 KS_COSIfHCInPkts_5, 1768 KS_COSIfHCInPkts_6, 1769 KS_COSIfHCInPkts_7, 1770 KS_COSIfHCInPkts_8, 1771 KS_COSIfHCInPkts_9, 1772 KS_COSIfHCInPkts_10, 1773 KS_COSIfHCInPkts_11, 1774 KS_COSIfHCInPkts_12, 1775 KS_COSIfHCInPkts_13, 1776 KS_COSIfHCInPkts_14, 1777 KS_COSIfHCInPkts_15, 1778 KS_COSIfHCInPkts_16, 1779 KS_COSFramesDroppedDueToFilters, 1780 KS_nicDmaWriteQueueFull, 1781 KS_nicDmaWriteHighPriQueueFull, 1782 KS_nicNoMoreRxBDs, 1783 KS_ifInDiscards, 1784 KS_ifInErrors, 1785 KS_nicRecvThresholdHit, 1786 1787 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1788 KS_COSIfHCOutPkts_2, 1789 KS_COSIfHCOutPkts_3, 1790 KS_COSIfHCOutPkts_4, 1791 KS_COSIfHCOutPkts_5, 1792 KS_COSIfHCOutPkts_6, 1793 KS_COSIfHCOutPkts_7, 1794 KS_COSIfHCOutPkts_8, 1795 KS_COSIfHCOutPkts_9, 1796 KS_COSIfHCOutPkts_10, 1797 KS_COSIfHCOutPkts_11, 1798 KS_COSIfHCOutPkts_12, 1799 KS_COSIfHCOutPkts_13, 1800 KS_COSIfHCOutPkts_14, 1801 KS_COSIfHCOutPkts_15, 1802 KS_COSIfHCOutPkts_16, 1803 KS_nicDmaReadQueueFull, 1804 KS_nicDmaReadHighPriQueueFull, 1805 KS_nicSendDataCompQueueFull, 1806 KS_nicRingSetSendProdIndex, 1807 KS_nicRingStatusUpdate, 1808 KS_nicInterrupts, 1809 KS_nicAvoidedInterrupts, 1810 KS_nicSendThresholdHit, 1811 1812 KS_STATS_SIZE = KS_ADDR(0xb00) 1813 } bge_stats_offset_t; 1814 1815 /* 1816 * Hardware-defined Statistics Block 1817 * 1818 * Another view of the statistic block, as a array and a structure ... 1819 */ 1820 1821 typedef union { 1822 uint64_t a[KS_STATS_SIZE]; 1823 struct { 1824 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1825 1826 uint64_t ifHCInOctets; /* 0x0400 */ 1827 uint64_t spare2[1]; 1828 uint64_t etherStatsFragments; 1829 uint64_t ifHCInUcastPkts; 1830 uint64_t ifHCInMulticastPkts; 1831 uint64_t ifHCInBroadcastPkts; 1832 uint64_t dot3StatsFCSErrors; 1833 uint64_t dot3StatsAlignmentErrors; 1834 uint64_t xonPauseFramesReceived; 1835 uint64_t xoffPauseFramesReceived; 1836 uint64_t macControlFramesReceived; 1837 uint64_t xoffStateEntered; 1838 uint64_t dot3StatsFrameTooLongs; 1839 uint64_t etherStatsJabbers; 1840 uint64_t etherStatsUndersizePkts; 1841 uint64_t inRangeLengthError; 1842 uint64_t outRangeLengthError; 1843 uint64_t etherStatsPkts64Octets; 1844 uint64_t etherStatsPkts65to127Octets; 1845 uint64_t etherStatsPkts128to255Octets; 1846 uint64_t etherStatsPkts256to511Octets; 1847 uint64_t etherStatsPkts512to1023Octets; 1848 uint64_t etherStatsPkts1024to1518Octets; 1849 uint64_t etherStatsPkts1519to2047Octets; 1850 uint64_t etherStatsPkts2048to4095Octets; 1851 uint64_t etherStatsPkts4096to8191Octets; 1852 uint64_t etherStatsPkts8192to9022Octets; 1853 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1854 1855 uint64_t ifHCOutOctets; /* 0x0600 */ 1856 uint64_t spare4[1]; 1857 uint64_t etherStatsCollisions; 1858 uint64_t outXonSent; 1859 uint64_t outXoffSent; 1860 uint64_t flowControlDone; 1861 uint64_t dot3StatsInternalMacTransmitErrors; 1862 uint64_t dot3StatsSingleCollisionFrames; 1863 uint64_t dot3StatsMultipleCollisionFrames; 1864 uint64_t dot3StatsDeferredTransmissions; 1865 uint64_t spare5[1]; 1866 uint64_t dot3StatsExcessiveCollisions; 1867 uint64_t dot3StatsLateCollisions; 1868 uint64_t dot3Collided2Times; 1869 uint64_t dot3Collided3Times; 1870 uint64_t dot3Collided4Times; 1871 uint64_t dot3Collided5Times; 1872 uint64_t dot3Collided6Times; 1873 uint64_t dot3Collided7Times; 1874 uint64_t dot3Collided8Times; 1875 uint64_t dot3Collided9Times; 1876 uint64_t dot3Collided10Times; 1877 uint64_t dot3Collided11Times; 1878 uint64_t dot3Collided12Times; 1879 uint64_t dot3Collided13Times; 1880 uint64_t dot3Collided14Times; 1881 uint64_t dot3Collided15Times; 1882 uint64_t ifHCOutUcastPkts; 1883 uint64_t ifHCOutMulticastPkts; 1884 uint64_t ifHCOutBroadcastPkts; 1885 uint64_t dot3StatsCarrierSenseErrors; 1886 uint64_t ifOutDiscards; 1887 uint64_t ifOutErrors; 1888 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1889 1890 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1891 uint64_t COSFramesDroppedDueToFilters; 1892 uint64_t nicDmaWriteQueueFull; 1893 uint64_t nicDmaWriteHighPriQueueFull; 1894 uint64_t nicNoMoreRxBDs; 1895 uint64_t ifInDiscards; 1896 uint64_t ifInErrors; 1897 uint64_t nicRecvThresholdHit; 1898 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1899 1900 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1901 uint64_t nicDmaReadQueueFull; 1902 uint64_t nicDmaReadHighPriQueueFull; 1903 uint64_t nicSendDataCompQueueFull; 1904 uint64_t nicRingSetSendProdIndex; 1905 uint64_t nicRingStatusUpdate; 1906 uint64_t nicInterrupts; 1907 uint64_t nicAvoidedInterrupts; 1908 uint64_t nicSendThresholdHit; 1909 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1910 } s; 1911 } bge_statistics_t; 1912 1913 #define KS_STAT_REG_SIZE (0x1B) 1914 #define KS_STAT_REG_BASE (0x800) 1915 1916 typedef struct { 1917 uint32_t ifHCOutOctets; 1918 uint32_t etherStatsCollisions; 1919 uint32_t outXonSent; 1920 uint32_t outXoffSent; 1921 uint32_t dot3StatsInternalMacTransmitErrors; 1922 uint32_t dot3StatsSingleCollisionFrames; 1923 uint32_t dot3StatsMultipleCollisionFrames; 1924 uint32_t dot3StatsDeferredTransmissions; 1925 uint32_t dot3StatsExcessiveCollisions; 1926 uint32_t dot3StatsLateCollisions; 1927 uint32_t ifHCOutUcastPkts; 1928 uint32_t ifHCOutMulticastPkts; 1929 uint32_t ifHCOutBroadcastPkts; 1930 uint32_t ifHCInOctets; 1931 uint32_t etherStatsFragments; 1932 uint32_t ifHCInUcastPkts; 1933 uint32_t ifHCInMulticastPkts; 1934 uint32_t ifHCInBroadcastPkts; 1935 uint32_t dot3StatsFCSErrors; 1936 uint32_t dot3StatsAlignmentErrors; 1937 uint32_t xonPauseFramesReceived; 1938 uint32_t xoffPauseFramesReceived; 1939 uint32_t macControlFramesReceived; 1940 uint32_t xoffStateEntered; 1941 uint32_t dot3StatsFrameTooLongs; 1942 uint32_t etherStatsJabbers; 1943 uint32_t etherStatsUndersizePkts; 1944 } bge_statistics_reg_t; 1945 1946 1947 #ifdef BGE_IPMI_ASF 1948 1949 /* 1950 * Device internal memory entries 1951 */ 1952 1953 #define BGE_FIRMWARE_MAILBOX 0x0b50 1954 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1955 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1956 1957 1958 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1959 #define BGE_NIC_DATA_SIG 0x4b657654 1960 1961 1962 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1963 1964 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1965 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1966 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1967 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1968 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1969 1970 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1971 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1972 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1973 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1974 1975 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1976 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1977 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1978 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1979 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1980 #define BGE_NIC_CFG_MINI_PCI 0x001000 1981 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1982 #define BGE_NIC_CFG_5753_12x12 0x100000 1983 1984 1985 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1986 1987 1988 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1989 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1990 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1991 1992 1993 #define BGE_CMD_MAILBOX 0x0b78 1994 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1995 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1996 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1997 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1998 1999 2000 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2001 #define BGE_CMD_DATA_MAILBOX 0x0b80 2002 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2003 2004 #define BGE_DRV_STATE_MAILBOX 0x0c04 2005 #define BGE_DRV_STATE_START 0x00000001 2006 #define BGE_DRV_STATE_START_DONE 0x80000001 2007 #define BGE_DRV_STATE_UNLOAD 0x00000002 2008 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2009 #define BGE_DRV_STATE_WOL 0x00000003 2010 #define BGE_DRV_STATE_SUSPEND 0x00000004 2011 2012 2013 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2014 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2015 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2016 2017 2018 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2019 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2020 2021 2022 /* 2023 * RX-RISC event register 2024 */ 2025 #define RX_RISC_EVENT_REG 0x6810 2026 #define RRER_ASF_EVENT 0x4000 2027 2028 #endif /* BGE_IPMI_ASF */ 2029 2030 #ifdef __cplusplus 2031 } 2032 #endif 2033 2034 #endif /* _BGE_HW_H */ 2035