1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_BGE_HW_H 28 #define _SYS_BGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Broadcom chips 42 * 43 * Note: the various ID values are *not* all unique ;-( 44 * 45 * Note: the presence of an ID here does *not* imply that the chip is 46 * supported. At this time, only the 5703C, 5704C, and 5704S devices 47 * used on the motherboards of certain Sun products are supported. 48 * 49 * Note: the revision-id values in the PCI revision ID register are 50 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 51 */ 52 53 #define VENDOR_ID_BROADCOM 0x14e4 54 #define VENDOR_ID_SUN 0x108e 55 56 #define DEVICE_ID_5700 0x1644 57 #define DEVICE_ID_5700x 0x0003 58 #define DEVICE_ID_5701 0x1645 59 #define DEVICE_ID_5702 0x16a6 60 #define DEVICE_ID_5702fe 0x164d 61 #define DEVICE_ID_5703C 0x1647 62 #define DEVICE_ID_5703S 0x16a7 63 #define DEVICE_ID_5703 0x16c7 64 #define DEVICE_ID_5704C 0x1648 65 #define DEVICE_ID_5704S 0x16a8 66 #define DEVICE_ID_5704 0x1649 67 #define DEVICE_ID_5705C 0x1653 68 #define DEVICE_ID_5705_2 0x1654 69 #define DEVICE_ID_5705M 0x165d 70 #define DEVICE_ID_5705MA3 0x165e 71 #define DEVICE_ID_5705F 0x166e 72 #define DEVICE_ID_5706 0x164a 73 #define DEVICE_ID_5782 0x1696 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5721 0x1659 81 #define DEVICE_ID_5714C 0x1668 82 #define DEVICE_ID_5714S 0x1669 83 #define DEVICE_ID_5715C 0x1678 84 #define DEVICE_ID_5715S 0x1679 85 86 #define REVISION_ID_5700_B0 0x10 87 #define REVISION_ID_5700_B2 0x12 88 #define REVISION_ID_5700_B3 0x13 89 #define REVISION_ID_5700_C0 0x20 90 #define REVISION_ID_5700_C1 0x21 91 #define REVISION_ID_5700_C2 0x22 92 93 #define REVISION_ID_5701_A0 0x08 94 #define REVISION_ID_5701_A2 0x12 95 #define REVISION_ID_5701_A3 0x15 96 97 #define REVISION_ID_5702_A0 0x00 98 99 #define REVISION_ID_5703_A0 0x00 100 #define REVISION_ID_5703_A1 0x01 101 #define REVISION_ID_5703_A2 0x02 102 103 #define REVISION_ID_5704_A0 0x00 104 #define REVISION_ID_5704_A1 0x01 105 #define REVISION_ID_5704_A2 0x02 106 #define REVISION_ID_5704_A3 0x03 107 #define REVISION_ID_5704_B0 0x10 108 109 #define REVISION_ID_5705_A0 0x00 110 #define REVISION_ID_5705_A1 0x01 111 #define REVISION_ID_5705_A2 0x02 112 #define REVISION_ID_5705_A3 0x03 113 114 #define REVISION_ID_5721_A0 0x00 115 #define REVISION_ID_5721_A1 0x01 116 117 #define REVISION_ID_5751_A0 0x00 118 #define REVISION_ID_5751_A1 0x01 119 120 #define REVISION_ID_5714_A0 0x00 121 #define REVISION_ID_5714_A1 0x01 122 #define REVISION_ID_5714_A2 0xA2 123 #define REVISION_ID_5714_A3 0xA3 124 125 #define REVISION_ID_5715_A0 0x00 126 #define REVISION_ID_5715_A1 0x01 127 #define REVISION_ID_5715_A2 0xA2 128 129 #define REVISION_ID_5715S_A0 0x00 130 #define REVISION_ID_5715S_A1 0x01 131 132 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 133 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 134 (bgep->chipid.device == DEVICE_ID_5701) ||\ 135 (bgep->chipid.device == DEVICE_ID_5702) ||\ 136 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 137 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 138 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 139 (bgep->chipid.device == DEVICE_ID_5703) ||\ 140 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 141 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 142 (bgep->chipid.device == DEVICE_ID_5704)) 143 144 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 145 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 146 (bgep->chipid.device == DEVICE_ID_5702fe)) 147 148 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 149 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 150 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 151 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 152 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 153 (bgep->chipid.device == DEVICE_ID_5782) ||\ 154 (bgep->chipid.device == DEVICE_ID_5788) ||\ 155 (bgep->chipid.device == DEVICE_ID_5705_2)) 156 157 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 158 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 159 (bgep->chipid.device == DEVICE_ID_5751) ||\ 160 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 161 (bgep->chipid.device == DEVICE_ID_5752) ||\ 162 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 163 (bgep->chipid.device == DEVICE_ID_5789)) 164 165 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 166 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 167 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 168 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 169 (bgep->chipid.device == DEVICE_ID_5715S)) 170 171 /* 172 * Second section: 173 * Offsets of important registers & definitions for bits therein 174 */ 175 176 /* 177 * PCI-X registers & bits 178 */ 179 #define PCIX_CONF_COMM 0x42 180 #define PCIX_COMM_RELAXED 0x0002 181 182 /* 183 * Miscellaneous Host Control Register, in PCI config space 184 */ 185 #define PCI_CONF_BGE_MHCR 0x68 186 #define MHCR_CHIP_REV_MASK 0xffff0000 187 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 188 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 189 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 190 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 191 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 192 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 193 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 194 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 195 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 196 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 197 198 #define MHCR_CHIP_REV_5700_B0 0x71000000 199 #define MHCR_CHIP_REV_5700_B2 0x71020000 200 #define MHCR_CHIP_REV_5700_B3 0x71030000 201 #define MHCR_CHIP_REV_5700_C0 0x72000000 202 #define MHCR_CHIP_REV_5700_C1 0x72010000 203 #define MHCR_CHIP_REV_5700_C2 0x72020000 204 205 #define MHCR_CHIP_REV_5701_A0 0x00000000 206 #define MHCR_CHIP_REV_5701_A2 0x00020000 207 #define MHCR_CHIP_REV_5701_A3 0x00030000 208 #define MHCR_CHIP_REV_5701_A5 0x01050000 209 210 #define MHCR_CHIP_REV_5702_A0 0x10000000 211 #define MHCR_CHIP_REV_5702_A1 0x10010000 212 #define MHCR_CHIP_REV_5702_A2 0x10020000 213 214 #define MHCR_CHIP_REV_5703_A0 0x10000000 215 #define MHCR_CHIP_REV_5703_A1 0x10010000 216 #define MHCR_CHIP_REV_5703_A2 0x10020000 217 #define MHCR_CHIP_REV_5703_B0 0x11000000 218 #define MHCR_CHIP_REV_5703_B1 0x11010000 219 220 #define MHCR_CHIP_REV_5704_A0 0x20000000 221 #define MHCR_CHIP_REV_5704_A1 0x20010000 222 #define MHCR_CHIP_REV_5704_A2 0x20020000 223 #define MHCR_CHIP_REV_5704_A3 0x20030000 224 #define MHCR_CHIP_REV_5704_B0 0x21000000 225 226 #define MHCR_CHIP_REV_5705_A0 0x30000000 227 #define MHCR_CHIP_REV_5705_A1 0x30010000 228 #define MHCR_CHIP_REV_5705_A2 0x30020000 229 #define MHCR_CHIP_REV_5705_A3 0x30030000 230 #define MHCR_CHIP_REV_5705_A5 0x30050000 231 232 #define MHCR_CHIP_REV_5782_A0 0x30030000 233 #define MHCR_CHIP_REV_5782_A1 0x30030088 234 235 #define MHCR_CHIP_REV_5788_A1 0x30050000 236 237 #define MHCR_CHIP_REV_5751_A0 0x40000000 238 #define MHCR_CHIP_REV_5751_A1 0x40010000 239 240 #define MHCR_CHIP_REV_5721_A0 0x41000000 241 #define MHCR_CHIP_REV_5721_A1 0x41010000 242 243 #define MHCR_CHIP_REV_5714_A0 0x50000000 244 #define MHCR_CHIP_REV_5714_A1 0x90010000 245 246 #define MHCR_CHIP_REV_5715_A0 0x50000000 247 #define MHCR_CHIP_REV_5715_A1 0x90010000 248 249 #define MHCR_CHIP_REV_5715S_A0 0x50000000 250 #define MHCR_CHIP_REV_5715S_A1 0x90010000 251 252 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 253 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 254 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 255 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 256 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 257 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 258 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 259 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 260 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 261 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 262 263 264 /* 265 * PCI DMA read/write Control Register, in PCI config space 266 * 267 * Note that several fields previously defined here have been deleted 268 * as they are not implemented in the 5703/4. 269 * 270 * Note: the value of this register is critical. It is possible to 271 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 272 * by programming the wrong value. The value #defined below has been 273 * tested and shown to avoid all known problems. If it is to be changed, 274 * correct operation must be reverified on all supported platforms. 275 * 276 * In particular, we set both watermark fields to 2xCacheLineSize (128) 277 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 278 * with Tomatillo's internal pipelines, that otherwise result in stalls, 279 * repeated retries, and DTOs. 280 */ 281 #define PCI_CONF_BGE_PDRWCR 0x6c 282 #define PDRWCR_RWCMD_MASK 0xFF000000 283 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 284 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 285 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 286 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 287 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 288 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 289 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 290 291 /* 292 * These are the actual values to be put into the fields shown above 293 */ 294 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 295 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 296 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 297 #define PDRWCR_MIN_BEATS 0x00000000 298 299 #define PDRWCR_VAR_DEFAULT 0x761b0000 300 #define PDRWCR_VAR_5721 0x76180000 301 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 302 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 303 304 /* 305 * PCI State Register, in PCI config space 306 * 307 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 308 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 309 */ 310 #define PCI_CONF_BGE_PCISTATE 0x70 311 #define PCISTATE_RETRY_SAME_DMA 0x00002000 312 #define PCISTATE_FLAT_VIEW 0x00000100 313 #define PCISTATE_EXT_ROM_RETRY 0x00000040 314 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 315 #define PCISTATE_BUS_IS_32_BIT 0x00000010 316 #define PCISTATE_BUS_IS_FAST 0x00000008 317 #define PCISTATE_BUS_IS_PCI 0x00000004 318 #define PCISTATE_INTA_STATE 0x00000002 319 #define PCISTATE_FORCE_RESET 0x00000001 320 321 /* 322 * PCI Clock Control Register, in PCI config space 323 */ 324 #define PCI_CONF_BGE_CLKCTL 0x74 325 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 326 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 327 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 328 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 329 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 330 #define CLKCTL_PCIE_A0_FIX 0x00101000 331 332 /* 333 * Dual MAC Control Register, in PCI config space 334 */ 335 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 336 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 337 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 338 339 /* 340 * Register Indirect Access Address Register, 0x78 in PCI config 341 * space. Once this is set, accesses to the Register Indirect 342 * Access Data Register (0x80) refer to the register whose address 343 * is given by *this* register. This allows access to all the 344 * operating registers, while using only config space accesses. 345 * 346 * Note that the address written to the RIIAR should lie in one 347 * of the following ranges: 348 * 0x00000000 <= address < 0x00008000 (regular registers) 349 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 350 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 351 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 352 */ 353 #define PCI_CONF_BGE_RIAAR 0x78 354 #define PCI_CONF_BGE_RIADR 0x80 355 356 #define RIAAR_REGISTER_MIN 0x00000000 357 #define RIAAR_REGISTER_MAX 0x00008000 358 #define RIAAR_RX_SCRATCH_MIN 0x00030000 359 #define RIAAR_RX_SCRATCH_MAX 0x00034000 360 #define RIAAR_TX_SCRATCH_MIN 0x00034000 361 #define RIAAR_TX_SCRATCH_MAX 0x00038000 362 #define RIAAR_RXROM_MIN 0x00038000 363 #define RIAAR_RXROM_MAX 0x00038800 364 365 /* 366 * Memory Window Base Address Register, 0x7c in PCI config space 367 * Once this is set, accesses to the Memory Window Data Access Register 368 * (0x84) refer to the word of NIC-local memory whose address is given 369 * by this register. When used in this way, the whole of the address 370 * written to this register is significant. 371 * 372 * This register also provides the 32K-aligned base address for a 32K 373 * region of NIC-local memory that the host can directly address in 374 * the upper 32K of the 64K of PCI memory space allocated to the chip. 375 * In this case, the bottom 15 bits of the register are ignored. 376 * 377 * Note that the address written to the MWBAR should lie in the range 378 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 379 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 380 * memory were present, but it's only supported on the 5700, not the 381 * 5701/5703/5704. 382 */ 383 #define PCI_CONF_BGE_MWBAR 0x7c 384 #define PCI_CONF_BGE_MWDAR 0x84 385 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 386 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 387 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 388 389 /* 390 * The PCI express device control register and device status register 391 * which are only applicable on BCM5751 and BCM5721. 392 */ 393 #define PCI_CONF_DEV_CTRL 0xd8 394 #define READ_REQ_SIZE_MAX 0x5000 395 #define DEV_CTRL_NO_SNOOP 0x0800 396 #define DEV_CTRL_RELAXED 0x0010 397 398 #define PCI_CONF_DEV_STUS 0xda 399 #define DEVICE_ERROR_STUS 0xf 400 401 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 402 403 /* 404 * Where to find things in NIC-local (on-chip) memory 405 */ 406 #define NIC_MEM_SEND_RINGS 0x0100 407 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 408 #define NIC_MEM_RECV_RINGS 0x0200 409 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 410 #define NIC_MEM_STATISTICS 0x0300 411 #define NIC_MEM_STATISTICS_SIZE 0x0800 412 #define NIC_MEM_STATUS_BLOCK 0x0b00 413 #define NIC_MEM_STATUS_SIZE 0x0050 414 #define NIC_MEM_GENCOMM 0x0b50 415 416 417 /* 418 * Note: the (non-bogus) values below are appropriate for systems 419 * without external memory. They would be different on a 5700 with 420 * external memory. 421 * 422 * Note: The higher send ring addresses and the mini ring shadow 423 * buffer address are dummies - systems without external memory 424 * are limited to 4 send rings and no mini receive ring. 425 */ 426 #define NIC_MEM_SHADOW_DMA 0x2000 427 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 428 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 429 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 430 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 431 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 432 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 433 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 434 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 435 436 /* 437 * Put this in the GENCOMM port to tell the firmware not to run PXE 438 */ 439 #define T3_MAGIC_NUMBER 0x4b657654u 440 441 /* 442 * The remaining registers appear in the low 32K of regular 443 * PCI Memory Address Space 444 */ 445 446 /* 447 * All the state machine control registers below have at least a 448 * <RESET> bit and an <ENABLE> bit as defined below. Some also 449 * have an <ATTN_ENABLE> bit. 450 */ 451 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 452 #define STATE_MACHINE_ENABLE_BIT 0x00000002 453 #define STATE_MACHINE_RESET_BIT 0x00000001 454 455 #define TRANSMIT_MAC_MODE_REG 0x045c 456 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 457 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 458 #define SEND_BD_SELECTOR_MODE_REG 0x1400 459 #define SEND_BD_INITIATOR_MODE_REG 0x1800 460 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 461 462 #define RECEIVE_MAC_MODE_REG 0x0468 463 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 464 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 465 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 466 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 467 #define RCV_BD_COMPLETION_MODE_REG 0x3000 468 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 469 470 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 471 #define HOST_COALESCE_MODE_REG 0x3c00 472 #define MEMORY_ARBITER_MODE_REG 0x4000 473 #define BUFFER_MANAGER_MODE_REG 0x4400 474 #define READ_DMA_MODE_REG 0x4800 475 #define WRITE_DMA_MODE_REG 0x4c00 476 #define DMA_COMPLETION_MODE_REG 0x6400 477 478 /* 479 * Other bits in some of the above state machine control registers 480 */ 481 482 /* 483 * Transmit MAC Mode Register 484 * (TRANSMIT_MAC_MODE_REG, 0x045c) 485 */ 486 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 487 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 488 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 489 490 /* 491 * Receive MAC Mode Register 492 * (RECEIVE_MAC_MODE_REG, 0x0468) 493 */ 494 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 495 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 496 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 497 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 498 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 499 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 500 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 501 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 502 503 /* 504 * Receive BD Initiator Mode Register 505 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 506 * 507 * Each of these bits controls whether ATTN is asserted 508 * on a particular condition 509 */ 510 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 511 512 /* 513 * Receive Data & Receive BD Initiator Mode Register 514 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 515 * 516 * Each of these bits controls whether ATTN is asserted 517 * on a particular condition 518 */ 519 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 520 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 521 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 522 523 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 524 525 /* 526 * Host Coalescing Mode Control Register 527 * (HOST_COALESCE_MODE_REG, 0x3c00) 528 */ 529 #define COALESCE_64_BYTE_RINGS 12 530 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 531 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 532 #define COALESCE_CLR_TICKS_TX 0x00000400 533 #define COALESCE_CLR_TICKS_RX 0x00000200 534 #define COALESCE_32_BYTE_STATUS 0x00000100 535 #define COALESCE_64_BYTE_STATUS 0x00000080 536 #define COALESCE_NOW 0x00000008 537 538 /* 539 * Buffer Manager Mode Register 540 * (BUFFER_MANAGER_MODE_REG, 0x4400) 541 * 542 * In addition to the usual error-attn common to most state machines 543 * this register has a separate bit for attn on running-low-on-mbufs 544 */ 545 #define BUFF_MGR_TEST_MODE 0x00000008 546 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 547 548 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 549 550 /* 551 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 552 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 553 * 554 * These registers each contain a 2-bit priority field, which controls 555 * the relative priority of that type of DMA (read vs. write vs. MSI), 556 * and a set of bits that control whether ATTN is asserted on each 557 * particular condition 558 */ 559 #define DMA_PRIORITY_MASK 0xc0000000 560 #define DMA_PRIORITY_SHIFT 30 561 #define ALL_DMA_ATTN_BITS 0x000003fc 562 563 /* 564 * End of state machine control register definitions 565 */ 566 567 568 /* 569 * Mailbox Registers (8 bytes each, but high half unused) 570 */ 571 #define INTERRUPT_MBOX_0_REG 0x0200 572 #define INTERRUPT_MBOX_1_REG 0x0208 573 #define INTERRUPT_MBOX_2_REG 0x0210 574 #define INTERRUPT_MBOX_3_REG 0x0218 575 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 576 577 /* 578 * Ring Producer/Consumer Index (Mailbox) Registers 579 */ 580 #define RECV_STD_PROD_INDEX_REG 0x0268 581 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 582 #define RECV_MINI_PROD_INDEX_REG 0x0278 583 #define RECV_RING_CONS_INDEX_REGS 0x0280 584 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 585 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 586 587 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 588 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 589 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 590 591 /* 592 * Ethernet MAC Mode Register 593 */ 594 #define ETHERNET_MAC_MODE_REG 0x0400 595 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 596 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 597 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 598 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 599 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 600 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 601 #define ETHERNET_MODE_SEND_CFGS 0x00020000 602 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 603 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 604 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 605 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 606 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 607 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 608 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 609 #define ETHERNET_MODE_MAX_DEFER 0x00000200 610 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 611 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 612 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 613 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 614 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 615 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 616 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 617 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 618 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 619 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 620 621 /* 622 * Ethernet MAC Status & Event Registers 623 */ 624 #define ETHERNET_MAC_STATUS_REG 0x0404 625 #define ETHERNET_STATUS_MI_INT 0x00800000 626 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 627 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 628 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 629 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 630 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 631 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 632 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 633 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 634 635 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 636 #define ETHERNET_EVENT_MI_INT 0x00800000 637 #define ETHERNET_EVENT_LINK_INT 0x00001000 638 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 639 640 /* 641 * Ethernet MAC LED Control Register 642 * 643 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 644 * the external LED driver circuitry is wired up to assume that this mode 645 * will always be selected. Software must not change it! 646 */ 647 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 648 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 649 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 650 #define LED_CONTROL_LED_MODE_MASK 0x00001800 651 #define LED_CONTROL_LED_MODE_5700 0x00000000 652 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 653 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 654 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 655 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 656 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 657 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 658 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 659 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 660 #define LED_CONTROL_TRAFFIC_LED 0x00000020 661 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 662 #define LED_CONTROL_10MBPS_LED 0x00000008 663 #define LED_CONTROL_100MBPS_LED 0x00000004 664 #define LED_CONTROL_1000MBPS_LED 0x00000002 665 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 666 #define LED_CONTROL_DEFAULT 0x02000800 667 668 /* 669 * MAC Address registers 670 * 671 * These four eight-byte registers each hold one unicast address 672 * (six bytes), right justified & zero-filled on the left. 673 * They will normally all be set to the same value, as a station 674 * usually only has one h/w address. The value in register 0 is 675 * used for pause packets; any of the four can be specified for 676 * substitution into other transmitted packets if required. 677 */ 678 #define MAC_ADDRESS_0_REG 0x0410 679 #define MAC_ADDRESS_1_REG 0x0418 680 #define MAC_ADDRESS_2_REG 0x0420 681 #define MAC_ADDRESS_3_REG 0x0428 682 683 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 684 #define MAC_ADDRESS_REGS_MAX 4 685 686 /* 687 * More MAC Registers ... 688 */ 689 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 690 #define MAC_RX_MTU_SIZE_REG 0x043c 691 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 692 #define MAC_TX_LENGTHS_REG 0x0464 693 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 694 695 /* 696 * MII access registers 697 */ 698 #define MI_COMMS_REG 0x044c 699 #define MI_COMMS_START 0x20000000 700 #define MI_COMMS_READ_FAILED 0x10000000 701 #define MI_COMMS_COMMAND_MASK 0x0c000000 702 #define MI_COMMS_COMMAND_READ 0x08000000 703 #define MI_COMMS_COMMAND_WRITE 0x04000000 704 #define MI_COMMS_ADDRESS_MASK 0x03e00000 705 #define MI_COMMS_ADDRESS_SHIFT 21 706 #define MI_COMMS_REGISTER_MASK 0x001f0000 707 #define MI_COMMS_REGISTER_SHIFT 16 708 #define MI_COMMS_DATA_MASK 0x0000ffff 709 #define MI_COMMS_DATA_SHIFT 0 710 711 #define MI_STATUS_REG 0x0450 712 #define MI_STATUS_10MBPS 0x00000002 713 #define MI_STATUS_LINK 0x00000001 714 715 #define MI_MODE_REG 0x0454 716 #define MI_MODE_CLOCK_MASK 0x001f0000 717 #define MI_MODE_AUTOPOLL 0x00000010 718 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 719 #define MI_MODE_DEFAULT 0x000c0000 720 721 #define MI_AUTOPOLL_STATUS_REG 0x0458 722 #define MI_AUTOPOLL_ERROR 0x00000001 723 724 #define TRANSMIT_MAC_STATUS_REG 0x0460 725 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 726 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 727 #define TRANSMIT_STATUS_LINK_UP 0x00000008 728 #define TRANSMIT_STATUS_SENT_XON 0x00000004 729 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 730 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 731 732 #define RECEIVE_MAC_STATUS_REG 0x046c 733 #define RECEIVE_STATUS_RCVD_XON 0x00000004 734 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 735 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 736 737 /* 738 * These four-byte registers constitute a hash table for deciding 739 * whether to accept incoming multicast packets. The bits are 740 * numbered in big-endian fashion, from hash 0 => the MSB of 741 * register 0 to hash 127 => the LSB of the highest-numbered 742 * register. 743 * 744 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 745 * enabled by setting the appropriate bit in the Rx MAC mode 746 * register. Otherwise, and on all earlier chips, the table 747 * is only 128 bits (registers 0-3). 748 */ 749 #define MAC_HASH_0_REG 0x0470 750 #define MAC_HASH_1_REG 0x0474 751 #define MAC_HASH_2_REG 0x0478 752 #define MAC_HASH_3_REG 0x047c 753 #define MAC_HASH_4_REG 0x???? 754 #define MAC_HASH_5_REG 0x???? 755 #define MAC_HASH_6_REG 0x???? 756 #define MAC_HASH_7_REG 0x???? 757 #define MAC_HASH_REG(n) (0x470+4*(n)) 758 759 /* 760 * Receive Rules Registers: 16 pairs of control+mask/value pairs 761 */ 762 #define RCV_RULES_CONTROL_0_REG 0x0480 763 #define RCV_RULES_MASK_0_REG 0x0484 764 #define RCV_RULES_CONTROL_15_REG 0x04f8 765 #define RCV_RULES_MASK_15_REG 0x04fc 766 #define RCV_RULES_CONFIG_REG 0x0500 767 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 768 769 #define RECV_RULES_NUM_MAX 16 770 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 771 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 772 773 #define RECV_RULE_CTL_ENABLE 0x80000000 774 #define RECV_RULE_CTL_AND 0x40000000 775 #define RECV_RULE_CTL_P1 0x20000000 776 #define RECV_RULE_CTL_P2 0x10000000 777 #define RECV_RULE_CTL_P3 0x08000000 778 #define RECV_RULE_CTL_MASK 0x04000000 779 #define RECV_RULE_CTL_DISCARD 0x02000000 780 #define RECV_RULE_CTL_MAP 0x01000000 781 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 782 #define RECV_RULE_CTL_OP 0x00030000 783 #define RECV_RULE_CTL_OP_EQ 0x00000000 784 #define RECV_RULE_CTL_OP_NEQ 0x00010000 785 #define RECV_RULE_CTL_OP_GREAT 0x00020000 786 #define RECV_RULE_CTL_OP_LESS 0x00030000 787 #define RECV_RULE_CTL_HEADER 0x0000e000 788 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 789 #define RECV_RULE_CTL_HEADER_IP 0x00002000 790 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 791 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 792 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 793 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 794 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 795 RECV_RULE_CTL_CLASS_BITS) 796 #define RECV_RULE_CTL_OFFSET 0x000000ff 797 798 /* 799 * Receive Rules definition 800 */ 801 #define RULE_MATCH_TO_RING 2 802 /* ring that traffic will go into when recv rule matches. */ 803 /* value is between 1 and 16, not 0 and 15 */ 804 805 #define IPHEADER_PROTO_OFFSET 0x08 806 #define IPHEADER_SIP_OFFSET 0x0c 807 808 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 809 RECV_RULE_CTL_OP_EQ | \ 810 RECV_RULE_CTL_HEADER_IP | \ 811 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 812 IPHEADER_PROTO_OFFSET) 813 #define RULE_TCP_MASK_VALUE 0x00ff0006 814 #define RULE_UDP_MASK_VALUE 0x00ff0011 815 #define RULE_ICMP_MASK_VALUE 0x00ff0001 816 817 #define RULE_SIP_ADDR 0x0a000001 818 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 819 820 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 821 RECV_RULE_CTL_HEADER_IP | \ 822 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 823 IPHEADER_SIP_OFFSET) 824 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 825 826 /* 827 * 1000BaseX low-level access registers 828 */ 829 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 830 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 831 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 832 #define TX_1000BASEX_AUTONEG_REG 0x0444 833 #define RX_1000BASEX_AUTONEG_REG 0x0448 834 835 /* 836 * Autoneg code bits for the 1000BASE-X AUTONEG registers 837 */ 838 #define AUTONEG_CODE_PAUSE 0x00008000 839 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 840 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 841 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 842 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 843 #define AUTONEG_CODE_FAULT_MASK 0x00000030 844 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 845 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 846 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 847 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 848 849 /* 850 * SerDes Registers (5703S/5704S only) 851 */ 852 #define SERDES_CONTROL_REG 0x0590 853 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 854 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 855 #define SERDES_CONTROL_TX_DISABLE 0x00004000 856 #define SERDES_STATUS_REG 0x0594 857 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 858 #define SERDES_STATUS_RXSTAT 0x000000ff 859 860 /* 861 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 862 */ 863 #define STAT_IFHCOUT_OCTETS_REG 0x0800 864 #define STAT_ETHER_COLLIS_REG 0x0808 865 #define STAT_OUTXON_SENT_REG 0x080c 866 #define STAT_OUTXOFF_SENT_REG 0x0810 867 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 868 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 869 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 870 #define STAT_DOT3_DEFERED_TX_REG 0x0824 871 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 872 #define STAT_DOT3_LATE_COLLI_REG 0x0830 873 #define STAT_IFHCOUT_UPKGS_REG 0x086c 874 #define STAT_IFHCOUT_MPKGS_REG 0x0870 875 #define STAT_IFHCOUT_BPKGS_REG 0x0874 876 877 #define STAT_IFHCIN_OCTETS_REG 0x0880 878 #define STAT_ETHER_FRAGMENT_REG 0x0888 879 #define STAT_IFHCIN_UPKGS_REG 0x088c 880 #define STAT_IFHCIN_MPKGS_REG 0x0890 881 #define STAT_IFHCIN_BPKGS_REG 0x0894 882 883 #define STAT_DOT3_FCS_ERR_REG 0x0898 884 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 885 #define STAT_XON_PAUSE_RX_REG 0x08a0 886 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 887 #define STAT_MAC_CTRL_RX_REG 0x08a8 888 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 889 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 890 #define STAT_ETHER_JABBERS_REG 0x08b4 891 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 892 #define SIZE_OF_STATISTIC_REG 0x1B 893 /* 894 * Send Data Initiator Registers 895 */ 896 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 897 #define SEND_INIT_STATS_ZERO 0x00000010 898 #define SEND_INIT_STATS_FLUSH 0x00000008 899 #define SEND_INIT_STATS_CLEAR 0x00000004 900 #define SEND_INIT_STATS_FASTER 0x00000002 901 #define SEND_INIT_STATS_ENABLE 0x00000001 902 903 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 904 905 /* 906 * Send Buffer Descriptor Selector Control Registers 907 */ 908 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 909 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 910 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 911 912 /* 913 * Receive List Placement Registers 914 */ 915 #define RCV_LP_CONFIG_REG 0x2010 916 #define RCV_LP_CONFIG_DEFAULT 0x00000009 917 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 918 919 #define RCV_LP_STATS_CONTROL_REG 0x2014 920 #define RCV_LP_STATS_ZERO 0x00000010 921 #define RCV_LP_STATS_FLUSH 0x00000008 922 #define RCV_LP_STATS_CLEAR 0x00000004 923 #define RCV_LP_STATS_FASTER 0x00000002 924 #define RCV_LP_STATS_ENABLE 0x00000001 925 926 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 927 928 /* 929 * Receive Data & BD Initiator Registers 930 */ 931 #define RCV_INITIATOR_STATUS_REG 0x2404 932 933 /* 934 * Receive Buffer Descriptor Ring Control Block Registers 935 * NB: sixteen bytes (128 bits) each 936 */ 937 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 938 #define STD_RCV_BD_RING_RCB_REG 0x2450 939 #define MINI_RCV_BD_RING_RCB_REG 0x2460 940 941 /* 942 * Receive Buffer Descriptor Ring Replenish Threshold Registers 943 */ 944 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 945 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 946 #define STD_RCV_BD_REPLENISH_REG 0x2c18 947 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 948 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 949 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 950 951 /* 952 * Host Coalescing Engine Control Registers 953 */ 954 #define RCV_COALESCE_TICKS_REG 0x3c08 955 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 956 #define SEND_COALESCE_TICKS_REG 0x3c0c 957 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 958 #define RCV_COALESCE_MAX_BD_REG 0x3c10 959 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 960 #define SEND_COALESCE_MAX_BD_REG 0x3c14 961 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 962 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 963 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 964 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 965 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 966 #define RCV_COALESCE_INT_BD_REG 0x3c20 967 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 968 #define SEND_COALESCE_INT_BD_REG 0x3c24 969 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 970 #define STATISTICS_TICKS_REG 0x3c28 971 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 972 #define STATISTICS_HOST_ADDR_REG 0x3c30 973 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 974 #define STATISTICS_BASE_ADDR_REG 0x3c40 975 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 976 #define FLOW_ATTN_REG 0x3c48 977 978 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 979 #define NIC_STD_RECV_INDEX_REG 0x3c54 980 #define NIC_MINI_RECV_INDEX_REG 0x3c58 981 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 982 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 983 984 /* 985 * Mbuf Pool Initialisation & Watermark Registers 986 * 987 * There are some conflicts in the PRM; compare the recommendations 988 * on pp. 115, 236, and 339. The values here were recommended by 989 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 990 */ 991 #define BUFFER_MANAGER_STATUS_REG 0x4404 992 #define MBUF_POOL_BASE_REG 0x4408 993 #define MBUF_POOL_BASE_DEFAULT 0x00008000 994 #define MBUF_POOL_BASE_5721 0x00010000 995 #define MBUF_POOL_BASE_5704 0x00010000 996 #define MBUF_POOL_BASE_5705 0x00010000 997 #define MBUF_POOL_LENGTH_REG 0x440c 998 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 999 #define MBUF_POOL_LENGTH_5704 0x00010000 1000 #define MBUF_POOL_LENGTH_5705 0x00008000 1001 #define MBUF_POOL_LENGTH_5721 0x00008000 1002 #define RDMA_MBUF_LOWAT_REG 0x4410 1003 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1004 #define RDMA_MBUF_LOWAT_5705 0x00000000 1005 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1006 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1007 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1008 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1009 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1010 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1011 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1012 #define MBUF_HIWAT_REG 0x4418 1013 #define MBUF_HIWAT_DEFAULT 0x00000060 1014 #define MBUF_HIWAT_5705 0x00000060 1015 #define MBUF_HIWAT_JUMBO 0x0000017c 1016 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1017 1018 /* 1019 * DMA Descriptor Pool Initialisation & Watermark Registers 1020 */ 1021 #define DMAD_POOL_BASE_REG 0x442c 1022 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1023 #define DMAD_POOL_LENGTH_REG 0x4430 1024 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1025 #define DMAD_POOL_LOWAT_REG 0x4434 1026 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1027 #define DMAD_POOL_HIWAT_REG 0x4438 1028 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1029 1030 /* 1031 * More threshold/watermark registers ... 1032 */ 1033 #define RECV_FLOW_THRESHOLD_REG 0x4458 1034 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1035 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1036 1037 /* 1038 * Read/Write DMA Status Registers 1039 */ 1040 #define READ_DMA_STATUS_REG 0x4804 1041 #define WRITE_DMA_STATUS_REG 0x4c04 1042 1043 /* 1044 * RX/TX RISC Registers 1045 */ 1046 #define RX_RISC_MODE_REG 0x5000 1047 #define RX_RISC_STATE_REG 0x5004 1048 #define RX_RISC_PC_REG 0x501c 1049 #define TX_RISC_MODE_REG 0x5400 1050 #define TX_RISC_STATE_REG 0x5404 1051 #define TX_RISC_PC_REG 0x541c 1052 1053 #define FTQ_RESET_REG 0x5c00 1054 1055 #define MSI_MODE_REG 0x6000 1056 #define MSI_PRI_HIGHEST 0xc0000000 1057 #define MSI_MSI_ENABLE 0x00000002 1058 1059 #define MODE_CONTROL_REG 0x6800 1060 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1061 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1062 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1063 #define MODE_INT_ON_DMA_ATTN 0x08000000 1064 #define MODE_INT_ON_MAC_ATTN 0x04000000 1065 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1066 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1067 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1068 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1069 #define MODE_HOST_SEND_BDS 0x00020000 1070 #define MODE_HOST_STACK_UP 0x00010000 1071 #define MODE_FORCE_32_BIT_PCI 0x00008000 1072 #define MODE_NO_INT_ON_RECV 0x00004000 1073 #define MODE_NO_INT_ON_SEND 0x00002000 1074 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1075 #define MODE_NO_CRC 0x00000400 1076 #define MODE_NO_FRAME_CRACKING 0x00000200 1077 #define MODE_WORD_SWAP_FRAME 0x00000020 1078 #define MODE_BYTE_SWAP_FRAME 0x00000010 1079 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1080 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1081 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1082 1083 /* 1084 * Miscellaneous Configuration Register 1085 * 1086 * This contains various bits relating to power control (which differ 1087 * among different members of the chip family), but the important bits 1088 * for our purposes are the RESET bit and the Timer Prescaler field. 1089 * 1090 * The RESET bit in this register serves to reset the whole chip, even 1091 * including the PCI interface(!) Once it's set, the chip will not 1092 * respond to ANY accesses -- not even CONFIG space -- until the reset 1093 * completes internally. According to the PRM, this should take less 1094 * than 100us. Any access during this period will get a bus error. 1095 * 1096 * The Timer Prescaler field must be programmed so that the timer period 1097 * is as near as possible to 1us. The value in this field should be 1098 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1099 * the Core Clock should always be 66MHz (independently of the bus speed, 1100 * at least for PCI rather than PCI-X), so this register must be set to 1101 * the value 0x82 ((66-1) << 1). 1102 */ 1103 #define CORE_CLOCK_MHZ 66 1104 #define MISC_CONFIG_REG 0x6804 1105 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1106 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1107 #define MISC_CONFIG_POWERDOWN 0x00100000 1108 #define MISC_CONFIG_POWER_STATE 0x00060000 1109 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1110 #define MISC_CONFIG_RESET_BIT 0x00000001 1111 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1112 1113 /* 1114 * Miscellaneous Local Control Register (MLCR) 1115 */ 1116 #define MISC_LOCAL_CONTROL_REG 0x6808 1117 #define MLCR_PCI_CTRL_SELECT 0x10000000 1118 #define MLCR_LEGACY_PCI_MODE 0x08000000 1119 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1120 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1121 #define MLCR_SSRAM_TYPE 0x00400000 1122 #define MLCR_BANK_SELECT 0x00200000 1123 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1124 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1125 1126 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1127 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1128 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1129 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1130 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1131 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1132 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1133 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1134 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1135 1136 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1137 #define MLCR_SET_INT 0x00000004 /* W/O */ 1138 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1139 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1140 1141 /* 1142 * This value defines all GPIO bits as INPUTS, but sets their default 1143 * values as outputs to HIGH, on the assumption that external circuits 1144 * (if any) will probably be active-LOW with passive pullups. 1145 * 1146 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1147 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1148 * enable writing. Otherwise, the SEEPROM is protected. 1149 */ 1150 #define MLCR_DEFAULT 0x0101c000 1151 #define MLCR_DEFAULT_5714 0x1901c000 1152 1153 /* 1154 * Serial EEPROM Data/Address Registers (auto-access mode) 1155 */ 1156 #define SERIAL_EEPROM_DATA_REG 0x683c 1157 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1158 #define SEEPROM_ACCESS_READ 0x80000000 1159 #define SEEPROM_ACCESS_WRITE 0x00000000 1160 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1161 #define SEEPROM_ACCESS_RESET 0x20000000 1162 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1163 #define SEEPROM_ACCESS_START 0x02000000 1164 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1165 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1166 1167 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1168 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1169 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1170 1171 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1172 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1173 1174 /* 1175 * "Linearised" address mask, treating multiple devices as consecutive 1176 */ 1177 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1178 1179 /* 1180 * Non-Volatile Memory Interface Registers 1181 * Note: on chips that support the flash interface (5702+), flash is the 1182 * default and the legacy seeprom interface must be explicitly enabled 1183 * if required. On older chips (5700/01), SEEPROM is the default (and 1184 * only) non-volatile memory available, and these registers don't exist! 1185 */ 1186 #define NVM_FLASH_CMD_REG 0x7000 1187 #define NVM_FLASH_CMD_LAST 0x00000100 1188 #define NVM_FLASH_CMD_FIRST 0x00000080 1189 #define NVM_FLASH_CMD_RD 0x00000000 1190 #define NVM_FLASH_CMD_WR 0x00000020 1191 #define NVM_FLASH_CMD_DOIT 0x00000010 1192 #define NVM_FLASH_CMD_DONE 0x00000008 1193 1194 #define NVM_FLASH_WRITE_REG 0x7008 1195 #define NVM_FLASH_READ_REG 0x7010 1196 1197 #define NVM_FLASH_ADDR_REG 0x700c 1198 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1199 1200 #define NVM_CONFIG1_REG 0x7014 1201 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1202 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1203 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1204 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1205 #define NVM_CFG1_FLASH_MODE 0x00000001 1206 1207 #define NVM_SW_ARBITRATION_REG 0x7020 1208 #define NVM_READ_REQ3 0X00008000 1209 #define NVM_READ_REQ2 0X00004000 1210 #define NVM_READ_REQ1 0X00002000 1211 #define NVM_READ_REQ0 0X00001000 1212 #define NVM_WON_REQ3 0X00000800 1213 #define NVM_WON_REQ2 0X00000400 1214 #define NVM_WON_REQ1 0X00000200 1215 #define NVM_WON_REQ0 0X00000100 1216 #define NVM_RESET_REQ3 0X00000080 1217 #define NVM_RESET_REQ2 0X00000040 1218 #define NVM_RESET_REQ1 0X00000020 1219 #define NVM_RESET_REQ0 0X00000010 1220 #define NVM_SET_REQ3 0X00000008 1221 #define NVM_SET_REQ2 0X00000004 1222 #define NVM_SET_REQ1 0X00000002 1223 #define NVM_SET_REQ0 0X00000001 1224 1225 /* 1226 * NVM access register 1227 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1228 * and BCM5715 only. 1229 */ 1230 #define NVM_ACCESS_REG 0X7024 1231 #define NVM_WRITE_ENABLE 0X00000002 1232 #define NVM_ACCESS_ENABLE 0X00000001 1233 1234 /* 1235 * TLP Control Register 1236 * Applicable to BCM5721 and BCM5751 only 1237 */ 1238 #define TLP_CONTROL_REG 0x7c00 1239 #define TLP_DATA_FIFO_PROTECT 0x02000000 1240 1241 /* 1242 * PHY Test Control Register 1243 * Applicable to BCM5721 and BCM5751 only 1244 */ 1245 #define PHY_TEST_CTRL_REG 0x7e2c 1246 #define PHY_PCIE_SCRAM_MODE 0x20 1247 #define PHY_PCIE_LTASS_MODE 0x40 1248 1249 /* 1250 * The internal firmware expects a certain layout of the non-volatile 1251 * memory (if fitted), and will check for it during startup, and use the 1252 * contents to initialise various internal parameters if it looks good. 1253 * 1254 * The offsets and field definitions below refer to where to find some 1255 * important values, and how to interpret them ... 1256 */ 1257 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1258 1259 /* 1260 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1261 */ 1262 1263 #define MII_AN_LPNXTPG 8 1264 #define MII_1000BASE_T_CONTROL 9 1265 #define MII_1000BASE_T_STATUS 10 1266 #define MII_IEEE_EXT_STATUS 15 1267 1268 /* 1269 * New bits in the MII_CONTROL register 1270 */ 1271 #define MII_CONTROL_1000MB 0x0040 1272 1273 /* 1274 * New bits in the MII_AN_ADVERT register 1275 */ 1276 #define MII_ABILITY_ASYM_PAUSE 0x0800 1277 #define MII_ABILITY_PAUSE 0x0400 1278 1279 /* 1280 * Values for the <selector> field of the MII_AN_ADVERT register 1281 */ 1282 #define MII_AN_SELECTOR_8023 0x0001 1283 1284 /* 1285 * Bits in the MII_1000BASE_T_CONTROL register 1286 * 1287 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1288 * (otherwise, roles are automatically negotiated). When this bit is set, 1289 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1290 */ 1291 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1292 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1293 #define MII_1000BT_CTL_ADV_FDX 0x0200 1294 #define MII_1000BT_CTL_ADV_HDX 0x0100 1295 1296 /* 1297 * Bits in the MII_1000BASE_T_STATUS register 1298 */ 1299 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1300 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1301 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1302 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1303 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1304 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1305 1306 /* 1307 * Vendor-specific MII registers 1308 */ 1309 #define MII_EXT_CONTROL MII_VENDOR(0) 1310 #define MII_EXT_STATUS MII_VENDOR(1) 1311 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1312 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1313 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1314 #define MII_AUX_CONTROL MII_VENDOR(8) 1315 #define MII_AUX_STATUS MII_VENDOR(9) 1316 #define MII_INTR_STATUS MII_VENDOR(10) 1317 #define MII_INTR_MASK MII_VENDOR(11) 1318 #define MII_HCD_STATUS MII_VENDOR(13) 1319 1320 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1321 1322 /* 1323 * Bits in the MII_EXT_CONTROL register 1324 */ 1325 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1326 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1327 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1328 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1329 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1330 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1331 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1332 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1333 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1334 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1335 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1336 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1337 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1338 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1339 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1340 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1341 1342 /* 1343 * Bits in the MII_EXT_STATUS register 1344 */ 1345 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1346 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1347 #define MII_EXT_STAT_MDIX_STATE 0x2000 1348 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1349 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1350 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1351 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1352 #define MII_EXT_STAT_LINK_STATUS 0x0100 1353 #define MII_EXT_STAT_CRC_ERROR 0x0080 1354 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1355 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1356 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1357 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1358 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1359 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1360 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1361 1362 /* 1363 * The AUX CONTROL register is seriously weird! 1364 * 1365 * It hides (up to) eight 'shadow' registers. When writing, which one 1366 * of them is written is determined by the low-order bits of the data 1367 * written(!), but when reading, which one is read is determined by the 1368 * value previously written to (part of) one of the shadow registers!!! 1369 */ 1370 1371 /* 1372 * Shadow register numbers 1373 */ 1374 #define MII_AUX_CTRL_NORMAL 0 1375 #define MII_AUX_CTRL_10BASE_T 1 1376 #define MII_AUX_CTRL_POWER 2 1377 #define MII_AUX_CTRL_TEST_1 4 1378 #define MII_AUX_CTRL_MISC 7 1379 1380 /* 1381 * Selected bits in some of the shadow registers ... 1382 */ 1383 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1384 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1385 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1386 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1387 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1388 1389 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1390 1391 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1392 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1393 1394 /* 1395 * Write this value to the AUX control register 1396 * to select which shadow register will be read 1397 */ 1398 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1399 1400 /* 1401 * Bits in the MII_AUX_STATUS register 1402 */ 1403 #define MII_AUX_STATUS_MODE_MASK 0x0700 1404 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1405 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1406 #define MII_AUX_STATUS_MODE_100_F 0x0500 1407 #define MII_AUX_STATUS_MODE_100_4 0x0400 1408 #define MII_AUX_STATUS_MODE_100_H 0x0300 1409 #define MII_AUX_STATUS_MODE_10_F 0x0200 1410 #define MII_AUX_STATUS_MODE_10_H 0x0100 1411 #define MII_AUX_STATUS_MODE_NONE 0x0000 1412 #define MII_AUX_STATUS_MODE_SHIFT 8 1413 1414 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1415 #define MII_AUX_STATUS_REM_FAULT 0x0040 1416 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1417 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1418 1419 #define MII_AUX_STATUS_LINKUP 0x0004 1420 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1421 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1422 1423 /* 1424 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1425 */ 1426 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1427 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1428 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1429 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1430 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1431 1432 1433 /* 1434 * Third section: 1435 * Hardware-defined data structures 1436 * 1437 * Note that the chip is naturally BIG-endian, so, for a big-endian 1438 * host, the structures defined below match those described in the PRM. 1439 * For little-endian hosts, some structures have to be swapped around. 1440 */ 1441 1442 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1443 #error Host endianness not defined 1444 #endif 1445 1446 /* 1447 * Architectural constants: absolute maximum numbers of each type of ring 1448 */ 1449 #ifdef BGE_EXT_MEM 1450 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1451 #else 1452 #define BGE_SEND_RINGS_MAX 4 1453 #endif 1454 #define BGE_SEND_RINGS_MAX_5705 1 1455 #define BGE_RECV_RINGS_MAX 16 1456 #define BGE_RECV_RINGS_MAX_5705 1 1457 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1458 /* only with ext mem) */ 1459 1460 #define BGE_SEND_SLOTS_MAX 512 1461 #define BGE_STD_SLOTS_MAX 512 1462 #define BGE_JUMBO_SLOTS_MAX 256 1463 #define BGE_MINI_SLOTS_MAX 1024 1464 #define BGE_RECV_SLOTS_MAX 2048 1465 #define BGE_RECV_SLOTS_5705 512 1466 #define BGE_RECV_SLOTS_5782 512 1467 #define BGE_RECV_SLOTS_5721 512 1468 1469 /* 1470 * Hardware-defined Ring Control Block 1471 */ 1472 typedef struct { 1473 uint64_t host_ring_addr; 1474 #ifdef _BIG_ENDIAN 1475 uint16_t max_len; 1476 uint16_t flags; 1477 uint32_t nic_ring_addr; 1478 #else 1479 uint32_t nic_ring_addr; 1480 uint16_t flags; 1481 uint16_t max_len; 1482 #endif /* _BIG_ENDIAN */ 1483 } bge_rcb_t; 1484 1485 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1486 #define RCB_FLAG_RING_DISABLED 0x0002 1487 1488 /* 1489 * Hardware-defined Send Buffer Descriptor 1490 */ 1491 typedef struct { 1492 uint64_t host_buf_addr; 1493 #ifdef _BIG_ENDIAN 1494 uint16_t len; 1495 uint16_t flags; 1496 uint16_t reserved; 1497 uint16_t vlan_tci; 1498 #else 1499 uint16_t vlan_tci; 1500 uint16_t reserved; 1501 uint16_t flags; 1502 uint16_t len; 1503 #endif /* _BIG_ENDIAN */ 1504 } bge_sbd_t; 1505 1506 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1507 #define SBD_FLAG_IP_CKSUM 0x0002 1508 #define SBD_FLAG_PACKET_END 0x0004 1509 #define SBD_FLAG_IP_FRAG 0x0008 1510 #define SBD_FLAG_IP_FRAG_END 0x0010 1511 1512 #define SBD_FLAG_VLAN_TAG 0x0040 1513 #define SBD_FLAG_COAL_NOW 0x0080 1514 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1515 #define SBD_FLAG_CPU_POST_DMA 0x0200 1516 1517 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1518 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1519 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1520 1521 /* 1522 * Hardware-defined Receive Buffer Descriptor 1523 */ 1524 typedef struct { 1525 uint64_t host_buf_addr; 1526 #ifdef _BIG_ENDIAN 1527 uint16_t index; 1528 uint16_t len; 1529 uint16_t type; 1530 uint16_t flags; 1531 uint16_t ip_cksum; 1532 uint16_t tcp_udp_cksum; 1533 uint16_t error_flag; 1534 uint16_t vlan_tci; 1535 uint32_t reserved; 1536 uint32_t opaque; 1537 #else 1538 uint16_t flags; 1539 uint16_t type; 1540 uint16_t len; 1541 uint16_t index; 1542 uint16_t vlan_tci; 1543 uint16_t error_flag; 1544 uint16_t tcp_udp_cksum; 1545 uint16_t ip_cksum; 1546 uint32_t opaque; 1547 uint32_t reserved; 1548 #endif /* _BIG_ENDIAN */ 1549 } bge_rbd_t; 1550 1551 #define RBD_FLAG_STD_RING 0x0000 1552 #define RBD_FLAG_PACKET_END 0x0004 1553 1554 #define RBD_FLAG_JUMBO_RING 0x0020 1555 #define RBD_FLAG_VLAN_TAG 0x0040 1556 1557 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1558 #define RBD_FLAG_MINI_RING 0x0800 1559 #define RBD_FLAG_IP_CHECKSUM 0x1000 1560 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1561 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1562 1563 #define RBD_FLAG_DEFAULT 0x0000 1564 1565 #define RBD_ERROR_BAD_CRC 0x00010000 1566 #define RBD_ERROR_COLL_DETECT 0x00020000 1567 #define RBD_ERROR_LINK_LOST 0x00040000 1568 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1569 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1570 #define RBD_ERROR_MAC_ABORT 0x00200000 1571 #define RBD_ERROR_LEN_LESS_64 0x00400000 1572 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1573 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1574 1575 /* 1576 * Hardware-defined Status Block,Size of status block 1577 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1578 * alignment.For BCM5705/5788/5721/5751/5752/5714 1579 * and 5715,there is only 1 recv and send ring index,but 1580 * driver defined 16 indexs here,please pay attention only 1581 * one ring is enabled in these chipsets. 1582 */ 1583 typedef struct { 1584 uint64_t flags_n_tag; 1585 uint16_t buff_cons_index[4]; 1586 struct { 1587 #ifdef _BIG_ENDIAN 1588 uint16_t send_cons_index; 1589 uint16_t recv_prod_index; 1590 #else 1591 uint16_t recv_prod_index; 1592 uint16_t send_cons_index; 1593 #endif /* _BIG_ENDIAN */ 1594 } index[16]; 1595 } bge_status_t; 1596 1597 /* 1598 * Hardware-defined Receive BD Rule 1599 */ 1600 typedef struct { 1601 uint32_t control; 1602 uint32_t mask_value; 1603 } bge_recv_rule_t; 1604 1605 /* 1606 * Indexes into the <buff_cons_index> array 1607 */ 1608 #ifdef _BIG_ENDIAN 1609 #define STATUS_STD_BUFF_CONS_INDEX 0 1610 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1611 #define STATUS_MINI_BUFF_CONS_INDEX 3 1612 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1613 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1614 #else 1615 #define STATUS_STD_BUFF_CONS_INDEX 3 1616 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1617 #define STATUS_MINI_BUFF_CONS_INDEX 0 1618 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1619 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1620 #endif /* _BIG_ENDIAN */ 1621 1622 /* 1623 * Bits in the <flags_n_tag> word 1624 */ 1625 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1626 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1627 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1628 #define STATUS_TAG_MASK 0x00000000000000FFull 1629 1630 /* 1631 * The tag from the status block is fed back to Interrupt Mailbox 0 1632 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1633 * lets the chip know what updates have been processed, so it can 1634 * reassert its interrupt if more updates have occurred since. 1635 * 1636 * These macros extract the tag from the <flags_n_tag> word, shift 1637 * it to the proper position in the Mailbox register, and provide 1638 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1639 * or enable interrupts 1640 */ 1641 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1642 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1643 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1644 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1645 1646 /* 1647 * Hardware-defined Statistics Block Offsets 1648 * 1649 * These are given in the manual as addresses in NIC memory, starting 1650 * from the NIC statistics area base address of 0x300; but here we 1651 * convert them into indexes into an array of (uint64_t)s, so we can 1652 * use them directly for accessing the copy of the statistics block 1653 * that the chip DMAs into main memory ... 1654 */ 1655 1656 #define KS_BASE 0x300 1657 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1658 1659 typedef enum { 1660 KS_ifHCInOctets = KS_ADDR(0x400), 1661 KS_etherStatsFragments = KS_ADDR(0x410), 1662 KS_ifHCInUcastPkts, 1663 KS_ifHCInMulticastPkts, 1664 KS_ifHCInBroadcastPkts, 1665 KS_dot3StatsFCSErrors, 1666 KS_dot3StatsAlignmentErrors, 1667 KS_xonPauseFramesReceived, 1668 KS_xoffPauseFramesReceived, 1669 KS_macControlFramesReceived, 1670 KS_xoffStateEntered, 1671 KS_dot3StatsFrameTooLongs, 1672 KS_etherStatsJabbers, 1673 KS_etherStatsUndersizePkts, 1674 KS_inRangeLengthError, 1675 KS_outRangeLengthError, 1676 KS_etherStatsPkts64Octets, 1677 KS_etherStatsPkts65to127Octets, 1678 KS_etherStatsPkts128to255Octets, 1679 KS_etherStatsPkts256to511Octets, 1680 KS_etherStatsPkts512to1023Octets, 1681 KS_etherStatsPkts1024to1518Octets, 1682 KS_etherStatsPkts1519to2047Octets, 1683 KS_etherStatsPkts2048to4095Octets, 1684 KS_etherStatsPkts4096to8191Octets, 1685 KS_etherStatsPkts8192to9022Octets, 1686 1687 KS_ifHCOutOctets = KS_ADDR(0x600), 1688 KS_etherStatsCollisions = KS_ADDR(0x610), 1689 KS_outXonSent, 1690 KS_outXoffSent, 1691 KS_flowControlDone, 1692 KS_dot3StatsInternalMacTransmitErrors, 1693 KS_dot3StatsSingleCollisionFrames, 1694 KS_dot3StatsMultipleCollisionFrames, 1695 KS_dot3StatsDeferredTransmissions, 1696 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1697 KS_dot3StatsLateCollisions, 1698 KS_dot3Collided2Times, 1699 KS_dot3Collided3Times, 1700 KS_dot3Collided4Times, 1701 KS_dot3Collided5Times, 1702 KS_dot3Collided6Times, 1703 KS_dot3Collided7Times, 1704 KS_dot3Collided8Times, 1705 KS_dot3Collided9Times, 1706 KS_dot3Collided10Times, 1707 KS_dot3Collided11Times, 1708 KS_dot3Collided12Times, 1709 KS_dot3Collided13Times, 1710 KS_dot3Collided14Times, 1711 KS_dot3Collided15Times, 1712 KS_ifHCOutUcastPkts, 1713 KS_ifHCOutMulticastPkts, 1714 KS_ifHCOutBroadcastPkts, 1715 KS_dot3StatsCarrierSenseErrors, 1716 KS_ifOutDiscards, 1717 KS_ifOutErrors, 1718 1719 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1720 KS_COSIfHCInPkts_2, 1721 KS_COSIfHCInPkts_3, 1722 KS_COSIfHCInPkts_4, 1723 KS_COSIfHCInPkts_5, 1724 KS_COSIfHCInPkts_6, 1725 KS_COSIfHCInPkts_7, 1726 KS_COSIfHCInPkts_8, 1727 KS_COSIfHCInPkts_9, 1728 KS_COSIfHCInPkts_10, 1729 KS_COSIfHCInPkts_11, 1730 KS_COSIfHCInPkts_12, 1731 KS_COSIfHCInPkts_13, 1732 KS_COSIfHCInPkts_14, 1733 KS_COSIfHCInPkts_15, 1734 KS_COSIfHCInPkts_16, 1735 KS_COSFramesDroppedDueToFilters, 1736 KS_nicDmaWriteQueueFull, 1737 KS_nicDmaWriteHighPriQueueFull, 1738 KS_nicNoMoreRxBDs, 1739 KS_ifInDiscards, 1740 KS_ifInErrors, 1741 KS_nicRecvThresholdHit, 1742 1743 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1744 KS_COSIfHCOutPkts_2, 1745 KS_COSIfHCOutPkts_3, 1746 KS_COSIfHCOutPkts_4, 1747 KS_COSIfHCOutPkts_5, 1748 KS_COSIfHCOutPkts_6, 1749 KS_COSIfHCOutPkts_7, 1750 KS_COSIfHCOutPkts_8, 1751 KS_COSIfHCOutPkts_9, 1752 KS_COSIfHCOutPkts_10, 1753 KS_COSIfHCOutPkts_11, 1754 KS_COSIfHCOutPkts_12, 1755 KS_COSIfHCOutPkts_13, 1756 KS_COSIfHCOutPkts_14, 1757 KS_COSIfHCOutPkts_15, 1758 KS_COSIfHCOutPkts_16, 1759 KS_nicDmaReadQueueFull, 1760 KS_nicDmaReadHighPriQueueFull, 1761 KS_nicSendDataCompQueueFull, 1762 KS_nicRingSetSendProdIndex, 1763 KS_nicRingStatusUpdate, 1764 KS_nicInterrupts, 1765 KS_nicAvoidedInterrupts, 1766 KS_nicSendThresholdHit, 1767 1768 KS_STATS_SIZE = KS_ADDR(0xb00) 1769 } bge_stats_offset_t; 1770 1771 /* 1772 * Hardware-defined Statistics Block 1773 * 1774 * Another view of the statistic block, as a array and a structure ... 1775 */ 1776 1777 typedef union { 1778 uint64_t a[KS_STATS_SIZE]; 1779 struct { 1780 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1781 1782 uint64_t ifHCInOctets; /* 0x0400 */ 1783 uint64_t spare2[1]; 1784 uint64_t etherStatsFragments; 1785 uint64_t ifHCInUcastPkts; 1786 uint64_t ifHCInMulticastPkts; 1787 uint64_t ifHCInBroadcastPkts; 1788 uint64_t dot3StatsFCSErrors; 1789 uint64_t dot3StatsAlignmentErrors; 1790 uint64_t xonPauseFramesReceived; 1791 uint64_t xoffPauseFramesReceived; 1792 uint64_t macControlFramesReceived; 1793 uint64_t xoffStateEntered; 1794 uint64_t dot3StatsFrameTooLongs; 1795 uint64_t etherStatsJabbers; 1796 uint64_t etherStatsUndersizePkts; 1797 uint64_t inRangeLengthError; 1798 uint64_t outRangeLengthError; 1799 uint64_t etherStatsPkts64Octets; 1800 uint64_t etherStatsPkts65to127Octets; 1801 uint64_t etherStatsPkts128to255Octets; 1802 uint64_t etherStatsPkts256to511Octets; 1803 uint64_t etherStatsPkts512to1023Octets; 1804 uint64_t etherStatsPkts1024to1518Octets; 1805 uint64_t etherStatsPkts1519to2047Octets; 1806 uint64_t etherStatsPkts2048to4095Octets; 1807 uint64_t etherStatsPkts4096to8191Octets; 1808 uint64_t etherStatsPkts8192to9022Octets; 1809 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1810 1811 uint64_t ifHCOutOctets; /* 0x0600 */ 1812 uint64_t spare4[1]; 1813 uint64_t etherStatsCollisions; 1814 uint64_t outXonSent; 1815 uint64_t outXoffSent; 1816 uint64_t flowControlDone; 1817 uint64_t dot3StatsInternalMacTransmitErrors; 1818 uint64_t dot3StatsSingleCollisionFrames; 1819 uint64_t dot3StatsMultipleCollisionFrames; 1820 uint64_t dot3StatsDeferredTransmissions; 1821 uint64_t spare5[1]; 1822 uint64_t dot3StatsExcessiveCollisions; 1823 uint64_t dot3StatsLateCollisions; 1824 uint64_t dot3Collided2Times; 1825 uint64_t dot3Collided3Times; 1826 uint64_t dot3Collided4Times; 1827 uint64_t dot3Collided5Times; 1828 uint64_t dot3Collided6Times; 1829 uint64_t dot3Collided7Times; 1830 uint64_t dot3Collided8Times; 1831 uint64_t dot3Collided9Times; 1832 uint64_t dot3Collided10Times; 1833 uint64_t dot3Collided11Times; 1834 uint64_t dot3Collided12Times; 1835 uint64_t dot3Collided13Times; 1836 uint64_t dot3Collided14Times; 1837 uint64_t dot3Collided15Times; 1838 uint64_t ifHCOutUcastPkts; 1839 uint64_t ifHCOutMulticastPkts; 1840 uint64_t ifHCOutBroadcastPkts; 1841 uint64_t dot3StatsCarrierSenseErrors; 1842 uint64_t ifOutDiscards; 1843 uint64_t ifOutErrors; 1844 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1845 1846 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1847 uint64_t COSFramesDroppedDueToFilters; 1848 uint64_t nicDmaWriteQueueFull; 1849 uint64_t nicDmaWriteHighPriQueueFull; 1850 uint64_t nicNoMoreRxBDs; 1851 uint64_t ifInDiscards; 1852 uint64_t ifInErrors; 1853 uint64_t nicRecvThresholdHit; 1854 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1855 1856 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1857 uint64_t nicDmaReadQueueFull; 1858 uint64_t nicDmaReadHighPriQueueFull; 1859 uint64_t nicSendDataCompQueueFull; 1860 uint64_t nicRingSetSendProdIndex; 1861 uint64_t nicRingStatusUpdate; 1862 uint64_t nicInterrupts; 1863 uint64_t nicAvoidedInterrupts; 1864 uint64_t nicSendThresholdHit; 1865 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1866 } s; 1867 } bge_statistics_t; 1868 1869 #define KS_STAT_REG_SIZE (0x1B) 1870 #define KS_STAT_REG_BASE (0x800) 1871 1872 typedef struct { 1873 uint32_t ifHCOutOctets; 1874 uint32_t etherStatsCollisions; 1875 uint32_t outXonSent; 1876 uint32_t outXoffSent; 1877 uint32_t dot3StatsInternalMacTransmitErrors; 1878 uint32_t dot3StatsSingleCollisionFrames; 1879 uint32_t dot3StatsMultipleCollisionFrames; 1880 uint32_t dot3StatsDeferredTransmissions; 1881 uint32_t dot3StatsExcessiveCollisions; 1882 uint32_t dot3StatsLateCollisions; 1883 uint32_t ifHCOutUcastPkts; 1884 uint32_t ifHCOutMulticastPkts; 1885 uint32_t ifHCOutBroadcastPkts; 1886 uint32_t ifHCInOctets; 1887 uint32_t etherStatsFragments; 1888 uint32_t ifHCInUcastPkts; 1889 uint32_t ifHCInMulticastPkts; 1890 uint32_t ifHCInBroadcastPkts; 1891 uint32_t dot3StatsFCSErrors; 1892 uint32_t dot3StatsAlignmentErrors; 1893 uint32_t xonPauseFramesReceived; 1894 uint32_t xoffPauseFramesReceived; 1895 uint32_t macControlFramesReceived; 1896 uint32_t xoffStateEntered; 1897 uint32_t dot3StatsFrameTooLongs; 1898 uint32_t etherStatsJabbers; 1899 uint32_t etherStatsUndersizePkts; 1900 } bge_statistics_reg_t; 1901 1902 1903 #ifdef BGE_IPMI_ASF 1904 1905 /* 1906 * Device internal memory entries 1907 */ 1908 1909 #define BGE_FIRMWARE_MAILBOX 0x0b50 1910 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1911 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1912 1913 1914 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1915 #define BGE_NIC_DATA_SIG 0x4b657654 1916 1917 1918 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1919 1920 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1921 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1922 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1923 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1924 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1925 1926 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1927 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1928 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1929 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1930 1931 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1932 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1933 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1934 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1935 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1936 #define BGE_NIC_CFG_MINI_PCI 0x001000 1937 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1938 #define BGE_NIC_CFG_5753_12x12 0x100000 1939 1940 1941 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1942 1943 1944 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1945 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1946 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1947 1948 1949 #define BGE_CMD_MAILBOX 0x0b78 1950 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1951 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1952 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1953 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1954 1955 1956 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 1957 #define BGE_CMD_DATA_MAILBOX 0x0b80 1958 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 1959 1960 #define BGE_DRV_STATE_MAILBOX 0x0c04 1961 #define BGE_DRV_STATE_START 0x00000001 1962 #define BGE_DRV_STATE_START_DONE 0x80000001 1963 #define BGE_DRV_STATE_UNLOAD 0x00000002 1964 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 1965 #define BGE_DRV_STATE_WOL 0x00000003 1966 #define BGE_DRV_STATE_SUSPEND 0x00000004 1967 1968 1969 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 1970 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 1971 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 1972 1973 1974 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 1975 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 1976 1977 1978 /* 1979 * RX-RISC event register 1980 */ 1981 #define RX_RISC_EVENT_REG 0x6810 1982 #define RRER_ASF_EVENT 0x4000 1983 1984 #endif /* BGE_IPMI_ASF */ 1985 1986 #ifdef __cplusplus 1987 } 1988 #endif 1989 1990 #endif /* _SYS_BGE_HW_H */ 1991