1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x16a7 60 #define DEVICE_ID_5703S 0x1647 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5705M 0x165d 68 #define DEVICE_ID_5705MA3 0x165e 69 #define DEVICE_ID_5705F 0x166e 70 #define DEVICE_ID_5780 0x166a 71 #define DEVICE_ID_5782 0x1696 72 #define DEVICE_ID_5787 0x169b 73 #define DEVICE_ID_5787M 0x1693 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5753 0x16fd 81 #define DEVICE_ID_5754 0x167a 82 #define DEVICE_ID_5755 0x167b 83 #define DEVICE_ID_5755M 0x1673 84 #define DEVICE_ID_5756M 0x1674 85 #define DEVICE_ID_5721 0x1659 86 #define DEVICE_ID_5722 0x165a 87 #define DEVICE_ID_5723 0x165b 88 #define DEVICE_ID_5714C 0x1668 89 #define DEVICE_ID_5714S 0x1669 90 #define DEVICE_ID_5715C 0x1678 91 #define DEVICE_ID_5715S 0x1679 92 #define DEVICE_ID_5761E 0x1680 93 #define DEVICE_ID_5761 0x1681 94 #define DEVICE_ID_5764 0x1684 95 #define DEVICE_ID_5906 0x1712 96 #define DEVICE_ID_5906M 0x1713 97 98 #define REVISION_ID_5700_B0 0x10 99 #define REVISION_ID_5700_B2 0x12 100 #define REVISION_ID_5700_B3 0x13 101 #define REVISION_ID_5700_C0 0x20 102 #define REVISION_ID_5700_C1 0x21 103 #define REVISION_ID_5700_C2 0x22 104 105 #define REVISION_ID_5701_A0 0x08 106 #define REVISION_ID_5701_A2 0x12 107 #define REVISION_ID_5701_A3 0x15 108 109 #define REVISION_ID_5702_A0 0x00 110 111 #define REVISION_ID_5703_A0 0x00 112 #define REVISION_ID_5703_A1 0x01 113 #define REVISION_ID_5703_A2 0x02 114 115 #define REVISION_ID_5704_A0 0x00 116 #define REVISION_ID_5704_A1 0x01 117 #define REVISION_ID_5704_A2 0x02 118 #define REVISION_ID_5704_A3 0x03 119 #define REVISION_ID_5704_B0 0x10 120 121 #define REVISION_ID_5705_A0 0x00 122 #define REVISION_ID_5705_A1 0x01 123 #define REVISION_ID_5705_A2 0x02 124 #define REVISION_ID_5705_A3 0x03 125 126 #define REVISION_ID_5721_A0 0x00 127 #define REVISION_ID_5721_A1 0x01 128 129 #define REVISION_ID_5751_A0 0x00 130 #define REVISION_ID_5751_A1 0x01 131 132 #define REVISION_ID_5714_A0 0x00 133 #define REVISION_ID_5714_A1 0x01 134 #define REVISION_ID_5714_A2 0xA2 135 #define REVISION_ID_5714_A3 0xA3 136 137 #define REVISION_ID_5715_A0 0x00 138 #define REVISION_ID_5715_A1 0x01 139 #define REVISION_ID_5715_A2 0xA2 140 141 #define REVISION_ID_5715S_A0 0x00 142 #define REVISION_ID_5715S_A1 0x01 143 144 #define REVISION_ID_5754_A0 0x00 145 #define REVISION_ID_5754_A1 0x01 146 147 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 148 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 149 (bgep->chipid.device == DEVICE_ID_5701) ||\ 150 (bgep->chipid.device == DEVICE_ID_5702) ||\ 151 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 152 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 153 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 154 (bgep->chipid.device == DEVICE_ID_5703) ||\ 155 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 156 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 157 (bgep->chipid.device == DEVICE_ID_5704)) 158 159 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 160 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 161 (bgep->chipid.device == DEVICE_ID_5702fe)) 162 163 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 164 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 165 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 166 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 167 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 168 (bgep->chipid.device == DEVICE_ID_5780) ||\ 169 (bgep->chipid.device == DEVICE_ID_5782) ||\ 170 (bgep->chipid.device == DEVICE_ID_5788) ||\ 171 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 172 (bgep->chipid.device == DEVICE_ID_5754) ||\ 173 (bgep->chipid.device == DEVICE_ID_5755) ||\ 174 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 175 (bgep->chipid.device == DEVICE_ID_5753)) 176 177 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 178 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 179 (bgep->chipid.device == DEVICE_ID_5751) ||\ 180 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 181 (bgep->chipid.device == DEVICE_ID_5752) ||\ 182 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 183 (bgep->chipid.device == DEVICE_ID_5789)) 184 185 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 186 ((bgep->chipid.device == DEVICE_ID_5723) ||\ 187 (bgep->chipid.device == DEVICE_ID_5761) ||\ 188 (bgep->chipid.device == DEVICE_ID_5761E) ||\ 189 (bgep->chipid.device == DEVICE_ID_5764)) 190 191 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 192 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 193 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 194 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 195 (bgep->chipid.device == DEVICE_ID_5715S)) 196 197 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 198 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 199 (bgep->chipid.device == DEVICE_ID_5906M)) 200 201 /* 202 * Second section: 203 * Offsets of important registers & definitions for bits therein 204 */ 205 206 /* 207 * PCI-X registers & bits 208 */ 209 #define PCIX_CONF_COMM 0x42 210 #define PCIX_COMM_RELAXED 0x0002 211 212 /* 213 * Miscellaneous Host Control Register, in PCI config space 214 */ 215 #define PCI_CONF_BGE_MHCR 0x68 216 #define MHCR_CHIP_REV_MASK 0xffff0000 217 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 218 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 219 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 220 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 221 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 222 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 223 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 224 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 225 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 226 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 227 228 #define MHCR_CHIP_REV_5700_B0 0x71000000 229 #define MHCR_CHIP_REV_5700_B2 0x71020000 230 #define MHCR_CHIP_REV_5700_B3 0x71030000 231 #define MHCR_CHIP_REV_5700_C0 0x72000000 232 #define MHCR_CHIP_REV_5700_C1 0x72010000 233 #define MHCR_CHIP_REV_5700_C2 0x72020000 234 235 #define MHCR_CHIP_REV_5701_A0 0x00000000 236 #define MHCR_CHIP_REV_5701_A2 0x00020000 237 #define MHCR_CHIP_REV_5701_A3 0x00030000 238 #define MHCR_CHIP_REV_5701_A5 0x01050000 239 240 #define MHCR_CHIP_REV_5702_A0 0x10000000 241 #define MHCR_CHIP_REV_5702_A1 0x10010000 242 #define MHCR_CHIP_REV_5702_A2 0x10020000 243 244 #define MHCR_CHIP_REV_5703_A0 0x10000000 245 #define MHCR_CHIP_REV_5703_A1 0x10010000 246 #define MHCR_CHIP_REV_5703_A2 0x10020000 247 #define MHCR_CHIP_REV_5703_B0 0x11000000 248 #define MHCR_CHIP_REV_5703_B1 0x11010000 249 250 #define MHCR_CHIP_REV_5704_A0 0x20000000 251 #define MHCR_CHIP_REV_5704_A1 0x20010000 252 #define MHCR_CHIP_REV_5704_A2 0x20020000 253 #define MHCR_CHIP_REV_5704_A3 0x20030000 254 #define MHCR_CHIP_REV_5704_B0 0x21000000 255 256 #define MHCR_CHIP_REV_5705_A0 0x30000000 257 #define MHCR_CHIP_REV_5705_A1 0x30010000 258 #define MHCR_CHIP_REV_5705_A2 0x30020000 259 #define MHCR_CHIP_REV_5705_A3 0x30030000 260 #define MHCR_CHIP_REV_5705_A5 0x30050000 261 262 #define MHCR_CHIP_REV_5782_A0 0x30030000 263 #define MHCR_CHIP_REV_5782_A1 0x30030088 264 265 #define MHCR_CHIP_REV_5788_A1 0x30050000 266 267 #define MHCR_CHIP_REV_5751_A0 0x40000000 268 #define MHCR_CHIP_REV_5751_A1 0x40010000 269 270 #define MHCR_CHIP_REV_5721_A0 0x41000000 271 #define MHCR_CHIP_REV_5721_A1 0x41010000 272 273 #define MHCR_CHIP_REV_5714_A0 0x50000000 274 #define MHCR_CHIP_REV_5714_A1 0x90010000 275 276 #define MHCR_CHIP_REV_5715_A0 0x50000000 277 #define MHCR_CHIP_REV_5715_A1 0x90010000 278 279 #define MHCR_CHIP_REV_5715S_A0 0x50000000 280 #define MHCR_CHIP_REV_5715S_A1 0x90010000 281 282 #define MHCR_CHIP_REV_5754_A0 0xb0000000 283 #define MHCR_CHIP_REV_5754_A1 0xb0010000 284 285 #define MHCR_CHIP_REV_5787_A0 0xb0000000 286 #define MHCR_CHIP_REV_5787_A1 0xb0010000 287 #define MHCR_CHIP_REV_5787_A2 0xb0020000 288 289 #define MHCR_CHIP_REV_5755_A0 0xa0000000 290 #define MHCR_CHIP_REV_5755_A1 0xa0010000 291 292 #define MHCR_CHIP_REV_5906_A0 0xc0000000 293 #define MHCR_CHIP_REV_5906_A1 0xc0010000 294 #define MHCR_CHIP_REV_5906_A2 0xc0020000 295 296 #define MHCR_CHIP_REV_5723_A0 0xf0000000 297 #define MHCR_CHIP_REV_5723_A1 0xf0010000 298 #define MHCR_CHIP_REV_5723_A2 0xf0020000 299 #define MHCR_CHIP_REV_5723_B0 0xf1000000 300 301 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 302 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 303 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 304 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 305 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 306 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 307 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 308 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 309 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 310 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 311 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 312 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 313 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 314 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 315 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 316 317 318 /* 319 * PCI DMA read/write Control Register, in PCI config space 320 * 321 * Note that several fields previously defined here have been deleted 322 * as they are not implemented in the 5703/4. 323 * 324 * Note: the value of this register is critical. It is possible to 325 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 326 * by programming the wrong value. The value #defined below has been 327 * tested and shown to avoid all known problems. If it is to be changed, 328 * correct operation must be reverified on all supported platforms. 329 * 330 * In particular, we set both watermark fields to 2xCacheLineSize (128) 331 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 332 * with Tomatillo's internal pipelines, that otherwise result in stalls, 333 * repeated retries, and DTOs. 334 */ 335 #define PCI_CONF_BGE_PDRWCR 0x6c 336 #define PDRWCR_RWCMD_MASK 0xFF000000 337 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 338 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 339 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 340 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 341 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 342 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 343 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 344 345 /* 346 * These are the actual values to be put into the fields shown above 347 */ 348 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 349 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 350 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 351 #define PDRWCR_MIN_BEATS 0x00000000 352 353 #define PDRWCR_VAR_DEFAULT 0x761b0000 354 #define PDRWCR_VAR_5721 0x76180000 355 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 356 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 357 358 /* 359 * PCI State Register, in PCI config space 360 * 361 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 362 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 363 */ 364 #define PCI_CONF_BGE_PCISTATE 0x70 365 #define PCISTATE_RETRY_SAME_DMA 0x00002000 366 #define PCISTATE_FLAT_VIEW 0x00000100 367 #define PCISTATE_EXT_ROM_RETRY 0x00000040 368 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 369 #define PCISTATE_BUS_IS_32_BIT 0x00000010 370 #define PCISTATE_BUS_IS_FAST 0x00000008 371 #define PCISTATE_BUS_IS_PCI 0x00000004 372 #define PCISTATE_INTA_STATE 0x00000002 373 #define PCISTATE_FORCE_RESET 0x00000001 374 375 /* 376 * PCI Clock Control Register, in PCI config space 377 */ 378 #define PCI_CONF_BGE_CLKCTL 0x74 379 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 380 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 381 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 382 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 383 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 384 #define CLKCTL_PCIE_A0_FIX 0x00101000 385 386 /* 387 * Dual MAC Control Register, in PCI config space 388 */ 389 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 390 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 391 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 392 393 /* 394 * Register Indirect Access Address Register, 0x78 in PCI config 395 * space. Once this is set, accesses to the Register Indirect 396 * Access Data Register (0x80) refer to the register whose address 397 * is given by *this* register. This allows access to all the 398 * operating registers, while using only config space accesses. 399 * 400 * Note that the address written to the RIIAR should lie in one 401 * of the following ranges: 402 * 0x00000000 <= address < 0x00008000 (regular registers) 403 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 404 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 405 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 406 */ 407 #define PCI_CONF_BGE_RIAAR 0x78 408 #define PCI_CONF_BGE_RIADR 0x80 409 410 #define RIAAR_REGISTER_MIN 0x00000000 411 #define RIAAR_REGISTER_MAX 0x00008000 412 #define RIAAR_RX_SCRATCH_MIN 0x00030000 413 #define RIAAR_RX_SCRATCH_MAX 0x00034000 414 #define RIAAR_TX_SCRATCH_MIN 0x00034000 415 #define RIAAR_TX_SCRATCH_MAX 0x00038000 416 #define RIAAR_RXROM_MIN 0x00038000 417 #define RIAAR_RXROM_MAX 0x00038800 418 419 /* 420 * Memory Window Base Address Register, 0x7c in PCI config space 421 * Once this is set, accesses to the Memory Window Data Access Register 422 * (0x84) refer to the word of NIC-local memory whose address is given 423 * by this register. When used in this way, the whole of the address 424 * written to this register is significant. 425 * 426 * This register also provides the 32K-aligned base address for a 32K 427 * region of NIC-local memory that the host can directly address in 428 * the upper 32K of the 64K of PCI memory space allocated to the chip. 429 * In this case, the bottom 15 bits of the register are ignored. 430 * 431 * Note that the address written to the MWBAR should lie in the range 432 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 433 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 434 * memory were present, but it's only supported on the 5700, not the 435 * 5701/5703/5704. 436 */ 437 #define PCI_CONF_BGE_MWBAR 0x7c 438 #define PCI_CONF_BGE_MWDAR 0x84 439 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 440 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 441 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 442 443 /* 444 * The PCI express device control register and device status register 445 * which are only applicable on BCM5751 and BCM5721. 446 */ 447 #define PCI_CONF_DEV_CTRL 0xd8 448 #define PCI_CONF_DEV_CTRL_5723 0xd4 449 #define READ_REQ_SIZE_MAX 0x5000 450 #define DEV_CTRL_NO_SNOOP 0x0800 451 #define DEV_CTRL_RELAXED 0x0010 452 453 #define PCI_CONF_DEV_STUS 0xda 454 #define PCI_CONF_DEV_STUS_5723 0xd6 455 #define DEVICE_ERROR_STUS 0xf 456 457 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 458 459 /* 460 * Where to find things in NIC-local (on-chip) memory 461 */ 462 #define NIC_MEM_SEND_RINGS 0x0100 463 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 464 #define NIC_MEM_RECV_RINGS 0x0200 465 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 466 #define NIC_MEM_STATISTICS 0x0300 467 #define NIC_MEM_STATISTICS_SIZE 0x0800 468 #define NIC_MEM_STATUS_BLOCK 0x0b00 469 #define NIC_MEM_STATUS_SIZE 0x0050 470 #define NIC_MEM_GENCOMM 0x0b50 471 472 473 /* 474 * Note: the (non-bogus) values below are appropriate for systems 475 * without external memory. They would be different on a 5700 with 476 * external memory. 477 * 478 * Note: The higher send ring addresses and the mini ring shadow 479 * buffer address are dummies - systems without external memory 480 * are limited to 4 send rings and no mini receive ring. 481 */ 482 #define NIC_MEM_SHADOW_DMA 0x2000 483 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 484 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 485 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 486 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 487 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 488 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 489 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 490 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 491 492 /* 493 * Put this in the GENCOMM port to tell the firmware not to run PXE 494 */ 495 #define T3_MAGIC_NUMBER 0x4b657654u 496 497 /* 498 * The remaining registers appear in the low 32K of regular 499 * PCI Memory Address Space 500 */ 501 502 /* 503 * All the state machine control registers below have at least a 504 * <RESET> bit and an <ENABLE> bit as defined below. Some also 505 * have an <ATTN_ENABLE> bit. 506 */ 507 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 508 #define STATE_MACHINE_ENABLE_BIT 0x00000002 509 #define STATE_MACHINE_RESET_BIT 0x00000001 510 511 #define TRANSMIT_MAC_MODE_REG 0x045c 512 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 513 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 514 #define SEND_BD_SELECTOR_MODE_REG 0x1400 515 #define SEND_BD_INITIATOR_MODE_REG 0x1800 516 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 517 518 #define RECEIVE_MAC_MODE_REG 0x0468 519 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 520 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 521 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 522 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 523 #define RCV_BD_COMPLETION_MODE_REG 0x3000 524 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 525 526 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 527 #define HOST_COALESCE_MODE_REG 0x3c00 528 #define MEMORY_ARBITER_MODE_REG 0x4000 529 #define BUFFER_MANAGER_MODE_REG 0x4400 530 #define READ_DMA_MODE_REG 0x4800 531 #define WRITE_DMA_MODE_REG 0x4c00 532 #define DMA_COMPLETION_MODE_REG 0x6400 533 534 /* 535 * Other bits in some of the above state machine control registers 536 */ 537 538 /* 539 * Transmit MAC Mode Register 540 * (TRANSMIT_MAC_MODE_REG, 0x045c) 541 */ 542 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 543 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 544 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 545 546 /* 547 * Receive MAC Mode Register 548 * (RECEIVE_MAC_MODE_REG, 0x0468) 549 */ 550 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 551 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 552 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 553 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 554 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 555 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 556 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 557 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 558 559 /* 560 * Receive BD Initiator Mode Register 561 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 562 * 563 * Each of these bits controls whether ATTN is asserted 564 * on a particular condition 565 */ 566 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 567 568 /* 569 * Receive Data & Receive BD Initiator Mode Register 570 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 571 * 572 * Each of these bits controls whether ATTN is asserted 573 * on a particular condition 574 */ 575 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 576 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 577 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 578 579 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 580 581 /* 582 * Host Coalescing Mode Control Register 583 * (HOST_COALESCE_MODE_REG, 0x3c00) 584 */ 585 #define COALESCE_64_BYTE_RINGS 12 586 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 587 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 588 #define COALESCE_CLR_TICKS_TX 0x00000400 589 #define COALESCE_CLR_TICKS_RX 0x00000200 590 #define COALESCE_32_BYTE_STATUS 0x00000100 591 #define COALESCE_64_BYTE_STATUS 0x00000080 592 #define COALESCE_NOW 0x00000008 593 594 /* 595 * Memory Arbiter Mode Register 596 * (MEMORY_ARBITER_MODE_REG, 0x4000) 597 */ 598 #define MEMORY_ARBITER_ENABLE 0x00000002 599 600 /* 601 * Buffer Manager Mode Register 602 * (BUFFER_MANAGER_MODE_REG, 0x4400) 603 * 604 * In addition to the usual error-attn common to most state machines 605 * this register has a separate bit for attn on running-low-on-mbufs 606 */ 607 #define BUFF_MGR_TEST_MODE 0x00000008 608 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 609 610 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 611 612 /* 613 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 614 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 615 * 616 * These registers each contain a 2-bit priority field, which controls 617 * the relative priority of that type of DMA (read vs. write vs. MSI), 618 * and a set of bits that control whether ATTN is asserted on each 619 * particular condition 620 */ 621 #define DMA_PRIORITY_MASK 0xc0000000 622 #define DMA_PRIORITY_SHIFT 30 623 #define ALL_DMA_ATTN_BITS 0x000003fc 624 625 /* 626 * BCM5755, 5755M, 5906, 5906M only 627 * 1 - Enable Fix. Device will send out the status block before 628 * the interrupt message 629 * 0 - Disable fix. Device will send out the interrupt message 630 * before the status block 631 */ 632 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 633 634 /* 635 * End of state machine control register definitions 636 */ 637 638 639 /* 640 * High priority mailbox registers. 641 * Mailbox Registers (8 bytes each, but high half unused) 642 */ 643 #define INTERRUPT_MBOX_0_REG 0x0200 644 #define INTERRUPT_MBOX_1_REG 0x0208 645 #define INTERRUPT_MBOX_2_REG 0x0210 646 #define INTERRUPT_MBOX_3_REG 0x0218 647 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 648 649 /* 650 * Low priority mailbox registers, for BCM5906, BCM5906M. 651 */ 652 #define INTERRUPT_LP_MBOX_0_REG 0x5800 653 654 /* 655 * Ring Producer/Consumer Index (Mailbox) Registers 656 */ 657 #define RECV_STD_PROD_INDEX_REG 0x0268 658 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 659 #define RECV_MINI_PROD_INDEX_REG 0x0278 660 #define RECV_RING_CONS_INDEX_REGS 0x0280 661 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 662 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 663 664 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 665 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 666 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 667 668 /* 669 * Ethernet MAC Mode Register 670 */ 671 #define ETHERNET_MAC_MODE_REG 0x0400 672 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 673 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 674 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 675 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 676 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 677 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 678 #define ETHERNET_MODE_SEND_CFGS 0x00020000 679 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 680 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 681 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 682 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 683 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 684 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 685 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 686 #define ETHERNET_MODE_MAX_DEFER 0x00000200 687 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 688 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 689 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 690 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 691 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 692 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 693 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 694 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 695 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 696 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 697 698 /* 699 * Ethernet MAC Status & Event Registers 700 */ 701 #define ETHERNET_MAC_STATUS_REG 0x0404 702 #define ETHERNET_STATUS_MI_INT 0x00800000 703 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 704 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 705 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 706 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 707 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 708 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 709 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 710 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 711 712 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 713 #define ETHERNET_EVENT_MI_INT 0x00800000 714 #define ETHERNET_EVENT_LINK_INT 0x00001000 715 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 716 717 /* 718 * Ethernet MAC LED Control Register 719 * 720 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 721 * the external LED driver circuitry is wired up to assume that this mode 722 * will always be selected. Software must not change it! 723 */ 724 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 725 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 726 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 727 #define LED_CONTROL_LED_MODE_MASK 0x00001800 728 #define LED_CONTROL_LED_MODE_5700 0x00000000 729 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 730 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 731 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 732 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 733 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 734 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 735 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 736 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 737 #define LED_CONTROL_TRAFFIC_LED 0x00000020 738 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 739 #define LED_CONTROL_10MBPS_LED 0x00000008 740 #define LED_CONTROL_100MBPS_LED 0x00000004 741 #define LED_CONTROL_1000MBPS_LED 0x00000002 742 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 743 #define LED_CONTROL_DEFAULT 0x02000800 744 745 /* 746 * MAC Address registers 747 * 748 * These four eight-byte registers each hold one unicast address 749 * (six bytes), right justified & zero-filled on the left. 750 * They will normally all be set to the same value, as a station 751 * usually only has one h/w address. The value in register 0 is 752 * used for pause packets; any of the four can be specified for 753 * substitution into other transmitted packets if required. 754 */ 755 #define MAC_ADDRESS_0_REG 0x0410 756 #define MAC_ADDRESS_1_REG 0x0418 757 #define MAC_ADDRESS_2_REG 0x0420 758 #define MAC_ADDRESS_3_REG 0x0428 759 760 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 761 #define MAC_ADDRESS_REGS_MAX 4 762 763 /* 764 * More MAC Registers ... 765 */ 766 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 767 #define MAC_RX_MTU_SIZE_REG 0x043c 768 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 769 #define MAC_TX_LENGTHS_REG 0x0464 770 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 771 772 /* 773 * MII access registers 774 */ 775 #define MI_COMMS_REG 0x044c 776 #define MI_COMMS_START 0x20000000 777 #define MI_COMMS_READ_FAILED 0x10000000 778 #define MI_COMMS_COMMAND_MASK 0x0c000000 779 #define MI_COMMS_COMMAND_READ 0x08000000 780 #define MI_COMMS_COMMAND_WRITE 0x04000000 781 #define MI_COMMS_ADDRESS_MASK 0x03e00000 782 #define MI_COMMS_ADDRESS_SHIFT 21 783 #define MI_COMMS_REGISTER_MASK 0x001f0000 784 #define MI_COMMS_REGISTER_SHIFT 16 785 #define MI_COMMS_DATA_MASK 0x0000ffff 786 #define MI_COMMS_DATA_SHIFT 0 787 788 #define MI_STATUS_REG 0x0450 789 #define MI_STATUS_10MBPS 0x00000002 790 #define MI_STATUS_LINK 0x00000001 791 792 #define MI_MODE_REG 0x0454 793 #define MI_MODE_CLOCK_MASK 0x001f0000 794 #define MI_MODE_AUTOPOLL 0x00000010 795 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 796 #define MI_MODE_DEFAULT 0x000c0000 797 798 #define MI_AUTOPOLL_STATUS_REG 0x0458 799 #define MI_AUTOPOLL_ERROR 0x00000001 800 801 #define TRANSMIT_MAC_STATUS_REG 0x0460 802 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 803 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 804 #define TRANSMIT_STATUS_LINK_UP 0x00000008 805 #define TRANSMIT_STATUS_SENT_XON 0x00000004 806 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 807 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 808 809 #define RECEIVE_MAC_STATUS_REG 0x046c 810 #define RECEIVE_STATUS_RCVD_XON 0x00000004 811 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 812 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 813 814 /* 815 * These four-byte registers constitute a hash table for deciding 816 * whether to accept incoming multicast packets. The bits are 817 * numbered in big-endian fashion, from hash 0 => the MSB of 818 * register 0 to hash 127 => the LSB of the highest-numbered 819 * register. 820 * 821 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 822 * enabled by setting the appropriate bit in the Rx MAC mode 823 * register. Otherwise, and on all earlier chips, the table 824 * is only 128 bits (registers 0-3). 825 */ 826 #define MAC_HASH_0_REG 0x0470 827 #define MAC_HASH_1_REG 0x0474 828 #define MAC_HASH_2_REG 0x0478 829 #define MAC_HASH_3_REG 0x047c 830 #define MAC_HASH_4_REG 0x???? 831 #define MAC_HASH_5_REG 0x???? 832 #define MAC_HASH_6_REG 0x???? 833 #define MAC_HASH_7_REG 0x???? 834 #define MAC_HASH_REG(n) (0x470+4*(n)) 835 836 /* 837 * Receive Rules Registers: 16 pairs of control+mask/value pairs 838 */ 839 #define RCV_RULES_CONTROL_0_REG 0x0480 840 #define RCV_RULES_MASK_0_REG 0x0484 841 #define RCV_RULES_CONTROL_15_REG 0x04f8 842 #define RCV_RULES_MASK_15_REG 0x04fc 843 #define RCV_RULES_CONFIG_REG 0x0500 844 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 845 846 #define RECV_RULES_NUM_MAX 16 847 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 848 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 849 850 #define RECV_RULE_CTL_ENABLE 0x80000000 851 #define RECV_RULE_CTL_AND 0x40000000 852 #define RECV_RULE_CTL_P1 0x20000000 853 #define RECV_RULE_CTL_P2 0x10000000 854 #define RECV_RULE_CTL_P3 0x08000000 855 #define RECV_RULE_CTL_MASK 0x04000000 856 #define RECV_RULE_CTL_DISCARD 0x02000000 857 #define RECV_RULE_CTL_MAP 0x01000000 858 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 859 #define RECV_RULE_CTL_OP 0x00030000 860 #define RECV_RULE_CTL_OP_EQ 0x00000000 861 #define RECV_RULE_CTL_OP_NEQ 0x00010000 862 #define RECV_RULE_CTL_OP_GREAT 0x00020000 863 #define RECV_RULE_CTL_OP_LESS 0x00030000 864 #define RECV_RULE_CTL_HEADER 0x0000e000 865 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 866 #define RECV_RULE_CTL_HEADER_IP 0x00002000 867 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 868 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 869 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 870 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 871 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 872 RECV_RULE_CTL_CLASS_BITS) 873 #define RECV_RULE_CTL_OFFSET 0x000000ff 874 875 /* 876 * Receive Rules definition 877 */ 878 #define ETHERHEADER_DEST_OFFSET 0x00 879 #define IPHEADER_PROTO_OFFSET 0x08 880 #define IPHEADER_SIP_OFFSET 0x0c 881 #define IPHEADER_DIP_OFFSET 0x10 882 #define TCPHEADER_SPORT_OFFSET 0x00 883 #define TCPHEADER_DPORT_OFFSET 0x02 884 #define UDPHEADER_SPORT_OFFSET 0x00 885 #define UDPHEADER_DPORT_OFFSET 0x02 886 887 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 888 RECV_RULE_CTL_CLASS((ring))) 889 890 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 891 892 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 893 RECV_RULE_CTL_HEADER_FRAME | \ 894 ETHERHEADER_DEST_OFFSET) 895 896 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 897 RECV_RULE_CTL_HEADER_FRAME | \ 898 ETHERHEADER_DEST_OFFSET + 4) 899 900 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 901 IPHEADER_DIP_OFFSET) 902 903 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 904 IPHEADER_SIP_OFFSET) 905 906 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 907 RECV_RULE_CTL_HEADER_IP | \ 908 IPHEADER_PROTO_OFFSET) 909 910 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 911 RECV_RULE_CTL_HEADER_TCP | \ 912 TCPHEADER_SPORT_OFFSET) 913 914 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 915 RECV_RULE_CTL_HEADER_TCP | \ 916 TCPHEADER_DPORT_OFFSET) 917 918 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 919 RECV_RULE_CTL_HEADER_UDP | \ 920 UDPHEADER_SPORT_OFFSET) 921 922 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 923 RECV_RULE_CTL_HEADER_UDP | \ 924 UDPHEADER_DPORT_OFFSET) 925 926 /* 927 * 1000BaseX low-level access registers 928 */ 929 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 930 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 931 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 932 #define TX_1000BASEX_AUTONEG_REG 0x0444 933 #define RX_1000BASEX_AUTONEG_REG 0x0448 934 935 /* 936 * Autoneg code bits for the 1000BASE-X AUTONEG registers 937 */ 938 #define AUTONEG_CODE_PAUSE 0x00008000 939 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 940 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 941 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 942 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 943 #define AUTONEG_CODE_FAULT_MASK 0x00000030 944 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 945 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 946 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 947 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 948 949 /* 950 * SerDes Registers (5703S/5704S only) 951 */ 952 #define SERDES_CONTROL_REG 0x0590 953 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 954 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 955 #define SERDES_CONTROL_TX_DISABLE 0x00004000 956 #define SERDES_STATUS_REG 0x0594 957 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 958 #define SERDES_STATUS_RXSTAT 0x000000ff 959 960 /* 961 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 962 */ 963 #define STAT_IFHCOUT_OCTETS_REG 0x0800 964 #define STAT_ETHER_COLLIS_REG 0x0808 965 #define STAT_OUTXON_SENT_REG 0x080c 966 #define STAT_OUTXOFF_SENT_REG 0x0810 967 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 968 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 969 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 970 #define STAT_DOT3_DEFERED_TX_REG 0x0824 971 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 972 #define STAT_DOT3_LATE_COLLI_REG 0x0830 973 #define STAT_IFHCOUT_UPKGS_REG 0x086c 974 #define STAT_IFHCOUT_MPKGS_REG 0x0870 975 #define STAT_IFHCOUT_BPKGS_REG 0x0874 976 977 #define STAT_IFHCIN_OCTETS_REG 0x0880 978 #define STAT_ETHER_FRAGMENT_REG 0x0888 979 #define STAT_IFHCIN_UPKGS_REG 0x088c 980 #define STAT_IFHCIN_MPKGS_REG 0x0890 981 #define STAT_IFHCIN_BPKGS_REG 0x0894 982 983 #define STAT_DOT3_FCS_ERR_REG 0x0898 984 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 985 #define STAT_XON_PAUSE_RX_REG 0x08a0 986 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 987 #define STAT_MAC_CTRL_RX_REG 0x08a8 988 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 989 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 990 #define STAT_ETHER_JABBERS_REG 0x08b4 991 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 992 #define SIZE_OF_STATISTIC_REG 0x1B 993 /* 994 * Send Data Initiator Registers 995 */ 996 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 997 #define SEND_INIT_STATS_ZERO 0x00000010 998 #define SEND_INIT_STATS_FLUSH 0x00000008 999 #define SEND_INIT_STATS_CLEAR 0x00000004 1000 #define SEND_INIT_STATS_FASTER 0x00000002 1001 #define SEND_INIT_STATS_ENABLE 0x00000001 1002 1003 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 1004 1005 /* 1006 * Send Buffer Descriptor Selector Control Registers 1007 */ 1008 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 1009 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 1010 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 1011 1012 /* 1013 * Receive List Placement Registers 1014 */ 1015 #define RCV_LP_CONFIG_REG 0x2010 1016 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1017 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1018 1019 #define RCV_LP_STATS_CONTROL_REG 0x2014 1020 #define RCV_LP_STATS_ZERO 0x00000010 1021 #define RCV_LP_STATS_FLUSH 0x00000008 1022 #define RCV_LP_STATS_CLEAR 0x00000004 1023 #define RCV_LP_STATS_FASTER 0x00000002 1024 #define RCV_LP_STATS_ENABLE 0x00000001 1025 1026 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1027 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1028 1029 /* 1030 * Receive Data & BD Initiator Registers 1031 */ 1032 #define RCV_INITIATOR_STATUS_REG 0x2404 1033 1034 /* 1035 * Receive Buffer Descriptor Ring Control Block Registers 1036 * NB: sixteen bytes (128 bits) each 1037 */ 1038 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1039 #define STD_RCV_BD_RING_RCB_REG 0x2450 1040 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1041 1042 /* 1043 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1044 */ 1045 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1046 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1047 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1048 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1049 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1050 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1051 1052 /* 1053 * Host Coalescing Engine Control Registers 1054 */ 1055 #define RCV_COALESCE_TICKS_REG 0x3c08 1056 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1057 #define SEND_COALESCE_TICKS_REG 0x3c0c 1058 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1059 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1060 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1061 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1062 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1063 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1064 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1065 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1066 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1067 #define RCV_COALESCE_INT_BD_REG 0x3c20 1068 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1069 #define SEND_COALESCE_INT_BD_REG 0x3c24 1070 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1071 #define STATISTICS_TICKS_REG 0x3c28 1072 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1073 #define STATISTICS_HOST_ADDR_REG 0x3c30 1074 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1075 #define STATISTICS_BASE_ADDR_REG 0x3c40 1076 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1077 #define FLOW_ATTN_REG 0x3c48 1078 1079 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1080 #define NIC_STD_RECV_INDEX_REG 0x3c54 1081 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1082 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1083 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1084 1085 /* 1086 * Mbuf Pool Initialisation & Watermark Registers 1087 * 1088 * There are some conflicts in the PRM; compare the recommendations 1089 * on pp. 115, 236, and 339. The values here were recommended by 1090 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1091 */ 1092 #define BUFFER_MANAGER_STATUS_REG 0x4404 1093 #define MBUF_POOL_BASE_REG 0x4408 1094 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1095 #define MBUF_POOL_BASE_5721 0x00010000 1096 #define MBUF_POOL_BASE_5704 0x00010000 1097 #define MBUF_POOL_BASE_5705 0x00010000 1098 #define MBUF_POOL_LENGTH_REG 0x440c 1099 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1100 #define MBUF_POOL_LENGTH_5704 0x00010000 1101 #define MBUF_POOL_LENGTH_5705 0x00008000 1102 #define MBUF_POOL_LENGTH_5721 0x00008000 1103 #define RDMA_MBUF_LOWAT_REG 0x4410 1104 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1105 #define RDMA_MBUF_LOWAT_5705 0x00000000 1106 #define RDMA_MBUF_LOWAT_5906 0x00000000 1107 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1108 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1109 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1110 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1111 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1112 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1113 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1114 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1115 #define MBUF_HIWAT_REG 0x4418 1116 #define MBUF_HIWAT_DEFAULT 0x00000060 1117 #define MBUF_HIWAT_5705 0x00000060 1118 #define MBUF_HIWAT_5906 0x00000010 1119 #define MBUF_HIWAT_JUMBO 0x0000017c 1120 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1121 1122 /* 1123 * DMA Descriptor Pool Initialisation & Watermark Registers 1124 */ 1125 #define DMAD_POOL_BASE_REG 0x442c 1126 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1127 #define DMAD_POOL_LENGTH_REG 0x4430 1128 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1129 #define DMAD_POOL_LOWAT_REG 0x4434 1130 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1131 #define DMAD_POOL_HIWAT_REG 0x4438 1132 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1133 1134 /* 1135 * More threshold/watermark registers ... 1136 */ 1137 #define RECV_FLOW_THRESHOLD_REG 0x4458 1138 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1139 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1140 1141 /* 1142 * Read/Write DMA Status Registers 1143 */ 1144 #define READ_DMA_STATUS_REG 0x4804 1145 #define WRITE_DMA_STATUS_REG 0x4c04 1146 1147 /* 1148 * RX/TX RISC Registers 1149 */ 1150 #define RX_RISC_MODE_REG 0x5000 1151 #define RX_RISC_STATE_REG 0x5004 1152 #define RX_RISC_PC_REG 0x501c 1153 #define TX_RISC_MODE_REG 0x5400 1154 #define TX_RISC_STATE_REG 0x5404 1155 #define TX_RISC_PC_REG 0x541c 1156 1157 /* 1158 * V? RISC Registerss 1159 */ 1160 #define VCPU_STATUS_REG 0x5100 1161 #define VCPU_INIT_DONE 0x04000000 1162 #define VCPU_DRV_RESET 0x08000000 1163 1164 #define VCPU_EXT_CTL 0x6890 1165 #define VCPU_EXT_CTL_HALF 0x00400000 1166 1167 #define FTQ_RESET_REG 0x5c00 1168 1169 #define MSI_MODE_REG 0x6000 1170 #define MSI_PRI_HIGHEST 0xc0000000 1171 #define MSI_MSI_ENABLE 0x00000002 1172 #define MSI_ERROR_ATTENTION 0x0000001c 1173 1174 #define MSI_STATUS_REG 0x6004 1175 1176 #define MODE_CONTROL_REG 0x6800 1177 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1178 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1179 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1180 #define MODE_INT_ON_DMA_ATTN 0x08000000 1181 #define MODE_INT_ON_MAC_ATTN 0x04000000 1182 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1183 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1184 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1185 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1186 #define MODE_HOST_SEND_BDS 0x00020000 1187 #define MODE_HOST_STACK_UP 0x00010000 1188 #define MODE_FORCE_32_BIT_PCI 0x00008000 1189 #define MODE_NO_INT_ON_RECV 0x00004000 1190 #define MODE_NO_INT_ON_SEND 0x00002000 1191 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1192 #define MODE_NO_CRC 0x00000400 1193 #define MODE_NO_FRAME_CRACKING 0x00000200 1194 #define MODE_WORD_SWAP_FRAME 0x00000020 1195 #define MODE_BYTE_SWAP_FRAME 0x00000010 1196 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1197 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1198 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1199 1200 /* 1201 * Miscellaneous Configuration Register 1202 * 1203 * This contains various bits relating to power control (which differ 1204 * among different members of the chip family), but the important bits 1205 * for our purposes are the RESET bit and the Timer Prescaler field. 1206 * 1207 * The RESET bit in this register serves to reset the whole chip, even 1208 * including the PCI interface(!) Once it's set, the chip will not 1209 * respond to ANY accesses -- not even CONFIG space -- until the reset 1210 * completes internally. According to the PRM, this should take less 1211 * than 100us. Any access during this period will get a bus error. 1212 * 1213 * The Timer Prescaler field must be programmed so that the timer period 1214 * is as near as possible to 1us. The value in this field should be 1215 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1216 * the Core Clock should always be 66MHz (independently of the bus speed, 1217 * at least for PCI rather than PCI-X), so this register must be set to 1218 * the value 0x82 ((66-1) << 1). 1219 */ 1220 #define CORE_CLOCK_MHZ 66 1221 #define MISC_CONFIG_REG 0x6804 1222 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1223 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1224 #define MISC_CONFIG_POWERDOWN 0x00100000 1225 #define MISC_CONFIG_POWER_STATE 0x00060000 1226 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1227 #define MISC_CONFIG_RESET_BIT 0x00000001 1228 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1229 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1230 1231 /* 1232 * Miscellaneous Local Control Register (MLCR) 1233 */ 1234 #define MISC_LOCAL_CONTROL_REG 0x6808 1235 #define MLCR_PCI_CTRL_SELECT 0x10000000 1236 #define MLCR_LEGACY_PCI_MODE 0x08000000 1237 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1238 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1239 #define MLCR_SSRAM_TYPE 0x00400000 1240 #define MLCR_BANK_SELECT 0x00200000 1241 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1242 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1243 1244 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1245 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1246 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1247 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1248 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1249 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1250 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1251 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1252 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1253 1254 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1255 #define MLCR_SET_INT 0x00000004 /* W/O */ 1256 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1257 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1258 1259 /* 1260 * This value defines all GPIO bits as INPUTS, but sets their default 1261 * values as outputs to HIGH, on the assumption that external circuits 1262 * (if any) will probably be active-LOW with passive pullups. 1263 * 1264 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1265 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1266 * enable writing. Otherwise, the SEEPROM is protected. 1267 */ 1268 #define MLCR_DEFAULT 0x0101c000 1269 #define MLCR_DEFAULT_5714 0x1901c000 1270 1271 /* 1272 * Serial EEPROM Data/Address Registers (auto-access mode) 1273 */ 1274 #define SERIAL_EEPROM_DATA_REG 0x683c 1275 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1276 #define SEEPROM_ACCESS_READ 0x80000000 1277 #define SEEPROM_ACCESS_WRITE 0x00000000 1278 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1279 #define SEEPROM_ACCESS_RESET 0x20000000 1280 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1281 #define SEEPROM_ACCESS_START 0x02000000 1282 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1283 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1284 1285 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1286 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1287 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1288 1289 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1290 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1291 1292 /* 1293 * "Linearised" address mask, treating multiple devices as consecutive 1294 */ 1295 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1296 1297 /* 1298 * Non-Volatile Memory Interface Registers 1299 * Note: on chips that support the flash interface (5702+), flash is the 1300 * default and the legacy seeprom interface must be explicitly enabled 1301 * if required. On older chips (5700/01), SEEPROM is the default (and 1302 * only) non-volatile memory available, and these registers don't exist! 1303 */ 1304 #define NVM_FLASH_CMD_REG 0x7000 1305 #define NVM_FLASH_CMD_LAST 0x00000100 1306 #define NVM_FLASH_CMD_FIRST 0x00000080 1307 #define NVM_FLASH_CMD_RD 0x00000000 1308 #define NVM_FLASH_CMD_WR 0x00000020 1309 #define NVM_FLASH_CMD_DOIT 0x00000010 1310 #define NVM_FLASH_CMD_DONE 0x00000008 1311 1312 #define NVM_FLASH_WRITE_REG 0x7008 1313 #define NVM_FLASH_READ_REG 0x7010 1314 1315 #define NVM_FLASH_ADDR_REG 0x700c 1316 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1317 1318 #define NVM_CONFIG1_REG 0x7014 1319 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1320 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1321 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1322 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1323 #define NVM_CFG1_FLASH_MODE 0x00000001 1324 1325 #define NVM_SW_ARBITRATION_REG 0x7020 1326 #define NVM_READ_REQ3 0X00008000 1327 #define NVM_READ_REQ2 0X00004000 1328 #define NVM_READ_REQ1 0X00002000 1329 #define NVM_READ_REQ0 0X00001000 1330 #define NVM_WON_REQ3 0X00000800 1331 #define NVM_WON_REQ2 0X00000400 1332 #define NVM_WON_REQ1 0X00000200 1333 #define NVM_WON_REQ0 0X00000100 1334 #define NVM_RESET_REQ3 0X00000080 1335 #define NVM_RESET_REQ2 0X00000040 1336 #define NVM_RESET_REQ1 0X00000020 1337 #define NVM_RESET_REQ0 0X00000010 1338 #define NVM_SET_REQ3 0X00000008 1339 #define NVM_SET_REQ2 0X00000004 1340 #define NVM_SET_REQ1 0X00000002 1341 #define NVM_SET_REQ0 0X00000001 1342 1343 /* 1344 * NVM access register 1345 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1346 * and BCM5715 only. 1347 */ 1348 #define NVM_ACCESS_REG 0X7024 1349 #define NVM_WRITE_ENABLE 0X00000002 1350 #define NVM_ACCESS_ENABLE 0X00000001 1351 1352 /* 1353 * TLP Control Register 1354 * Applicable to BCM5721 and BCM5751 only 1355 */ 1356 #define TLP_CONTROL_REG 0x7c00 1357 #define TLP_DATA_FIFO_PROTECT 0x02000000 1358 1359 /* 1360 * PHY Test Control Register 1361 * Applicable to BCM5721 and BCM5751 only 1362 */ 1363 #define PHY_TEST_CTRL_REG 0x7e2c 1364 #define PHY_PCIE_SCRAM_MODE 0x20 1365 #define PHY_PCIE_LTASS_MODE 0x40 1366 1367 /* 1368 * The internal firmware expects a certain layout of the non-volatile 1369 * memory (if fitted), and will check for it during startup, and use the 1370 * contents to initialise various internal parameters if it looks good. 1371 * 1372 * The offsets and field definitions below refer to where to find some 1373 * important values, and how to interpret them ... 1374 */ 1375 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1376 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1377 1378 /* 1379 * Vendor-specific MII registers 1380 */ 1381 #define MII_EXT_CONTROL MII_VENDOR(0) 1382 #define MII_EXT_STATUS MII_VENDOR(1) 1383 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1384 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1385 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1386 #define MII_AUX_CONTROL MII_VENDOR(8) 1387 #define MII_AUX_STATUS MII_VENDOR(9) 1388 #define MII_INTR_STATUS MII_VENDOR(10) 1389 #define MII_INTR_MASK MII_VENDOR(11) 1390 #define MII_HCD_STATUS MII_VENDOR(13) 1391 1392 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1393 1394 /* 1395 * Bits in the MII_EXT_CONTROL register 1396 */ 1397 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1398 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1399 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1400 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1401 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1402 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1403 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1404 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1405 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1406 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1407 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1408 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1409 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1410 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1411 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1412 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1413 1414 /* 1415 * Bits in the MII_EXT_STATUS register 1416 */ 1417 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1418 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1419 #define MII_EXT_STAT_MDIX_STATE 0x2000 1420 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1421 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1422 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1423 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1424 #define MII_EXT_STAT_LINK_STATUS 0x0100 1425 #define MII_EXT_STAT_CRC_ERROR 0x0080 1426 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1427 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1428 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1429 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1430 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1431 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1432 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1433 1434 /* 1435 * The AUX CONTROL register is seriously weird! 1436 * 1437 * It hides (up to) eight 'shadow' registers. When writing, which one 1438 * of them is written is determined by the low-order bits of the data 1439 * written(!), but when reading, which one is read is determined by the 1440 * value previously written to (part of) one of the shadow registers!!! 1441 */ 1442 1443 /* 1444 * Shadow register numbers 1445 */ 1446 #define MII_AUX_CTRL_NORMAL 0 1447 #define MII_AUX_CTRL_10BASE_T 1 1448 #define MII_AUX_CTRL_POWER 2 1449 #define MII_AUX_CTRL_TEST_1 4 1450 #define MII_AUX_CTRL_MISC 7 1451 1452 /* 1453 * Selected bits in some of the shadow registers ... 1454 */ 1455 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1456 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1457 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1458 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1459 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1460 1461 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1462 1463 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1464 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1465 1466 /* 1467 * Write this value to the AUX control register 1468 * to select which shadow register will be read 1469 */ 1470 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1471 1472 /* 1473 * Bits in the MII_AUX_STATUS register 1474 */ 1475 #define MII_AUX_STATUS_MODE_MASK 0x0700 1476 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1477 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1478 #define MII_AUX_STATUS_MODE_100_F 0x0500 1479 #define MII_AUX_STATUS_MODE_100_4 0x0400 1480 #define MII_AUX_STATUS_MODE_100_H 0x0300 1481 #define MII_AUX_STATUS_MODE_10_F 0x0200 1482 #define MII_AUX_STATUS_MODE_10_H 0x0100 1483 #define MII_AUX_STATUS_MODE_NONE 0x0000 1484 #define MII_AUX_STATUS_MODE_SHIFT 8 1485 1486 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1487 #define MII_AUX_STATUS_REM_FAULT 0x0040 1488 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1489 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1490 1491 #define MII_AUX_STATUS_LINKUP 0x0004 1492 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1493 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1494 1495 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1496 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1497 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1498 1499 /* 1500 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1501 */ 1502 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1503 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1504 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1505 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1506 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1507 1508 1509 /* 1510 * Third section: 1511 * Hardware-defined data structures 1512 * 1513 * Note that the chip is naturally BIG-endian, so, for a big-endian 1514 * host, the structures defined below match those described in the PRM. 1515 * For little-endian hosts, some structures have to be swapped around. 1516 */ 1517 1518 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1519 #error Host endianness not defined 1520 #endif 1521 1522 /* 1523 * Architectural constants: absolute maximum numbers of each type of ring 1524 */ 1525 #ifdef BGE_EXT_MEM 1526 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1527 #else 1528 #define BGE_SEND_RINGS_MAX 4 1529 #endif 1530 #define BGE_SEND_RINGS_MAX_5705 1 1531 #define BGE_RECV_RINGS_MAX 16 1532 #define BGE_RECV_RINGS_MAX_5705 1 1533 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1534 /* only with ext mem) */ 1535 1536 #define BGE_SEND_SLOTS_MAX 512 1537 #define BGE_STD_SLOTS_MAX 512 1538 #define BGE_JUMBO_SLOTS_MAX 256 1539 #define BGE_MINI_SLOTS_MAX 1024 1540 #define BGE_RECV_SLOTS_MAX 2048 1541 #define BGE_RECV_SLOTS_5705 512 1542 #define BGE_RECV_SLOTS_5782 512 1543 #define BGE_RECV_SLOTS_5721 512 1544 1545 /* 1546 * Hardware-defined Ring Control Block 1547 */ 1548 typedef struct { 1549 uint64_t host_ring_addr; 1550 #ifdef _BIG_ENDIAN 1551 uint16_t max_len; 1552 uint16_t flags; 1553 uint32_t nic_ring_addr; 1554 #else 1555 uint32_t nic_ring_addr; 1556 uint16_t flags; 1557 uint16_t max_len; 1558 #endif /* _BIG_ENDIAN */ 1559 } bge_rcb_t; 1560 1561 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1562 #define RCB_FLAG_RING_DISABLED 0x0002 1563 1564 /* 1565 * Hardware-defined Send Buffer Descriptor 1566 */ 1567 typedef struct { 1568 uint64_t host_buf_addr; 1569 #ifdef _BIG_ENDIAN 1570 uint16_t len; 1571 uint16_t flags; 1572 uint16_t reserved; 1573 uint16_t vlan_tci; 1574 #else 1575 uint16_t vlan_tci; 1576 uint16_t reserved; 1577 uint16_t flags; 1578 uint16_t len; 1579 #endif /* _BIG_ENDIAN */ 1580 } bge_sbd_t; 1581 1582 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1583 #define SBD_FLAG_IP_CKSUM 0x0002 1584 #define SBD_FLAG_PACKET_END 0x0004 1585 #define SBD_FLAG_IP_FRAG 0x0008 1586 #define SBD_FLAG_IP_FRAG_END 0x0010 1587 1588 #define SBD_FLAG_VLAN_TAG 0x0040 1589 #define SBD_FLAG_COAL_NOW 0x0080 1590 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1591 #define SBD_FLAG_CPU_POST_DMA 0x0200 1592 1593 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1594 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1595 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1596 1597 /* 1598 * Hardware-defined Receive Buffer Descriptor 1599 */ 1600 typedef struct { 1601 uint64_t host_buf_addr; 1602 #ifdef _BIG_ENDIAN 1603 uint16_t index; 1604 uint16_t len; 1605 uint16_t type; 1606 uint16_t flags; 1607 uint16_t ip_cksum; 1608 uint16_t tcp_udp_cksum; 1609 uint16_t error_flag; 1610 uint16_t vlan_tci; 1611 uint32_t reserved; 1612 uint32_t opaque; 1613 #else 1614 uint16_t flags; 1615 uint16_t type; 1616 uint16_t len; 1617 uint16_t index; 1618 uint16_t vlan_tci; 1619 uint16_t error_flag; 1620 uint16_t tcp_udp_cksum; 1621 uint16_t ip_cksum; 1622 uint32_t opaque; 1623 uint32_t reserved; 1624 #endif /* _BIG_ENDIAN */ 1625 } bge_rbd_t; 1626 1627 #define RBD_FLAG_STD_RING 0x0000 1628 #define RBD_FLAG_PACKET_END 0x0004 1629 1630 #define RBD_FLAG_JUMBO_RING 0x0020 1631 #define RBD_FLAG_VLAN_TAG 0x0040 1632 1633 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1634 #define RBD_FLAG_MINI_RING 0x0800 1635 #define RBD_FLAG_IP_CHECKSUM 0x1000 1636 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1637 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1638 1639 #define RBD_FLAG_DEFAULT 0x0000 1640 1641 #define RBD_ERROR_BAD_CRC 0x00010000 1642 #define RBD_ERROR_COLL_DETECT 0x00020000 1643 #define RBD_ERROR_LINK_LOST 0x00040000 1644 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1645 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1646 #define RBD_ERROR_MAC_ABORT 0x00200000 1647 #define RBD_ERROR_LEN_LESS_64 0x00400000 1648 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1649 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1650 1651 /* 1652 * Hardware-defined Status Block,Size of status block 1653 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1654 * alignment.For BCM5705/5788/5721/5751/5752/5714 1655 * and 5715,there is only 1 recv and send ring index,but 1656 * driver defined 16 indexs here,please pay attention only 1657 * one ring is enabled in these chipsets. 1658 */ 1659 typedef struct { 1660 uint64_t flags_n_tag; 1661 uint16_t buff_cons_index[4]; 1662 struct { 1663 #ifdef _BIG_ENDIAN 1664 uint16_t send_cons_index; 1665 uint16_t recv_prod_index; 1666 #else 1667 uint16_t recv_prod_index; 1668 uint16_t send_cons_index; 1669 #endif /* _BIG_ENDIAN */ 1670 } index[16]; 1671 } bge_status_t; 1672 1673 /* 1674 * Hardware-defined Receive BD Rule 1675 */ 1676 typedef struct { 1677 uint32_t control; 1678 uint32_t mask_value; 1679 } bge_recv_rule_t; 1680 1681 /* 1682 * This describes which sub-rule slots are used by a particular rule. 1683 */ 1684 typedef struct { 1685 int start; 1686 int count; 1687 } bge_rule_info_t; 1688 1689 /* 1690 * Indexes into the <buff_cons_index> array 1691 */ 1692 #ifdef _BIG_ENDIAN 1693 #define STATUS_STD_BUFF_CONS_INDEX 0 1694 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1695 #define STATUS_MINI_BUFF_CONS_INDEX 3 1696 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1697 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1698 #else 1699 #define STATUS_STD_BUFF_CONS_INDEX 3 1700 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1701 #define STATUS_MINI_BUFF_CONS_INDEX 0 1702 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1703 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1704 #endif /* _BIG_ENDIAN */ 1705 1706 /* 1707 * Bits in the <flags_n_tag> word 1708 */ 1709 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1710 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1711 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1712 #define STATUS_TAG_MASK 0x00000000000000FFull 1713 1714 /* 1715 * The tag from the status block is fed back to Interrupt Mailbox 0 1716 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1717 * lets the chip know what updates have been processed, so it can 1718 * reassert its interrupt if more updates have occurred since. 1719 * 1720 * These macros extract the tag from the <flags_n_tag> word, shift 1721 * it to the proper position in the Mailbox register, and provide 1722 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1723 * or enable interrupts 1724 */ 1725 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1726 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1727 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1728 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1729 1730 /* 1731 * Hardware-defined Statistics Block Offsets 1732 * 1733 * These are given in the manual as addresses in NIC memory, starting 1734 * from the NIC statistics area base address of 0x300; but here we 1735 * convert them into indexes into an array of (uint64_t)s, so we can 1736 * use them directly for accessing the copy of the statistics block 1737 * that the chip DMAs into main memory ... 1738 */ 1739 1740 #define KS_BASE 0x300 1741 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1742 1743 typedef enum { 1744 KS_ifHCInOctets = KS_ADDR(0x400), 1745 KS_etherStatsFragments = KS_ADDR(0x410), 1746 KS_ifHCInUcastPkts, 1747 KS_ifHCInMulticastPkts, 1748 KS_ifHCInBroadcastPkts, 1749 KS_dot3StatsFCSErrors, 1750 KS_dot3StatsAlignmentErrors, 1751 KS_xonPauseFramesReceived, 1752 KS_xoffPauseFramesReceived, 1753 KS_macControlFramesReceived, 1754 KS_xoffStateEntered, 1755 KS_dot3StatsFrameTooLongs, 1756 KS_etherStatsJabbers, 1757 KS_etherStatsUndersizePkts, 1758 KS_inRangeLengthError, 1759 KS_outRangeLengthError, 1760 KS_etherStatsPkts64Octets, 1761 KS_etherStatsPkts65to127Octets, 1762 KS_etherStatsPkts128to255Octets, 1763 KS_etherStatsPkts256to511Octets, 1764 KS_etherStatsPkts512to1023Octets, 1765 KS_etherStatsPkts1024to1518Octets, 1766 KS_etherStatsPkts1519to2047Octets, 1767 KS_etherStatsPkts2048to4095Octets, 1768 KS_etherStatsPkts4096to8191Octets, 1769 KS_etherStatsPkts8192to9022Octets, 1770 1771 KS_ifHCOutOctets = KS_ADDR(0x600), 1772 KS_etherStatsCollisions = KS_ADDR(0x610), 1773 KS_outXonSent, 1774 KS_outXoffSent, 1775 KS_flowControlDone, 1776 KS_dot3StatsInternalMacTransmitErrors, 1777 KS_dot3StatsSingleCollisionFrames, 1778 KS_dot3StatsMultipleCollisionFrames, 1779 KS_dot3StatsDeferredTransmissions, 1780 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1781 KS_dot3StatsLateCollisions, 1782 KS_dot3Collided2Times, 1783 KS_dot3Collided3Times, 1784 KS_dot3Collided4Times, 1785 KS_dot3Collided5Times, 1786 KS_dot3Collided6Times, 1787 KS_dot3Collided7Times, 1788 KS_dot3Collided8Times, 1789 KS_dot3Collided9Times, 1790 KS_dot3Collided10Times, 1791 KS_dot3Collided11Times, 1792 KS_dot3Collided12Times, 1793 KS_dot3Collided13Times, 1794 KS_dot3Collided14Times, 1795 KS_dot3Collided15Times, 1796 KS_ifHCOutUcastPkts, 1797 KS_ifHCOutMulticastPkts, 1798 KS_ifHCOutBroadcastPkts, 1799 KS_dot3StatsCarrierSenseErrors, 1800 KS_ifOutDiscards, 1801 KS_ifOutErrors, 1802 1803 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1804 KS_COSIfHCInPkts_2, 1805 KS_COSIfHCInPkts_3, 1806 KS_COSIfHCInPkts_4, 1807 KS_COSIfHCInPkts_5, 1808 KS_COSIfHCInPkts_6, 1809 KS_COSIfHCInPkts_7, 1810 KS_COSIfHCInPkts_8, 1811 KS_COSIfHCInPkts_9, 1812 KS_COSIfHCInPkts_10, 1813 KS_COSIfHCInPkts_11, 1814 KS_COSIfHCInPkts_12, 1815 KS_COSIfHCInPkts_13, 1816 KS_COSIfHCInPkts_14, 1817 KS_COSIfHCInPkts_15, 1818 KS_COSIfHCInPkts_16, 1819 KS_COSFramesDroppedDueToFilters, 1820 KS_nicDmaWriteQueueFull, 1821 KS_nicDmaWriteHighPriQueueFull, 1822 KS_nicNoMoreRxBDs, 1823 KS_ifInDiscards, 1824 KS_ifInErrors, 1825 KS_nicRecvThresholdHit, 1826 1827 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1828 KS_COSIfHCOutPkts_2, 1829 KS_COSIfHCOutPkts_3, 1830 KS_COSIfHCOutPkts_4, 1831 KS_COSIfHCOutPkts_5, 1832 KS_COSIfHCOutPkts_6, 1833 KS_COSIfHCOutPkts_7, 1834 KS_COSIfHCOutPkts_8, 1835 KS_COSIfHCOutPkts_9, 1836 KS_COSIfHCOutPkts_10, 1837 KS_COSIfHCOutPkts_11, 1838 KS_COSIfHCOutPkts_12, 1839 KS_COSIfHCOutPkts_13, 1840 KS_COSIfHCOutPkts_14, 1841 KS_COSIfHCOutPkts_15, 1842 KS_COSIfHCOutPkts_16, 1843 KS_nicDmaReadQueueFull, 1844 KS_nicDmaReadHighPriQueueFull, 1845 KS_nicSendDataCompQueueFull, 1846 KS_nicRingSetSendProdIndex, 1847 KS_nicRingStatusUpdate, 1848 KS_nicInterrupts, 1849 KS_nicAvoidedInterrupts, 1850 KS_nicSendThresholdHit, 1851 1852 KS_STATS_SIZE = KS_ADDR(0xb00) 1853 } bge_stats_offset_t; 1854 1855 /* 1856 * Hardware-defined Statistics Block 1857 * 1858 * Another view of the statistic block, as a array and a structure ... 1859 */ 1860 1861 typedef union { 1862 uint64_t a[KS_STATS_SIZE]; 1863 struct { 1864 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1865 1866 uint64_t ifHCInOctets; /* 0x0400 */ 1867 uint64_t spare2[1]; 1868 uint64_t etherStatsFragments; 1869 uint64_t ifHCInUcastPkts; 1870 uint64_t ifHCInMulticastPkts; 1871 uint64_t ifHCInBroadcastPkts; 1872 uint64_t dot3StatsFCSErrors; 1873 uint64_t dot3StatsAlignmentErrors; 1874 uint64_t xonPauseFramesReceived; 1875 uint64_t xoffPauseFramesReceived; 1876 uint64_t macControlFramesReceived; 1877 uint64_t xoffStateEntered; 1878 uint64_t dot3StatsFrameTooLongs; 1879 uint64_t etherStatsJabbers; 1880 uint64_t etherStatsUndersizePkts; 1881 uint64_t inRangeLengthError; 1882 uint64_t outRangeLengthError; 1883 uint64_t etherStatsPkts64Octets; 1884 uint64_t etherStatsPkts65to127Octets; 1885 uint64_t etherStatsPkts128to255Octets; 1886 uint64_t etherStatsPkts256to511Octets; 1887 uint64_t etherStatsPkts512to1023Octets; 1888 uint64_t etherStatsPkts1024to1518Octets; 1889 uint64_t etherStatsPkts1519to2047Octets; 1890 uint64_t etherStatsPkts2048to4095Octets; 1891 uint64_t etherStatsPkts4096to8191Octets; 1892 uint64_t etherStatsPkts8192to9022Octets; 1893 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1894 1895 uint64_t ifHCOutOctets; /* 0x0600 */ 1896 uint64_t spare4[1]; 1897 uint64_t etherStatsCollisions; 1898 uint64_t outXonSent; 1899 uint64_t outXoffSent; 1900 uint64_t flowControlDone; 1901 uint64_t dot3StatsInternalMacTransmitErrors; 1902 uint64_t dot3StatsSingleCollisionFrames; 1903 uint64_t dot3StatsMultipleCollisionFrames; 1904 uint64_t dot3StatsDeferredTransmissions; 1905 uint64_t spare5[1]; 1906 uint64_t dot3StatsExcessiveCollisions; 1907 uint64_t dot3StatsLateCollisions; 1908 uint64_t dot3Collided2Times; 1909 uint64_t dot3Collided3Times; 1910 uint64_t dot3Collided4Times; 1911 uint64_t dot3Collided5Times; 1912 uint64_t dot3Collided6Times; 1913 uint64_t dot3Collided7Times; 1914 uint64_t dot3Collided8Times; 1915 uint64_t dot3Collided9Times; 1916 uint64_t dot3Collided10Times; 1917 uint64_t dot3Collided11Times; 1918 uint64_t dot3Collided12Times; 1919 uint64_t dot3Collided13Times; 1920 uint64_t dot3Collided14Times; 1921 uint64_t dot3Collided15Times; 1922 uint64_t ifHCOutUcastPkts; 1923 uint64_t ifHCOutMulticastPkts; 1924 uint64_t ifHCOutBroadcastPkts; 1925 uint64_t dot3StatsCarrierSenseErrors; 1926 uint64_t ifOutDiscards; 1927 uint64_t ifOutErrors; 1928 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1929 1930 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1931 uint64_t COSFramesDroppedDueToFilters; 1932 uint64_t nicDmaWriteQueueFull; 1933 uint64_t nicDmaWriteHighPriQueueFull; 1934 uint64_t nicNoMoreRxBDs; 1935 uint64_t ifInDiscards; 1936 uint64_t ifInErrors; 1937 uint64_t nicRecvThresholdHit; 1938 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1939 1940 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1941 uint64_t nicDmaReadQueueFull; 1942 uint64_t nicDmaReadHighPriQueueFull; 1943 uint64_t nicSendDataCompQueueFull; 1944 uint64_t nicRingSetSendProdIndex; 1945 uint64_t nicRingStatusUpdate; 1946 uint64_t nicInterrupts; 1947 uint64_t nicAvoidedInterrupts; 1948 uint64_t nicSendThresholdHit; 1949 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1950 } s; 1951 } bge_statistics_t; 1952 1953 #define KS_STAT_REG_SIZE (0x1B) 1954 #define KS_STAT_REG_BASE (0x800) 1955 1956 typedef struct { 1957 uint32_t ifHCOutOctets; 1958 uint32_t etherStatsCollisions; 1959 uint32_t outXonSent; 1960 uint32_t outXoffSent; 1961 uint32_t dot3StatsInternalMacTransmitErrors; 1962 uint32_t dot3StatsSingleCollisionFrames; 1963 uint32_t dot3StatsMultipleCollisionFrames; 1964 uint32_t dot3StatsDeferredTransmissions; 1965 uint32_t dot3StatsExcessiveCollisions; 1966 uint32_t dot3StatsLateCollisions; 1967 uint32_t ifHCOutUcastPkts; 1968 uint32_t ifHCOutMulticastPkts; 1969 uint32_t ifHCOutBroadcastPkts; 1970 uint32_t ifHCInOctets; 1971 uint32_t etherStatsFragments; 1972 uint32_t ifHCInUcastPkts; 1973 uint32_t ifHCInMulticastPkts; 1974 uint32_t ifHCInBroadcastPkts; 1975 uint32_t dot3StatsFCSErrors; 1976 uint32_t dot3StatsAlignmentErrors; 1977 uint32_t xonPauseFramesReceived; 1978 uint32_t xoffPauseFramesReceived; 1979 uint32_t macControlFramesReceived; 1980 uint32_t xoffStateEntered; 1981 uint32_t dot3StatsFrameTooLongs; 1982 uint32_t etherStatsJabbers; 1983 uint32_t etherStatsUndersizePkts; 1984 } bge_statistics_reg_t; 1985 1986 1987 #ifdef BGE_IPMI_ASF 1988 1989 /* 1990 * Device internal memory entries 1991 */ 1992 1993 #define BGE_FIRMWARE_MAILBOX 0x0b50 1994 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1995 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1996 1997 1998 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1999 #define BGE_NIC_DATA_SIG 0x4b657654 2000 2001 2002 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2003 2004 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2005 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2006 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2007 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2008 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2009 2010 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2011 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2012 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2013 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2014 2015 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2016 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2017 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2018 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2019 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2020 #define BGE_NIC_CFG_MINI_PCI 0x001000 2021 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2022 #define BGE_NIC_CFG_5753_12x12 0x100000 2023 2024 2025 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2026 2027 2028 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2029 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2030 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2031 2032 2033 #define BGE_CMD_MAILBOX 0x0b78 2034 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2035 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2036 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2037 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2038 2039 2040 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2041 #define BGE_CMD_DATA_MAILBOX 0x0b80 2042 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2043 2044 #define BGE_DRV_STATE_MAILBOX 0x0c04 2045 #define BGE_DRV_STATE_START 0x00000001 2046 #define BGE_DRV_STATE_START_DONE 0x80000001 2047 #define BGE_DRV_STATE_UNLOAD 0x00000002 2048 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2049 #define BGE_DRV_STATE_WOL 0x00000003 2050 #define BGE_DRV_STATE_SUSPEND 0x00000004 2051 2052 2053 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2054 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2055 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2056 2057 2058 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2059 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2060 2061 2062 /* 2063 * RX-RISC event register 2064 */ 2065 #define RX_RISC_EVENT_REG 0x6810 2066 #define RRER_ASF_EVENT 0x4000 2067 2068 #endif /* BGE_IPMI_ASF */ 2069 2070 #ifdef __cplusplus 2071 } 2072 #endif 2073 2074 #endif /* _BGE_HW_H */ 2075