1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) { 515 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 516 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 517 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 518 } else 519 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 520 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 521 } 522 } 523 524 #ifdef __amd64 525 /* 526 * Distinguish CPU types 527 * 528 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 529 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 530 * for PCI-Express based network interface card. This is the work-around 531 * for those nics. 532 */ 533 static boolean_t bge_get_em64t_type(void); 534 #pragma inline(bge_get_em64t_type) 535 536 static boolean_t 537 bge_get_em64t_type(void) 538 { 539 540 return (x86_vendor == X86_VENDOR_Intel); 541 } 542 #endif 543 544 /* 545 * Operating register get/set access routines 546 */ 547 548 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 549 #pragma inline(bge_reg_get32) 550 551 uint32_t 552 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 553 { 554 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 555 (void *)bgep, regno)); 556 557 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 558 } 559 560 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 561 #pragma inline(bge_reg_put32) 562 563 void 564 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 565 { 566 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 567 (void *)bgep, regno, data)); 568 569 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 570 BGE_PCICHK(bgep); 571 } 572 573 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 574 #pragma inline(bge_reg_set32) 575 576 void 577 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 578 { 579 uint32_t regval; 580 581 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 582 (void *)bgep, regno, bits)); 583 584 regval = bge_reg_get32(bgep, regno); 585 regval |= bits; 586 bge_reg_put32(bgep, regno, regval); 587 } 588 589 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 590 #pragma inline(bge_reg_clr32) 591 592 void 593 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 594 { 595 uint32_t regval; 596 597 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 598 (void *)bgep, regno, bits)); 599 600 regval = bge_reg_get32(bgep, regno); 601 regval &= ~bits; 602 bge_reg_put32(bgep, regno, regval); 603 } 604 605 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 606 #pragma inline(bge_reg_get64) 607 608 static uint64_t 609 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 610 { 611 uint64_t regval; 612 613 #ifdef __amd64 614 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 615 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 616 regval <<= 32; 617 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 } else { 619 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 620 } 621 #elif defined(__sparc) 622 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 623 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 624 regval <<= 32; 625 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 626 } else { 627 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 628 } 629 #else 630 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 631 #endif 632 633 #ifdef _LITTLE_ENDIAN 634 regval = (regval >> 32) | (regval << 32); 635 #endif /* _LITTLE_ENDIAN */ 636 637 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 638 (void *)bgep, regno, regval)); 639 640 return (regval); 641 } 642 643 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 644 #pragma inline(bge_reg_put64) 645 646 static void 647 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 648 { 649 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 650 (void *)bgep, regno, data)); 651 652 #ifdef _LITTLE_ENDIAN 653 data = ((data >> 32) | (data << 32)); 654 #endif /* _LITTLE_ENDIAN */ 655 656 #ifdef __amd64 657 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 658 ddi_put32(bgep->io_handle, 659 PIO_ADDR(bgep, regno), (uint32_t)data); 660 BGE_PCICHK(bgep); 661 ddi_put32(bgep->io_handle, 662 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 663 664 } else { 665 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 666 } 667 #elif defined(__sparc) 668 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 669 ddi_put32(bgep->io_handle, 670 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 671 BGE_PCICHK(bgep); 672 ddi_put32(bgep->io_handle, 673 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 674 } else { 675 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 676 } 677 #else 678 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 679 #endif 680 681 BGE_PCICHK(bgep); 682 } 683 684 /* 685 * The DDI doesn't provide get/put functions for 128 bit data 686 * so we put RCBs out as two 64-bit chunks instead. 687 */ 688 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 689 #pragma inline(bge_reg_putrcb) 690 691 static void 692 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 693 { 694 uint64_t *p; 695 696 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 697 (void *)bgep, addr, rcbp->host_ring_addr, 698 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 699 700 ASSERT((addr % sizeof (*rcbp)) == 0); 701 702 p = (void *)rcbp; 703 bge_reg_put64(bgep, addr, *p++); 704 bge_reg_put64(bgep, addr+8, *p); 705 } 706 707 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 708 #pragma inline(bge_mbx_put) 709 710 void 711 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 712 { 713 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 714 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 715 716 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 717 (void *)bgep, regno, data)); 718 719 /* 720 * Mailbox registers are nominally 64 bits on the 5701, but 721 * the MSW isn't used. On the 5703, they're only 32 bits 722 * anyway. So here we just write the lower(!) 32 bits - 723 * remembering that the chip is big-endian, even though the 724 * PCI bus is little-endian ... 725 */ 726 #ifdef _BIG_ENDIAN 727 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 728 #else 729 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 730 #endif /* _BIG_ENDIAN */ 731 BGE_PCICHK(bgep); 732 } 733 734 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 735 #pragma inline(bge_mbx_get) 736 737 uint32_t 738 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 739 { 740 uint32_t val32; 741 742 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 743 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 744 745 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 746 (void *)bgep, regno)); 747 748 #ifdef _BIG_ENDIAN 749 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 750 #else 751 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 752 #endif /* _BIG_ENDIAN */ 753 BGE_PCICHK(bgep); 754 755 return (val32); 756 } 757 758 759 #if BGE_DEBUGGING 760 761 void bge_led_mark(bge_t *bgep); 762 #pragma no_inline(bge_led_mark) 763 764 void 765 bge_led_mark(bge_t *bgep) 766 { 767 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 768 LED_CONTROL_1000MBPS_LED | 769 LED_CONTROL_100MBPS_LED | 770 LED_CONTROL_10MBPS_LED; 771 772 /* 773 * Blink all three LINK LEDs on simultaneously, then all off, 774 * then restore to automatic hardware control. This is used 775 * in laboratory testing to trigger a logic analyser or scope. 776 */ 777 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 778 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 779 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 780 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 781 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 782 } 783 784 #endif /* BGE_DEBUGGING */ 785 786 /* 787 * NIC on-chip memory access routines 788 * 789 * Only 32K of NIC memory is visible at a time, controlled by the 790 * Memory Window Base Address Register (in PCI config space). Once 791 * this is set, the 32K region of NIC-local memory that it refers 792 * to can be directly addressed in the upper 32K of the 64K of PCI 793 * memory space used for the device. 794 */ 795 796 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 797 #pragma inline(bge_nic_setwin) 798 799 static void 800 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 801 { 802 chip_id_t *cidp; 803 804 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 805 (void *)bgep, base)); 806 807 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 808 809 /* 810 * Don't do repeated zero data writes, 811 * if the device is BCM5714C/15C. 812 */ 813 cidp = &bgep->chipid; 814 if ((cidp->device == DEVICE_ID_5714C) || 815 (cidp->device == DEVICE_ID_5715C)) { 816 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 817 return; 818 /* Adjust lastWriteZeroData */ 819 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 820 B_TRUE : B_FALSE); 821 } 822 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 823 } 824 825 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 826 #pragma inline(bge_nic_get32) 827 828 static uint32_t 829 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 830 { 831 uint32_t data; 832 833 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 834 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 835 /* workaround for word swap error */ 836 if (addr & 4) 837 addr = addr - 4; 838 else 839 addr = addr + 4; 840 } 841 #endif 842 843 #ifdef __sparc 844 data = bge_nic_read32(bgep, addr); 845 #else 846 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 847 addr &= MWBAR_GRANULE_MASK; 848 addr += NIC_MEM_WINDOW_OFFSET; 849 850 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 851 #endif 852 853 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 854 (void *)bgep, addr, data)); 855 856 return (data); 857 } 858 859 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 860 #pragma inline(bge_nic_put32) 861 862 void 863 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 864 { 865 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 866 (void *)bgep, addr, data)); 867 868 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 869 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 870 /* workaround for word swap error */ 871 if (addr & 4) 872 addr = addr - 4; 873 else 874 addr = addr + 4; 875 } 876 #endif 877 878 #ifdef __sparc 879 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 880 data = LE_32(data); 881 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 882 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 883 #else 884 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 885 addr &= MWBAR_GRANULE_MASK; 886 addr += NIC_MEM_WINDOW_OFFSET; 887 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 888 BGE_PCICHK(bgep); 889 #endif 890 } 891 892 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 893 #pragma inline(bge_nic_get64) 894 895 static uint64_t 896 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 897 { 898 uint64_t data; 899 900 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 901 addr &= MWBAR_GRANULE_MASK; 902 addr += NIC_MEM_WINDOW_OFFSET; 903 904 #ifdef __amd64 905 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 906 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 data <<= 32; 908 data |= ddi_get32(bgep->io_handle, 909 PIO_ADDR(bgep, addr + 4)); 910 } else { 911 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 912 } 913 #elif defined(__sparc) 914 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 915 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 916 data <<= 32; 917 data |= ddi_get32(bgep->io_handle, 918 PIO_ADDR(bgep, addr + 4)); 919 } else { 920 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 921 } 922 #else 923 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 924 #endif 925 926 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 927 (void *)bgep, addr, data)); 928 929 return (data); 930 } 931 932 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 933 #pragma inline(bge_nic_put64) 934 935 static void 936 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 937 { 938 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 939 (void *)bgep, addr, data)); 940 941 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 942 addr &= MWBAR_GRANULE_MASK; 943 addr += NIC_MEM_WINDOW_OFFSET; 944 945 #ifdef __amd64 946 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 947 ddi_put32(bgep->io_handle, 948 PIO_ADDR(bgep, addr), (uint32_t)data); 949 BGE_PCICHK(bgep); 950 ddi_put32(bgep->io_handle, 951 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 952 } else { 953 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 954 } 955 #elif defined(__sparc) 956 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 957 ddi_put32(bgep->io_handle, 958 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 959 BGE_PCICHK(bgep); 960 ddi_put32(bgep->io_handle, 961 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 962 } else { 963 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 964 } 965 #else 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 967 #endif 968 969 BGE_PCICHK(bgep); 970 } 971 972 /* 973 * The DDI doesn't provide get/put functions for 128 bit data 974 * so we put RCBs out as two 64-bit chunks instead. 975 */ 976 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 977 #pragma inline(bge_nic_putrcb) 978 979 static void 980 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 981 { 982 uint64_t *p; 983 984 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 985 (void *)bgep, addr, rcbp->host_ring_addr, 986 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 987 988 ASSERT((addr % sizeof (*rcbp)) == 0); 989 990 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 991 addr &= MWBAR_GRANULE_MASK; 992 addr += NIC_MEM_WINDOW_OFFSET; 993 994 p = (void *)rcbp; 995 #ifdef __amd64 996 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 997 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 998 (uint32_t)(*p)); 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1000 (uint32_t)(*p >> 32)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1002 (uint32_t)(*(p + 1))); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1004 (uint32_t)(*p >> 32)); 1005 1006 } else { 1007 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1008 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1009 } 1010 #elif defined(__sparc) 1011 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 1012 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1013 (uint32_t)(*p)); 1014 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1015 (uint32_t)(*p >> 32)); 1016 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1017 (uint32_t)(*(p + 1))); 1018 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1019 (uint32_t)(*p >> 32)); 1020 } else { 1021 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1022 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1023 } 1024 #else 1025 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1026 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1027 #endif 1028 1029 BGE_PCICHK(bgep); 1030 } 1031 1032 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1033 #pragma inline(bge_nic_zero) 1034 1035 static void 1036 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1037 { 1038 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1039 (void *)bgep, addr, nbytes)); 1040 1041 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1042 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1043 1044 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1045 addr &= MWBAR_GRANULE_MASK; 1046 addr += NIC_MEM_WINDOW_OFFSET; 1047 1048 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1049 nbytes, 1, DDI_DATA_SZ08_ACC); 1050 BGE_PCICHK(bgep); 1051 } 1052 1053 /* 1054 * MII (PHY) register get/set access routines 1055 * 1056 * These use the chip's MII auto-access method, controlled by the 1057 * MII Communication register at 0x044c, so the CPU doesn't have 1058 * to fiddle with the individual bits. 1059 */ 1060 1061 #undef BGE_DBG 1062 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1063 1064 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1065 uint16_t data, uint32_t cmd); 1066 #pragma no_inline(bge_mii_access) 1067 1068 static uint16_t 1069 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1070 { 1071 uint32_t timeout; 1072 uint32_t regval1; 1073 uint32_t regval2; 1074 1075 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1076 (void *)bgep, regno, data, cmd)); 1077 1078 ASSERT(mutex_owned(bgep->genlock)); 1079 1080 /* 1081 * Assemble the command ... 1082 */ 1083 cmd |= data << MI_COMMS_DATA_SHIFT; 1084 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1085 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1086 cmd |= MI_COMMS_START; 1087 1088 /* 1089 * Wait for any command already in progress ... 1090 * 1091 * Note: this *shouldn't* ever find that there is a command 1092 * in progress, because we already hold the <genlock> mutex. 1093 * Nonetheless, we have sometimes seen the MI_COMMS_START 1094 * bit set here -- it seems that the chip can initiate MII 1095 * accesses internally, even with polling OFF. 1096 */ 1097 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1098 for (timeout = 100; ; ) { 1099 if ((regval2 & MI_COMMS_START) == 0) { 1100 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1101 break; 1102 } 1103 if (--timeout == 0) 1104 break; 1105 drv_usecwait(10); 1106 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1107 } 1108 1109 if (timeout == 0) 1110 return ((uint16_t)~0u); 1111 1112 if (timeout != 100) 1113 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1114 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1115 cmd, 10*(100-timeout), regval1, regval2)); 1116 1117 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1118 for (timeout = 1000; ; ) { 1119 if ((regval1 & MI_COMMS_START) == 0) 1120 break; 1121 if (--timeout == 0) 1122 break; 1123 drv_usecwait(10); 1124 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1125 } 1126 1127 /* 1128 * Drop out early if the READ FAILED bit is set -- this chip 1129 * could be a 5703/4S, with a SerDes instead of a PHY! 1130 */ 1131 if (regval2 & MI_COMMS_READ_FAILED) 1132 return ((uint16_t)~0u); 1133 1134 if (timeout == 0) 1135 return ((uint16_t)~0u); 1136 1137 /* 1138 * The PRM says to wait 5us after seeing the START bit clear 1139 * and then re-read the register to get the final value of the 1140 * data field, in order to avoid a race condition where the 1141 * START bit is clear but the data field isn't yet valid. 1142 * 1143 * Note: we don't actually seem to be encounter this race; 1144 * except when the START bit is seen set again (see below), 1145 * the data field doesn't change during this 5us interval. 1146 */ 1147 drv_usecwait(5); 1148 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1149 1150 /* 1151 * Unfortunately, when following the PRMs instructions above, 1152 * we have occasionally seen the START bit set again(!) in the 1153 * value read after the 5us delay. This seems to be due to the 1154 * chip autonomously starting another MII access internally. 1155 * In such cases, the command/data/etc fields relate to the 1156 * internal command, rather than the one that we thought had 1157 * just finished. So in this case, we fall back to returning 1158 * the data from the original read that showed START clear. 1159 */ 1160 if (regval2 & MI_COMMS_START) { 1161 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1162 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1163 cmd, regval1, regval2)); 1164 regval2 = regval1; 1165 } 1166 1167 if (regval2 & MI_COMMS_START) 1168 return ((uint16_t)~0u); 1169 1170 if (regval2 & MI_COMMS_READ_FAILED) 1171 return ((uint16_t)~0u); 1172 1173 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1174 } 1175 1176 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1177 #pragma no_inline(bge_mii_get16) 1178 1179 uint16_t 1180 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1181 { 1182 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1183 (void *)bgep, regno)); 1184 1185 ASSERT(mutex_owned(bgep->genlock)); 1186 1187 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1188 (regno == MII_1000BASE_T_CONTROL))) 1189 return (0); 1190 1191 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1192 } 1193 1194 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1195 #pragma no_inline(bge_mii_put16) 1196 1197 void 1198 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1199 { 1200 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1201 (void *)bgep, regno, data)); 1202 1203 ASSERT(mutex_owned(bgep->genlock)); 1204 1205 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1206 (regno == MII_1000BASE_T_CONTROL))) 1207 return; 1208 1209 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1210 } 1211 1212 #undef BGE_DBG 1213 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1214 1215 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1216 1217 /* 1218 * Basic SEEPROM get/set access routine 1219 * 1220 * This uses the chip's SEEPROM auto-access method, controlled by the 1221 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1222 * doesn't have to fiddle with the individual bits. 1223 * 1224 * The caller should hold <genlock> and *also* have already acquired 1225 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1226 * 1227 * Return value: 1228 * 0 on success, 1229 * ENODATA on access timeout (maybe retryable: device may just be busy) 1230 * EPROTO on other h/w or s/w errors. 1231 * 1232 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1233 * from a (successful) SEEPROM_ACCESS_READ. 1234 */ 1235 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1236 uint32_t *dp); 1237 #pragma no_inline(bge_seeprom_access) 1238 1239 static int 1240 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1241 { 1242 uint32_t tries; 1243 uint32_t regval; 1244 1245 ASSERT(mutex_owned(bgep->genlock)); 1246 1247 /* 1248 * On the newer chips that support both SEEPROM & Flash, we need 1249 * to specifically enable SEEPROM access (Flash is the default). 1250 * On older chips, we don't; SEEPROM is the only NVtype supported, 1251 * and the NVM control registers don't exist ... 1252 */ 1253 switch (bgep->chipid.nvtype) { 1254 case BGE_NVTYPE_NONE: 1255 case BGE_NVTYPE_UNKNOWN: 1256 _NOTE(NOTREACHED) 1257 case BGE_NVTYPE_SEEPROM: 1258 break; 1259 1260 case BGE_NVTYPE_LEGACY_SEEPROM: 1261 case BGE_NVTYPE_UNBUFFERED_FLASH: 1262 case BGE_NVTYPE_BUFFERED_FLASH: 1263 default: 1264 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1265 NVM_CFG1_LEGACY_SEEPROM_MODE); 1266 break; 1267 } 1268 1269 /* 1270 * Check there's no command in progress. 1271 * 1272 * Note: this *shouldn't* ever find that there is a command 1273 * in progress, because we already hold the <genlock> mutex. 1274 * Also, to ensure we don't have a conflict with the chip's 1275 * internal firmware or a process accessing the same (shared) 1276 * SEEPROM through the other port of a 5704, we've already 1277 * been through the "software arbitration" protocol. 1278 * So this is just a final consistency check: we shouldn't 1279 * see EITHER the START bit (command started but not complete) 1280 * OR the COMPLETE bit (command completed but not cleared). 1281 */ 1282 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1283 if (regval & SEEPROM_ACCESS_START) 1284 return (EPROTO); 1285 if (regval & SEEPROM_ACCESS_COMPLETE) 1286 return (EPROTO); 1287 1288 /* 1289 * Assemble the command ... 1290 */ 1291 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1292 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1293 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1294 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1295 cmd |= SEEPROM_ACCESS_START; 1296 cmd |= SEEPROM_ACCESS_COMPLETE; 1297 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1298 1299 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1300 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1301 1302 /* 1303 * By observation, a successful access takes ~20us on a 5703/4, 1304 * but apparently much longer (up to 1000us) on the obsolescent 1305 * BCM5700/BCM5701. We want to be sure we don't get any false 1306 * timeouts here; but OTOH, we don't want a bogus access to lock 1307 * out interrupts for longer than necessary. So we'll allow up 1308 * to 1000us ... 1309 */ 1310 for (tries = 0; tries < 1000; ++tries) { 1311 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1312 if (regval & SEEPROM_ACCESS_COMPLETE) 1313 break; 1314 drv_usecwait(1); 1315 } 1316 1317 if (regval & SEEPROM_ACCESS_COMPLETE) { 1318 /* 1319 * All OK; read the SEEPROM data register, then write back 1320 * the value read from the address register in order to 1321 * clear the <complete> bit and leave the SEEPROM access 1322 * state machine idle, ready for the next access ... 1323 */ 1324 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1325 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1326 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1327 return (0); 1328 } 1329 1330 /* 1331 * Hmm ... what happened here? 1332 * 1333 * Most likely, the user addressed a non-existent SEEPROM. Or 1334 * maybe the SEEPROM was busy internally (e.g. processing a write) 1335 * and didn't respond to being addressed. Either way, it's left 1336 * the SEEPROM access state machine wedged. So we'll reset it 1337 * before we leave, so it's ready for next time ... 1338 */ 1339 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1340 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1341 return (ENODATA); 1342 } 1343 1344 /* 1345 * Basic Flash get/set access routine 1346 * 1347 * These use the chip's Flash auto-access method, controlled by the 1348 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1349 * fiddle with the individual bits. 1350 * 1351 * The caller should hold <genlock> and *also* have already acquired 1352 * the right to access the Flash, via bge_nvmem_acquire() above. 1353 * 1354 * Return value: 1355 * 0 on success, 1356 * ENODATA on access timeout (maybe retryable: device may just be busy) 1357 * ENODEV if the NVmem device is missing or otherwise unusable 1358 * 1359 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1360 * from a (successful) NVM_FLASH_CMD_RD. 1361 */ 1362 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1363 uint32_t *dp); 1364 #pragma no_inline(bge_flash_access) 1365 1366 static int 1367 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1368 { 1369 uint32_t tries; 1370 uint32_t regval; 1371 1372 ASSERT(mutex_owned(bgep->genlock)); 1373 1374 /* 1375 * On the newer chips that support both SEEPROM & Flash, we need 1376 * to specifically disable SEEPROM access while accessing Flash. 1377 * The older chips don't support Flash, and the NVM registers don't 1378 * exist, so we shouldn't be here at all! 1379 */ 1380 switch (bgep->chipid.nvtype) { 1381 case BGE_NVTYPE_NONE: 1382 case BGE_NVTYPE_UNKNOWN: 1383 _NOTE(NOTREACHED) 1384 case BGE_NVTYPE_SEEPROM: 1385 return (ENODEV); 1386 1387 case BGE_NVTYPE_LEGACY_SEEPROM: 1388 case BGE_NVTYPE_UNBUFFERED_FLASH: 1389 case BGE_NVTYPE_BUFFERED_FLASH: 1390 default: 1391 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1392 NVM_CFG1_LEGACY_SEEPROM_MODE); 1393 break; 1394 } 1395 1396 /* 1397 * Assemble the command ... 1398 */ 1399 addr &= NVM_FLASH_ADDR_MASK; 1400 cmd |= NVM_FLASH_CMD_DOIT; 1401 cmd |= NVM_FLASH_CMD_FIRST; 1402 cmd |= NVM_FLASH_CMD_LAST; 1403 cmd |= NVM_FLASH_CMD_DONE; 1404 1405 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1406 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1407 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1408 1409 /* 1410 * Allow up to 1000ms ... 1411 */ 1412 for (tries = 0; tries < 1000; ++tries) { 1413 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1414 if (regval & NVM_FLASH_CMD_DONE) 1415 break; 1416 drv_usecwait(1); 1417 } 1418 1419 if (regval & NVM_FLASH_CMD_DONE) { 1420 /* 1421 * All OK; read the data from the Flash read register 1422 */ 1423 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1424 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1425 return (0); 1426 } 1427 1428 /* 1429 * Hmm ... what happened here? 1430 * 1431 * Most likely, the user addressed a non-existent Flash. Or 1432 * maybe the Flash was busy internally (e.g. processing a write) 1433 * and didn't respond to being addressed. Either way, there's 1434 * nothing we can here ... 1435 */ 1436 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1437 return (ENODATA); 1438 } 1439 1440 /* 1441 * The next two functions regulate access to the NVram (if fitted). 1442 * 1443 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1444 * (SPI) interface, but they can be accessed through either port. These 1445 * are managed by different instance of this driver and have no software 1446 * state in common. 1447 * 1448 * In addition (and even on a single core chip) the chip's internal 1449 * firmware can access the SEEPROM/Flash, most notably after a RESET 1450 * when it may download code to run internally. 1451 * 1452 * So we need to arbitrate between these various software agents. For 1453 * this purpose, the chip provides the Software Arbitration Register, 1454 * which implements hardware(!) arbitration. 1455 * 1456 * This functionality didn't exist on older (5700/5701) chips, so there's 1457 * nothing we can do by way of arbitration on those; also, if there's no 1458 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1459 * nothing to do. 1460 * 1461 * The internal firmware appears to use Request 0, which is the highest 1462 * priority. So we'd like to use Request 2, leaving one higher and one 1463 * lower for any future developments ... but apparently this doesn't 1464 * always work. So for now, the code uses Request 1 ;-( 1465 */ 1466 1467 #define NVM_READ_REQ NVM_READ_REQ1 1468 #define NVM_RESET_REQ NVM_RESET_REQ1 1469 #define NVM_SET_REQ NVM_SET_REQ1 1470 1471 static void bge_nvmem_relinquish(bge_t *bgep); 1472 #pragma no_inline(bge_nvmem_relinquish) 1473 1474 static void 1475 bge_nvmem_relinquish(bge_t *bgep) 1476 { 1477 ASSERT(mutex_owned(bgep->genlock)); 1478 1479 switch (bgep->chipid.nvtype) { 1480 case BGE_NVTYPE_NONE: 1481 case BGE_NVTYPE_UNKNOWN: 1482 _NOTE(NOTREACHED) 1483 return; 1484 1485 case BGE_NVTYPE_SEEPROM: 1486 /* 1487 * No arbitration performed, no release needed 1488 */ 1489 return; 1490 1491 case BGE_NVTYPE_LEGACY_SEEPROM: 1492 case BGE_NVTYPE_UNBUFFERED_FLASH: 1493 case BGE_NVTYPE_BUFFERED_FLASH: 1494 default: 1495 break; 1496 } 1497 1498 /* 1499 * Our own request should be present (whether or not granted) ... 1500 */ 1501 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1502 1503 /* 1504 * ... this will make it go away. 1505 */ 1506 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1507 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1508 } 1509 1510 /* 1511 * Arbitrate for access to the NVmem, if necessary 1512 * 1513 * Return value: 1514 * 0 on success 1515 * EAGAIN if the device is in use (retryable) 1516 * ENODEV if the NVmem device is missing or otherwise unusable 1517 */ 1518 static int bge_nvmem_acquire(bge_t *bgep); 1519 #pragma no_inline(bge_nvmem_acquire) 1520 1521 static int 1522 bge_nvmem_acquire(bge_t *bgep) 1523 { 1524 uint32_t regval; 1525 uint32_t tries; 1526 1527 ASSERT(mutex_owned(bgep->genlock)); 1528 1529 switch (bgep->chipid.nvtype) { 1530 case BGE_NVTYPE_NONE: 1531 case BGE_NVTYPE_UNKNOWN: 1532 /* 1533 * Access denied: no (recognisable) device fitted 1534 */ 1535 return (ENODEV); 1536 1537 case BGE_NVTYPE_SEEPROM: 1538 /* 1539 * Access granted: no arbitration needed (or possible) 1540 */ 1541 return (0); 1542 1543 case BGE_NVTYPE_LEGACY_SEEPROM: 1544 case BGE_NVTYPE_UNBUFFERED_FLASH: 1545 case BGE_NVTYPE_BUFFERED_FLASH: 1546 default: 1547 /* 1548 * Access conditional: conduct arbitration protocol 1549 */ 1550 break; 1551 } 1552 1553 /* 1554 * We're holding the per-port mutex <genlock>, so no-one other 1555 * thread can be attempting to access the NVmem through *this* 1556 * port. But it could be in use by the *other* port (of a 5704), 1557 * or by the chip's internal firmware, so we have to go through 1558 * the full (hardware) arbitration protocol ... 1559 * 1560 * Note that *because* we're holding <genlock>, the interrupt handler 1561 * won't be able to progress. So we're only willing to spin for a 1562 * fairly short time. Specifically: 1563 * 1564 * We *must* wait long enough for the hardware to resolve all 1565 * requests and determine the winner. Fortunately, this is 1566 * "almost instantaneous", even as observed by GHz CPUs. 1567 * 1568 * A successful access by another Solaris thread (via either 1569 * port) typically takes ~20us. So waiting a bit longer than 1570 * that will give a good chance of success, if the other user 1571 * *is* another thread on the other port. 1572 * 1573 * However, the internal firmware can hold on to the NVmem 1574 * for *much* longer: at least 10 milliseconds just after a 1575 * RESET, and maybe even longer if the NVmem actually contains 1576 * code to download and run on the internal CPUs. 1577 * 1578 * So, we'll allow 50us; if that's not enough then it's up to the 1579 * caller to retry later (hence the choice of return code EAGAIN). 1580 */ 1581 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1582 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1583 1584 for (tries = 0; tries < 50; ++tries) { 1585 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1586 if (regval & NVM_WON_REQ1) 1587 break; 1588 drv_usecwait(1); 1589 } 1590 1591 if (regval & NVM_WON_REQ1) { 1592 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1593 return (0); 1594 } 1595 1596 /* 1597 * Somebody else must be accessing the NVmem, so abandon our 1598 * attempt take control of it. The caller can try again later ... 1599 */ 1600 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1601 bge_nvmem_relinquish(bgep); 1602 return (EAGAIN); 1603 } 1604 1605 /* 1606 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1607 * write protect line in such a way that the NVmem is protected when 1608 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1609 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1610 * 1611 * Note: there's only one set of GPIO pins on a 5704, even though they 1612 * can be accessed through either port. So the chip has to resolve what 1613 * happens if the two ports program a single pin differently ... the rule 1614 * it uses is that if the ports disagree about the *direction* of a pin, 1615 * "output" wins over "input", but if they disagree about its *value* as 1616 * an output, then the pin is TRISTATED instead! In such a case, no-one 1617 * wins, and the external signal does whatever the external circuitry 1618 * defines as the default -- which we've assumed is the PROTECTED state. 1619 * So, we always change GPIO1 back to being an *input* whenever we're not 1620 * specifically using it to unprotect the NVmem. This allows either port 1621 * to update the NVmem, although obviously only one at a time! 1622 * 1623 * The caller should hold <genlock> and *also* have already acquired the 1624 * right to access the NVmem, via bge_nvmem_acquire() above. 1625 */ 1626 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1627 #pragma inline(bge_nvmem_protect) 1628 1629 static void 1630 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1631 { 1632 uint32_t regval; 1633 1634 ASSERT(mutex_owned(bgep->genlock)); 1635 1636 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1637 if (protect) { 1638 regval |= MLCR_MISC_PINS_OUTPUT_1; 1639 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1640 } else { 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1642 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1643 } 1644 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1645 } 1646 1647 /* 1648 * Now put it all together ... 1649 * 1650 * Try to acquire control of the NVmem; if successful, then: 1651 * unprotect it (if we want to write to it) 1652 * perform the requested access 1653 * reprotect it (after a write) 1654 * relinquish control 1655 * 1656 * Return value: 1657 * 0 on success, 1658 * EAGAIN if the device is in use (retryable) 1659 * ENODATA on access timeout (maybe retryable: device may just be busy) 1660 * ENODEV if the NVmem device is missing or otherwise unusable 1661 * EPROTO on other h/w or s/w errors. 1662 */ 1663 static int 1664 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1665 { 1666 int err; 1667 1668 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1669 switch (cmd) { 1670 case BGE_SEE_READ: 1671 err = bge_seeprom_access(bgep, 1672 SEEPROM_ACCESS_READ, addr, dp); 1673 break; 1674 1675 case BGE_SEE_WRITE: 1676 bge_nvmem_protect(bgep, B_FALSE); 1677 err = bge_seeprom_access(bgep, 1678 SEEPROM_ACCESS_WRITE, addr, dp); 1679 bge_nvmem_protect(bgep, B_TRUE); 1680 break; 1681 1682 case BGE_FLASH_READ: 1683 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1684 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1685 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1686 bge_reg_set32(bgep, NVM_ACCESS_REG, 1687 NVM_ACCESS_ENABLE); 1688 } 1689 err = bge_flash_access(bgep, 1690 NVM_FLASH_CMD_RD, addr, dp); 1691 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1692 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1702 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1703 bge_reg_set32(bgep, NVM_ACCESS_REG, 1704 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1705 } 1706 bge_nvmem_protect(bgep, B_FALSE); 1707 err = bge_flash_access(bgep, 1708 NVM_FLASH_CMD_WR, addr, dp); 1709 bge_nvmem_protect(bgep, B_TRUE); 1710 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1711 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1712 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1713 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1714 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1715 } 1716 1717 break; 1718 1719 default: 1720 _NOTE(NOTREACHED) 1721 break; 1722 } 1723 bge_nvmem_relinquish(bgep); 1724 } 1725 1726 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1727 return (err); 1728 } 1729 1730 /* 1731 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1732 */ 1733 static uint64_t bge_get_nvmac(bge_t *bgep); 1734 #pragma no_inline(bge_get_nvmac) 1735 1736 static uint64_t 1737 bge_get_nvmac(bge_t *bgep) 1738 { 1739 uint32_t mac_high; 1740 uint32_t mac_low; 1741 uint32_t addr; 1742 uint32_t cmd; 1743 uint64_t mac; 1744 1745 BGE_TRACE(("bge_get_nvmac($%p)", 1746 (void *)bgep)); 1747 1748 switch (bgep->chipid.nvtype) { 1749 case BGE_NVTYPE_NONE: 1750 case BGE_NVTYPE_UNKNOWN: 1751 default: 1752 return (0ULL); 1753 1754 case BGE_NVTYPE_SEEPROM: 1755 case BGE_NVTYPE_LEGACY_SEEPROM: 1756 cmd = BGE_SEE_READ; 1757 break; 1758 1759 case BGE_NVTYPE_UNBUFFERED_FLASH: 1760 case BGE_NVTYPE_BUFFERED_FLASH: 1761 cmd = BGE_FLASH_READ; 1762 break; 1763 } 1764 1765 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1766 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1767 else 1768 addr = NVMEM_DATA_MAC_ADDRESS; 1769 1770 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1771 return (0ULL); 1772 addr += 4; 1773 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1774 return (0ULL); 1775 1776 /* 1777 * The Broadcom chip is natively BIG-endian, so that's how the 1778 * MAC address is represented in NVmem. We may need to swap it 1779 * around on a little-endian host ... 1780 */ 1781 #ifdef _BIG_ENDIAN 1782 mac = mac_high; 1783 mac = mac << 32; 1784 mac |= mac_low; 1785 #else 1786 mac = BGE_BSWAP_32(mac_high); 1787 mac = mac << 32; 1788 mac |= BGE_BSWAP_32(mac_low); 1789 #endif /* _BIG_ENDIAN */ 1790 1791 return (mac); 1792 } 1793 1794 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1795 1796 /* 1797 * Dummy version for when we're not supporting NVmem access 1798 */ 1799 static uint64_t bge_get_nvmac(bge_t *bgep); 1800 #pragma inline(bge_get_nvmac) 1801 1802 static uint64_t 1803 bge_get_nvmac(bge_t *bgep) 1804 { 1805 _NOTE(ARGUNUSED(bgep)) 1806 return (0ULL); 1807 } 1808 1809 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1810 1811 /* 1812 * Determine the type of NVmem that is (or may be) attached to this chip, 1813 */ 1814 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1815 #pragma no_inline(bge_nvmem_id) 1816 1817 static enum bge_nvmem_type 1818 bge_nvmem_id(bge_t *bgep) 1819 { 1820 enum bge_nvmem_type nvtype; 1821 uint32_t config1; 1822 1823 BGE_TRACE(("bge_nvmem_id($%p)", 1824 (void *)bgep)); 1825 1826 switch (bgep->chipid.device) { 1827 default: 1828 /* 1829 * We shouldn't get here; it means we don't recognise 1830 * the chip, which means we don't know how to determine 1831 * what sort of NVmem (if any) it has. So we'll say 1832 * NONE, to disable the NVmem access code ... 1833 */ 1834 nvtype = BGE_NVTYPE_NONE; 1835 break; 1836 1837 case DEVICE_ID_5700: 1838 case DEVICE_ID_5700x: 1839 case DEVICE_ID_5701: 1840 /* 1841 * These devices support *only* SEEPROMs 1842 */ 1843 nvtype = BGE_NVTYPE_SEEPROM; 1844 break; 1845 1846 case DEVICE_ID_5702: 1847 case DEVICE_ID_5702fe: 1848 case DEVICE_ID_5703C: 1849 case DEVICE_ID_5703S: 1850 case DEVICE_ID_5704C: 1851 case DEVICE_ID_5704S: 1852 case DEVICE_ID_5704: 1853 case DEVICE_ID_5705M: 1854 case DEVICE_ID_5705C: 1855 case DEVICE_ID_5705_2: 1856 case DEVICE_ID_5780: 1857 case DEVICE_ID_5782: 1858 case DEVICE_ID_5787: 1859 case DEVICE_ID_5787M: 1860 case DEVICE_ID_5788: 1861 case DEVICE_ID_5789: 1862 case DEVICE_ID_5751: 1863 case DEVICE_ID_5751M: 1864 case DEVICE_ID_5752: 1865 case DEVICE_ID_5752M: 1866 case DEVICE_ID_5754: 1867 case DEVICE_ID_5755: 1868 case DEVICE_ID_5755M: 1869 case DEVICE_ID_5756M: 1870 case DEVICE_ID_5721: 1871 case DEVICE_ID_5722: 1872 case DEVICE_ID_5723: 1873 case DEVICE_ID_5761: 1874 case DEVICE_ID_5761E: 1875 case DEVICE_ID_5714C: 1876 case DEVICE_ID_5714S: 1877 case DEVICE_ID_5715C: 1878 case DEVICE_ID_5715S: 1879 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1880 if (config1 & NVM_CFG1_FLASH_MODE) 1881 if (config1 & NVM_CFG1_BUFFERED_MODE) 1882 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1883 else 1884 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1885 else 1886 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1887 break; 1888 case DEVICE_ID_5906: 1889 case DEVICE_ID_5906M: 1890 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1891 break; 1892 } 1893 1894 return (nvtype); 1895 } 1896 1897 #undef BGE_DBG 1898 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1899 1900 static void 1901 bge_init_recv_rule(bge_t *bgep) 1902 { 1903 bge_recv_rule_t *rulep = bgep->recv_rules; 1904 uint32_t i; 1905 1906 /* 1907 * Initialize receive rule registers. 1908 * Note that rules may persist across each bge_m_start/stop() call. 1909 */ 1910 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1911 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1912 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1913 } 1914 } 1915 1916 /* 1917 * Using the values captured by bge_chip_cfg_init(), and additional probes 1918 * as required, characterise the chip fully: determine the label by which 1919 * to refer to this chip, the correct settings for various registers, and 1920 * of course whether the device and/or subsystem are supported! 1921 */ 1922 int bge_chip_id_init(bge_t *bgep); 1923 #pragma no_inline(bge_chip_id_init) 1924 1925 int 1926 bge_chip_id_init(bge_t *bgep) 1927 { 1928 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1929 boolean_t sys_ok; 1930 boolean_t dev_ok; 1931 chip_id_t *cidp; 1932 uint32_t subid; 1933 char *devname; 1934 char *sysname; 1935 int *ids; 1936 int err; 1937 uint_t i; 1938 1939 sys_ok = dev_ok = B_FALSE; 1940 cidp = &bgep->chipid; 1941 1942 /* 1943 * Check the PCI device ID to determine the generic chip type and 1944 * select parameters that depend on this. 1945 * 1946 * Note: because the SPARC platforms in general don't fit the 1947 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1948 * as zero - which is why we use <asic_rev> rather than <revision> 1949 * below ... 1950 * 1951 * Note: in general we can't distinguish between the Copper/SerDes 1952 * versions by ID alone, as some Copper devices (e.g. some but not 1953 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1954 * treat them the same here, and the MII code works out the media 1955 * type later on ... 1956 */ 1957 cidp->mbuf_base = bge_mbuf_pool_base; 1958 cidp->mbuf_length = bge_mbuf_pool_len; 1959 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1960 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1961 cidp->pci_type = BGE_PCI_X; 1962 cidp->statistic_type = BGE_STAT_BLK; 1963 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1964 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1965 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1966 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1967 cidp->rx_count_norm = bge_rx_count_norm; 1968 1969 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1970 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1971 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1972 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1973 1974 cidp->msi_enabled = B_FALSE; 1975 1976 switch (cidp->device) { 1977 case DEVICE_ID_5700: 1978 case DEVICE_ID_5700x: 1979 cidp->chip_label = 5700; 1980 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1981 break; 1982 1983 case DEVICE_ID_5701: 1984 cidp->chip_label = 5701; 1985 dev_ok = B_TRUE; 1986 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1987 break; 1988 1989 case DEVICE_ID_5702: 1990 case DEVICE_ID_5702fe: 1991 cidp->chip_label = 5702; 1992 dev_ok = B_TRUE; 1993 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1994 cidp->pci_type = BGE_PCI; 1995 break; 1996 1997 case DEVICE_ID_5703C: 1998 case DEVICE_ID_5703S: 1999 case DEVICE_ID_5703: 2000 /* 2001 * Revision A0 of the 5703/5793 had various errata 2002 * that we can't or don't work around, so it's not 2003 * supported, but all later versions are 2004 */ 2005 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2006 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2007 dev_ok = B_TRUE; 2008 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2009 break; 2010 2011 case DEVICE_ID_5704C: 2012 case DEVICE_ID_5704S: 2013 case DEVICE_ID_5704: 2014 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2015 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2016 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2017 dev_ok = B_TRUE; 2018 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2019 break; 2020 2021 case DEVICE_ID_5705C: 2022 case DEVICE_ID_5705M: 2023 case DEVICE_ID_5705MA3: 2024 case DEVICE_ID_5705F: 2025 case DEVICE_ID_5705_2: 2026 case DEVICE_ID_5754: 2027 if (cidp->device == DEVICE_ID_5754) { 2028 cidp->chip_label = 5754; 2029 cidp->pci_type = BGE_PCI_E; 2030 } else { 2031 cidp->chip_label = 5705; 2032 cidp->pci_type = BGE_PCI; 2033 } 2034 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2035 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2036 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2037 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2038 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2039 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2040 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2041 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2042 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2043 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2044 cidp->statistic_type = BGE_STAT_REG; 2045 dev_ok = B_TRUE; 2046 break; 2047 2048 case DEVICE_ID_5906: 2049 case DEVICE_ID_5906M: 2050 cidp->chip_label = 5906; 2051 cidp->pci_type = BGE_PCI_E; 2052 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2053 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2054 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2055 cidp->mbuf_base = bge_mbuf_pool_base; 2056 cidp->mbuf_length = bge_mbuf_pool_len; 2057 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2058 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2059 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2060 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2061 cidp->statistic_type = BGE_STAT_REG; 2062 dev_ok = B_TRUE; 2063 break; 2064 2065 case DEVICE_ID_5753: 2066 cidp->chip_label = 5753; 2067 cidp->pci_type = BGE_PCI_E; 2068 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2069 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2070 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2071 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2072 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2073 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2074 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2075 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2076 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2077 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2078 cidp->statistic_type = BGE_STAT_REG; 2079 dev_ok = B_TRUE; 2080 break; 2081 2082 case DEVICE_ID_5755: 2083 case DEVICE_ID_5755M: 2084 cidp->chip_label = 5755; 2085 cidp->pci_type = BGE_PCI_E; 2086 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2087 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2088 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2089 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2090 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2091 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2092 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2093 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2094 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2095 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2096 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2097 cidp->statistic_type = BGE_STAT_REG; 2098 dev_ok = B_TRUE; 2099 break; 2100 2101 case DEVICE_ID_5756M: 2102 /* 2103 * This is nearly identical to the 5755M. 2104 * (Actually reports the 5755 chip ID.) 2105 */ 2106 cidp->chip_label = 5756; 2107 cidp->pci_type = BGE_PCI_E; 2108 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2109 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2110 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2111 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2112 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2113 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2114 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2115 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2116 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2117 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2118 cidp->statistic_type = BGE_STAT_REG; 2119 dev_ok = B_TRUE; 2120 break; 2121 2122 case DEVICE_ID_5787: 2123 case DEVICE_ID_5787M: 2124 cidp->chip_label = 5787; 2125 cidp->pci_type = BGE_PCI_E; 2126 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2127 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2128 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2129 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2130 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2131 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2132 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2133 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2134 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2135 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2136 cidp->statistic_type = BGE_STAT_REG; 2137 dev_ok = B_TRUE; 2138 break; 2139 2140 case DEVICE_ID_5723: 2141 case DEVICE_ID_5761: 2142 case DEVICE_ID_5761E: 2143 cidp->chip_label = cidp->device == DEVICE_ID_5723 ? 5723: 5761; 2144 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2145 cidp->msi_enabled = bge_enable_msi; 2146 cidp->pci_type = BGE_PCI_E; 2147 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2148 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2149 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2150 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2151 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2152 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2153 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2154 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2155 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2156 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2157 cidp->statistic_type = BGE_STAT_REG; 2158 dev_ok = B_TRUE; 2159 break; 2160 2161 case DEVICE_ID_5780: 2162 cidp->chip_label = 5780; 2163 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2164 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2165 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2166 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2167 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2168 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2169 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2170 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2171 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2172 cidp->statistic_type = BGE_STAT_REG; 2173 cidp->pci_type = BGE_PCI; 2174 dev_ok = B_TRUE; 2175 break; 2176 2177 case DEVICE_ID_5782: 2178 /* 2179 * Apart from the label, we treat this as a 5705(?) 2180 */ 2181 cidp->chip_label = 5782; 2182 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2183 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2184 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2185 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2186 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2187 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2188 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2189 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2190 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2191 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2192 cidp->statistic_type = BGE_STAT_REG; 2193 dev_ok = B_TRUE; 2194 break; 2195 2196 case DEVICE_ID_5788: 2197 /* 2198 * Apart from the label, we treat this as a 5705(?) 2199 */ 2200 cidp->chip_label = 5788; 2201 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2202 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2203 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2204 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2205 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2206 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2207 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2208 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2209 cidp->statistic_type = BGE_STAT_REG; 2210 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2211 dev_ok = B_TRUE; 2212 break; 2213 2214 case DEVICE_ID_5714C: 2215 if (cidp->revision >= REVISION_ID_5714_A2) 2216 cidp->msi_enabled = bge_enable_msi; 2217 /* FALLTHRU */ 2218 case DEVICE_ID_5714S: 2219 cidp->chip_label = 5714; 2220 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2221 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2222 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2223 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2224 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2225 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2226 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2227 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2228 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2229 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2230 cidp->pci_type = BGE_PCI_E; 2231 cidp->statistic_type = BGE_STAT_REG; 2232 dev_ok = B_TRUE; 2233 break; 2234 2235 case DEVICE_ID_5715C: 2236 case DEVICE_ID_5715S: 2237 cidp->chip_label = 5715; 2238 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2239 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2240 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2241 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2242 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2243 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2244 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2245 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2246 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2247 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2248 cidp->pci_type = BGE_PCI_E; 2249 cidp->statistic_type = BGE_STAT_REG; 2250 if (cidp->revision >= REVISION_ID_5715_A2) 2251 cidp->msi_enabled = bge_enable_msi; 2252 dev_ok = B_TRUE; 2253 break; 2254 2255 case DEVICE_ID_5721: 2256 cidp->chip_label = 5721; 2257 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2258 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2259 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2260 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2261 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2262 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2263 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2264 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2265 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2266 cidp->pci_type = BGE_PCI_E; 2267 cidp->statistic_type = BGE_STAT_REG; 2268 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2269 dev_ok = B_TRUE; 2270 break; 2271 2272 case DEVICE_ID_5722: 2273 cidp->chip_label = 5722; 2274 cidp->pci_type = BGE_PCI_E; 2275 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2276 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2277 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2278 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2279 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2280 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2281 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2282 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2283 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2284 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2285 cidp->statistic_type = BGE_STAT_REG; 2286 dev_ok = B_TRUE; 2287 break; 2288 2289 case DEVICE_ID_5751: 2290 case DEVICE_ID_5751M: 2291 cidp->chip_label = 5751; 2292 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2293 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2294 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2295 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2296 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2297 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2298 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2299 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2300 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2301 cidp->pci_type = BGE_PCI_E; 2302 cidp->statistic_type = BGE_STAT_REG; 2303 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2304 dev_ok = B_TRUE; 2305 break; 2306 2307 case DEVICE_ID_5752: 2308 case DEVICE_ID_5752M: 2309 cidp->chip_label = 5752; 2310 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2311 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2312 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2313 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2314 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2315 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2316 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2317 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2318 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2319 cidp->pci_type = BGE_PCI_E; 2320 cidp->statistic_type = BGE_STAT_REG; 2321 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2322 dev_ok = B_TRUE; 2323 break; 2324 2325 case DEVICE_ID_5789: 2326 cidp->chip_label = 5789; 2327 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2328 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2329 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2330 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2331 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2332 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2333 cidp->pci_type = BGE_PCI_E; 2334 cidp->statistic_type = BGE_STAT_REG; 2335 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2336 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2337 cidp->msi_enabled = B_TRUE; 2338 dev_ok = B_TRUE; 2339 break; 2340 2341 } 2342 2343 /* 2344 * Setup the default jumbo parameter. 2345 */ 2346 cidp->ethmax_size = ETHERMAX; 2347 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2348 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2349 2350 /* 2351 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2352 * setup below jumbo specific parameters. 2353 * 2354 * For BCM5714/5715, there is only one standard receive ring. So the 2355 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2356 * feature is enabled. 2357 */ 2358 if (bge_jumbo_enable && 2359 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2360 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2361 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2362 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2363 cidp->mbuf_lo_water_rdma = 2364 RDMA_MBUF_LOWAT_5714_JUMBO; 2365 cidp->mbuf_lo_water_rmac = 2366 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2367 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2368 cidp->jumbo_slots = 0; 2369 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2370 } else { 2371 cidp->mbuf_lo_water_rdma = 2372 RDMA_MBUF_LOWAT_JUMBO; 2373 cidp->mbuf_lo_water_rmac = 2374 MAC_RX_MBUF_LOWAT_JUMBO; 2375 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2376 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2377 } 2378 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2379 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2380 cidp->ethmax_size = cidp->default_mtu + 2381 sizeof (struct ether_header); 2382 } 2383 2384 /* 2385 * Identify the NV memory type: SEEPROM or Flash? 2386 */ 2387 cidp->nvtype = bge_nvmem_id(bgep); 2388 2389 /* 2390 * Now, we want to check whether this device is part of a 2391 * supported subsystem (e.g., on the motherboard of a Sun 2392 * branded platform). 2393 * 2394 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2395 */ 2396 if (cidp->subven == VENDOR_ID_SUN) 2397 sys_ok = B_TRUE; 2398 2399 /* 2400 * Rule 2: If it's on the list on known subsystems, then it's OK. 2401 * Note: 0x14e41647 should *not* appear in the list, but the code 2402 * doesn't enforce that. 2403 */ 2404 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2405 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2406 if (err == DDI_PROP_SUCCESS) { 2407 /* 2408 * Got the list; scan for a matching subsystem vendor/device 2409 */ 2410 subid = (cidp->subven << 16) | cidp->subdev; 2411 while (i--) 2412 if (ids[i] == subid) 2413 sys_ok = B_TRUE; 2414 ddi_prop_free(ids); 2415 } 2416 2417 /* 2418 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2419 * 2420 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2421 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2422 * we have to check specially for the exact device paths to the 2423 * motherboard devices on those platforms ;-( 2424 * 2425 * Note: we can't just use the "supported-subsystems" mechanism 2426 * above, because the entry would have to be 0x14e41647 -- which 2427 * would then accept *any* plugin card that *didn't* contain a 2428 * (valid) SEEPROM ;-( 2429 */ 2430 sysname = ddi_node_name(ddi_root_node()); 2431 devname = ddi_pathname(bgep->devinfo, buf); 2432 ASSERT(strlen(devname) > 0); 2433 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2434 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2435 sys_ok = B_TRUE; 2436 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2437 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2438 sys_ok = B_TRUE; 2439 2440 /* 2441 * Now check what we've discovered: is this truly a supported 2442 * chip on (the motherboard of) a supported platform? 2443 * 2444 * Possible problems here: 2445 * 1) it's a completely unheard-of chip 2446 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2447 * 3) it's a chip we would support if it were on the motherboard 2448 * of a Sun platform, but this one isn't ;-( 2449 */ 2450 if (cidp->chip_label == 0) 2451 bge_problem(bgep, 2452 "Device 'pci%04x,%04x' not recognized (%d?)", 2453 cidp->vendor, cidp->device, cidp->device); 2454 else if (!dev_ok) 2455 bge_problem(bgep, 2456 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2457 cidp->vendor, cidp->device, cidp->chip_label, 2458 cidp->revision); 2459 #if BGE_DEBUGGING 2460 else if (!sys_ok) 2461 bge_problem(bgep, 2462 "%d-based subsystem 'pci%04x,%04x' not validated", 2463 cidp->chip_label, cidp->subven, cidp->subdev); 2464 #endif 2465 else 2466 cidp->flags |= CHIP_FLAG_SUPPORTED; 2467 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2468 return (EIO); 2469 return (0); 2470 } 2471 2472 void 2473 bge_chip_msi_trig(bge_t *bgep) 2474 { 2475 uint32_t regval; 2476 2477 regval = bgep->param_msi_cnt<<4; 2478 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2479 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2480 } 2481 2482 /* 2483 * Various registers that control the chip's internal engines (state 2484 * machines) have a <reset> and <enable> bits (fortunately, in the 2485 * same place in each such register :-). 2486 * 2487 * To reset the state machine, the <reset> bit must be written with 1; 2488 * it will then read back as 1 while the reset is in progress, but 2489 * self-clear to 0 when the reset completes. 2490 * 2491 * To enable a state machine, one must set the <enable> bit, which 2492 * will continue to read back as 0 until the state machine is running. 2493 * 2494 * To disable a state machine, the <enable> bit must be cleared, but 2495 * it will continue to read back as 1 until the state machine actually 2496 * stops. 2497 * 2498 * This routine implements polling for completion of a reset, enable 2499 * or disable operation, returning B_TRUE on success (bit reached the 2500 * required state) or B_FALSE on timeout (200*100us == 20ms). 2501 */ 2502 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2503 uint32_t mask, uint32_t val); 2504 #pragma no_inline(bge_chip_poll_engine) 2505 2506 static boolean_t 2507 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2508 uint32_t mask, uint32_t val) 2509 { 2510 uint32_t regval; 2511 uint32_t n; 2512 2513 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2514 (void *)bgep, regno, mask, val)); 2515 2516 for (n = 200; n; --n) { 2517 regval = bge_reg_get32(bgep, regno); 2518 if ((regval & mask) == val) 2519 return (B_TRUE); 2520 drv_usecwait(100); 2521 } 2522 2523 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2524 return (B_FALSE); 2525 } 2526 2527 /* 2528 * Various registers that control the chip's internal engines (state 2529 * machines) have a <reset> bit (fortunately, in the same place in 2530 * each such register :-). To reset the state machine, this bit must 2531 * be written with 1; it will then read back as 1 while the reset is 2532 * in progress, but self-clear to 0 when the reset completes. 2533 * 2534 * This code sets the bit, then polls for it to read back as zero. 2535 * The return value is B_TRUE on success (reset bit cleared itself), 2536 * or B_FALSE if the state machine didn't recover :( 2537 * 2538 * NOTE: the Core reset is similar to other resets, except that we 2539 * can't poll for completion, since the Core reset disables memory 2540 * access! So we just have to assume that it will all complete in 2541 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2542 */ 2543 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2544 #pragma no_inline(bge_chip_reset_engine) 2545 2546 static boolean_t 2547 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2548 { 2549 uint32_t regval; 2550 uint32_t val32; 2551 2552 regval = bge_reg_get32(bgep, regno); 2553 2554 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2555 (void *)bgep, regno)); 2556 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2557 regno, regval)); 2558 2559 regval |= STATE_MACHINE_RESET_BIT; 2560 2561 switch (regno) { 2562 case MISC_CONFIG_REG: 2563 /* 2564 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2565 * resetting PCIE block and bringing PCIE link down, bit 29 2566 * in the register needs to be set first, and then set it again 2567 * while the reset bit is written. 2568 * See:P500 of 57xx-PG102-RDS.pdf. 2569 */ 2570 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2571 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2572 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2573 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2574 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2575 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2576 if (bgep->chipid.pci_type == BGE_PCI_E) { 2577 if (bgep->chipid.asic_rev == 2578 MHCR_CHIP_REV_5751_A0 || 2579 bgep->chipid.asic_rev == 2580 MHCR_CHIP_REV_5721_A0 || 2581 bgep->chipid.asic_rev == 2582 MHCR_CHIP_REV_5755_A0) { 2583 val32 = bge_reg_get32(bgep, 2584 PHY_TEST_CTRL_REG); 2585 if (val32 == (PHY_PCIE_SCRAM_MODE | 2586 PHY_PCIE_LTASS_MODE)) 2587 bge_reg_put32(bgep, 2588 PHY_TEST_CTRL_REG, 2589 PHY_PCIE_SCRAM_MODE); 2590 val32 = pci_config_get32 2591 (bgep->cfg_handle, 2592 PCI_CONF_BGE_CLKCTL); 2593 val32 |= CLKCTL_PCIE_A0_FIX; 2594 pci_config_put32(bgep->cfg_handle, 2595 PCI_CONF_BGE_CLKCTL, val32); 2596 } 2597 bge_reg_set32(bgep, regno, 2598 MISC_CONFIG_GRC_RESET_DISABLE); 2599 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2600 } 2601 } 2602 2603 /* 2604 * Special case - causes Core reset 2605 * 2606 * On SPARC v9 we want to ensure that we don't start 2607 * timing until the I/O access has actually reached 2608 * the chip, otherwise we might make the next access 2609 * too early. And we can't just force the write out 2610 * by following it with a read (even to config space) 2611 * because that would cause the fault we're trying 2612 * to avoid. Hence the need for membar_sync() here. 2613 */ 2614 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2615 #ifdef __sparcv9 2616 membar_sync(); 2617 #endif /* __sparcv9 */ 2618 /* 2619 * On some platforms,system need about 300us for 2620 * link setup. 2621 */ 2622 drv_usecwait(300); 2623 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2624 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2625 bge_reg_clr32( 2626 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2627 } 2628 2629 if (bgep->chipid.pci_type == BGE_PCI_E) { 2630 /* PCI-E device need more reset time */ 2631 drv_usecwait(120000); 2632 2633 /* Set PCIE max payload size and clear error status. */ 2634 if ((bgep->chipid.chip_label == 5721) || 2635 (bgep->chipid.chip_label == 5751) || 2636 (bgep->chipid.chip_label == 5752) || 2637 (bgep->chipid.chip_label == 5789) || 2638 (bgep->chipid.chip_label == 5906)) { 2639 pci_config_put16(bgep->cfg_handle, 2640 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2641 pci_config_put16(bgep->cfg_handle, 2642 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2643 } 2644 2645 if ((bgep->chipid.chip_label == 5723) || 2646 (bgep->chipid.chip_label == 5761)) { 2647 pci_config_put16(bgep->cfg_handle, 2648 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2649 pci_config_put16(bgep->cfg_handle, 2650 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2651 } 2652 } 2653 2654 BGE_PCICHK(bgep); 2655 return (B_TRUE); 2656 2657 default: 2658 bge_reg_put32(bgep, regno, regval); 2659 return (bge_chip_poll_engine(bgep, regno, 2660 STATE_MACHINE_RESET_BIT, 0)); 2661 } 2662 } 2663 2664 /* 2665 * Various registers that control the chip's internal engines (state 2666 * machines) have an <enable> bit (fortunately, in the same place in 2667 * each such register :-). To stop the state machine, this bit must 2668 * be written with 0, then polled to see when the state machine has 2669 * actually stopped. 2670 * 2671 * The return value is B_TRUE on success (enable bit cleared), or 2672 * B_FALSE if the state machine didn't stop :( 2673 */ 2674 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2675 uint32_t morebits); 2676 #pragma no_inline(bge_chip_disable_engine) 2677 2678 static boolean_t 2679 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2680 { 2681 uint32_t regval; 2682 2683 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2684 (void *)bgep, regno, morebits)); 2685 2686 switch (regno) { 2687 case FTQ_RESET_REG: 2688 /* 2689 * For Schumacher's bugfix CR6490108 2690 */ 2691 #ifdef BGE_IPMI_ASF 2692 #ifdef BGE_NETCONSOLE 2693 if (bgep->asf_enabled) 2694 return (B_TRUE); 2695 #endif 2696 #endif 2697 /* 2698 * Not quite like the others; it doesn't 2699 * have an <enable> bit, but instead we 2700 * have to set and then clear all the bits 2701 */ 2702 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2703 drv_usecwait(100); 2704 bge_reg_put32(bgep, regno, 0); 2705 return (B_TRUE); 2706 2707 default: 2708 regval = bge_reg_get32(bgep, regno); 2709 regval &= ~STATE_MACHINE_ENABLE_BIT; 2710 regval &= ~morebits; 2711 bge_reg_put32(bgep, regno, regval); 2712 return (bge_chip_poll_engine(bgep, regno, 2713 STATE_MACHINE_ENABLE_BIT, 0)); 2714 } 2715 } 2716 2717 /* 2718 * Various registers that control the chip's internal engines (state 2719 * machines) have an <enable> bit (fortunately, in the same place in 2720 * each such register :-). To start the state machine, this bit must 2721 * be written with 1, then polled to see when the state machine has 2722 * actually started. 2723 * 2724 * The return value is B_TRUE on success (enable bit set), or 2725 * B_FALSE if the state machine didn't start :( 2726 */ 2727 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2728 uint32_t morebits); 2729 #pragma no_inline(bge_chip_enable_engine) 2730 2731 static boolean_t 2732 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2733 { 2734 uint32_t regval; 2735 2736 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2737 (void *)bgep, regno, morebits)); 2738 2739 switch (regno) { 2740 case FTQ_RESET_REG: 2741 #ifdef BGE_IPMI_ASF 2742 #ifdef BGE_NETCONSOLE 2743 if (bgep->asf_enabled) 2744 return (B_TRUE); 2745 #endif 2746 #endif 2747 /* 2748 * Not quite like the others; it doesn't 2749 * have an <enable> bit, but instead we 2750 * have to set and then clear all the bits 2751 */ 2752 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2753 drv_usecwait(100); 2754 bge_reg_put32(bgep, regno, 0); 2755 return (B_TRUE); 2756 2757 default: 2758 regval = bge_reg_get32(bgep, regno); 2759 regval |= STATE_MACHINE_ENABLE_BIT; 2760 regval |= morebits; 2761 bge_reg_put32(bgep, regno, regval); 2762 return (bge_chip_poll_engine(bgep, regno, 2763 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2764 } 2765 } 2766 2767 /* 2768 * Reprogram the Ethernet, Transmit, and Receive MAC 2769 * modes to match the param_* variables 2770 */ 2771 void bge_sync_mac_modes(bge_t *bgep); 2772 #pragma no_inline(bge_sync_mac_modes) 2773 2774 void 2775 bge_sync_mac_modes(bge_t *bgep) 2776 { 2777 uint32_t macmode; 2778 uint32_t regval; 2779 2780 ASSERT(mutex_owned(bgep->genlock)); 2781 2782 /* 2783 * Reprogram the Ethernet MAC mode ... 2784 */ 2785 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2786 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2787 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2788 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2789 macmode |= ETHERNET_MODE_LINK_POLARITY; 2790 else 2791 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2792 else 2793 macmode |= ETHERNET_MODE_LINK_POLARITY; 2794 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2795 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2796 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2797 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2798 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2799 else 2800 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2801 } else if (bgep->param_link_speed == 10 || 2802 bgep->param_link_speed == 100) 2803 macmode |= ETHERNET_MODE_PORTMODE_MII; 2804 else 2805 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2806 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2807 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2808 else 2809 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2810 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2811 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2812 else 2813 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2814 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2815 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2816 (void *)bgep, regval, macmode)); 2817 2818 /* 2819 * ... the Transmit MAC mode ... 2820 */ 2821 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2822 if (bgep->param_link_tx_pause) 2823 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2824 else 2825 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2826 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2827 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2828 (void *)bgep, regval, macmode)); 2829 2830 /* 2831 * ... and the Receive MAC mode 2832 */ 2833 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2834 if (bgep->param_link_rx_pause) 2835 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2836 else 2837 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2838 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2839 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2840 (void *)bgep, regval, macmode)); 2841 } 2842 2843 /* 2844 * bge_chip_sync() -- program the chip with the unicast MAC address, 2845 * the multicast hash table, the required level of promiscuity, and 2846 * the current loopback mode ... 2847 */ 2848 #ifdef BGE_IPMI_ASF 2849 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2850 #else 2851 int bge_chip_sync(bge_t *bgep); 2852 #endif 2853 #pragma no_inline(bge_chip_sync) 2854 2855 int 2856 #ifdef BGE_IPMI_ASF 2857 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2858 #else 2859 bge_chip_sync(bge_t *bgep) 2860 #endif 2861 { 2862 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2863 boolean_t promisc; 2864 uint64_t macaddr; 2865 uint32_t fill = 0; 2866 int i, j; 2867 int retval = DDI_SUCCESS; 2868 2869 BGE_TRACE(("bge_chip_sync($%p)", 2870 (void *)bgep)); 2871 2872 ASSERT(mutex_owned(bgep->genlock)); 2873 2874 promisc = B_FALSE; 2875 fill = ~(uint32_t)0; 2876 2877 if (bgep->promisc) 2878 promisc = B_TRUE; 2879 else 2880 fill = (uint32_t)0; 2881 2882 /* 2883 * If the TX/RX MAC engines are already running, we should stop 2884 * them (and reset the RX engine) before changing the parameters. 2885 * If they're not running, this will have no effect ... 2886 * 2887 * NOTE: this is currently disabled by default because stopping 2888 * and restarting the Tx engine may cause an outgoing packet in 2889 * transit to be truncated. Also, stopping and restarting the 2890 * Rx engine seems to not work correctly on the 5705. Testing 2891 * has not (yet!) revealed any problems with NOT stopping and 2892 * restarting these engines (and Broadcom say their drivers don't 2893 * do this), but if it is found to cause problems, this variable 2894 * can be patched to re-enable the old behaviour ... 2895 */ 2896 if (bge_stop_start_on_sync) { 2897 #ifdef BGE_IPMI_ASF 2898 if (!bgep->asf_enabled) { 2899 if (!bge_chip_disable_engine(bgep, 2900 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2901 retval = DDI_FAILURE; 2902 } else { 2903 if (!bge_chip_disable_engine(bgep, 2904 RECEIVE_MAC_MODE_REG, 0)) 2905 retval = DDI_FAILURE; 2906 } 2907 #else 2908 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2909 RECEIVE_MODE_KEEP_VLAN_TAG)) 2910 retval = DDI_FAILURE; 2911 #endif 2912 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2913 retval = DDI_FAILURE; 2914 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2915 retval = DDI_FAILURE; 2916 } 2917 2918 /* 2919 * Reprogram the hashed multicast address table ... 2920 */ 2921 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2922 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2923 2924 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2925 bge_reg_put32(bgep, MAC_HASH_REG(i), 2926 bgep->mcast_hash[i] | fill); 2927 2928 #ifdef BGE_IPMI_ASF 2929 if (!bgep->asf_enabled || !asf_keeplive) { 2930 #endif 2931 /* 2932 * Transform the MAC address(es) from host to chip format, then 2933 * reprogram the transmit random backoff seed and the unicast 2934 * MAC address(es) ... 2935 */ 2936 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2937 for (i = 0, macaddr = 0ull; 2938 i < ETHERADDRL; ++i) { 2939 macaddr <<= 8; 2940 macaddr |= bgep->curr_addr[j].addr[i]; 2941 } 2942 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2943 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2944 2945 BGE_DEBUG(("bge_chip_sync($%p) " 2946 "setting MAC address %012llx", 2947 (void *)bgep, macaddr)); 2948 } 2949 #ifdef BGE_IPMI_ASF 2950 } 2951 #endif 2952 /* 2953 * Set random seed of backoff interval 2954 * - Writing zero means no backoff interval 2955 */ 2956 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2957 if (fill == 0) 2958 fill = 1; 2959 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2960 2961 /* 2962 * Set or clear the PROMISCUOUS mode bit 2963 */ 2964 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2965 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2966 2967 /* 2968 * Sync the rest of the MAC modes too ... 2969 */ 2970 bge_sync_mac_modes(bgep); 2971 2972 /* 2973 * Restart RX/TX MAC engines if required ... 2974 */ 2975 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2976 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2977 retval = DDI_FAILURE; 2978 #ifdef BGE_IPMI_ASF 2979 if (!bgep->asf_enabled) { 2980 if (!bge_chip_enable_engine(bgep, 2981 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2982 retval = DDI_FAILURE; 2983 } else { 2984 if (!bge_chip_enable_engine(bgep, 2985 RECEIVE_MAC_MODE_REG, 0)) 2986 retval = DDI_FAILURE; 2987 } 2988 #else 2989 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2990 RECEIVE_MODE_KEEP_VLAN_TAG)) 2991 retval = DDI_FAILURE; 2992 #endif 2993 } 2994 return (retval); 2995 } 2996 2997 /* 2998 * This array defines the sequence of state machine control registers 2999 * in which the <enable> bit must be cleared to bring the chip to a 3000 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 3001 */ 3002 static bge_regno_t shutdown_engine_regs[] = { 3003 RECEIVE_MAC_MODE_REG, 3004 RCV_BD_INITIATOR_MODE_REG, 3005 RCV_LIST_PLACEMENT_MODE_REG, 3006 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3007 RCV_DATA_BD_INITIATOR_MODE_REG, 3008 RCV_DATA_COMPLETION_MODE_REG, 3009 RCV_BD_COMPLETION_MODE_REG, 3010 3011 SEND_BD_SELECTOR_MODE_REG, 3012 SEND_BD_INITIATOR_MODE_REG, 3013 SEND_DATA_INITIATOR_MODE_REG, 3014 READ_DMA_MODE_REG, 3015 SEND_DATA_COMPLETION_MODE_REG, 3016 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3017 SEND_BD_COMPLETION_MODE_REG, 3018 TRANSMIT_MAC_MODE_REG, 3019 3020 HOST_COALESCE_MODE_REG, 3021 WRITE_DMA_MODE_REG, 3022 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3023 FTQ_RESET_REG, /* special - see code */ 3024 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3025 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3026 BGE_REGNO_NONE /* terminator */ 3027 }; 3028 3029 #ifndef __sparc 3030 static bge_regno_t quiesce_regs[] = { 3031 READ_DMA_MODE_REG, 3032 DMA_COMPLETION_MODE_REG, 3033 WRITE_DMA_MODE_REG, 3034 BGE_REGNO_NONE 3035 }; 3036 3037 void bge_chip_stop_nonblocking(bge_t *bgep); 3038 #pragma no_inline(bge_chip_stop_nonblocking) 3039 3040 /* 3041 * This function is called by bge_quiesce(). We 3042 * turn off all the DMA engines here. 3043 */ 3044 void 3045 bge_chip_stop_nonblocking(bge_t *bgep) 3046 { 3047 bge_regno_t *rbp; 3048 3049 /* 3050 * Flag that no more activity may be initiated 3051 */ 3052 bgep->progress &= ~PROGRESS_READY; 3053 3054 rbp = quiesce_regs; 3055 while (*rbp != BGE_REGNO_NONE) { 3056 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3057 ++rbp; 3058 } 3059 3060 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3061 } 3062 3063 #endif 3064 3065 /* 3066 * bge_chip_stop() -- stop all chip processing 3067 * 3068 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3069 * we've detected a problem internally; otherwise, this is a normal 3070 * (clean) stop (at user request i.e. the last STREAM has been closed). 3071 */ 3072 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3073 #pragma no_inline(bge_chip_stop) 3074 3075 void 3076 bge_chip_stop(bge_t *bgep, boolean_t fault) 3077 { 3078 bge_regno_t regno; 3079 bge_regno_t *rbp; 3080 boolean_t ok; 3081 3082 BGE_TRACE(("bge_chip_stop($%p)", 3083 (void *)bgep)); 3084 3085 ASSERT(mutex_owned(bgep->genlock)); 3086 3087 rbp = shutdown_engine_regs; 3088 /* 3089 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3090 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3091 * -ory arbiter should not be disabled. 3092 */ 3093 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3094 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3095 ok &= bge_chip_disable_engine(bgep, regno, 0); 3096 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3097 (regno != DMA_COMPLETION_MODE_REG) && 3098 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3099 (regno != BUFFER_MANAGER_MODE_REG) && 3100 (regno != MEMORY_ARBITER_MODE_REG)) 3101 ok &= bge_chip_disable_engine(bgep, 3102 regno, 0); 3103 } 3104 3105 if (!ok && !fault) 3106 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3107 3108 /* 3109 * Finally, disable (all) MAC events & clear the MAC status 3110 */ 3111 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3112 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3113 3114 /* 3115 * if we're stopping the chip because of a detected fault then do 3116 * appropriate actions 3117 */ 3118 if (fault) { 3119 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3120 bgep->bge_chip_state = BGE_CHIP_FAULT; 3121 if (!bgep->manual_reset) 3122 ddi_fm_service_impact(bgep->devinfo, 3123 DDI_SERVICE_LOST); 3124 if (bgep->bge_dma_error) { 3125 /* 3126 * need to free buffers in case the fault was 3127 * due to a memory error in a buffer - got to 3128 * do a fair bit of tidying first 3129 */ 3130 if (bgep->progress & PROGRESS_KSTATS) { 3131 bge_fini_kstats(bgep); 3132 bgep->progress &= ~PROGRESS_KSTATS; 3133 } 3134 if (bgep->progress & PROGRESS_INTR) { 3135 bge_intr_disable(bgep); 3136 rw_enter(bgep->errlock, RW_WRITER); 3137 bge_fini_rings(bgep); 3138 rw_exit(bgep->errlock); 3139 bgep->progress &= ~PROGRESS_INTR; 3140 } 3141 if (bgep->progress & PROGRESS_BUFS) { 3142 bge_free_bufs(bgep); 3143 bgep->progress &= ~PROGRESS_BUFS; 3144 } 3145 bgep->bge_dma_error = B_FALSE; 3146 } 3147 } 3148 } else 3149 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3150 } 3151 3152 /* 3153 * Poll for completion of chip's ROM firmware; also, at least on the 3154 * first time through, find and return the hardware MAC address, if any. 3155 */ 3156 static uint64_t bge_poll_firmware(bge_t *bgep); 3157 #pragma no_inline(bge_poll_firmware) 3158 3159 static uint64_t 3160 bge_poll_firmware(bge_t *bgep) 3161 { 3162 uint64_t magic; 3163 uint64_t mac; 3164 uint32_t gen, val; 3165 uint32_t i; 3166 3167 /* 3168 * Step 19: poll for firmware completion (GENCOMM port set 3169 * to the ones complement of T3_MAGIC_NUMBER). 3170 * 3171 * While we're at it, we also read the MAC address register; 3172 * at some stage the firmware will load this with the 3173 * factory-set value. 3174 * 3175 * When both the magic number and the MAC address are set, 3176 * we're done; but we impose a time limit of one second 3177 * (1000*1000us) in case the firmware fails in some fashion 3178 * or the SEEPROM that provides that MAC address isn't fitted. 3179 * 3180 * After the first time through (chip state != INITIAL), we 3181 * don't need the MAC address to be set (we've already got it 3182 * or not, from the first time), so we don't wait for it, but 3183 * we still have to wait for the T3_MAGIC_NUMBER. 3184 * 3185 * Note: the magic number is only a 32-bit quantity, but the NIC 3186 * memory is 64-bit (and big-endian) internally. Addressing the 3187 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3188 * it work correctly on both big- and little-endian hosts. 3189 */ 3190 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3191 MHCR_CHIP_ASIC_REV_5906) { 3192 for (i = 0; i < 1000; ++i) { 3193 drv_usecwait(1000); 3194 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3195 if (val & VCPU_INIT_DONE) 3196 break; 3197 } 3198 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3199 (void *)bgep, i)); 3200 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3201 } else { 3202 for (i = 0; i < 1000; ++i) { 3203 drv_usecwait(1000); 3204 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3205 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3206 drv_usecwait(100000); 3207 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3208 #ifdef BGE_IPMI_ASF 3209 if (!bgep->asf_enabled) { 3210 #endif 3211 if (gen != ~T3_MAGIC_NUMBER) 3212 continue; 3213 #ifdef BGE_IPMI_ASF 3214 } 3215 #endif 3216 if (mac != 0ULL) 3217 break; 3218 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3219 break; 3220 } 3221 } 3222 3223 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3224 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3225 (void *)bgep, gen, i)); 3226 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3227 mac, magic)); 3228 3229 return (mac); 3230 } 3231 3232 /* 3233 * Maximum times of trying to get the NVRAM access lock 3234 * by calling bge_nvmem_acquire() 3235 */ 3236 #define MAX_TRY_NVMEM_ACQUIRE 10000 3237 3238 #ifdef BGE_IPMI_ASF 3239 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3240 #else 3241 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3242 #endif 3243 #pragma no_inline(bge_chip_reset) 3244 3245 int 3246 #ifdef BGE_IPMI_ASF 3247 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3248 #else 3249 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3250 #endif 3251 { 3252 chip_id_t chipid; 3253 uint64_t mac; 3254 uint64_t magic; 3255 uint32_t modeflags; 3256 uint32_t mhcr; 3257 uint32_t sx0; 3258 uint32_t i, tries; 3259 #ifdef BGE_IPMI_ASF 3260 uint32_t mailbox; 3261 #endif 3262 int retval = DDI_SUCCESS; 3263 3264 BGE_TRACE(("bge_chip_reset($%p, %d)", 3265 (void *)bgep, enable_dma)); 3266 3267 ASSERT(mutex_owned(bgep->genlock)); 3268 3269 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3270 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3271 3272 /* 3273 * Do we need to stop the chip cleanly before resetting? 3274 */ 3275 switch (bgep->bge_chip_state) { 3276 default: 3277 _NOTE(NOTREACHED) 3278 return (DDI_FAILURE); 3279 3280 case BGE_CHIP_INITIAL: 3281 case BGE_CHIP_STOPPED: 3282 case BGE_CHIP_RESET: 3283 break; 3284 3285 case BGE_CHIP_RUNNING: 3286 case BGE_CHIP_ERROR: 3287 case BGE_CHIP_FAULT: 3288 bge_chip_stop(bgep, B_FALSE); 3289 break; 3290 } 3291 3292 #ifdef BGE_IPMI_ASF 3293 if (bgep->asf_enabled) { 3294 #ifdef __sparc 3295 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3296 MHCR_ENABLE_TAGGED_STATUS_MODE | 3297 MHCR_MASK_INTERRUPT_MODE | 3298 MHCR_MASK_PCI_INT_OUTPUT | 3299 MHCR_CLEAR_INTERRUPT_INTA | 3300 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3301 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3302 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3303 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3304 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3305 MEMORY_ARBITER_ENABLE); 3306 #endif 3307 if (asf_mode == ASF_MODE_INIT) { 3308 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3309 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3310 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3311 } 3312 } 3313 #endif 3314 /* 3315 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3316 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3317 * 3318 * Before reset Core clock,it is 3319 * also required to initialize the Memory Arbiter as specified in step9 3320 * and Misc Host Control Register as specified in step-13 3321 * Step 4-5: reset Core clock & wait for completion 3322 * Steps 6-8: are done by bge_chip_cfg_init() 3323 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3324 */ 3325 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3326 retval = DDI_FAILURE; 3327 3328 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3329 MHCR_ENABLE_TAGGED_STATUS_MODE | 3330 MHCR_MASK_INTERRUPT_MODE | 3331 MHCR_MASK_PCI_INT_OUTPUT | 3332 MHCR_CLEAR_INTERRUPT_INTA; 3333 #ifdef _BIG_ENDIAN 3334 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3335 #endif /* _BIG_ENDIAN */ 3336 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3337 #ifdef BGE_IPMI_ASF 3338 if (bgep->asf_enabled) 3339 bgep->asf_wordswapped = B_FALSE; 3340 #endif 3341 /* 3342 * NVRAM Corruption Workaround 3343 */ 3344 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3345 if (bge_nvmem_acquire(bgep) != EAGAIN) 3346 break; 3347 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3348 BGE_DEBUG(("%s: fail to acquire nvram lock", 3349 bgep->ifname)); 3350 3351 #ifdef BGE_IPMI_ASF 3352 if (!bgep->asf_enabled) { 3353 #endif 3354 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3355 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3356 #ifdef BGE_IPMI_ASF 3357 } 3358 #endif 3359 3360 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3361 retval = DDI_FAILURE; 3362 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3363 3364 /* 3365 * Step 8a: This may belong elsewhere, but BCM5721 needs 3366 * a bit set to avoid a fifo overflow/underflow bug. 3367 */ 3368 if ((bgep->chipid.chip_label == 5721) || 3369 (bgep->chipid.chip_label == 5751) || 3370 (bgep->chipid.chip_label == 5752) || 3371 (bgep->chipid.chip_label == 5755) || 3372 (bgep->chipid.chip_label == 5756) || 3373 (bgep->chipid.chip_label == 5789) || 3374 (bgep->chipid.chip_label == 5906)) 3375 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3376 3377 3378 /* 3379 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3380 * not be changed. 3381 */ 3382 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3383 retval = DDI_FAILURE; 3384 3385 /* 3386 * Steps 10-11: configure PIO endianness options and 3387 * enable indirect register access -- already done 3388 * Steps 12-13: enable writing to the PCI state & clock 3389 * control registers -- not required; we aren't going to 3390 * use those features. 3391 * Steps 14-15: Configure DMA endianness options. See 3392 * the comments on the setting of the MHCR above. 3393 */ 3394 #ifdef _BIG_ENDIAN 3395 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3396 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3397 #else 3398 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3399 #endif /* _BIG_ENDIAN */ 3400 #ifdef BGE_IPMI_ASF 3401 if (bgep->asf_enabled) 3402 modeflags |= MODE_HOST_STACK_UP; 3403 #endif 3404 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3405 3406 #ifdef BGE_IPMI_ASF 3407 if (bgep->asf_enabled) { 3408 #ifdef __sparc 3409 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3410 MEMORY_ARBITER_ENABLE | 3411 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3412 #endif 3413 3414 #ifdef BGE_NETCONSOLE 3415 if (!bgep->asf_newhandshake) { 3416 if ((asf_mode == ASF_MODE_INIT) || 3417 (asf_mode == ASF_MODE_POST_INIT)) { 3418 bge_asf_post_reset_old_mode(bgep, 3419 BGE_INIT_RESET); 3420 } else { 3421 bge_asf_post_reset_old_mode(bgep, 3422 BGE_SHUTDOWN_RESET); 3423 } 3424 } 3425 #endif 3426 3427 /* Wait for NVRAM init */ 3428 i = 0; 3429 drv_usecwait(5000); 3430 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3431 3432 while ((mailbox != (uint32_t) 3433 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3434 (i < 10000)) { 3435 drv_usecwait(100); 3436 mailbox = bge_nic_get32(bgep, 3437 BGE_FIRMWARE_MAILBOX); 3438 i++; 3439 } 3440 3441 #ifndef BGE_NETCONSOLE 3442 if (!bgep->asf_newhandshake) { 3443 if ((asf_mode == ASF_MODE_INIT) || 3444 (asf_mode == ASF_MODE_POST_INIT)) { 3445 3446 bge_asf_post_reset_old_mode(bgep, 3447 BGE_INIT_RESET); 3448 } else { 3449 bge_asf_post_reset_old_mode(bgep, 3450 BGE_SHUTDOWN_RESET); 3451 } 3452 } 3453 #endif 3454 } 3455 #endif 3456 /* 3457 * Steps 16-17: poll for firmware completion 3458 */ 3459 mac = bge_poll_firmware(bgep); 3460 3461 /* 3462 * Step 18: enable external memory -- doesn't apply. 3463 * 3464 * However we take the opportunity to set the MLCR anyway, as 3465 * this register also controls the SEEPROM auto-access method 3466 * which we may want to use later ... 3467 * 3468 * The proper value here depends on the way the chip is wired 3469 * into the circuit board, as this register *also* controls which 3470 * of the "Miscellaneous I/O" pins are driven as outputs and the 3471 * values driven onto those pins! 3472 * 3473 * See also step 74 in the PRM ... 3474 */ 3475 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3476 bgep->chipid.bge_mlcr_default); 3477 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3478 3479 /* 3480 * Step 20: clear the Ethernet MAC mode register 3481 */ 3482 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3483 3484 /* 3485 * Step 21: restore cache-line-size, latency timer, and 3486 * subsystem ID registers to their original values (not 3487 * those read into the local structure <chipid>, 'cos 3488 * that was after they were cleared by the RESET). 3489 * 3490 * Note: the Subsystem Vendor/Device ID registers are not 3491 * directly writable in config space, so we use the shadow 3492 * copy in "Page Zero" of register space to restore them 3493 * both in one go ... 3494 */ 3495 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3496 bgep->chipid.clsize); 3497 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3498 bgep->chipid.latency); 3499 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3500 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3501 3502 /* 3503 * The SEND INDEX registers should be reset to zero by the 3504 * global chip reset; if they're not, there'll be trouble 3505 * later on. 3506 */ 3507 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3508 if (sx0 != 0) { 3509 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3510 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3511 retval = DDI_FAILURE; 3512 } 3513 3514 /* Enable MSI code */ 3515 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3516 bge_reg_set32(bgep, MSI_MODE_REG, 3517 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3518 3519 /* 3520 * On the first time through, save the factory-set MAC address 3521 * (if any). If bge_poll_firmware() above didn't return one 3522 * (from a chip register) consider looking in the attached NV 3523 * memory device, if any. Once we have it, we save it in both 3524 * register-image (64-bit) and byte-array forms. All-zero and 3525 * all-one addresses are not valid, and we refuse to stash those. 3526 */ 3527 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3528 if (mac == 0ULL) 3529 mac = bge_get_nvmac(bgep); 3530 if (mac != 0ULL && mac != ~0ULL) { 3531 bgep->chipid.hw_mac_addr = mac; 3532 for (i = ETHERADDRL; i-- != 0; ) { 3533 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3534 mac >>= 8; 3535 } 3536 bgep->chipid.vendor_addr.set = B_TRUE; 3537 } 3538 } 3539 3540 #ifdef BGE_IPMI_ASF 3541 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3542 if (asf_mode != ASF_MODE_NONE) { 3543 if ((asf_mode == ASF_MODE_INIT) || 3544 (asf_mode == ASF_MODE_POST_INIT)) { 3545 3546 bge_asf_post_reset_new_mode(bgep, 3547 BGE_INIT_RESET); 3548 } else { 3549 bge_asf_post_reset_new_mode(bgep, 3550 BGE_SHUTDOWN_RESET); 3551 } 3552 } 3553 } 3554 #endif 3555 3556 /* 3557 * Record the new state 3558 */ 3559 bgep->chip_resets += 1; 3560 bgep->bge_chip_state = BGE_CHIP_RESET; 3561 return (retval); 3562 } 3563 3564 /* 3565 * bge_chip_start() -- start the chip transmitting and/or receiving, 3566 * including enabling interrupts 3567 */ 3568 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3569 #pragma no_inline(bge_chip_start) 3570 3571 int 3572 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3573 { 3574 uint32_t coalmode; 3575 uint32_t ledctl; 3576 uint32_t mtu; 3577 uint32_t maxring; 3578 uint32_t stats_mask; 3579 uint32_t dma_wrprio; 3580 uint64_t ring; 3581 int retval = DDI_SUCCESS; 3582 3583 BGE_TRACE(("bge_chip_start($%p)", 3584 (void *)bgep)); 3585 3586 ASSERT(mutex_owned(bgep->genlock)); 3587 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3588 3589 /* 3590 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3591 * The document specifies 95 separate steps to fully 3592 * initialise the chip!!!! 3593 * 3594 * The reset code above has already got us as far as step 3595 * 21, so we continue with ... 3596 * 3597 * Step 22: clear the MAC statistics block 3598 * (0x0300-0x0aff in NIC-local memory) 3599 */ 3600 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3601 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3602 NIC_MEM_STATISTICS_SIZE); 3603 3604 /* 3605 * Step 23: clear the status block (in host memory) 3606 */ 3607 DMA_ZERO(bgep->status_block); 3608 3609 /* 3610 * Step 24: set DMA read/write control register 3611 */ 3612 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3613 bgep->chipid.bge_dma_rwctrl); 3614 3615 /* 3616 * Step 25: Configure DMA endianness -- already done (16/17) 3617 * Step 26: Configure Host-Based Send Rings 3618 * Step 27: Indicate Host Stack Up 3619 */ 3620 bge_reg_set32(bgep, MODE_CONTROL_REG, 3621 MODE_HOST_SEND_BDS | 3622 MODE_HOST_STACK_UP); 3623 3624 /* 3625 * Step 28: Configure checksum options: 3626 * Solaris supports the hardware default checksum options. 3627 * 3628 * Workaround for Incorrect pseudo-header checksum calculation. 3629 */ 3630 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3631 bge_reg_set32(bgep, MODE_CONTROL_REG, 3632 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3633 3634 /* 3635 * Step 29: configure Timer Prescaler. The value is always the 3636 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3637 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3638 * for the whole chip! 3639 */ 3640 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3641 3642 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3643 drv_usecwait(40); 3644 /* put PHY into ready state */ 3645 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3646 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3647 drv_usecwait(40); 3648 } 3649 3650 /* 3651 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3652 * 3653 * If the mbuf_length is specified as 0, we just leave these at 3654 * their hardware defaults, rather than explicitly setting them. 3655 * As the Broadcom HRM,driver better not change the parameters 3656 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3657 */ 3658 if ((bgep->chipid.mbuf_length != 0) && 3659 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3660 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3661 bgep->chipid.mbuf_base); 3662 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3663 bgep->chipid.mbuf_length); 3664 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3665 DMAD_POOL_BASE_DEFAULT); 3666 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3667 DMAD_POOL_LENGTH_DEFAULT); 3668 } 3669 3670 /* 3671 * Step 32: configure MAC memory pool watermarks 3672 */ 3673 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3674 bgep->chipid.mbuf_lo_water_rdma); 3675 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3676 bgep->chipid.mbuf_lo_water_rmac); 3677 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3678 bgep->chipid.mbuf_hi_water); 3679 3680 /* 3681 * Step 33: configure DMA resource watermarks 3682 */ 3683 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3684 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3685 bge_dmad_lo_water); 3686 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3687 bge_dmad_hi_water); 3688 } 3689 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3690 3691 /* 3692 * Steps 34-36: enable buffer manager & internal h/w queues 3693 */ 3694 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3695 STATE_MACHINE_ATTN_ENABLE_BIT)) 3696 retval = DDI_FAILURE; 3697 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3698 retval = DDI_FAILURE; 3699 3700 /* 3701 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3702 */ 3703 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3704 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3705 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3706 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3707 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3708 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3709 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3710 } 3711 3712 /* 3713 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3714 */ 3715 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3716 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3717 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3718 bge_replenish_jumbo); 3719 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3720 bge_replenish_mini); 3721 } 3722 3723 /* 3724 * Steps 41-43: clear Send Ring Producer Indices and initialise 3725 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3726 */ 3727 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3728 maxring = BGE_SEND_RINGS_MAX; 3729 else 3730 maxring = BGE_SEND_RINGS_MAX_5705; 3731 for (ring = 0; ring < maxring; ++ring) { 3732 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3733 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3734 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3735 &bgep->send[ring].hw_rcb); 3736 } 3737 3738 /* 3739 * Steps 44-45: initialise Receive Return Rings 3740 * (0x0200-0x02ff in NIC-local memory) 3741 */ 3742 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3743 maxring = BGE_RECV_RINGS_MAX; 3744 else 3745 maxring = BGE_RECV_RINGS_MAX_5705; 3746 for (ring = 0; ring < maxring; ++ring) 3747 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3748 &bgep->recv[ring].hw_rcb); 3749 3750 /* 3751 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3752 */ 3753 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3754 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3755 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3756 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3757 } 3758 /* 3759 * Step 47: configure the MAC unicast address 3760 * Step 48: configure the random backoff seed 3761 * Step 96: set up multicast filters 3762 */ 3763 #ifdef BGE_IPMI_ASF 3764 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3765 #else 3766 if (bge_chip_sync(bgep) == DDI_FAILURE) 3767 #endif 3768 retval = DDI_FAILURE; 3769 3770 /* 3771 * Step 49: configure the MTU 3772 */ 3773 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3774 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3775 3776 /* 3777 * Step 50: configure the IPG et al 3778 */ 3779 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3780 3781 /* 3782 * Step 51: configure the default Rx Return Ring 3783 */ 3784 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3785 3786 /* 3787 * Steps 52-54: configure Receive List Placement, 3788 * and enable Receive List Placement Statistics 3789 */ 3790 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3791 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3792 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3793 case MHCR_CHIP_ASIC_REV_5700: 3794 case MHCR_CHIP_ASIC_REV_5701: 3795 case MHCR_CHIP_ASIC_REV_5703: 3796 case MHCR_CHIP_ASIC_REV_5704: 3797 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3798 break; 3799 case MHCR_CHIP_ASIC_REV_5705: 3800 break; 3801 default: 3802 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3803 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3804 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3805 break; 3806 } 3807 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3808 3809 if (bgep->chipid.rx_rings > 1) 3810 bge_init_recv_rule(bgep); 3811 3812 /* 3813 * Steps 55-56: enable Send Data Initiator Statistics 3814 */ 3815 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3816 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3817 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3818 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3819 } else { 3820 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3821 SEND_INIT_STATS_ENABLE); 3822 } 3823 /* 3824 * Steps 57-58: stop (?) the Host Coalescing Engine 3825 */ 3826 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3827 retval = DDI_FAILURE; 3828 3829 /* 3830 * Steps 59-62: initialise Host Coalescing parameters 3831 */ 3832 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3833 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3834 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3835 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3836 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3837 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3838 bge_tx_count_intr); 3839 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3840 bge_tx_ticks_intr); 3841 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3842 bge_rx_count_intr); 3843 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3844 bge_rx_ticks_intr); 3845 } 3846 3847 /* 3848 * Steps 63-64: initialise status block & statistics 3849 * host memory addresses 3850 * The statistic block does not exist in some chipsets 3851 * Step 65: initialise Statistics Coalescing Tick Counter 3852 */ 3853 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3854 bgep->status_block.cookie.dmac_laddress); 3855 3856 /* 3857 * Steps 66-67: initialise status block & statistics 3858 * NIC-local memory addresses 3859 */ 3860 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3861 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3862 bgep->statistics.cookie.dmac_laddress); 3863 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3864 STATISTICS_TICKS_DEFAULT); 3865 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3866 NIC_MEM_STATUS_BLOCK); 3867 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3868 NIC_MEM_STATISTICS); 3869 } 3870 3871 /* 3872 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3873 * Completion Engine, the Receive List Placement Engine, and the 3874 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3875 * and BCM5715. 3876 */ 3877 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3878 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3879 coalmode = COALESCE_64_BYTE_STATUS; 3880 else 3881 coalmode = 0; 3882 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3883 retval = DDI_FAILURE; 3884 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3885 STATE_MACHINE_ATTN_ENABLE_BIT)) 3886 retval = DDI_FAILURE; 3887 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3888 retval = DDI_FAILURE; 3889 3890 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3891 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3892 STATE_MACHINE_ATTN_ENABLE_BIT)) 3893 retval = DDI_FAILURE; 3894 3895 /* 3896 * Step 72: Enable MAC DMA engines 3897 * Step 73: Clear & enable MAC statistics 3898 */ 3899 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3900 ETHERNET_MODE_ENABLE_FHDE | 3901 ETHERNET_MODE_ENABLE_RDE | 3902 ETHERNET_MODE_ENABLE_TDE); 3903 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3904 ETHERNET_MODE_ENABLE_TX_STATS | 3905 ETHERNET_MODE_ENABLE_RX_STATS | 3906 ETHERNET_MODE_CLEAR_TX_STATS | 3907 ETHERNET_MODE_CLEAR_RX_STATS); 3908 3909 /* 3910 * Step 74: configure the MLCR (Miscellaneous Local Control 3911 * Register); not required, as we set up the MLCR in step 10 3912 * (part of the reset code) above. 3913 * 3914 * Step 75: clear Interrupt Mailbox 0 3915 */ 3916 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3917 3918 /* 3919 * Steps 76-87: Gentlemen, start your engines ... 3920 * 3921 * Enable the DMA Completion Engine, the Write DMA Engine, 3922 * the Read DMA Engine, Receive Data Completion Engine, 3923 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3924 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3925 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3926 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3927 * 3928 * Beware exhaust fumes? 3929 */ 3930 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3931 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3932 retval = DDI_FAILURE; 3933 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3934 ALL_DMA_ATTN_BITS; 3935 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3936 MHCR_CHIP_ASIC_REV_5755) || 3937 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3938 MHCR_CHIP_ASIC_REV_5906)) { 3939 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3940 } 3941 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3942 dma_wrprio)) 3943 retval = DDI_FAILURE; 3944 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3945 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3946 retval = DDI_FAILURE; 3947 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3948 STATE_MACHINE_ATTN_ENABLE_BIT)) 3949 retval = DDI_FAILURE; 3950 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3951 if (!bge_chip_enable_engine(bgep, 3952 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3953 retval = DDI_FAILURE; 3954 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3955 retval = DDI_FAILURE; 3956 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3957 STATE_MACHINE_ATTN_ENABLE_BIT)) 3958 retval = DDI_FAILURE; 3959 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3960 RCV_BD_DISABLED_RING_ATTN)) 3961 retval = DDI_FAILURE; 3962 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3963 RCV_DATA_BD_ILL_RING_ATTN)) 3964 retval = DDI_FAILURE; 3965 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3966 retval = DDI_FAILURE; 3967 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3968 STATE_MACHINE_ATTN_ENABLE_BIT)) 3969 retval = DDI_FAILURE; 3970 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3971 STATE_MACHINE_ATTN_ENABLE_BIT)) 3972 retval = DDI_FAILURE; 3973 3974 /* 3975 * Step 88: download firmware -- doesn't apply 3976 * Steps 89-90: enable Transmit & Receive MAC Engines 3977 */ 3978 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3979 retval = DDI_FAILURE; 3980 #ifdef BGE_IPMI_ASF 3981 if (!bgep->asf_enabled) { 3982 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3983 RECEIVE_MODE_KEEP_VLAN_TAG)) 3984 retval = DDI_FAILURE; 3985 } else { 3986 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3987 retval = DDI_FAILURE; 3988 } 3989 #else 3990 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3991 RECEIVE_MODE_KEEP_VLAN_TAG)) 3992 retval = DDI_FAILURE; 3993 #endif 3994 3995 /* 3996 * Step 91: disable auto-polling of PHY status 3997 */ 3998 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3999 4000 /* 4001 * Step 92: configure D0 power state (not required) 4002 * Step 93: initialise LED control register () 4003 */ 4004 ledctl = LED_CONTROL_DEFAULT; 4005 switch (bgep->chipid.device) { 4006 case DEVICE_ID_5700: 4007 case DEVICE_ID_5700x: 4008 case DEVICE_ID_5701: 4009 /* 4010 * Switch to 5700 (MAC) mode on these older chips 4011 */ 4012 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4013 ledctl |= LED_CONTROL_LED_MODE_5700; 4014 break; 4015 4016 default: 4017 break; 4018 } 4019 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4020 4021 /* 4022 * Step 94: activate link 4023 */ 4024 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4025 4026 /* 4027 * Step 95: set up physical layer (PHY/SerDes) 4028 * restart autoneg (if required) 4029 */ 4030 if (reset_phys) 4031 if (bge_phys_update(bgep) == DDI_FAILURE) 4032 retval = DDI_FAILURE; 4033 4034 /* 4035 * Extra step (DSG): hand over all the Receive Buffers to the chip 4036 */ 4037 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4038 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4039 bgep->buff[ring].rf_next); 4040 4041 /* 4042 * MSI bits:The least significant MSI 16-bit word. 4043 * ISR will be triggered different. 4044 */ 4045 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4046 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4047 4048 /* 4049 * Extra step (DSG): select which interrupts are enabled 4050 * 4051 * Program the Ethernet MAC engine to signal attention on 4052 * Link Change events, then enable interrupts on MAC, DMA, 4053 * and FLOW attention signals. 4054 */ 4055 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4056 ETHERNET_EVENT_LINK_INT | 4057 ETHERNET_STATUS_PCS_ERROR_INT); 4058 #ifdef BGE_IPMI_ASF 4059 if (bgep->asf_enabled) { 4060 bge_reg_set32(bgep, MODE_CONTROL_REG, 4061 MODE_INT_ON_FLOW_ATTN | 4062 MODE_INT_ON_DMA_ATTN | 4063 MODE_HOST_STACK_UP| 4064 MODE_INT_ON_MAC_ATTN); 4065 } else { 4066 #endif 4067 bge_reg_set32(bgep, MODE_CONTROL_REG, 4068 MODE_INT_ON_FLOW_ATTN | 4069 MODE_INT_ON_DMA_ATTN | 4070 MODE_INT_ON_MAC_ATTN); 4071 #ifdef BGE_IPMI_ASF 4072 } 4073 #endif 4074 4075 /* 4076 * Step 97: enable PCI interrupts!!! 4077 */ 4078 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4079 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4080 MHCR_MASK_PCI_INT_OUTPUT); 4081 4082 /* 4083 * All done! 4084 */ 4085 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4086 return (retval); 4087 } 4088 4089 4090 /* 4091 * ========== Hardware interrupt handler ========== 4092 */ 4093 4094 #undef BGE_DBG 4095 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4096 4097 /* 4098 * Sync the status block, then atomically clear the specified bits in 4099 * the <flags-and-tag> field of the status block. 4100 * the <flags> word of the status block, returning the value of the 4101 * <tag> and the <flags> before the bits were cleared. 4102 */ 4103 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4104 #pragma inline(bge_status_sync) 4105 4106 static int 4107 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4108 { 4109 bge_status_t *bsp; 4110 int retval; 4111 4112 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4113 (void *)bgep, bits)); 4114 4115 ASSERT(bgep->bge_guard == BGE_GUARD); 4116 4117 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4118 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4119 if (retval != DDI_FM_OK) 4120 return (retval); 4121 4122 bsp = DMA_VPTR(bgep->status_block); 4123 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4124 4125 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4126 (void *)bgep, bits, *flags)); 4127 4128 return (retval); 4129 } 4130 4131 void bge_wake_factotum(bge_t *bgep); 4132 #pragma inline(bge_wake_factotum) 4133 4134 void 4135 bge_wake_factotum(bge_t *bgep) 4136 { 4137 mutex_enter(bgep->softintrlock); 4138 if (bgep->factotum_flag == 0) { 4139 bgep->factotum_flag = 1; 4140 ddi_trigger_softintr(bgep->factotum_id); 4141 } 4142 mutex_exit(bgep->softintrlock); 4143 } 4144 4145 /* 4146 * bge_intr() -- handle chip interrupts 4147 */ 4148 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4149 #pragma no_inline(bge_intr) 4150 4151 uint_t 4152 bge_intr(caddr_t arg1, caddr_t arg2) 4153 { 4154 bge_t *bgep = (void *)arg1; /* private device info */ 4155 bge_status_t *bsp; 4156 uint64_t flags; 4157 uint32_t regval; 4158 uint_t result; 4159 int retval, loop_cnt = 0; 4160 4161 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4162 4163 /* 4164 * GLD v2 checks that s/w setup is complete before passing 4165 * interrupts to this routine, thus eliminating the old 4166 * (and well-known) race condition around ddi_add_intr() 4167 */ 4168 ASSERT(bgep->progress & PROGRESS_HWINT); 4169 4170 result = DDI_INTR_UNCLAIMED; 4171 mutex_enter(bgep->genlock); 4172 4173 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4174 /* 4175 * Check whether chip's says it's asserting #INTA; 4176 * if not, don't process or claim the interrupt. 4177 * 4178 * Note that the PCI signal is active low, so the 4179 * bit is *zero* when the interrupt is asserted. 4180 */ 4181 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4182 if (regval & MLCR_INTA_STATE) { 4183 if (bge_check_acc_handle(bgep, bgep->io_handle) 4184 != DDI_FM_OK) 4185 goto chip_stop; 4186 mutex_exit(bgep->genlock); 4187 return (result); 4188 } 4189 4190 /* 4191 * Block further PCI interrupts ... 4192 */ 4193 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4194 MHCR_MASK_PCI_INT_OUTPUT); 4195 4196 } else { 4197 /* 4198 * Check MSI status 4199 */ 4200 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4201 if (regval & MSI_ERROR_ATTENTION) { 4202 BGE_REPORT((bgep, "msi error attention," 4203 " status=0x%x", regval)); 4204 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4205 } 4206 } 4207 4208 result = DDI_INTR_CLAIMED; 4209 4210 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4211 4212 /* 4213 * Sync the status block and grab the flags-n-tag from it. 4214 * We count the number of interrupts where there doesn't 4215 * seem to have been a DMA update of the status block; if 4216 * it *has* been updated, the counter will be cleared in 4217 * the while() loop below ... 4218 */ 4219 bgep->missed_dmas += 1; 4220 bsp = DMA_VPTR(bgep->status_block); 4221 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4222 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4223 /* 4224 * bge_chip_stop() may have freed dma area etc 4225 * while we were in this interrupt handler - 4226 * better not call bge_status_sync() 4227 */ 4228 (void) bge_check_acc_handle(bgep, 4229 bgep->io_handle); 4230 mutex_exit(bgep->genlock); 4231 return (DDI_INTR_CLAIMED); 4232 } 4233 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4234 &flags); 4235 if (retval != DDI_FM_OK) { 4236 bgep->bge_dma_error = B_TRUE; 4237 goto chip_stop; 4238 } 4239 4240 if (!(flags & STATUS_FLAG_UPDATED)) 4241 break; 4242 4243 /* 4244 * Tell the chip that we're processing the interrupt 4245 */ 4246 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4247 INTERRUPT_MBOX_DISABLE(flags)); 4248 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4249 DDI_FM_OK) 4250 goto chip_stop; 4251 4252 /* 4253 * Drop the mutex while we: 4254 * Receive any newly-arrived packets 4255 * Recycle any newly-finished send buffers 4256 */ 4257 bgep->bge_intr_running = B_TRUE; 4258 mutex_exit(bgep->genlock); 4259 bge_receive(bgep, bsp); 4260 bge_recycle(bgep, bsp); 4261 mutex_enter(bgep->genlock); 4262 bgep->bge_intr_running = B_FALSE; 4263 4264 /* 4265 * Tell the chip we've finished processing, and 4266 * give it the tag that we got from the status 4267 * block earlier, so that it knows just how far 4268 * we've gone. If it's got more for us to do, 4269 * it will now update the status block and try 4270 * to assert an interrupt (but we've got the 4271 * #INTA blocked at present). If we see the 4272 * update, we'll loop around to do some more. 4273 * Eventually we'll get out of here ... 4274 */ 4275 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4276 INTERRUPT_MBOX_ENABLE(flags)); 4277 if (bgep->chipid.pci_type == BGE_PCI_E) 4278 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4279 bgep->missed_dmas = 0; 4280 } 4281 4282 /* 4283 * Check for exceptional conditions that we need to handle 4284 * 4285 * Link status changed 4286 * Status block not updated 4287 */ 4288 if (flags & STATUS_FLAG_LINK_CHANGED) 4289 bge_wake_factotum(bgep); 4290 4291 if (bgep->missed_dmas) { 4292 /* 4293 * Probably due to the internal status tag not 4294 * being reset. Force a status block update now; 4295 * this should ensure that we get an update and 4296 * a new interrupt. After that, we should be in 4297 * sync again ... 4298 */ 4299 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4300 "not updated?", flags)); 4301 bgep->missed_updates++; 4302 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4303 COALESCE_NOW); 4304 4305 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4306 /* 4307 * If this happens multiple times in a row, 4308 * it means DMA is just not working. Maybe 4309 * the chip's failed, or maybe there's a 4310 * problem on the PCI bus or in the host-PCI 4311 * bridge (Tomatillo). 4312 * 4313 * At all events, we want to stop further 4314 * interrupts and let the recovery code take 4315 * over to see whether anything can be done 4316 * about it ... 4317 */ 4318 bge_fm_ereport(bgep, 4319 DDI_FM_DEVICE_BADINT_LIMIT); 4320 goto chip_stop; 4321 } 4322 } 4323 4324 /* 4325 * Reenable assertion of #INTA, unless there's a DMA fault 4326 */ 4327 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4328 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4329 MHCR_MASK_PCI_INT_OUTPUT); 4330 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4331 DDI_FM_OK) 4332 goto chip_stop; 4333 } 4334 4335 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4336 goto chip_stop; 4337 4338 mutex_exit(bgep->genlock); 4339 return (result); 4340 4341 chip_stop: 4342 #ifdef BGE_IPMI_ASF 4343 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4344 /* 4345 * We must stop ASF heart beat before 4346 * bge_chip_stop(), otherwise some 4347 * computers (ex. IBM HS20 blade 4348 * server) may crash. 4349 */ 4350 bge_asf_update_status(bgep); 4351 bge_asf_stop_timer(bgep); 4352 bgep->asf_status = ASF_STAT_STOP; 4353 4354 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4355 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4356 } 4357 #endif 4358 bge_chip_stop(bgep, B_TRUE); 4359 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4360 mutex_exit(bgep->genlock); 4361 return (result); 4362 } 4363 4364 /* 4365 * ========== Factotum, implemented as a softint handler ========== 4366 */ 4367 4368 #undef BGE_DBG 4369 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4370 4371 static void bge_factotum_error_handler(bge_t *bgep); 4372 #pragma no_inline(bge_factotum_error_handler) 4373 4374 static void 4375 bge_factotum_error_handler(bge_t *bgep) 4376 { 4377 uint32_t flow; 4378 uint32_t rdma; 4379 uint32_t wdma; 4380 uint32_t tmac; 4381 uint32_t rmac; 4382 uint32_t rxrs; 4383 uint32_t txrs = 0; 4384 4385 ASSERT(mutex_owned(bgep->genlock)); 4386 4387 /* 4388 * Read all the registers that show the possible 4389 * reasons for the ERROR bit to be asserted 4390 */ 4391 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4392 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4393 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4394 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4395 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4396 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4397 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4398 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4399 4400 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4401 (void *)bgep, flow, rdma, wdma)); 4402 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4403 (void *)bgep, tmac, rmac, rxrs, txrs)); 4404 4405 /* 4406 * For now, just clear all the errors ... 4407 */ 4408 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4409 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4410 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4411 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4412 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4413 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4414 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4415 } 4416 4417 /* 4418 * Handler for hardware link state change. 4419 * 4420 * When this routine is called, the hardware link state has changed 4421 * and the new state is reflected in the param_* variables. Here 4422 * we must update the softstate and reprogram the MAC to match. 4423 */ 4424 static void bge_factotum_link_handler(bge_t *bgep); 4425 #pragma no_inline(bge_factotum_link_handler) 4426 4427 static void 4428 bge_factotum_link_handler(bge_t *bgep) 4429 { 4430 ASSERT(mutex_owned(bgep->genlock)); 4431 4432 /* 4433 * Update the s/w link_state 4434 */ 4435 if (bgep->param_link_up) 4436 bgep->link_state = LINK_STATE_UP; 4437 else 4438 bgep->link_state = LINK_STATE_DOWN; 4439 4440 /* 4441 * Reprogram the MAC modes to match 4442 */ 4443 bge_sync_mac_modes(bgep); 4444 } 4445 4446 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4447 #pragma no_inline(bge_factotum_link_check) 4448 4449 static boolean_t 4450 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4451 { 4452 boolean_t check; 4453 uint64_t flags; 4454 uint32_t tmac_status; 4455 4456 ASSERT(mutex_owned(bgep->genlock)); 4457 4458 /* 4459 * Get & clear the writable status bits in the Tx status register 4460 * (some bits are write-1-to-clear, others are just readonly). 4461 */ 4462 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4463 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4464 4465 /* 4466 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4467 */ 4468 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4469 STATUS_FLAG_LINK_CHANGED, &flags); 4470 if (*dma_state != DDI_FM_OK) 4471 return (B_FALSE); 4472 4473 /* 4474 * Clear any errors flagged in the status block ... 4475 */ 4476 if (flags & STATUS_FLAG_ERROR) 4477 bge_factotum_error_handler(bgep); 4478 4479 /* 4480 * We need to check the link status if: 4481 * the status block says there's been a link change 4482 * or there's any discrepancy between the various 4483 * flags indicating the link state (link_state, 4484 * param_link_up, and the LINK STATE bit in the 4485 * Transmit MAC status register). 4486 */ 4487 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4488 switch (bgep->link_state) { 4489 case LINK_STATE_UP: 4490 check |= (bgep->param_link_up == B_FALSE); 4491 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4492 break; 4493 4494 case LINK_STATE_DOWN: 4495 check |= (bgep->param_link_up != B_FALSE); 4496 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4497 break; 4498 4499 default: 4500 check = B_TRUE; 4501 break; 4502 } 4503 4504 /* 4505 * If <check> is false, we're sure the link hasn't changed. 4506 * If true, however, it's not yet definitive; we have to call 4507 * bge_phys_check() to determine whether the link has settled 4508 * into a new state yet ... and if it has, then call the link 4509 * state change handler.But when the chip is 5700 in Dell 6650 4510 * ,even if check is false, the link may have changed.So we 4511 * have to call bge_phys_check() to determine the link state. 4512 */ 4513 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4514 check = bge_phys_check(bgep); 4515 if (check) 4516 bge_factotum_link_handler(bgep); 4517 } 4518 4519 return (check); 4520 } 4521 4522 /* 4523 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4524 */ 4525 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4526 #pragma no_inline(bge_factotum_stall_check) 4527 4528 static boolean_t 4529 bge_factotum_stall_check(bge_t *bgep) 4530 { 4531 uint32_t dogval; 4532 4533 ASSERT(mutex_owned(bgep->genlock)); 4534 4535 /* 4536 * Specific check for Tx stall ... 4537 * 4538 * The 'watchdog' counter is incremented whenever a packet 4539 * is queued, reset to 1 when some (but not all) buffers 4540 * are reclaimed, reset to 0 (disabled) when all buffers 4541 * are reclaimed, and shifted left here. If it exceeds the 4542 * threshold value, the chip is assumed to have stalled and 4543 * is put into the ERROR state. The factotum will then reset 4544 * it on the next pass. 4545 * 4546 * All of which should ensure that we don't get into a state 4547 * where packets are left pending indefinitely! 4548 */ 4549 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4550 if (dogval < bge_watchdog_count) 4551 return (B_FALSE); 4552 4553 #if !defined(BGE_NETCONSOLE) 4554 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4555 #endif 4556 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4557 return (B_TRUE); 4558 } 4559 4560 /* 4561 * The factotum is woken up when there's something to do that we'd rather 4562 * not do from inside a hardware interrupt handler or high-level cyclic. 4563 * Its two main tasks are: 4564 * reset & restart the chip after an error 4565 * check the link status whenever necessary 4566 */ 4567 uint_t bge_chip_factotum(caddr_t arg); 4568 #pragma no_inline(bge_chip_factotum) 4569 4570 uint_t 4571 bge_chip_factotum(caddr_t arg) 4572 { 4573 bge_t *bgep; 4574 uint_t result; 4575 boolean_t error; 4576 boolean_t linkchg; 4577 int dma_state; 4578 4579 bgep = (void *)arg; 4580 4581 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4582 4583 mutex_enter(bgep->softintrlock); 4584 if (bgep->factotum_flag == 0) { 4585 mutex_exit(bgep->softintrlock); 4586 return (DDI_INTR_UNCLAIMED); 4587 } 4588 bgep->factotum_flag = 0; 4589 mutex_exit(bgep->softintrlock); 4590 4591 result = DDI_INTR_CLAIMED; 4592 error = B_FALSE; 4593 linkchg = B_FALSE; 4594 4595 mutex_enter(bgep->genlock); 4596 switch (bgep->bge_chip_state) { 4597 default: 4598 break; 4599 4600 case BGE_CHIP_RUNNING: 4601 linkchg = bge_factotum_link_check(bgep, &dma_state); 4602 error = bge_factotum_stall_check(bgep); 4603 if (dma_state != DDI_FM_OK) { 4604 bgep->bge_dma_error = B_TRUE; 4605 error = B_TRUE; 4606 } 4607 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4608 error = B_TRUE; 4609 if (error) 4610 bgep->bge_chip_state = BGE_CHIP_ERROR; 4611 break; 4612 4613 case BGE_CHIP_ERROR: 4614 error = B_TRUE; 4615 break; 4616 4617 case BGE_CHIP_FAULT: 4618 /* 4619 * Fault detected, time to reset ... 4620 */ 4621 if (bge_autorecover) { 4622 if (!(bgep->progress & PROGRESS_BUFS)) { 4623 /* 4624 * if we can't allocate the ring buffers, 4625 * try later 4626 */ 4627 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4628 mutex_exit(bgep->genlock); 4629 return (result); 4630 } 4631 bgep->progress |= PROGRESS_BUFS; 4632 } 4633 if (!(bgep->progress & PROGRESS_INTR)) { 4634 bge_init_rings(bgep); 4635 bge_intr_enable(bgep); 4636 bgep->progress |= PROGRESS_INTR; 4637 } 4638 if (!(bgep->progress & PROGRESS_KSTATS)) { 4639 bge_init_kstats(bgep, 4640 ddi_get_instance(bgep->devinfo)); 4641 bgep->progress |= PROGRESS_KSTATS; 4642 } 4643 4644 BGE_REPORT((bgep, "automatic recovery activated")); 4645 4646 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4647 bgep->bge_chip_state = BGE_CHIP_ERROR; 4648 error = B_TRUE; 4649 } 4650 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4651 DDI_FM_OK) { 4652 bgep->bge_chip_state = BGE_CHIP_ERROR; 4653 error = B_TRUE; 4654 } 4655 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4656 DDI_FM_OK) { 4657 bgep->bge_chip_state = BGE_CHIP_ERROR; 4658 error = B_TRUE; 4659 } 4660 if (error == B_FALSE) { 4661 #ifdef BGE_IPMI_ASF 4662 if (bgep->asf_enabled && 4663 bgep->asf_status != ASF_STAT_RUN) { 4664 bgep->asf_timeout_id = timeout( 4665 bge_asf_heartbeat, (void *)bgep, 4666 drv_usectohz( 4667 BGE_ASF_HEARTBEAT_INTERVAL)); 4668 bgep->asf_status = ASF_STAT_RUN; 4669 } 4670 #endif 4671 if (!bgep->manual_reset) { 4672 ddi_fm_service_impact(bgep->devinfo, 4673 DDI_SERVICE_RESTORED); 4674 } 4675 } 4676 } 4677 break; 4678 } 4679 4680 4681 /* 4682 * If an error is detected, stop the chip now, marking it as 4683 * faulty, so that it will be reset next time through ... 4684 * 4685 * Note that if intr_running is set, then bge_intr() has dropped 4686 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4687 * this point so have to wait until the next time the factotum runs. 4688 */ 4689 if (error && !bgep->bge_intr_running) { 4690 #ifdef BGE_IPMI_ASF 4691 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4692 /* 4693 * We must stop ASF heart beat before bge_chip_stop(), 4694 * otherwise some computers (ex. IBM HS20 blade server) 4695 * may crash. 4696 */ 4697 bge_asf_update_status(bgep); 4698 bge_asf_stop_timer(bgep); 4699 bgep->asf_status = ASF_STAT_STOP; 4700 4701 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4702 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4703 } 4704 #endif 4705 bge_chip_stop(bgep, B_TRUE); 4706 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4707 } 4708 mutex_exit(bgep->genlock); 4709 4710 /* 4711 * If the link state changed, tell the world about it. 4712 * Note: can't do this while still holding the mutex. 4713 */ 4714 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4715 bgep->link_state != LINK_STATE_UNKNOWN) 4716 linkchg = B_TRUE; 4717 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4718 bgep->link_state == LINK_STATE_DOWN) 4719 linkchg = B_FALSE; 4720 4721 if (linkchg) { 4722 mac_link_update(bgep->mh, bgep->link_state); 4723 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4724 } 4725 if (bgep->manual_reset) { 4726 bgep->manual_reset = B_FALSE; 4727 } 4728 4729 return (result); 4730 } 4731 4732 /* 4733 * High-level cyclic handler 4734 * 4735 * This routine schedules a (low-level) softint callback to the 4736 * factotum, and prods the chip to update the status block (which 4737 * will cause a hardware interrupt when complete). 4738 */ 4739 void bge_chip_cyclic(void *arg); 4740 #pragma no_inline(bge_chip_cyclic) 4741 4742 void 4743 bge_chip_cyclic(void *arg) 4744 { 4745 bge_t *bgep; 4746 4747 bgep = arg; 4748 4749 switch (bgep->bge_chip_state) { 4750 default: 4751 return; 4752 4753 case BGE_CHIP_RUNNING: 4754 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4755 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4756 ddi_fm_service_impact(bgep->devinfo, 4757 DDI_SERVICE_UNAFFECTED); 4758 4759 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4760 bgep->link_update_timer++; 4761 4762 break; 4763 4764 case BGE_CHIP_FAULT: 4765 case BGE_CHIP_ERROR: 4766 break; 4767 } 4768 4769 bge_wake_factotum(bgep); 4770 } 4771 4772 4773 /* 4774 * ========== Ioctl subfunctions ========== 4775 */ 4776 4777 #undef BGE_DBG 4778 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4779 4780 #if BGE_DEBUGGING || BGE_DO_PPIO 4781 4782 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4783 #pragma no_inline(bge_chip_peek_cfg) 4784 4785 static void 4786 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4787 { 4788 uint64_t regval; 4789 uint64_t regno; 4790 4791 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4792 (void *)bgep, (void *)ppd)); 4793 4794 regno = ppd->pp_acc_offset; 4795 4796 switch (ppd->pp_acc_size) { 4797 case 1: 4798 regval = pci_config_get8(bgep->cfg_handle, regno); 4799 break; 4800 4801 case 2: 4802 regval = pci_config_get16(bgep->cfg_handle, regno); 4803 break; 4804 4805 case 4: 4806 regval = pci_config_get32(bgep->cfg_handle, regno); 4807 break; 4808 4809 case 8: 4810 regval = pci_config_get64(bgep->cfg_handle, regno); 4811 break; 4812 } 4813 4814 ppd->pp_acc_data = regval; 4815 } 4816 4817 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4818 #pragma no_inline(bge_chip_poke_cfg) 4819 4820 static void 4821 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4822 { 4823 uint64_t regval; 4824 uint64_t regno; 4825 4826 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4827 (void *)bgep, (void *)ppd)); 4828 4829 regno = ppd->pp_acc_offset; 4830 regval = ppd->pp_acc_data; 4831 4832 switch (ppd->pp_acc_size) { 4833 case 1: 4834 pci_config_put8(bgep->cfg_handle, regno, regval); 4835 break; 4836 4837 case 2: 4838 pci_config_put16(bgep->cfg_handle, regno, regval); 4839 break; 4840 4841 case 4: 4842 pci_config_put32(bgep->cfg_handle, regno, regval); 4843 break; 4844 4845 case 8: 4846 pci_config_put64(bgep->cfg_handle, regno, regval); 4847 break; 4848 } 4849 } 4850 4851 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4852 #pragma no_inline(bge_chip_peek_reg) 4853 4854 static void 4855 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4856 { 4857 uint64_t regval; 4858 void *regaddr; 4859 4860 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4861 (void *)bgep, (void *)ppd)); 4862 4863 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4864 4865 switch (ppd->pp_acc_size) { 4866 case 1: 4867 regval = ddi_get8(bgep->io_handle, regaddr); 4868 break; 4869 4870 case 2: 4871 regval = ddi_get16(bgep->io_handle, regaddr); 4872 break; 4873 4874 case 4: 4875 regval = ddi_get32(bgep->io_handle, regaddr); 4876 break; 4877 4878 case 8: 4879 regval = ddi_get64(bgep->io_handle, regaddr); 4880 break; 4881 } 4882 4883 ppd->pp_acc_data = regval; 4884 } 4885 4886 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4887 #pragma no_inline(bge_chip_peek_reg) 4888 4889 static void 4890 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4891 { 4892 uint64_t regval; 4893 void *regaddr; 4894 4895 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4896 (void *)bgep, (void *)ppd)); 4897 4898 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4899 regval = ppd->pp_acc_data; 4900 4901 switch (ppd->pp_acc_size) { 4902 case 1: 4903 ddi_put8(bgep->io_handle, regaddr, regval); 4904 break; 4905 4906 case 2: 4907 ddi_put16(bgep->io_handle, regaddr, regval); 4908 break; 4909 4910 case 4: 4911 ddi_put32(bgep->io_handle, regaddr, regval); 4912 break; 4913 4914 case 8: 4915 ddi_put64(bgep->io_handle, regaddr, regval); 4916 break; 4917 } 4918 BGE_PCICHK(bgep); 4919 } 4920 4921 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4922 #pragma no_inline(bge_chip_peek_nic) 4923 4924 static void 4925 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4926 { 4927 uint64_t regoff; 4928 uint64_t regval; 4929 void *regaddr; 4930 4931 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4932 (void *)bgep, (void *)ppd)); 4933 4934 regoff = ppd->pp_acc_offset; 4935 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4936 regoff &= MWBAR_GRANULE_MASK; 4937 regoff += NIC_MEM_WINDOW_OFFSET; 4938 regaddr = PIO_ADDR(bgep, regoff); 4939 4940 switch (ppd->pp_acc_size) { 4941 case 1: 4942 regval = ddi_get8(bgep->io_handle, regaddr); 4943 break; 4944 4945 case 2: 4946 regval = ddi_get16(bgep->io_handle, regaddr); 4947 break; 4948 4949 case 4: 4950 regval = ddi_get32(bgep->io_handle, regaddr); 4951 break; 4952 4953 case 8: 4954 regval = ddi_get64(bgep->io_handle, regaddr); 4955 break; 4956 } 4957 4958 ppd->pp_acc_data = regval; 4959 } 4960 4961 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4962 #pragma no_inline(bge_chip_poke_nic) 4963 4964 static void 4965 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4966 { 4967 uint64_t regoff; 4968 uint64_t regval; 4969 void *regaddr; 4970 4971 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4972 (void *)bgep, (void *)ppd)); 4973 4974 regoff = ppd->pp_acc_offset; 4975 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4976 regoff &= MWBAR_GRANULE_MASK; 4977 regoff += NIC_MEM_WINDOW_OFFSET; 4978 regaddr = PIO_ADDR(bgep, regoff); 4979 regval = ppd->pp_acc_data; 4980 4981 switch (ppd->pp_acc_size) { 4982 case 1: 4983 ddi_put8(bgep->io_handle, regaddr, regval); 4984 break; 4985 4986 case 2: 4987 ddi_put16(bgep->io_handle, regaddr, regval); 4988 break; 4989 4990 case 4: 4991 ddi_put32(bgep->io_handle, regaddr, regval); 4992 break; 4993 4994 case 8: 4995 ddi_put64(bgep->io_handle, regaddr, regval); 4996 break; 4997 } 4998 BGE_PCICHK(bgep); 4999 } 5000 5001 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5002 #pragma no_inline(bge_chip_peek_mii) 5003 5004 static void 5005 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5006 { 5007 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5008 (void *)bgep, (void *)ppd)); 5009 5010 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5011 } 5012 5013 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5014 #pragma no_inline(bge_chip_poke_mii) 5015 5016 static void 5017 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5018 { 5019 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5020 (void *)bgep, (void *)ppd)); 5021 5022 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5023 } 5024 5025 #if BGE_SEE_IO32 5026 5027 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5028 #pragma no_inline(bge_chip_peek_seeprom) 5029 5030 static void 5031 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5032 { 5033 uint32_t data; 5034 int err; 5035 5036 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5037 (void *)bgep, (void *)ppd)); 5038 5039 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5040 ppd->pp_acc_data = err ? ~0ull : data; 5041 } 5042 5043 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5044 #pragma no_inline(bge_chip_poke_seeprom) 5045 5046 static void 5047 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5048 { 5049 uint32_t data; 5050 5051 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5052 (void *)bgep, (void *)ppd)); 5053 5054 data = ppd->pp_acc_data; 5055 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5056 } 5057 #endif /* BGE_SEE_IO32 */ 5058 5059 #if BGE_FLASH_IO32 5060 5061 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5062 #pragma no_inline(bge_chip_peek_flash) 5063 5064 static void 5065 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5066 { 5067 uint32_t data; 5068 int err; 5069 5070 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5071 (void *)bgep, (void *)ppd)); 5072 5073 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5074 ppd->pp_acc_data = err ? ~0ull : data; 5075 } 5076 5077 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5078 #pragma no_inline(bge_chip_poke_flash) 5079 5080 static void 5081 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5082 { 5083 uint32_t data; 5084 5085 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5086 (void *)bgep, (void *)ppd)); 5087 5088 data = ppd->pp_acc_data; 5089 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5090 ppd->pp_acc_offset, &data); 5091 } 5092 #endif /* BGE_FLASH_IO32 */ 5093 5094 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5095 #pragma no_inline(bge_chip_peek_mem) 5096 5097 static void 5098 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5099 { 5100 uint64_t regval; 5101 void *vaddr; 5102 5103 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5104 (void *)bgep, (void *)ppd)); 5105 5106 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5107 5108 switch (ppd->pp_acc_size) { 5109 case 1: 5110 regval = *(uint8_t *)vaddr; 5111 break; 5112 5113 case 2: 5114 regval = *(uint16_t *)vaddr; 5115 break; 5116 5117 case 4: 5118 regval = *(uint32_t *)vaddr; 5119 break; 5120 5121 case 8: 5122 regval = *(uint64_t *)vaddr; 5123 break; 5124 } 5125 5126 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5127 (void *)bgep, (void *)ppd, regval, vaddr)); 5128 5129 ppd->pp_acc_data = regval; 5130 } 5131 5132 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5133 #pragma no_inline(bge_chip_poke_mem) 5134 5135 static void 5136 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5137 { 5138 uint64_t regval; 5139 void *vaddr; 5140 5141 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5142 (void *)bgep, (void *)ppd)); 5143 5144 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5145 regval = ppd->pp_acc_data; 5146 5147 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5148 (void *)bgep, (void *)ppd, regval, vaddr)); 5149 5150 switch (ppd->pp_acc_size) { 5151 case 1: 5152 *(uint8_t *)vaddr = (uint8_t)regval; 5153 break; 5154 5155 case 2: 5156 *(uint16_t *)vaddr = (uint16_t)regval; 5157 break; 5158 5159 case 4: 5160 *(uint32_t *)vaddr = (uint32_t)regval; 5161 break; 5162 5163 case 8: 5164 *(uint64_t *)vaddr = (uint64_t)regval; 5165 break; 5166 } 5167 } 5168 5169 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5170 struct iocblk *iocp); 5171 #pragma no_inline(bge_pp_ioctl) 5172 5173 static enum ioc_reply 5174 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5175 { 5176 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5177 bge_peekpoke_t *ppd; 5178 dma_area_t *areap; 5179 uint64_t sizemask; 5180 uint64_t mem_va; 5181 uint64_t maxoff; 5182 boolean_t peek; 5183 5184 switch (cmd) { 5185 default: 5186 /* NOTREACHED */ 5187 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5188 return (IOC_INVAL); 5189 5190 case BGE_PEEK: 5191 peek = B_TRUE; 5192 break; 5193 5194 case BGE_POKE: 5195 peek = B_FALSE; 5196 break; 5197 } 5198 5199 /* 5200 * Validate format of ioctl 5201 */ 5202 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5203 return (IOC_INVAL); 5204 if (mp->b_cont == NULL) 5205 return (IOC_INVAL); 5206 ppd = (void *)mp->b_cont->b_rptr; 5207 5208 /* 5209 * Validate request parameters 5210 */ 5211 switch (ppd->pp_acc_space) { 5212 default: 5213 return (IOC_INVAL); 5214 5215 case BGE_PP_SPACE_CFG: 5216 /* 5217 * Config space 5218 */ 5219 sizemask = 8|4|2|1; 5220 mem_va = 0; 5221 maxoff = PCI_CONF_HDR_SIZE; 5222 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5223 break; 5224 5225 case BGE_PP_SPACE_REG: 5226 /* 5227 * Memory-mapped I/O space 5228 */ 5229 sizemask = 8|4|2|1; 5230 mem_va = 0; 5231 maxoff = RIAAR_REGISTER_MAX; 5232 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5233 break; 5234 5235 case BGE_PP_SPACE_NIC: 5236 /* 5237 * NIC on-chip memory 5238 */ 5239 sizemask = 8|4|2|1; 5240 mem_va = 0; 5241 maxoff = MWBAR_ONCHIP_MAX; 5242 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5243 break; 5244 5245 case BGE_PP_SPACE_MII: 5246 /* 5247 * PHY's MII registers 5248 * NB: all PHY registers are two bytes, but the 5249 * addresses increment in ones (word addressing). 5250 * So we scale the address here, then undo the 5251 * transformation inside the peek/poke functions. 5252 */ 5253 ppd->pp_acc_offset *= 2; 5254 sizemask = 2; 5255 mem_va = 0; 5256 maxoff = (MII_MAXREG+1)*2; 5257 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5258 break; 5259 5260 #if BGE_SEE_IO32 5261 case BGE_PP_SPACE_SEEPROM: 5262 /* 5263 * Attached SEEPROM(s), if any. 5264 * NB: we use the high-order bits of the 'address' as 5265 * a device select to accommodate multiple SEEPROMS, 5266 * If each one is the maximum size (64kbytes), this 5267 * makes them appear contiguous. Otherwise, there may 5268 * be holes in the mapping. ENxS doesn't have any 5269 * SEEPROMs anyway ... 5270 */ 5271 sizemask = 4; 5272 mem_va = 0; 5273 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5274 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5275 break; 5276 #endif /* BGE_SEE_IO32 */ 5277 5278 #if BGE_FLASH_IO32 5279 case BGE_PP_SPACE_FLASH: 5280 /* 5281 * Attached Flash device (if any); a maximum of one device 5282 * is currently supported. But it can be up to 1MB (unlike 5283 * the 64k limit on SEEPROMs) so why would you need more ;-) 5284 */ 5285 sizemask = 4; 5286 mem_va = 0; 5287 maxoff = NVM_FLASH_ADDR_MASK; 5288 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5289 break; 5290 #endif /* BGE_FLASH_IO32 */ 5291 5292 case BGE_PP_SPACE_BGE: 5293 /* 5294 * BGE data structure! 5295 */ 5296 sizemask = 8|4|2|1; 5297 mem_va = (uintptr_t)bgep; 5298 maxoff = sizeof (*bgep); 5299 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5300 break; 5301 5302 case BGE_PP_SPACE_STATUS: 5303 case BGE_PP_SPACE_STATISTICS: 5304 case BGE_PP_SPACE_TXDESC: 5305 case BGE_PP_SPACE_TXBUFF: 5306 case BGE_PP_SPACE_RXDESC: 5307 case BGE_PP_SPACE_RXBUFF: 5308 /* 5309 * Various DMA_AREAs 5310 */ 5311 switch (ppd->pp_acc_space) { 5312 case BGE_PP_SPACE_TXDESC: 5313 areap = &bgep->tx_desc; 5314 break; 5315 case BGE_PP_SPACE_TXBUFF: 5316 areap = &bgep->tx_buff[0]; 5317 break; 5318 case BGE_PP_SPACE_RXDESC: 5319 areap = &bgep->rx_desc[0]; 5320 break; 5321 case BGE_PP_SPACE_RXBUFF: 5322 areap = &bgep->rx_buff[0]; 5323 break; 5324 case BGE_PP_SPACE_STATUS: 5325 areap = &bgep->status_block; 5326 break; 5327 case BGE_PP_SPACE_STATISTICS: 5328 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5329 areap = &bgep->statistics; 5330 break; 5331 } 5332 5333 sizemask = 8|4|2|1; 5334 mem_va = (uintptr_t)areap->mem_va; 5335 maxoff = areap->alength; 5336 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5337 break; 5338 } 5339 5340 switch (ppd->pp_acc_size) { 5341 default: 5342 return (IOC_INVAL); 5343 5344 case 8: 5345 case 4: 5346 case 2: 5347 case 1: 5348 if ((ppd->pp_acc_size & sizemask) == 0) 5349 return (IOC_INVAL); 5350 break; 5351 } 5352 5353 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5354 return (IOC_INVAL); 5355 5356 if (ppd->pp_acc_offset >= maxoff) 5357 return (IOC_INVAL); 5358 5359 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5360 return (IOC_INVAL); 5361 5362 /* 5363 * All OK - go do it! 5364 */ 5365 ppd->pp_acc_offset += mem_va; 5366 (*ppfn)(bgep, ppd); 5367 return (peek ? IOC_REPLY : IOC_ACK); 5368 } 5369 5370 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5371 struct iocblk *iocp); 5372 #pragma no_inline(bge_diag_ioctl) 5373 5374 static enum ioc_reply 5375 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5376 { 5377 ASSERT(mutex_owned(bgep->genlock)); 5378 5379 switch (cmd) { 5380 default: 5381 /* NOTREACHED */ 5382 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5383 return (IOC_INVAL); 5384 5385 case BGE_DIAG: 5386 /* 5387 * Currently a no-op 5388 */ 5389 return (IOC_ACK); 5390 5391 case BGE_PEEK: 5392 case BGE_POKE: 5393 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5394 5395 case BGE_PHY_RESET: 5396 return (IOC_RESTART_ACK); 5397 5398 case BGE_SOFT_RESET: 5399 case BGE_HARD_RESET: 5400 /* 5401 * Reset and reinitialise the 570x hardware 5402 */ 5403 bgep->bge_chip_state = BGE_CHIP_FAULT; 5404 ddi_trigger_softintr(bgep->factotum_id); 5405 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5406 return (IOC_ACK); 5407 } 5408 5409 /* NOTREACHED */ 5410 } 5411 5412 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5413 5414 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5415 struct iocblk *iocp); 5416 #pragma no_inline(bge_mii_ioctl) 5417 5418 static enum ioc_reply 5419 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5420 { 5421 struct bge_mii_rw *miirwp; 5422 5423 /* 5424 * Validate format of ioctl 5425 */ 5426 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5427 return (IOC_INVAL); 5428 if (mp->b_cont == NULL) 5429 return (IOC_INVAL); 5430 miirwp = (void *)mp->b_cont->b_rptr; 5431 5432 /* 5433 * Validate request parameters ... 5434 */ 5435 if (miirwp->mii_reg > MII_MAXREG) 5436 return (IOC_INVAL); 5437 5438 switch (cmd) { 5439 default: 5440 /* NOTREACHED */ 5441 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5442 return (IOC_INVAL); 5443 5444 case BGE_MII_READ: 5445 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5446 return (IOC_REPLY); 5447 5448 case BGE_MII_WRITE: 5449 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5450 return (IOC_ACK); 5451 } 5452 5453 /* NOTREACHED */ 5454 } 5455 5456 #if BGE_SEE_IO32 5457 5458 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5459 struct iocblk *iocp); 5460 #pragma no_inline(bge_see_ioctl) 5461 5462 static enum ioc_reply 5463 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5464 { 5465 struct bge_see_rw *seerwp; 5466 5467 /* 5468 * Validate format of ioctl 5469 */ 5470 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5471 return (IOC_INVAL); 5472 if (mp->b_cont == NULL) 5473 return (IOC_INVAL); 5474 seerwp = (void *)mp->b_cont->b_rptr; 5475 5476 /* 5477 * Validate request parameters ... 5478 */ 5479 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5480 return (IOC_INVAL); 5481 5482 switch (cmd) { 5483 default: 5484 /* NOTREACHED */ 5485 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5486 return (IOC_INVAL); 5487 5488 case BGE_SEE_READ: 5489 case BGE_SEE_WRITE: 5490 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5491 seerwp->see_addr, &seerwp->see_data); 5492 return (IOC_REPLY); 5493 } 5494 5495 /* NOTREACHED */ 5496 } 5497 5498 #endif /* BGE_SEE_IO32 */ 5499 5500 #if BGE_FLASH_IO32 5501 5502 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5503 struct iocblk *iocp); 5504 #pragma no_inline(bge_flash_ioctl) 5505 5506 static enum ioc_reply 5507 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5508 { 5509 struct bge_flash_rw *flashrwp; 5510 5511 /* 5512 * Validate format of ioctl 5513 */ 5514 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5515 return (IOC_INVAL); 5516 if (mp->b_cont == NULL) 5517 return (IOC_INVAL); 5518 flashrwp = (void *)mp->b_cont->b_rptr; 5519 5520 /* 5521 * Validate request parameters ... 5522 */ 5523 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5524 return (IOC_INVAL); 5525 5526 switch (cmd) { 5527 default: 5528 /* NOTREACHED */ 5529 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5530 return (IOC_INVAL); 5531 5532 case BGE_FLASH_READ: 5533 case BGE_FLASH_WRITE: 5534 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5535 flashrwp->flash_addr, &flashrwp->flash_data); 5536 return (IOC_REPLY); 5537 } 5538 5539 /* NOTREACHED */ 5540 } 5541 5542 #endif /* BGE_FLASH_IO32 */ 5543 5544 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5545 struct iocblk *iocp); 5546 #pragma no_inline(bge_chip_ioctl) 5547 5548 enum ioc_reply 5549 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5550 { 5551 int cmd; 5552 5553 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5554 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5555 5556 ASSERT(mutex_owned(bgep->genlock)); 5557 5558 cmd = iocp->ioc_cmd; 5559 switch (cmd) { 5560 default: 5561 /* NOTREACHED */ 5562 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5563 return (IOC_INVAL); 5564 5565 case BGE_DIAG: 5566 case BGE_PEEK: 5567 case BGE_POKE: 5568 case BGE_PHY_RESET: 5569 case BGE_SOFT_RESET: 5570 case BGE_HARD_RESET: 5571 #if BGE_DEBUGGING || BGE_DO_PPIO 5572 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5573 #else 5574 return (IOC_INVAL); 5575 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5576 5577 case BGE_MII_READ: 5578 case BGE_MII_WRITE: 5579 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5580 5581 #if BGE_SEE_IO32 5582 case BGE_SEE_READ: 5583 case BGE_SEE_WRITE: 5584 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5585 #endif /* BGE_SEE_IO32 */ 5586 5587 #if BGE_FLASH_IO32 5588 case BGE_FLASH_READ: 5589 case BGE_FLASH_WRITE: 5590 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5591 #endif /* BGE_FLASH_IO32 */ 5592 } 5593 5594 /* NOTREACHED */ 5595 } 5596 5597 /* ARGSUSED */ 5598 void 5599 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5600 { 5601 recv_ring_t *rrp = arg; 5602 bge_t *bgep = rrp->bgep; 5603 5604 mutex_enter(bgep->genlock); 5605 rrp->poll_flag = flag; 5606 #ifdef NOT_YET 5607 /* 5608 * XXX-Sunay: Since most broadcom cards support only one 5609 * interrupt but multiple rx rings, we can't disable the 5610 * physical interrupt. This need to be done via capability 5611 * negotiation depending on the NIC. 5612 */ 5613 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5614 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5615 #endif 5616 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5617 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5618 mutex_exit(bgep->genlock); 5619 } 5620 5621 #ifdef BGE_IPMI_ASF 5622 5623 uint32_t 5624 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5625 { 5626 uint32_t data; 5627 5628 #ifndef __sparc 5629 if (!bgep->asf_wordswapped) { 5630 /* a workaround word swap error */ 5631 if (addr & 4) 5632 addr = addr - 4; 5633 else 5634 addr = addr + 4; 5635 } 5636 #endif 5637 5638 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5639 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5640 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5641 5642 data = LE_32(data); 5643 return (data); 5644 } 5645 5646 void 5647 bge_asf_update_status(bge_t *bgep) 5648 { 5649 uint32_t event; 5650 5651 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5652 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5653 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5654 5655 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5656 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5657 } 5658 5659 5660 /* 5661 * The driver is supposed to notify ASF that the OS is still running 5662 * every three seconds, otherwise the management server may attempt 5663 * to reboot the machine. If it hasn't actually failed, this is 5664 * not a desirable result. However, this isn't running as a real-time 5665 * thread, and even if it were, it might not be able to generate the 5666 * heartbeat in a timely manner due to system load. As it isn't a 5667 * significant strain on the machine, we will set the interval to half 5668 * of the required value. 5669 */ 5670 void 5671 bge_asf_heartbeat(void *arg) 5672 { 5673 bge_t *bgep = (bge_t *)arg; 5674 5675 mutex_enter(bgep->genlock); 5676 bge_asf_update_status((bge_t *)bgep); 5677 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5678 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5679 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5680 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5681 mutex_exit(bgep->genlock); 5682 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5683 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5684 } 5685 5686 5687 void 5688 bge_asf_stop_timer(bge_t *bgep) 5689 { 5690 timeout_id_t tmp_id = 0; 5691 5692 while ((bgep->asf_timeout_id != 0) && 5693 (tmp_id != bgep->asf_timeout_id)) { 5694 tmp_id = bgep->asf_timeout_id; 5695 (void) untimeout(tmp_id); 5696 } 5697 bgep->asf_timeout_id = 0; 5698 } 5699 5700 5701 5702 /* 5703 * This function should be placed at the earliest position of bge_attach(). 5704 */ 5705 void 5706 bge_asf_get_config(bge_t *bgep) 5707 { 5708 uint32_t nicsig; 5709 uint32_t niccfg; 5710 5711 bgep->asf_enabled = B_FALSE; 5712 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5713 if (nicsig == BGE_NIC_DATA_SIG) { 5714 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5715 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5716 /* 5717 * Here, we don't consider BAXTER, because BGE haven't 5718 * supported BAXTER (that is 5752). Also, as I know, 5719 * BAXTER doesn't support ASF feature. 5720 */ 5721 bgep->asf_enabled = B_TRUE; 5722 else 5723 bgep->asf_enabled = B_FALSE; 5724 } else 5725 bgep->asf_enabled = B_FALSE; 5726 } 5727 5728 5729 void 5730 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5731 { 5732 uint32_t tries; 5733 uint32_t event; 5734 5735 ASSERT(bgep->asf_enabled); 5736 5737 /* Issues "pause firmware" command and wait for ACK */ 5738 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5739 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5740 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5741 5742 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5743 tries = 0; 5744 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5745 drv_usecwait(1); 5746 tries ++; 5747 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5748 } 5749 5750 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5751 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5752 5753 if (bgep->asf_newhandshake) { 5754 switch (mode) { 5755 case BGE_INIT_RESET: 5756 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5757 BGE_DRV_STATE_START); 5758 break; 5759 case BGE_SHUTDOWN_RESET: 5760 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5761 BGE_DRV_STATE_UNLOAD); 5762 break; 5763 case BGE_SUSPEND_RESET: 5764 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5765 BGE_DRV_STATE_SUSPEND); 5766 break; 5767 default: 5768 break; 5769 } 5770 } 5771 } 5772 5773 5774 void 5775 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5776 { 5777 switch (mode) { 5778 case BGE_INIT_RESET: 5779 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5780 BGE_DRV_STATE_START); 5781 break; 5782 case BGE_SHUTDOWN_RESET: 5783 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5784 BGE_DRV_STATE_UNLOAD); 5785 break; 5786 case BGE_SUSPEND_RESET: 5787 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5788 BGE_DRV_STATE_SUSPEND); 5789 break; 5790 default: 5791 break; 5792 } 5793 } 5794 5795 5796 void 5797 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5798 { 5799 switch (mode) { 5800 case BGE_INIT_RESET: 5801 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5802 BGE_DRV_STATE_START_DONE); 5803 break; 5804 case BGE_SHUTDOWN_RESET: 5805 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5806 BGE_DRV_STATE_UNLOAD_DONE); 5807 break; 5808 default: 5809 break; 5810 } 5811 } 5812 5813 #endif /* BGE_IPMI_ASF */ 5814