xref: /titanic_50/usr/src/uts/common/io/bge/bge_chip2.c (revision be6e67355fa2266ba427189118d91a9e67b9163f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #include "bge_impl.h"
28 
29 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
30 
31 /*
32  * Future features ... ?
33  */
34 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
35 #define	BGE_IND_IO32	1	/* indirect access code		*/
36 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
37 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
38 
39 /*
40  * BGE MSI tunable:
41  *
42  * By default MSI is enabled on all supported platforms but it is disabled
43  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
44  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
45  */
46 boolean_t bge_enable_msi = B_TRUE;
47 
48 /*
49  * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
50  */
51 boolean_t bge_relaxed_ordering = B_TRUE;
52 
53 /*
54  * Property names
55  */
56 static char knownids_propname[] = "bge-known-subsystems";
57 
58 /*
59  * Patchable globals:
60  *
61  *	bge_autorecover
62  *		Enables/disables automatic recovery after fault detection
63  *
64  *	bge_mlcr_default
65  *		Value to program into the MLCR; controls the chip's GPIO pins
66  *
67  *	bge_dma_{rd,wr}prio
68  *		Relative priorities of DMA reads & DMA writes respectively.
69  *		These may each be patched to any value 0-3.  Equal values
70  *		will give "fair" (round-robin) arbitration for PCI access.
71  *		Unequal values will give one or the other function priority.
72  *
73  *	bge_dma_rwctrl
74  *		Value to put in the Read/Write DMA control register.  See
75  *	        the Broadcom PRM for things you can fiddle with in this
76  *		register ...
77  *
78  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
79  *		Send/receive interrupt coalescing parameters.  Counts are
80  *		#s of descriptors, ticks are in microseconds.  *norm* values
81  *		apply between status updates/interrupts; the *intr* values
82  *		refer to the 'during-interrupt' versions - see the PRM.
83  *
84  *		NOTE: these values have been determined by measurement. They
85  *		differ significantly from the values recommended in the PRM.
86  */
87 static uint32_t bge_autorecover = 1;
88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
89 
90 static uint32_t bge_dma_rdprio = 1;
91 static uint32_t bge_dma_wrprio = 0;
92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
96 
97 uint32_t bge_rx_ticks_norm = 128;
98 uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
99 uint32_t bge_rx_count_norm = 8;
100 uint32_t bge_tx_count_norm = 128;
101 
102 static uint32_t bge_rx_ticks_intr = 128;
103 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
104 static uint32_t bge_rx_count_intr = 2;
105 static uint32_t bge_tx_count_intr = 0;
106 
107 /*
108  * Memory pool configuration parameters.
109  *
110  * These are generally specific to each member of the chip family, since
111  * each one may have a different memory size/configuration.
112  *
113  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
114  * the driver from programming the various registers; instead they are left
115  * at their hardware defaults.  This is the preferred option for later chips
116  * (5705+), whereas the older chips *required* these registers to be set,
117  * since the h/w default was 0 ;-(
118  */
119 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
120 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
121 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
123 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
124 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
125 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
126 static uint32_t bge_mbuf_pool_len_5721	= 0;
127 
128 /*
129  * Various high and low water marks, thresholds, etc ...
130  *
131  * Note: these are taken from revision 7 of the PRM, and some are different
132  * from both the values in earlier PRMs *and* those determined experimentally
133  * and used in earlier versions of this driver ...
134  */
135 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
136 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
137 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
138 
139 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
140 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
141 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
142 
143 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
144 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
145 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
146 
147 static uint32_t	bge_watchdog_count	= 1 << 16;
148 static uint16_t bge_dma_miss_limit	= 20;
149 
150 static uint32_t bge_stop_start_on_sync	= 0;
151 
152 boolean_t bge_jumbo_enable		= B_TRUE;
153 
154 /*
155  * bge_intr_max_loop controls the maximum loop number within bge_intr.
156  * When loading NIC with heavy network traffic, it is useful.
157  * Increasing this value could have positive effect to throughput,
158  * but it might also increase ticks of a bge ISR stick on CPU, which might
159  * lead to bad UI interactive experience. So tune this with caution.
160  */
161 static int bge_intr_max_loop = 1;
162 
163 /*
164  * ========== Low-level chip & ring buffer manipulation ==========
165  */
166 
167 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
168 
169 
170 /*
171  * Config space read-modify-write routines
172  */
173 
174 #if	BGE_CFG_IO8
175 
176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
177 #pragma	inline(bge_cfg_clr16)
178 
179 static void
180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
181 {
182 	uint16_t regval;
183 
184 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
185 	    (void *)bgep, regno, bits));
186 
187 	regval = pci_config_get16(bgep->cfg_handle, regno);
188 
189 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
190 	    (void *)bgep, regno, bits, regval, regval & ~bits));
191 
192 	regval &= ~bits;
193 	pci_config_put16(bgep->cfg_handle, regno, regval);
194 }
195 
196 #endif	/* BGE_CFG_IO8 */
197 
198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
199 #pragma	inline(bge_cfg_clr32)
200 
201 static void
202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
203 {
204 	uint32_t regval;
205 
206 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
207 	    (void *)bgep, regno, bits));
208 
209 	regval = pci_config_get32(bgep->cfg_handle, regno);
210 
211 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
212 	    (void *)bgep, regno, bits, regval, regval & ~bits));
213 
214 	regval &= ~bits;
215 	pci_config_put32(bgep->cfg_handle, regno, regval);
216 }
217 
218 #if	BGE_IND_IO32
219 
220 /*
221  * Indirect access to registers & RISC scratchpads, using config space
222  * accesses only.
223  *
224  * This isn't currently used, but someday we might want to use it for
225  * restoring the Subsystem Device/Vendor registers (which aren't directly
226  * writable in Config Space), or for downloading firmware into the RISCs
227  *
228  * In any case there are endian issues to be resolved before this code is
229  * enabled; the bizarre way that bytes get twisted by this chip AND by
230  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
231  * it's been thoroughly tested for all access sizes on all supported
232  * architectures (SPARC *and* x86!).
233  */
234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
235 #pragma	inline(bge_ind_get32)
236 
237 uint32_t
238 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
239 {
240 	uint32_t val;
241 
242 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
243 
244 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
245 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
246 
247 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
248 	    (void *)bgep, regno, val));
249 
250 	val = LE_32(val);
251 
252 	return (val);
253 }
254 
255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
256 #pragma	inline(bge_ind_put32)
257 
258 void
259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
260 {
261 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
262 	    (void *)bgep, regno, val));
263 
264 	val = LE_32(val);
265 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
266 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
267 }
268 
269 #endif	/* BGE_IND_IO32 */
270 
271 #if	BGE_DEBUGGING
272 
273 static void bge_pci_check(bge_t *bgep);
274 #pragma	no_inline(bge_pci_check)
275 
276 static void
277 bge_pci_check(bge_t *bgep)
278 {
279 	uint16_t pcistatus;
280 
281 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
282 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
283 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
284 		    (void *)bgep, pcistatus));
285 }
286 
287 #endif	/* BGE_DEBUGGING */
288 
289 /*
290  * Perform first-stage chip (re-)initialisation, using only config-space
291  * accesses:
292  *
293  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
294  *   returning the data in the structure pointed to by <idp>.
295  * + Configure the target-mode endianness (swap) options.
296  * + Disable interrupts and enable Memory Space accesses.
297  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
298  *
299  * This sequence is adapted from Broadcom document 570X-PG102-R,
300  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
301  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
302  *
303  * This function MUST be called before any non-config-space accesses
304  * are made; on this first call <enable_dma> is B_FALSE, and it
305  * effectively performs steps 3-1(!) of the initialisation sequence
306  * (the rest are not required but should be harmless).
307  *
308  * It MUST also be called after a chip reset, as this disables
309  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
310  * it is effectively performing steps 6-8.
311  */
312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
313 #pragma	no_inline(bge_chip_cfg_init)
314 
315 void
316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
317 {
318 	ddi_acc_handle_t handle;
319 	uint16_t command;
320 	uint32_t mhcr;
321 	uint16_t value16;
322 	int i;
323 
324 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
325 	    (void *)bgep, (void *)cidp, enable_dma));
326 
327 	/*
328 	 * Step 3: save PCI cache line size and subsystem vendor ID
329 	 *
330 	 * Read all the config-space registers that characterise the
331 	 * chip, specifically vendor/device/revision/subsystem vendor
332 	 * and subsystem device id.  We expect (but don't check) that
333 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
334 	 *
335 	 * Also save all bus-transaction related registers (cache-line
336 	 * size, bus-grant/latency parameters, etc).  Some of these are
337 	 * cleared by reset, so we'll have to restore them later.  This
338 	 * comes from the Broadcom document 570X-PG102-R ...
339 	 *
340 	 * Note: Broadcom document 570X-PG102-R seems to be in error
341 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
342 	 * Subsystem (Device) ID registers, which are the opposite way
343 	 * round according to the PCI standard.  For good measure, we
344 	 * save/restore both anyway.
345 	 */
346 	handle = bgep->cfg_handle;
347 
348 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
349 	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
350 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
351 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
352 
353 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
354 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
355 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
356 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
357 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
358 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
359 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
360 
361 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
362 	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
363 	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
364 	    cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
365 	    cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
366 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
367 	    cidp->vendor, cidp->device, cidp->revision));
368 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
369 	    cidp->subven, cidp->subdev, cidp->asic_rev));
370 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
371 	    cidp->clsize, cidp->latency, cidp->command));
372 
373 	/*
374 	 * Step 2 (also step 6): disable and clear interrupts.
375 	 * Steps 11-13: configure PIO endianness options, and enable
376 	 * indirect register access.  We'll also select any other
377 	 * options controlled by the MHCR (e.g. tagged status, mask
378 	 * interrupt mode) at this stage ...
379 	 *
380 	 * Note: internally, the chip is 64-bit and BIG-endian, but
381 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
382 	 * it normally swaps bytes around at the PCI interface.
383 	 * However, the PCI host bridge on SPARC systems normally
384 	 * swaps the byte lanes around too, since SPARCs are also
385 	 * BIG-endian.  So it turns out that on SPARC, the right
386 	 * option is to tell the chip to swap (and the host bridge
387 	 * will swap back again), whereas on x86 we ask the chip
388 	 * NOT to swap, so the natural little-endianness of the
389 	 * PCI bus is assumed.  Then the only thing that doesn't
390 	 * automatically work right is access to an 8-byte register
391 	 * by a little-endian host; but we don't want to set the
392 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
393 	 * accesses don't go where expected ;-(  So we live with
394 	 * that, and perform word-swaps in software in the few cases
395 	 * where a chip register is defined as an 8-byte value --
396 	 * see the code below for details ...
397 	 *
398 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
399 	 * very clear in the register description in the PRM, but
400 	 * Broadcom document 570X-PG104-R page 248 explains a little
401 	 * more (under "Broadcom Mask Mode").  The bit changes the way
402 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
403 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
404 	 * way as the 5700 did, which isn't very convenient.  Setting
405 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
406 	 * bit do just what its name says -- MASK the PCI #INTA output
407 	 * (i.e. deassert the signal at the pin) leaving all internal
408 	 * state unchanged.  This is much more convenient for our
409 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
410 	 *
411 	 * Note: the inconvenient semantics of the interrupt mailbox
412 	 * (nonzero disables and acknowledges/clears the interrupt,
413 	 * zero enables AND CLEARS it) would make race conditions
414 	 * likely in the interrupt handler:
415 	 *
416 	 * (1)	acknowledge & disable interrupts
417 	 * (2)	while (more to do)
418 	 * 		process packets
419 	 * (3)	enable interrupts -- also clears pending
420 	 *
421 	 * If the chip received more packets and internally generated
422 	 * an interrupt between the check at (2) and the mbox write
423 	 * at (3), this interrupt would be lost :-(
424 	 *
425 	 * The best way to avoid this is to use TAGGED STATUS mode,
426 	 * where the chip includes a unique tag in each status block
427 	 * update, and the host, when re-enabling interrupts, passes
428 	 * the last tag it saw back to the chip; then the chip can
429 	 * see whether the host is truly up to date, and regenerate
430 	 * its interrupt if not.
431 	 */
432 	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
433 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
434 	    MHCR_MASK_INTERRUPT_MODE |
435 	    MHCR_CLEAR_INTERRUPT_INTA;
436 
437 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
438 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
439 
440 #ifdef	_BIG_ENDIAN
441 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
442 #endif	/* _BIG_ENDIAN */
443 
444 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
445 
446 #ifdef BGE_IPMI_ASF
447 	bgep->asf_wordswapped = B_FALSE;
448 #endif
449 	/*
450 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
451 	 *			 Disable Memory Write/Invalidate
452 	 *			 Enable or disable Bus Mastering
453 	 *
454 	 * Note that all other bits are taken from the original value saved
455 	 * the first time through here, rather than from the current register
456 	 * value, 'cos that will have been cleared by a soft RESET since.
457 	 * In this way we preserve the OBP/nexus-parent's preferred settings
458 	 * of the parity-error and system-error enable bits across multiple
459 	 * chip RESETs.
460 	 */
461 	command = bgep->chipid.command | PCI_COMM_MAE;
462 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
463 	if (enable_dma)
464 		command |= PCI_COMM_ME;
465 	/*
466 	 * on BCM5714 revision A0, false parity error gets generated
467 	 * due to a logic bug. Provide a workaround by disabling parity
468 	 * error.
469 	 */
470 	if (((cidp->device == DEVICE_ID_5714C) ||
471 	    (cidp->device == DEVICE_ID_5714S)) &&
472 	    (cidp->revision == REVISION_ID_5714_A0)) {
473 		command &= ~PCI_COMM_PARITY_DETECT;
474 	}
475 	pci_config_put16(handle, PCI_CONF_COMM, command);
476 
477 	/*
478 	 * On some PCI-E device, there were instances when
479 	 * the device was still link training.
480 	 */
481 	if (bgep->chipid.pci_type == BGE_PCI_E) {
482 		i = 0;
483 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
484 		while ((value16 != command) && (i < 100)) {
485 			drv_usecwait(200);
486 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
487 			++i;
488 		}
489 	}
490 
491 	/*
492 	 * Clear any remaining error status bits
493 	 */
494 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
495 
496 	/*
497 	 * Do following if and only if the device is NOT BCM5714C OR
498 	 * BCM5715C
499 	 */
500 	if (!((cidp->device == DEVICE_ID_5714C) ||
501 	    (cidp->device == DEVICE_ID_5715C))) {
502 		/*
503 		 * Make sure these indirect-access registers are sane
504 		 * rather than random after power-up or reset
505 		 */
506 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
507 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
508 	}
509 	/*
510 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
511 	 */
512 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
513 
514 	if (cidp->pci_type == BGE_PCI_E)
515 		bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
516 		    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
517 }
518 
519 #ifdef __amd64
520 /*
521  * Distinguish CPU types
522  *
523  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
524  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
525  * for PCI-Express based network interface card. This is the work-around
526  * for those nics.
527  */
528 static boolean_t bge_get_em64t_type(void);
529 #pragma	inline(bge_get_em64t_type)
530 
531 static boolean_t
532 bge_get_em64t_type(void)
533 {
534 
535 	return (x86_vendor == X86_VENDOR_Intel);
536 }
537 #endif
538 
539 /*
540  * Operating register get/set access routines
541  */
542 
543 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
544 #pragma	inline(bge_reg_get32)
545 
546 uint32_t
547 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
548 {
549 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
550 	    (void *)bgep, regno));
551 
552 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
553 }
554 
555 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
556 #pragma	inline(bge_reg_put32)
557 
558 void
559 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
560 {
561 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
562 	    (void *)bgep, regno, data));
563 
564 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
565 	BGE_PCICHK(bgep);
566 }
567 
568 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
569 #pragma	inline(bge_reg_set32)
570 
571 void
572 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
573 {
574 	uint32_t regval;
575 
576 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
577 	    (void *)bgep, regno, bits));
578 
579 	regval = bge_reg_get32(bgep, regno);
580 	regval |= bits;
581 	bge_reg_put32(bgep, regno, regval);
582 }
583 
584 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
585 #pragma	inline(bge_reg_clr32)
586 
587 void
588 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
589 {
590 	uint32_t regval;
591 
592 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
593 	    (void *)bgep, regno, bits));
594 
595 	regval = bge_reg_get32(bgep, regno);
596 	regval &= ~bits;
597 	bge_reg_put32(bgep, regno, regval);
598 }
599 
600 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
601 #pragma	inline(bge_reg_get64)
602 
603 static uint64_t
604 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
605 {
606 	uint64_t regval;
607 
608 #ifdef	__amd64
609 	if (bge_get_em64t_type()) {
610 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
611 		regval <<= 32;
612 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
613 	} else {
614 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
615 	}
616 #else
617 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
618 #endif
619 
620 #ifdef	_LITTLE_ENDIAN
621 	regval = (regval >> 32) | (regval << 32);
622 #endif	/* _LITTLE_ENDIAN */
623 
624 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
625 	    (void *)bgep, regno, regval));
626 
627 	return (regval);
628 }
629 
630 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
631 #pragma	inline(bge_reg_put64)
632 
633 static void
634 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
635 {
636 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
637 	    (void *)bgep, regno, data));
638 
639 #ifdef	_LITTLE_ENDIAN
640 	data = ((data >> 32) | (data << 32));
641 #endif	/* _LITTLE_ENDIAN */
642 
643 #ifdef	__amd64
644 	if (bge_get_em64t_type()) {
645 		ddi_put32(bgep->io_handle,
646 		    PIO_ADDR(bgep, regno), (uint32_t)data);
647 		BGE_PCICHK(bgep);
648 		ddi_put32(bgep->io_handle,
649 		    PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
650 
651 	} else {
652 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
653 	}
654 #else
655 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
656 #endif
657 
658 	BGE_PCICHK(bgep);
659 }
660 
661 /*
662  * The DDI doesn't provide get/put functions for 128 bit data
663  * so we put RCBs out as two 64-bit chunks instead.
664  */
665 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
666 #pragma	inline(bge_reg_putrcb)
667 
668 static void
669 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
670 {
671 	uint64_t *p;
672 
673 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
674 	    (void *)bgep, addr, rcbp->host_ring_addr,
675 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
676 
677 	ASSERT((addr % sizeof (*rcbp)) == 0);
678 
679 	p = (void *)rcbp;
680 	bge_reg_put64(bgep, addr, *p++);
681 	bge_reg_put64(bgep, addr+8, *p);
682 }
683 
684 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
685 #pragma	inline(bge_mbx_put)
686 
687 void
688 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
689 {
690 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
691 	    (void *)bgep, regno, data));
692 
693 	/*
694 	 * Mailbox registers are nominally 64 bits on the 5701, but
695 	 * the MSW isn't used.  On the 5703, they're only 32 bits
696 	 * anyway.  So here we just write the lower(!) 32 bits -
697 	 * remembering that the chip is big-endian, even though the
698 	 * PCI bus is little-endian ...
699 	 */
700 #ifdef	_BIG_ENDIAN
701 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
702 #else
703 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
704 #endif	/* _BIG_ENDIAN */
705 	BGE_PCICHK(bgep);
706 }
707 
708 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
709 #pragma inline(bge_mbx_get)
710 
711 uint32_t
712 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
713 {
714 	uint32_t val32;
715 
716 	BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
717 	    (void *)bgep, regno));
718 
719 #ifdef	_BIG_ENDIAN
720 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
721 #else
722 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
723 #endif	/* _BIG_ENDIAN */
724 	BGE_PCICHK(bgep);
725 
726 	return (val32);
727 }
728 
729 
730 #if	BGE_DEBUGGING
731 
732 void bge_led_mark(bge_t *bgep);
733 #pragma	no_inline(bge_led_mark)
734 
735 void
736 bge_led_mark(bge_t *bgep)
737 {
738 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
739 	    LED_CONTROL_1000MBPS_LED |
740 	    LED_CONTROL_100MBPS_LED |
741 	    LED_CONTROL_10MBPS_LED;
742 
743 	/*
744 	 * Blink all three LINK LEDs on simultaneously, then all off,
745 	 * then restore to automatic hardware control.  This is used
746 	 * in laboratory testing to trigger a logic analyser or scope.
747 	 */
748 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
749 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
750 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
751 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
752 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
753 }
754 
755 #endif	/* BGE_DEBUGGING */
756 
757 /*
758  * NIC on-chip memory access routines
759  *
760  * Only 32K of NIC memory is visible at a time, controlled by the
761  * Memory Window Base Address Register (in PCI config space).  Once
762  * this is set, the 32K region of NIC-local memory that it refers
763  * to can be directly addressed in the upper 32K of the 64K of PCI
764  * memory space used for the device.
765  */
766 
767 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
768 #pragma	inline(bge_nic_setwin)
769 
770 static void
771 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
772 {
773 	chip_id_t *cidp;
774 
775 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
776 	    (void *)bgep, base));
777 
778 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
779 
780 	/*
781 	 * Don't do repeated zero data writes,
782 	 * if the device is BCM5714C/15C.
783 	 */
784 	cidp = &bgep->chipid;
785 	if ((cidp->device == DEVICE_ID_5714C) ||
786 	    (cidp->device == DEVICE_ID_5715C)) {
787 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
788 			return;
789 		/* Adjust lastWriteZeroData */
790 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
791 		    B_TRUE : B_FALSE);
792 	}
793 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
794 }
795 
796 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
797 #pragma	inline(bge_nic_get32)
798 
799 static uint32_t
800 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
801 {
802 	uint32_t data;
803 
804 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
805 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
806 		/* workaround for word swap error */
807 		if (addr & 4)
808 			addr = addr - 4;
809 		else
810 			addr = addr + 4;
811 	}
812 #endif
813 
814 #ifdef __sparc
815 	data = bge_nic_read32(bgep, addr);
816 #else
817 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
818 	addr &= MWBAR_GRANULE_MASK;
819 	addr += NIC_MEM_WINDOW_OFFSET;
820 
821 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
822 #endif
823 
824 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
825 	    (void *)bgep, addr, data));
826 
827 	return (data);
828 }
829 
830 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
831 #pragma inline(bge_nic_put32)
832 
833 void
834 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
835 {
836 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
837 	    (void *)bgep, addr, data));
838 
839 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
840 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
841 		/* workaround for word swap error */
842 		if (addr & 4)
843 			addr = addr - 4;
844 		else
845 			addr = addr + 4;
846 	}
847 #endif
848 
849 #ifdef __sparc
850 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
851 	data = LE_32(data);
852 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
853 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
854 #else
855 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
856 	addr &= MWBAR_GRANULE_MASK;
857 	addr += NIC_MEM_WINDOW_OFFSET;
858 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
859 	BGE_PCICHK(bgep);
860 #endif
861 }
862 
863 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
864 #pragma	inline(bge_nic_get64)
865 
866 static uint64_t
867 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
868 {
869 	uint64_t data;
870 
871 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
872 	addr &= MWBAR_GRANULE_MASK;
873 	addr += NIC_MEM_WINDOW_OFFSET;
874 
875 #ifdef	__amd64
876 		if (bge_get_em64t_type()) {
877 			data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
878 			data <<= 32;
879 			data |= ddi_get32(bgep->io_handle,
880 			    PIO_ADDR(bgep, addr + 4));
881 		} else {
882 			data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
883 		}
884 #else
885 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
886 #endif
887 
888 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
889 	    (void *)bgep, addr, data));
890 
891 	return (data);
892 }
893 
894 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
895 #pragma	inline(bge_nic_put64)
896 
897 static void
898 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
899 {
900 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
901 	    (void *)bgep, addr, data));
902 
903 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
904 	addr &= MWBAR_GRANULE_MASK;
905 	addr += NIC_MEM_WINDOW_OFFSET;
906 
907 #ifdef	__amd64
908 	if (bge_get_em64t_type()) {
909 		ddi_put32(bgep->io_handle,
910 		    PIO_ADDR(bgep, addr), (uint32_t)data);
911 		BGE_PCICHK(bgep);
912 		ddi_put32(bgep->io_handle,
913 		    PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32));
914 	} else {
915 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
916 	}
917 #else
918 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
919 #endif
920 
921 	BGE_PCICHK(bgep);
922 }
923 
924 /*
925  * The DDI doesn't provide get/put functions for 128 bit data
926  * so we put RCBs out as two 64-bit chunks instead.
927  */
928 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
929 #pragma	inline(bge_nic_putrcb)
930 
931 static void
932 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
933 {
934 	uint64_t *p;
935 
936 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
937 	    (void *)bgep, addr, rcbp->host_ring_addr,
938 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
939 
940 	ASSERT((addr % sizeof (*rcbp)) == 0);
941 
942 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
943 	addr &= MWBAR_GRANULE_MASK;
944 	addr += NIC_MEM_WINDOW_OFFSET;
945 
946 	p = (void *)rcbp;
947 #ifdef	__amd64
948 	if (bge_get_em64t_type()) {
949 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
950 		    (uint32_t)(*p));
951 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
952 		    (uint32_t)(*p >> 32));
953 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
954 		    (uint32_t)(*(p + 1)));
955 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
956 		    (uint32_t)(*p >> 32));
957 
958 	} else {
959 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
960 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
961 	}
962 #else
963 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
964 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
965 #endif
966 
967 	BGE_PCICHK(bgep);
968 }
969 
970 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
971 #pragma	inline(bge_nic_zero)
972 
973 static void
974 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
975 {
976 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
977 	    (void *)bgep, addr, nbytes));
978 
979 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
980 	    ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
981 
982 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
983 	addr &= MWBAR_GRANULE_MASK;
984 	addr += NIC_MEM_WINDOW_OFFSET;
985 
986 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
987 	    nbytes, 1, DDI_DATA_SZ08_ACC);
988 	BGE_PCICHK(bgep);
989 }
990 
991 /*
992  * MII (PHY) register get/set access routines
993  *
994  * These use the chip's MII auto-access method, controlled by the
995  * MII Communication register at 0x044c, so the CPU doesn't have
996  * to fiddle with the individual bits.
997  */
998 
999 #undef	BGE_DBG
1000 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1001 
1002 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1003 				uint16_t data, uint32_t cmd);
1004 #pragma	no_inline(bge_mii_access)
1005 
1006 static uint16_t
1007 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1008 {
1009 	uint32_t timeout;
1010 	uint32_t regval1;
1011 	uint32_t regval2;
1012 
1013 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1014 	    (void *)bgep, regno, data, cmd));
1015 
1016 	ASSERT(mutex_owned(bgep->genlock));
1017 
1018 	/*
1019 	 * Assemble the command ...
1020 	 */
1021 	cmd |= data << MI_COMMS_DATA_SHIFT;
1022 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1023 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1024 	cmd |= MI_COMMS_START;
1025 
1026 	/*
1027 	 * Wait for any command already in progress ...
1028 	 *
1029 	 * Note: this *shouldn't* ever find that there is a command
1030 	 * in progress, because we already hold the <genlock> mutex.
1031 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1032 	 * bit set here -- it seems that the chip can initiate MII
1033 	 * accesses internally, even with polling OFF.
1034 	 */
1035 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1036 	for (timeout = 100; ; ) {
1037 		if ((regval2 & MI_COMMS_START) == 0) {
1038 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1039 			break;
1040 		}
1041 		if (--timeout == 0)
1042 			break;
1043 		drv_usecwait(10);
1044 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1045 	}
1046 
1047 	if (timeout == 0)
1048 		return ((uint16_t)~0u);
1049 
1050 	if (timeout != 100)
1051 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1052 		    "MI_COMMS_START set for %d us; 0x%x->0x%x",
1053 		    cmd, 10*(100-timeout), regval1, regval2));
1054 
1055 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1056 	for (timeout = 1000; ; ) {
1057 		if ((regval1 & MI_COMMS_START) == 0)
1058 			break;
1059 		if (--timeout == 0)
1060 			break;
1061 		drv_usecwait(10);
1062 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1063 	}
1064 
1065 	/*
1066 	 * Drop out early if the READ FAILED bit is set -- this chip
1067 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1068 	 */
1069 	if (regval2 & MI_COMMS_READ_FAILED)
1070 		return ((uint16_t)~0u);
1071 
1072 	if (timeout == 0)
1073 		return ((uint16_t)~0u);
1074 
1075 	/*
1076 	 * The PRM says to wait 5us after seeing the START bit clear
1077 	 * and then re-read the register to get the final value of the
1078 	 * data field, in order to avoid a race condition where the
1079 	 * START bit is clear but the data field isn't yet valid.
1080 	 *
1081 	 * Note: we don't actually seem to be encounter this race;
1082 	 * except when the START bit is seen set again (see below),
1083 	 * the data field doesn't change during this 5us interval.
1084 	 */
1085 	drv_usecwait(5);
1086 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1087 
1088 	/*
1089 	 * Unfortunately, when following the PRMs instructions above,
1090 	 * we have occasionally seen the START bit set again(!) in the
1091 	 * value read after the 5us delay. This seems to be due to the
1092 	 * chip autonomously starting another MII access internally.
1093 	 * In such cases, the command/data/etc fields relate to the
1094 	 * internal command, rather than the one that we thought had
1095 	 * just finished.  So in this case, we fall back to returning
1096 	 * the data from the original read that showed START clear.
1097 	 */
1098 	if (regval2 & MI_COMMS_START) {
1099 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1100 		    "MI_COMMS_START set after transaction; 0x%x->0x%x",
1101 		    cmd, regval1, regval2));
1102 		regval2 = regval1;
1103 	}
1104 
1105 	if (regval2 & MI_COMMS_START)
1106 		return ((uint16_t)~0u);
1107 
1108 	if (regval2 & MI_COMMS_READ_FAILED)
1109 		return ((uint16_t)~0u);
1110 
1111 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1112 }
1113 
1114 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1115 #pragma	no_inline(bge_mii_get16)
1116 
1117 uint16_t
1118 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1119 {
1120 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1121 	    (void *)bgep, regno));
1122 
1123 	ASSERT(mutex_owned(bgep->genlock));
1124 
1125 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1126 }
1127 
1128 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1129 #pragma	no_inline(bge_mii_put16)
1130 
1131 void
1132 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1133 {
1134 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1135 	    (void *)bgep, regno, data));
1136 
1137 	ASSERT(mutex_owned(bgep->genlock));
1138 
1139 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1140 }
1141 
1142 #undef	BGE_DBG
1143 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1144 
1145 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1146 
1147 /*
1148  * Basic SEEPROM get/set access routine
1149  *
1150  * This uses the chip's SEEPROM auto-access method, controlled by the
1151  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1152  * doesn't have to fiddle with the individual bits.
1153  *
1154  * The caller should hold <genlock> and *also* have already acquired
1155  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1156  *
1157  * Return value:
1158  *	0 on success,
1159  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1160  *	EPROTO on other h/w or s/w errors.
1161  *
1162  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1163  * from a (successful) SEEPROM_ACCESS_READ.
1164  */
1165 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1166 				uint32_t *dp);
1167 #pragma	no_inline(bge_seeprom_access)
1168 
1169 static int
1170 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1171 {
1172 	uint32_t tries;
1173 	uint32_t regval;
1174 
1175 	ASSERT(mutex_owned(bgep->genlock));
1176 
1177 	/*
1178 	 * On the newer chips that support both SEEPROM & Flash, we need
1179 	 * to specifically enable SEEPROM access (Flash is the default).
1180 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1181 	 * and the NVM control registers don't exist ...
1182 	 */
1183 	switch (bgep->chipid.nvtype) {
1184 	case BGE_NVTYPE_NONE:
1185 	case BGE_NVTYPE_UNKNOWN:
1186 		_NOTE(NOTREACHED)
1187 	case BGE_NVTYPE_SEEPROM:
1188 		break;
1189 
1190 	case BGE_NVTYPE_LEGACY_SEEPROM:
1191 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1192 	case BGE_NVTYPE_BUFFERED_FLASH:
1193 	default:
1194 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1195 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1196 		break;
1197 	}
1198 
1199 	/*
1200 	 * Check there's no command in progress.
1201 	 *
1202 	 * Note: this *shouldn't* ever find that there is a command
1203 	 * in progress, because we already hold the <genlock> mutex.
1204 	 * Also, to ensure we don't have a conflict with the chip's
1205 	 * internal firmware or a process accessing the same (shared)
1206 	 * SEEPROM through the other port of a 5704, we've already
1207 	 * been through the "software arbitration" protocol.
1208 	 * So this is just a final consistency check: we shouldn't
1209 	 * see EITHER the START bit (command started but not complete)
1210 	 * OR the COMPLETE bit (command completed but not cleared).
1211 	 */
1212 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1213 	if (regval & SEEPROM_ACCESS_START)
1214 		return (EPROTO);
1215 	if (regval & SEEPROM_ACCESS_COMPLETE)
1216 		return (EPROTO);
1217 
1218 	/*
1219 	 * Assemble the command ...
1220 	 */
1221 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1222 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1223 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1224 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1225 	cmd |= SEEPROM_ACCESS_START;
1226 	cmd |= SEEPROM_ACCESS_COMPLETE;
1227 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1228 
1229 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1230 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1231 
1232 	/*
1233 	 * By observation, a successful access takes ~20us on a 5703/4,
1234 	 * but apparently much longer (up to 1000us) on the obsolescent
1235 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1236 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1237 	 * out interrupts for longer than necessary. So we'll allow up
1238 	 * to 1000us ...
1239 	 */
1240 	for (tries = 0; tries < 1000; ++tries) {
1241 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1242 		if (regval & SEEPROM_ACCESS_COMPLETE)
1243 			break;
1244 		drv_usecwait(1);
1245 	}
1246 
1247 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1248 		/*
1249 		 * All OK; read the SEEPROM data register, then write back
1250 		 * the value read from the address register in order to
1251 		 * clear the <complete> bit and leave the SEEPROM access
1252 		 * state machine idle, ready for the next access ...
1253 		 */
1254 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1255 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1256 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1257 		return (0);
1258 	}
1259 
1260 	/*
1261 	 * Hmm ... what happened here?
1262 	 *
1263 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1264 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1265 	 * and didn't respond to being addressed. Either way, it's left
1266 	 * the SEEPROM access state machine wedged. So we'll reset it
1267 	 * before we leave, so it's ready for next time ...
1268 	 */
1269 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1270 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1271 	return (ENODATA);
1272 }
1273 
1274 /*
1275  * Basic Flash get/set access routine
1276  *
1277  * These use the chip's Flash auto-access method, controlled by the
1278  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1279  * fiddle with the individual bits.
1280  *
1281  * The caller should hold <genlock> and *also* have already acquired
1282  * the right to access the Flash, via bge_nvmem_acquire() above.
1283  *
1284  * Return value:
1285  *	0 on success,
1286  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1287  *	ENODEV if the NVmem device is missing or otherwise unusable
1288  *
1289  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1290  * from a (successful) NVM_FLASH_CMD_RD.
1291  */
1292 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1293 				uint32_t *dp);
1294 #pragma	no_inline(bge_flash_access)
1295 
1296 static int
1297 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1298 {
1299 	uint32_t tries;
1300 	uint32_t regval;
1301 
1302 	ASSERT(mutex_owned(bgep->genlock));
1303 
1304 	/*
1305 	 * On the newer chips that support both SEEPROM & Flash, we need
1306 	 * to specifically disable SEEPROM access while accessing Flash.
1307 	 * The older chips don't support Flash, and the NVM registers don't
1308 	 * exist, so we shouldn't be here at all!
1309 	 */
1310 	switch (bgep->chipid.nvtype) {
1311 	case BGE_NVTYPE_NONE:
1312 	case BGE_NVTYPE_UNKNOWN:
1313 		_NOTE(NOTREACHED)
1314 	case BGE_NVTYPE_SEEPROM:
1315 		return (ENODEV);
1316 
1317 	case BGE_NVTYPE_LEGACY_SEEPROM:
1318 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1319 	case BGE_NVTYPE_BUFFERED_FLASH:
1320 	default:
1321 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1322 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1323 		break;
1324 	}
1325 
1326 	/*
1327 	 * Assemble the command ...
1328 	 */
1329 	addr &= NVM_FLASH_ADDR_MASK;
1330 	cmd |= NVM_FLASH_CMD_DOIT;
1331 	cmd |= NVM_FLASH_CMD_FIRST;
1332 	cmd |= NVM_FLASH_CMD_LAST;
1333 	cmd |= NVM_FLASH_CMD_DONE;
1334 
1335 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1336 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1337 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1338 
1339 	/*
1340 	 * Allow up to 1000ms ...
1341 	 */
1342 	for (tries = 0; tries < 1000; ++tries) {
1343 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1344 		if (regval & NVM_FLASH_CMD_DONE)
1345 			break;
1346 		drv_usecwait(1);
1347 	}
1348 
1349 	if (regval & NVM_FLASH_CMD_DONE) {
1350 		/*
1351 		 * All OK; read the data from the Flash read register
1352 		 */
1353 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1354 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1355 		return (0);
1356 	}
1357 
1358 	/*
1359 	 * Hmm ... what happened here?
1360 	 *
1361 	 * Most likely, the user addressed a non-existent Flash. Or
1362 	 * maybe the Flash was busy internally (e.g. processing a write)
1363 	 * and didn't respond to being addressed. Either way, there's
1364 	 * nothing we can here ...
1365 	 */
1366 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1367 	return (ENODATA);
1368 }
1369 
1370 /*
1371  * The next two functions regulate access to the NVram (if fitted).
1372  *
1373  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1374  * (SPI) interface, but they can be accessed through either port. These
1375  * are managed by different instance of this driver and have no software
1376  * state in common.
1377  *
1378  * In addition (and even on a single core chip) the chip's internal
1379  * firmware can access the SEEPROM/Flash, most notably after a RESET
1380  * when it may download code to run internally.
1381  *
1382  * So we need to arbitrate between these various software agents.  For
1383  * this purpose, the chip provides the Software Arbitration Register,
1384  * which implements hardware(!) arbitration.
1385  *
1386  * This functionality didn't exist on older (5700/5701) chips, so there's
1387  * nothing we can do by way of arbitration on those; also, if there's no
1388  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1389  * nothing to do.
1390  *
1391  * The internal firmware appears to use Request 0, which is the highest
1392  * priority.  So we'd like to use Request 2, leaving one higher and one
1393  * lower for any future developments ... but apparently this doesn't
1394  * always work.  So for now, the code uses Request 1 ;-(
1395  */
1396 
1397 #define	NVM_READ_REQ	NVM_READ_REQ1
1398 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1399 #define	NVM_SET_REQ	NVM_SET_REQ1
1400 
1401 static void bge_nvmem_relinquish(bge_t *bgep);
1402 #pragma	no_inline(bge_nvmem_relinquish)
1403 
1404 static void
1405 bge_nvmem_relinquish(bge_t *bgep)
1406 {
1407 	ASSERT(mutex_owned(bgep->genlock));
1408 
1409 	switch (bgep->chipid.nvtype) {
1410 	case BGE_NVTYPE_NONE:
1411 	case BGE_NVTYPE_UNKNOWN:
1412 		_NOTE(NOTREACHED)
1413 		return;
1414 
1415 	case BGE_NVTYPE_SEEPROM:
1416 		/*
1417 		 * No arbitration performed, no release needed
1418 		 */
1419 		return;
1420 
1421 	case BGE_NVTYPE_LEGACY_SEEPROM:
1422 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1423 	case BGE_NVTYPE_BUFFERED_FLASH:
1424 	default:
1425 		break;
1426 	}
1427 
1428 	/*
1429 	 * Our own request should be present (whether or not granted) ...
1430 	 */
1431 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1432 
1433 	/*
1434 	 * ... this will make it go away.
1435 	 */
1436 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1437 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1438 }
1439 
1440 /*
1441  * Arbitrate for access to the NVmem, if necessary
1442  *
1443  * Return value:
1444  *	0 on success
1445  *	EAGAIN if the device is in use (retryable)
1446  *	ENODEV if the NVmem device is missing or otherwise unusable
1447  */
1448 static int bge_nvmem_acquire(bge_t *bgep);
1449 #pragma	no_inline(bge_nvmem_acquire)
1450 
1451 static int
1452 bge_nvmem_acquire(bge_t *bgep)
1453 {
1454 	uint32_t regval;
1455 	uint32_t tries;
1456 
1457 	ASSERT(mutex_owned(bgep->genlock));
1458 
1459 	switch (bgep->chipid.nvtype) {
1460 	case BGE_NVTYPE_NONE:
1461 	case BGE_NVTYPE_UNKNOWN:
1462 		/*
1463 		 * Access denied: no (recognisable) device fitted
1464 		 */
1465 		return (ENODEV);
1466 
1467 	case BGE_NVTYPE_SEEPROM:
1468 		/*
1469 		 * Access granted: no arbitration needed (or possible)
1470 		 */
1471 		return (0);
1472 
1473 	case BGE_NVTYPE_LEGACY_SEEPROM:
1474 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1475 	case BGE_NVTYPE_BUFFERED_FLASH:
1476 	default:
1477 		/*
1478 		 * Access conditional: conduct arbitration protocol
1479 		 */
1480 		break;
1481 	}
1482 
1483 	/*
1484 	 * We're holding the per-port mutex <genlock>, so no-one other
1485 	 * thread can be attempting to access the NVmem through *this*
1486 	 * port. But it could be in use by the *other* port (of a 5704),
1487 	 * or by the chip's internal firmware, so we have to go through
1488 	 * the full (hardware) arbitration protocol ...
1489 	 *
1490 	 * Note that *because* we're holding <genlock>, the interrupt handler
1491 	 * won't be able to progress.  So we're only willing to spin for a
1492 	 * fairly short time.  Specifically:
1493 	 *
1494 	 *	We *must* wait long enough for the hardware to resolve all
1495 	 *	requests and determine the winner.  Fortunately, this is
1496 	 *	"almost instantaneous", even as observed by GHz CPUs.
1497 	 *
1498 	 *	A successful access by another Solaris thread (via either
1499 	 *	port) typically takes ~20us.  So waiting a bit longer than
1500 	 *	that will give a good chance of success, if the other user
1501 	 *	*is* another thread on the other port.
1502 	 *
1503 	 *	However, the internal firmware can hold on to the NVmem
1504 	 *	for *much* longer: at least 10 milliseconds just after a
1505 	 *	RESET, and maybe even longer if the NVmem actually contains
1506 	 *	code to download and run on the internal CPUs.
1507 	 *
1508 	 * So, we'll allow 50us; if that's not enough then it's up to the
1509 	 * caller to retry later (hence the choice of return code EAGAIN).
1510 	 */
1511 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1512 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1513 
1514 	for (tries = 0; tries < 50; ++tries) {
1515 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1516 		if (regval & NVM_WON_REQ1)
1517 			break;
1518 		drv_usecwait(1);
1519 	}
1520 
1521 	if (regval & NVM_WON_REQ1) {
1522 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1523 		return (0);
1524 	}
1525 
1526 	/*
1527 	 * Somebody else must be accessing the NVmem, so abandon our
1528 	 * attempt take control of it.  The caller can try again later ...
1529 	 */
1530 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1531 	bge_nvmem_relinquish(bgep);
1532 	return (EAGAIN);
1533 }
1534 
1535 /*
1536  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1537  * write protect line in such a way that the NVmem is protected when
1538  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1539  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1540  *
1541  * Note: there's only one set of GPIO pins on a 5704, even though they
1542  * can be accessed through either port.  So the chip has to resolve what
1543  * happens if the two ports program a single pin differently ... the rule
1544  * it uses is that if the ports disagree about the *direction* of a pin,
1545  * "output" wins over "input", but if they disagree about its *value* as
1546  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1547  * wins, and the external signal does whatever the external circuitry
1548  * defines as the default -- which we've assumed is the PROTECTED state.
1549  * So, we always change GPIO1 back to being an *input* whenever we're not
1550  * specifically using it to unprotect the NVmem. This allows either port
1551  * to update the NVmem, although obviously only one at a time!
1552  *
1553  * The caller should hold <genlock> and *also* have already acquired the
1554  * right to access the NVmem, via bge_nvmem_acquire() above.
1555  */
1556 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1557 #pragma	inline(bge_nvmem_protect)
1558 
1559 static void
1560 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1561 {
1562 	uint32_t regval;
1563 
1564 	ASSERT(mutex_owned(bgep->genlock));
1565 
1566 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1567 	if (protect) {
1568 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1569 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1570 	} else {
1571 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1572 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1573 	}
1574 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1575 }
1576 
1577 /*
1578  * Now put it all together ...
1579  *
1580  * Try to acquire control of the NVmem; if successful, then:
1581  *	unprotect it (if we want to write to it)
1582  *	perform the requested access
1583  *	reprotect it (after a write)
1584  *	relinquish control
1585  *
1586  * Return value:
1587  *	0 on success,
1588  *	EAGAIN if the device is in use (retryable)
1589  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1590  *	ENODEV if the NVmem device is missing or otherwise unusable
1591  *	EPROTO on other h/w or s/w errors.
1592  */
1593 static int
1594 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1595 {
1596 	int err;
1597 
1598 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1599 		switch (cmd) {
1600 		case BGE_SEE_READ:
1601 			err = bge_seeprom_access(bgep,
1602 			    SEEPROM_ACCESS_READ, addr, dp);
1603 			break;
1604 
1605 		case BGE_SEE_WRITE:
1606 			bge_nvmem_protect(bgep, B_FALSE);
1607 			err = bge_seeprom_access(bgep,
1608 			    SEEPROM_ACCESS_WRITE, addr, dp);
1609 			bge_nvmem_protect(bgep, B_TRUE);
1610 			break;
1611 
1612 		case BGE_FLASH_READ:
1613 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1614 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1615 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1616 				    NVM_ACCESS_ENABLE);
1617 			}
1618 			err = bge_flash_access(bgep,
1619 			    NVM_FLASH_CMD_RD, addr, dp);
1620 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1621 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1622 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1623 				    NVM_ACCESS_ENABLE);
1624 			}
1625 			break;
1626 
1627 		case BGE_FLASH_WRITE:
1628 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1629 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1630 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1631 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1632 			}
1633 			bge_nvmem_protect(bgep, B_FALSE);
1634 			err = bge_flash_access(bgep,
1635 			    NVM_FLASH_CMD_WR, addr, dp);
1636 			bge_nvmem_protect(bgep, B_TRUE);
1637 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1638 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1639 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1640 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1641 			}
1642 
1643 			break;
1644 
1645 		default:
1646 			_NOTE(NOTREACHED)
1647 			break;
1648 		}
1649 		bge_nvmem_relinquish(bgep);
1650 	}
1651 
1652 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1653 	return (err);
1654 }
1655 
1656 /*
1657  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1658  */
1659 static uint64_t bge_get_nvmac(bge_t *bgep);
1660 #pragma no_inline(bge_get_nvmac)
1661 
1662 static uint64_t
1663 bge_get_nvmac(bge_t *bgep)
1664 {
1665 	uint32_t mac_high;
1666 	uint32_t mac_low;
1667 	uint32_t addr;
1668 	uint32_t cmd;
1669 	uint64_t mac;
1670 
1671 	BGE_TRACE(("bge_get_nvmac($%p)",
1672 	    (void *)bgep));
1673 
1674 	switch (bgep->chipid.nvtype) {
1675 	case BGE_NVTYPE_NONE:
1676 	case BGE_NVTYPE_UNKNOWN:
1677 	default:
1678 		return (0ULL);
1679 
1680 	case BGE_NVTYPE_SEEPROM:
1681 	case BGE_NVTYPE_LEGACY_SEEPROM:
1682 		cmd = BGE_SEE_READ;
1683 		break;
1684 
1685 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1686 	case BGE_NVTYPE_BUFFERED_FLASH:
1687 		cmd = BGE_FLASH_READ;
1688 		break;
1689 	}
1690 
1691 	addr = NVMEM_DATA_MAC_ADDRESS;
1692 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1693 		return (0ULL);
1694 	addr += 4;
1695 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1696 		return (0ULL);
1697 
1698 	/*
1699 	 * The Broadcom chip is natively BIG-endian, so that's how the
1700 	 * MAC address is represented in NVmem.  We may need to swap it
1701 	 * around on a little-endian host ...
1702 	 */
1703 #ifdef	_BIG_ENDIAN
1704 	mac = mac_high;
1705 	mac = mac << 32;
1706 	mac |= mac_low;
1707 #else
1708 	mac = BGE_BSWAP_32(mac_high);
1709 	mac = mac << 32;
1710 	mac |= BGE_BSWAP_32(mac_low);
1711 #endif	/* _BIG_ENDIAN */
1712 
1713 	return (mac);
1714 }
1715 
1716 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1717 
1718 /*
1719  * Dummy version for when we're not supporting NVmem access
1720  */
1721 static uint64_t bge_get_nvmac(bge_t *bgep);
1722 #pragma inline(bge_get_nvmac)
1723 
1724 static uint64_t
1725 bge_get_nvmac(bge_t *bgep)
1726 {
1727 	_NOTE(ARGUNUSED(bgep))
1728 	return (0ULL);
1729 }
1730 
1731 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1732 
1733 /*
1734  * Determine the type of NVmem that is (or may be) attached to this chip,
1735  */
1736 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1737 #pragma no_inline(bge_nvmem_id)
1738 
1739 static enum bge_nvmem_type
1740 bge_nvmem_id(bge_t *bgep)
1741 {
1742 	enum bge_nvmem_type nvtype;
1743 	uint32_t config1;
1744 
1745 	BGE_TRACE(("bge_nvmem_id($%p)",
1746 	    (void *)bgep));
1747 
1748 	switch (bgep->chipid.device) {
1749 	default:
1750 		/*
1751 		 * We shouldn't get here; it means we don't recognise
1752 		 * the chip, which means we don't know how to determine
1753 		 * what sort of NVmem (if any) it has.  So we'll say
1754 		 * NONE, to disable the NVmem access code ...
1755 		 */
1756 		nvtype = BGE_NVTYPE_NONE;
1757 		break;
1758 
1759 	case DEVICE_ID_5700:
1760 	case DEVICE_ID_5700x:
1761 	case DEVICE_ID_5701:
1762 		/*
1763 		 * These devices support *only* SEEPROMs
1764 		 */
1765 		nvtype = BGE_NVTYPE_SEEPROM;
1766 		break;
1767 
1768 	case DEVICE_ID_5702:
1769 	case DEVICE_ID_5702fe:
1770 	case DEVICE_ID_5703C:
1771 	case DEVICE_ID_5703S:
1772 	case DEVICE_ID_5704C:
1773 	case DEVICE_ID_5704S:
1774 	case DEVICE_ID_5704:
1775 	case DEVICE_ID_5705M:
1776 	case DEVICE_ID_5705C:
1777 	case DEVICE_ID_5705_2:
1778 	case DEVICE_ID_5706:
1779 	case DEVICE_ID_5782:
1780 	case DEVICE_ID_5787:
1781 	case DEVICE_ID_5787M:
1782 	case DEVICE_ID_5788:
1783 	case DEVICE_ID_5789:
1784 	case DEVICE_ID_5751:
1785 	case DEVICE_ID_5751M:
1786 	case DEVICE_ID_5752:
1787 	case DEVICE_ID_5752M:
1788 	case DEVICE_ID_5754:
1789 	case DEVICE_ID_5755:
1790 	case DEVICE_ID_5755M:
1791 	case DEVICE_ID_5721:
1792 	case DEVICE_ID_5722:
1793 	case DEVICE_ID_5714C:
1794 	case DEVICE_ID_5714S:
1795 	case DEVICE_ID_5715C:
1796 	case DEVICE_ID_5715S:
1797 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1798 		if (config1 & NVM_CFG1_FLASH_MODE)
1799 			if (config1 & NVM_CFG1_BUFFERED_MODE)
1800 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1801 			else
1802 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1803 		else
1804 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1805 		break;
1806 	}
1807 
1808 	return (nvtype);
1809 }
1810 
1811 #undef	BGE_DBG
1812 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
1813 
1814 static void
1815 bge_init_recv_rule(bge_t *bgep)
1816 {
1817 	bge_recv_rule_t *rulep;
1818 	uint32_t i;
1819 
1820 	/*
1821 	 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING
1822 	 * 1. to direct UDP traffic, set:
1823 	 * 	rulep->control = RULE_PROTO_CONTROL;
1824 	 * 	rulep->mask_value = RULE_UDP_MASK_VALUE;
1825 	 * 2. to direct ICMP traffic, set:
1826 	 * 	rulep->control = RULE_PROTO_CONTROL;
1827 	 * 	rulep->mask_value = RULE_ICMP_MASK_VALUE;
1828 	 * 3. to direct traffic by source ip, set:
1829 	 * 	rulep->control = RULE_SIP_CONTROL;
1830 	 * 	rulep->mask_value = RULE_SIP_MASK_VALUE;
1831 	 */
1832 	rulep = bgep->recv_rules;
1833 	rulep->control = RULE_PROTO_CONTROL;
1834 	rulep->mask_value = RULE_TCP_MASK_VALUE;
1835 
1836 	/*
1837 	 * set receive rule registers
1838 	 */
1839 	rulep = bgep->recv_rules;
1840 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1841 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1842 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1843 	}
1844 }
1845 
1846 /*
1847  * Using the values captured by bge_chip_cfg_init(), and additional probes
1848  * as required, characterise the chip fully: determine the label by which
1849  * to refer to this chip, the correct settings for various registers, and
1850  * of course whether the device and/or subsystem are supported!
1851  */
1852 int bge_chip_id_init(bge_t *bgep);
1853 #pragma	no_inline(bge_chip_id_init)
1854 
1855 int
1856 bge_chip_id_init(bge_t *bgep)
1857 {
1858 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
1859 	boolean_t sys_ok;
1860 	boolean_t dev_ok;
1861 	chip_id_t *cidp;
1862 	uint32_t subid;
1863 	char *devname;
1864 	char *sysname;
1865 	int *ids;
1866 	int err;
1867 	uint_t i;
1868 
1869 	sys_ok = dev_ok = B_FALSE;
1870 	cidp = &bgep->chipid;
1871 
1872 	/*
1873 	 * Check the PCI device ID to determine the generic chip type and
1874 	 * select parameters that depend on this.
1875 	 *
1876 	 * Note: because the SPARC platforms in general don't fit the
1877 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
1878 	 * as zero - which is why we use <asic_rev> rather than <revision>
1879 	 * below ...
1880 	 *
1881 	 * Note: in general we can't distinguish between the Copper/SerDes
1882 	 * versions by ID alone, as some Copper devices (e.g. some but not
1883 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
1884 	 * treat them the same here, and the MII code works out the media
1885 	 * type later on ...
1886 	 */
1887 	cidp->mbuf_base = bge_mbuf_pool_base;
1888 	cidp->mbuf_length = bge_mbuf_pool_len;
1889 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
1890 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
1891 	cidp->pci_type = BGE_PCI_X;
1892 	cidp->statistic_type = BGE_STAT_BLK;
1893 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
1894 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
1895 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
1896 	cidp->rx_ticks_norm = bge_rx_ticks_norm;
1897 	cidp->rx_count_norm = bge_rx_count_norm;
1898 
1899 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
1900 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
1901 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
1902 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
1903 
1904 	cidp->msi_enabled = B_FALSE;
1905 
1906 	switch (cidp->device) {
1907 	case DEVICE_ID_5700:
1908 	case DEVICE_ID_5700x:
1909 		cidp->chip_label = 5700;
1910 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1911 		break;
1912 
1913 	case DEVICE_ID_5701:
1914 		cidp->chip_label = 5701;
1915 		dev_ok = B_TRUE;
1916 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1917 		break;
1918 
1919 	case DEVICE_ID_5702:
1920 	case DEVICE_ID_5702fe:
1921 		cidp->chip_label = 5702;
1922 		dev_ok = B_TRUE;
1923 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1924 		cidp->pci_type = BGE_PCI;
1925 		break;
1926 
1927 	case DEVICE_ID_5703C:
1928 	case DEVICE_ID_5703S:
1929 	case DEVICE_ID_5703:
1930 		/*
1931 		 * Revision A0 of the 5703/5793 had various errata
1932 		 * that we can't or don't work around, so it's not
1933 		 * supported, but all later versions are
1934 		 */
1935 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
1936 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
1937 			dev_ok = B_TRUE;
1938 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1939 		break;
1940 
1941 	case DEVICE_ID_5704C:
1942 	case DEVICE_ID_5704S:
1943 	case DEVICE_ID_5704:
1944 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
1945 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
1946 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
1947 		dev_ok = B_TRUE;
1948 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1949 		break;
1950 
1951 	case DEVICE_ID_5705C:
1952 	case DEVICE_ID_5705M:
1953 	case DEVICE_ID_5705MA3:
1954 	case DEVICE_ID_5705F:
1955 	case DEVICE_ID_5705_2:
1956 	case DEVICE_ID_5754:
1957 		if (cidp->device == DEVICE_ID_5754) {
1958 			cidp->chip_label = 5754;
1959 			cidp->pci_type = BGE_PCI_E;
1960 		} else {
1961 			cidp->chip_label = 5705;
1962 			cidp->pci_type = BGE_PCI;
1963 		}
1964 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
1965 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
1966 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
1967 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
1968 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
1969 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
1970 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
1971 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
1972 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
1973 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1974 		cidp->statistic_type = BGE_STAT_REG;
1975 		dev_ok = B_TRUE;
1976 		break;
1977 
1978 	case DEVICE_ID_5753:
1979 		cidp->chip_label = 5753;
1980 		cidp->pci_type = BGE_PCI_E;
1981 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
1982 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
1983 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
1984 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
1985 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
1986 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
1987 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1988 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
1989 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
1990 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
1991 		cidp->statistic_type = BGE_STAT_REG;
1992 		dev_ok = B_TRUE;
1993 		break;
1994 
1995 	case DEVICE_ID_5755:
1996 	case DEVICE_ID_5755M:
1997 		cidp->chip_label = 5755;
1998 		cidp->pci_type = BGE_PCI_E;
1999 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2000 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2001 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2002 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2003 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2004 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2005 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2006 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2007 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2008 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2009 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2010 		cidp->statistic_type = BGE_STAT_REG;
2011 		dev_ok = B_TRUE;
2012 		break;
2013 
2014 	case DEVICE_ID_5787:
2015 	case DEVICE_ID_5787M:
2016 		cidp->chip_label = 5787;
2017 		cidp->pci_type = BGE_PCI_E;
2018 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2019 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2020 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2021 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2022 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2023 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2024 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2025 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2026 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2027 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2028 		cidp->statistic_type = BGE_STAT_REG;
2029 		dev_ok = B_TRUE;
2030 		break;
2031 
2032 	case DEVICE_ID_5706:
2033 		cidp->chip_label = 5706;
2034 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2035 		break;
2036 
2037 	case DEVICE_ID_5782:
2038 		/*
2039 		 * Apart from the label, we treat this as a 5705(?)
2040 		 */
2041 		cidp->chip_label = 5782;
2042 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2043 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2044 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2045 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2046 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2047 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2048 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2049 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2050 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2051 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2052 		cidp->statistic_type = BGE_STAT_REG;
2053 		dev_ok = B_TRUE;
2054 		break;
2055 
2056 	case DEVICE_ID_5788:
2057 		/*
2058 		 * Apart from the label, we treat this as a 5705(?)
2059 		 */
2060 		cidp->chip_label = 5788;
2061 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2062 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2063 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2064 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2065 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2066 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2067 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2068 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2069 		cidp->statistic_type = BGE_STAT_REG;
2070 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2071 		dev_ok = B_TRUE;
2072 		break;
2073 
2074 	case DEVICE_ID_5714C:
2075 		if (cidp->revision >= REVISION_ID_5714_A2)
2076 			cidp->msi_enabled = bge_enable_msi;
2077 		/* FALLTHRU */
2078 	case DEVICE_ID_5714S:
2079 		cidp->chip_label = 5714;
2080 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2081 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2082 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2083 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2084 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2085 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2086 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2087 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2088 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2089 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2090 		cidp->pci_type = BGE_PCI_E;
2091 		cidp->statistic_type = BGE_STAT_REG;
2092 		dev_ok = B_TRUE;
2093 		break;
2094 
2095 	case DEVICE_ID_5715C:
2096 	case DEVICE_ID_5715S:
2097 		cidp->chip_label = 5715;
2098 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2099 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2100 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2101 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2102 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2103 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2104 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2105 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2106 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2107 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2108 		cidp->pci_type = BGE_PCI_E;
2109 		cidp->statistic_type = BGE_STAT_REG;
2110 		if (cidp->revision >= REVISION_ID_5715_A2)
2111 			cidp->msi_enabled = bge_enable_msi;
2112 		dev_ok = B_TRUE;
2113 		break;
2114 
2115 	case DEVICE_ID_5721:
2116 		cidp->chip_label = 5721;
2117 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2118 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2119 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2120 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2121 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2122 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2123 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2124 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2125 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2126 		cidp->pci_type = BGE_PCI_E;
2127 		cidp->statistic_type = BGE_STAT_REG;
2128 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2129 		dev_ok = B_TRUE;
2130 		break;
2131 
2132 	case DEVICE_ID_5722:
2133 		cidp->chip_label = 5722;
2134 		cidp->pci_type = BGE_PCI_E;
2135 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2136 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2137 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2138 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2139 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2140 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2141 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2142 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2143 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2144 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2145 		cidp->statistic_type = BGE_STAT_REG;
2146 		dev_ok = B_TRUE;
2147 		break;
2148 
2149 	case DEVICE_ID_5751:
2150 	case DEVICE_ID_5751M:
2151 		cidp->chip_label = 5751;
2152 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2153 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2154 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2155 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2156 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2157 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2158 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2159 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2160 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2161 		cidp->pci_type = BGE_PCI_E;
2162 		cidp->statistic_type = BGE_STAT_REG;
2163 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2164 		dev_ok = B_TRUE;
2165 		break;
2166 
2167 	case DEVICE_ID_5752:
2168 	case DEVICE_ID_5752M:
2169 		cidp->chip_label = 5752;
2170 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2171 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2172 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2173 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2174 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2175 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2176 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2177 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2178 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2179 		cidp->pci_type = BGE_PCI_E;
2180 		cidp->statistic_type = BGE_STAT_REG;
2181 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2182 		dev_ok = B_TRUE;
2183 		break;
2184 
2185 	case DEVICE_ID_5789:
2186 		cidp->chip_label = 5789;
2187 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2188 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2189 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2190 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2191 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2192 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2193 		cidp->pci_type = BGE_PCI_E;
2194 		cidp->statistic_type = BGE_STAT_REG;
2195 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2196 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2197 		cidp->msi_enabled = B_TRUE;
2198 		dev_ok = B_TRUE;
2199 		break;
2200 
2201 	}
2202 
2203 	/*
2204 	 * Setup the default jumbo parameter.
2205 	 */
2206 	cidp->ethmax_size = ETHERMAX;
2207 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2208 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2209 
2210 	/*
2211 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2212 	 * setup below jumbo specific parameters.
2213 	 *
2214 	 * For BCM5714/5715, there is only one standard receive ring. So the
2215 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2216 	 * feature is enabled.
2217 	 */
2218 	if (bge_jumbo_enable &&
2219 	    !(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2220 	    (cidp->default_mtu > BGE_DEFAULT_MTU) &&
2221 	    (cidp->default_mtu <= BGE_MAXIMUM_MTU)) {
2222 		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2223 			cidp->mbuf_lo_water_rdma =
2224 			    RDMA_MBUF_LOWAT_5714_JUMBO;
2225 			cidp->mbuf_lo_water_rmac =
2226 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
2227 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2228 			cidp->jumbo_slots = 0;
2229 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2230 		} else {
2231 			cidp->mbuf_lo_water_rdma =
2232 			    RDMA_MBUF_LOWAT_JUMBO;
2233 			cidp->mbuf_lo_water_rmac =
2234 			    MAC_RX_MBUF_LOWAT_JUMBO;
2235 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2236 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2237 		}
2238 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2239 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2240 		cidp->ethmax_size = cidp->default_mtu +
2241 		    sizeof (struct ether_header);
2242 	}
2243 
2244 	/*
2245 	 * Identify the NV memory type: SEEPROM or Flash?
2246 	 */
2247 	cidp->nvtype = bge_nvmem_id(bgep);
2248 
2249 	/*
2250 	 * Now, we want to check whether this device is part of a
2251 	 * supported subsystem (e.g., on the motherboard of a Sun
2252 	 * branded platform).
2253 	 *
2254 	 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2255 	 */
2256 	if (cidp->subven == VENDOR_ID_SUN)
2257 		sys_ok = B_TRUE;
2258 
2259 	/*
2260 	 * Rule 2: If it's on the list on known subsystems, then it's OK.
2261 	 * Note: 0x14e41647 should *not* appear in the list, but the code
2262 	 * doesn't enforce that.
2263 	 */
2264 	err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2265 	    DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2266 	if (err == DDI_PROP_SUCCESS) {
2267 		/*
2268 		 * Got the list; scan for a matching subsystem vendor/device
2269 		 */
2270 		subid = (cidp->subven << 16) | cidp->subdev;
2271 		while (i--)
2272 			if (ids[i] == subid)
2273 				sys_ok = B_TRUE;
2274 		ddi_prop_free(ids);
2275 	}
2276 
2277 	/*
2278 	 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2279 	 *
2280 	 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2281 	 * the Subsystem Vendor ID, so it defaults to Broadcom.  Therefore,
2282 	 * we have to check specially for the exact device paths to the
2283 	 * motherboard devices on those platforms ;-(
2284 	 *
2285 	 * Note: we can't just use the "supported-subsystems" mechanism
2286 	 * above, because the entry would have to be 0x14e41647 -- which
2287 	 * would then accept *any* plugin card that *didn't* contain a
2288 	 * (valid) SEEPROM ;-(
2289 	 */
2290 	sysname = ddi_node_name(ddi_root_node());
2291 	devname = ddi_pathname(bgep->devinfo, buf);
2292 	ASSERT(strlen(devname) > 0);
2293 	if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0)	/* Taco */
2294 		if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2295 			sys_ok = B_TRUE;
2296 	if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0)	/* ENWS */
2297 		if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2298 			sys_ok = B_TRUE;
2299 
2300 	/*
2301 	 * Now check what we've discovered: is this truly a supported
2302 	 * chip on (the motherboard of) a supported platform?
2303 	 *
2304 	 * Possible problems here:
2305 	 * 1)	it's a completely unheard-of chip (e.g. 5761)
2306 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2307 	 * 3)	it's a chip we would support if it were on the motherboard
2308 	 *	of a Sun platform, but this one isn't ;-(
2309 	 */
2310 	if (cidp->chip_label == 0)
2311 		bge_problem(bgep,
2312 		    "Device 'pci%04x,%04x' not recognized (%d?)",
2313 		    cidp->vendor, cidp->device, cidp->device);
2314 	else if (!dev_ok)
2315 		bge_problem(bgep,
2316 		    "Device 'pci%04x,%04x' (%d) revision %d not supported",
2317 		    cidp->vendor, cidp->device, cidp->chip_label,
2318 		    cidp->revision);
2319 #if	BGE_DEBUGGING
2320 	else if (!sys_ok)
2321 		bge_problem(bgep,
2322 		    "%d-based subsystem 'pci%04x,%04x' not validated",
2323 		    cidp->chip_label, cidp->subven, cidp->subdev);
2324 #endif
2325 	else
2326 		cidp->flags |= CHIP_FLAG_SUPPORTED;
2327 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2328 		return (EIO);
2329 	return (0);
2330 }
2331 
2332 void
2333 bge_chip_msi_trig(bge_t *bgep)
2334 {
2335 	uint32_t	regval;
2336 
2337 	regval = bgep->param_msi_cnt<<4;
2338 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2339 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2340 }
2341 
2342 /*
2343  * Various registers that control the chip's internal engines (state
2344  * machines) have a <reset> and <enable> bits (fortunately, in the
2345  * same place in each such register :-).
2346  *
2347  * To reset the state machine, the <reset> bit must be written with 1;
2348  * it will then read back as 1 while the reset is in progress, but
2349  * self-clear to 0 when the reset completes.
2350  *
2351  * To enable a state machine, one must set the <enable> bit, which
2352  * will continue to read back as 0 until the state machine is running.
2353  *
2354  * To disable a state machine, the <enable> bit must be cleared, but
2355  * it will continue to read back as 1 until the state machine actually
2356  * stops.
2357  *
2358  * This routine implements polling for completion of a reset, enable
2359  * or disable operation, returning B_TRUE on success (bit reached the
2360  * required state) or B_FALSE on timeout (200*100us == 20ms).
2361  */
2362 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2363 					uint32_t mask, uint32_t val);
2364 #pragma	no_inline(bge_chip_poll_engine)
2365 
2366 static boolean_t
2367 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2368 	uint32_t mask, uint32_t val)
2369 {
2370 	uint32_t regval;
2371 	uint32_t n;
2372 
2373 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2374 	    (void *)bgep, regno, mask, val));
2375 
2376 	for (n = 200; n; --n) {
2377 		regval = bge_reg_get32(bgep, regno);
2378 		if ((regval & mask) == val)
2379 			return (B_TRUE);
2380 		drv_usecwait(100);
2381 	}
2382 
2383 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2384 	return (B_FALSE);
2385 }
2386 
2387 /*
2388  * Various registers that control the chip's internal engines (state
2389  * machines) have a <reset> bit (fortunately, in the same place in
2390  * each such register :-).  To reset the state machine, this bit must
2391  * be written with 1; it will then read back as 1 while the reset is
2392  * in progress, but self-clear to 0 when the reset completes.
2393  *
2394  * This code sets the bit, then polls for it to read back as zero.
2395  * The return value is B_TRUE on success (reset bit cleared itself),
2396  * or B_FALSE if the state machine didn't recover :(
2397  *
2398  * NOTE: the Core reset is similar to other resets, except that we
2399  * can't poll for completion, since the Core reset disables memory
2400  * access!  So we just have to assume that it will all complete in
2401  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
2402  */
2403 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2404 #pragma	no_inline(bge_chip_reset_engine)
2405 
2406 static boolean_t
2407 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2408 {
2409 	uint32_t regval;
2410 	uint32_t val32;
2411 
2412 	regval = bge_reg_get32(bgep, regno);
2413 
2414 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2415 	    (void *)bgep, regno));
2416 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2417 	    regno, regval));
2418 
2419 	regval |= STATE_MACHINE_RESET_BIT;
2420 
2421 	switch (regno) {
2422 	case MISC_CONFIG_REG:
2423 		/*
2424 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2425 		 * resetting PCIE block and bringing PCIE link down, bit 29
2426 		 * in the register needs to be set first, and then set it again
2427 		 * while the reset bit is written.
2428 		 * See:P500 of 57xx-PG102-RDS.pdf.
2429 		 */
2430 		if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2431 		    DEVICE_5721_SERIES_CHIPSETS(bgep)||
2432 		    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2433 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2434 			if (bgep->chipid.pci_type == BGE_PCI_E) {
2435 				if (bgep->chipid.asic_rev ==
2436 				    MHCR_CHIP_REV_5751_A0 ||
2437 				    bgep->chipid.asic_rev ==
2438 				    MHCR_CHIP_REV_5721_A0 ||
2439 				    bgep->chipid.asic_rev ==
2440 				    MHCR_CHIP_REV_5755_A0) {
2441 					val32 = bge_reg_get32(bgep,
2442 					    PHY_TEST_CTRL_REG);
2443 					if (val32 == (PHY_PCIE_SCRAM_MODE |
2444 					    PHY_PCIE_LTASS_MODE))
2445 						bge_reg_put32(bgep,
2446 						    PHY_TEST_CTRL_REG,
2447 						    PHY_PCIE_SCRAM_MODE);
2448 					val32 = pci_config_get32
2449 					    (bgep->cfg_handle,
2450 					    PCI_CONF_BGE_CLKCTL);
2451 					val32 |= CLKCTL_PCIE_A0_FIX;
2452 					pci_config_put32(bgep->cfg_handle,
2453 					    PCI_CONF_BGE_CLKCTL, val32);
2454 				}
2455 				bge_reg_set32(bgep, regno,
2456 				    MISC_CONFIG_GRC_RESET_DISABLE);
2457 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2458 			}
2459 		}
2460 
2461 		/*
2462 		 * Special case - causes Core reset
2463 		 *
2464 		 * On SPARC v9 we want to ensure that we don't start
2465 		 * timing until the I/O access has actually reached
2466 		 * the chip, otherwise we might make the next access
2467 		 * too early.  And we can't just force the write out
2468 		 * by following it with a read (even to config space)
2469 		 * because that would cause the fault we're trying
2470 		 * to avoid.  Hence the need for membar_sync() here.
2471 		 */
2472 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2473 #ifdef	__sparcv9
2474 		membar_sync();
2475 #endif	/* __sparcv9 */
2476 		/*
2477 		 * On some platforms,system need about 300us for
2478 		 * link setup.
2479 		 */
2480 		drv_usecwait(300);
2481 
2482 		if (bgep->chipid.pci_type == BGE_PCI_E) {
2483 			/* PCI-E device need more reset time */
2484 			drv_usecwait(120000);
2485 
2486 			/* Set PCIE max payload size and clear error status. */
2487 			if ((bgep->chipid.chip_label == 5721) ||
2488 			    (bgep->chipid.chip_label == 5751) ||
2489 			    (bgep->chipid.chip_label == 5752) ||
2490 			    (bgep->chipid.chip_label == 5789)) {
2491 				pci_config_put16(bgep->cfg_handle,
2492 				    PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2493 				pci_config_put16(bgep->cfg_handle,
2494 				    PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2495 			}
2496 		}
2497 
2498 		BGE_PCICHK(bgep);
2499 		return (B_TRUE);
2500 
2501 	default:
2502 		bge_reg_put32(bgep, regno, regval);
2503 		return (bge_chip_poll_engine(bgep, regno,
2504 		    STATE_MACHINE_RESET_BIT, 0));
2505 	}
2506 }
2507 
2508 /*
2509  * Various registers that control the chip's internal engines (state
2510  * machines) have an <enable> bit (fortunately, in the same place in
2511  * each such register :-).  To stop the state machine, this bit must
2512  * be written with 0, then polled to see when the state machine has
2513  * actually stopped.
2514  *
2515  * The return value is B_TRUE on success (enable bit cleared), or
2516  * B_FALSE if the state machine didn't stop :(
2517  */
2518 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2519 						uint32_t morebits);
2520 #pragma	no_inline(bge_chip_disable_engine)
2521 
2522 static boolean_t
2523 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2524 {
2525 	uint32_t regval;
2526 
2527 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2528 	    (void *)bgep, regno, morebits));
2529 
2530 	switch (regno) {
2531 	case FTQ_RESET_REG:
2532 		/*
2533 		 * For Schumacher's bugfix CR6490108
2534 		 */
2535 #ifdef BGE_IPMI_ASF
2536 #ifdef BGE_NETCONSOLE
2537 		if (bgep->asf_enabled)
2538 			return (B_TRUE);
2539 #endif
2540 #endif
2541 		/*
2542 		 * Not quite like the others; it doesn't
2543 		 * have an <enable> bit, but instead we
2544 		 * have to set and then clear all the bits
2545 		 */
2546 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2547 		drv_usecwait(100);
2548 		bge_reg_put32(bgep, regno, 0);
2549 		return (B_TRUE);
2550 
2551 	default:
2552 		regval = bge_reg_get32(bgep, regno);
2553 		regval &= ~STATE_MACHINE_ENABLE_BIT;
2554 		regval &= ~morebits;
2555 		bge_reg_put32(bgep, regno, regval);
2556 		return (bge_chip_poll_engine(bgep, regno,
2557 		    STATE_MACHINE_ENABLE_BIT, 0));
2558 	}
2559 }
2560 
2561 /*
2562  * Various registers that control the chip's internal engines (state
2563  * machines) have an <enable> bit (fortunately, in the same place in
2564  * each such register :-).  To start the state machine, this bit must
2565  * be written with 1, then polled to see when the state machine has
2566  * actually started.
2567  *
2568  * The return value is B_TRUE on success (enable bit set), or
2569  * B_FALSE if the state machine didn't start :(
2570  */
2571 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2572 					uint32_t morebits);
2573 #pragma	no_inline(bge_chip_enable_engine)
2574 
2575 static boolean_t
2576 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2577 {
2578 	uint32_t regval;
2579 
2580 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2581 	    (void *)bgep, regno, morebits));
2582 
2583 	switch (regno) {
2584 	case FTQ_RESET_REG:
2585 #ifdef BGE_IPMI_ASF
2586 #ifdef BGE_NETCONSOLE
2587 		if (bgep->asf_enabled)
2588 			return (B_TRUE);
2589 #endif
2590 #endif
2591 		/*
2592 		 * Not quite like the others; it doesn't
2593 		 * have an <enable> bit, but instead we
2594 		 * have to set and then clear all the bits
2595 		 */
2596 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2597 		drv_usecwait(100);
2598 		bge_reg_put32(bgep, regno, 0);
2599 		return (B_TRUE);
2600 
2601 	default:
2602 		regval = bge_reg_get32(bgep, regno);
2603 		regval |= STATE_MACHINE_ENABLE_BIT;
2604 		regval |= morebits;
2605 		bge_reg_put32(bgep, regno, regval);
2606 		return (bge_chip_poll_engine(bgep, regno,
2607 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2608 	}
2609 }
2610 
2611 /*
2612  * Reprogram the Ethernet, Transmit, and Receive MAC
2613  * modes to match the param_* variables
2614  */
2615 void bge_sync_mac_modes(bge_t *bgep);
2616 #pragma	no_inline(bge_sync_mac_modes)
2617 
2618 void
2619 bge_sync_mac_modes(bge_t *bgep)
2620 {
2621 	uint32_t macmode;
2622 	uint32_t regval;
2623 
2624 	ASSERT(mutex_owned(bgep->genlock));
2625 
2626 	/*
2627 	 * Reprogram the Ethernet MAC mode ...
2628 	 */
2629 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2630 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2631 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2632 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2633 			macmode |= ETHERNET_MODE_LINK_POLARITY;
2634 		else
2635 			macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2636 	else
2637 		macmode |= ETHERNET_MODE_LINK_POLARITY;
2638 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2639 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2640 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
2641 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2642 			macmode |= ETHERNET_MODE_PORTMODE_GMII;
2643 		else
2644 			macmode |= ETHERNET_MODE_PORTMODE_TBI;
2645 	} else if (bgep->param_link_speed == 10 ||
2646 	    bgep->param_link_speed == 100)
2647 		macmode |= ETHERNET_MODE_PORTMODE_MII;
2648 	else
2649 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
2650 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2651 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
2652 	else
2653 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2654 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2655 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2656 	else
2657 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2658 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2659 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2660 	    (void *)bgep, regval, macmode));
2661 
2662 	/*
2663 	 * ... the Transmit MAC mode ...
2664 	 */
2665 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2666 	if (bgep->param_link_tx_pause)
2667 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2668 	else
2669 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2670 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2671 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2672 	    (void *)bgep, regval, macmode));
2673 
2674 	/*
2675 	 * ... and the Receive MAC mode
2676 	 */
2677 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2678 	if (bgep->param_link_rx_pause)
2679 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
2680 	else
2681 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2682 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2683 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2684 	    (void *)bgep, regval, macmode));
2685 }
2686 
2687 /*
2688  * bge_chip_sync() -- program the chip with the unicast MAC address,
2689  * the multicast hash table, the required level of promiscuity, and
2690  * the current loopback mode ...
2691  */
2692 #ifdef BGE_IPMI_ASF
2693 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2694 #else
2695 int bge_chip_sync(bge_t *bgep);
2696 #endif
2697 #pragma	no_inline(bge_chip_sync)
2698 
2699 int
2700 #ifdef BGE_IPMI_ASF
2701 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2702 #else
2703 bge_chip_sync(bge_t *bgep)
2704 #endif
2705 {
2706 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2707 	boolean_t promisc;
2708 	uint64_t macaddr;
2709 	uint32_t fill;
2710 	int i, j;
2711 	int retval = DDI_SUCCESS;
2712 
2713 	BGE_TRACE(("bge_chip_sync($%p)",
2714 	    (void *)bgep));
2715 
2716 	ASSERT(mutex_owned(bgep->genlock));
2717 
2718 	promisc = B_FALSE;
2719 	fill = ~(uint32_t)0;
2720 
2721 	if (bgep->promisc)
2722 		promisc = B_TRUE;
2723 	else
2724 		fill = (uint32_t)0;
2725 
2726 	/*
2727 	 * If the TX/RX MAC engines are already running, we should stop
2728 	 * them (and reset the RX engine) before changing the parameters.
2729 	 * If they're not running, this will have no effect ...
2730 	 *
2731 	 * NOTE: this is currently disabled by default because stopping
2732 	 * and restarting the Tx engine may cause an outgoing packet in
2733 	 * transit to be truncated.  Also, stopping and restarting the
2734 	 * Rx engine seems to not work correctly on the 5705.  Testing
2735 	 * has not (yet!) revealed any problems with NOT stopping and
2736 	 * restarting these engines (and Broadcom say their drivers don't
2737 	 * do this), but if it is found to cause problems, this variable
2738 	 * can be patched to re-enable the old behaviour ...
2739 	 */
2740 	if (bge_stop_start_on_sync) {
2741 #ifdef BGE_IPMI_ASF
2742 		if (!bgep->asf_enabled) {
2743 			if (!bge_chip_disable_engine(bgep,
2744 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2745 				retval = DDI_FAILURE;
2746 		} else {
2747 			if (!bge_chip_disable_engine(bgep,
2748 			    RECEIVE_MAC_MODE_REG, 0))
2749 				retval = DDI_FAILURE;
2750 		}
2751 #else
2752 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
2753 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2754 			retval = DDI_FAILURE;
2755 #endif
2756 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2757 			retval = DDI_FAILURE;
2758 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
2759 			retval = DDI_FAILURE;
2760 	}
2761 
2762 	/*
2763 	 * Reprogram the hashed multicast address table ...
2764 	 */
2765 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2766 		bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
2767 
2768 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2769 		bge_reg_put32(bgep, MAC_HASH_REG(i),
2770 			bgep->mcast_hash[i] | fill);
2771 
2772 #ifdef BGE_IPMI_ASF
2773 	if (!bgep->asf_enabled || !asf_keeplive) {
2774 #endif
2775 		/*
2776 		 * Transform the MAC address(es) from host to chip format, then
2777 		 * reprogram the transmit random backoff seed and the unicast
2778 		 * MAC address(es) ...
2779 		 */
2780 		for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
2781 			for (i = 0, fill = 0, macaddr = 0ull;
2782 			    i < ETHERADDRL; ++i) {
2783 				macaddr <<= 8;
2784 				macaddr |= bgep->curr_addr[j].addr[i];
2785 				fill += bgep->curr_addr[j].addr[i];
2786 			}
2787 			bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
2788 			bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
2789 		}
2790 
2791 		BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx",
2792 			(void *)bgep, macaddr));
2793 #ifdef BGE_IPMI_ASF
2794 	}
2795 #endif
2796 
2797 	/*
2798 	 * Set or clear the PROMISCUOUS mode bit
2799 	 */
2800 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
2801 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
2802 
2803 	/*
2804 	 * Sync the rest of the MAC modes too ...
2805 	 */
2806 	bge_sync_mac_modes(bgep);
2807 
2808 	/*
2809 	 * Restart RX/TX MAC engines if required ...
2810 	 */
2811 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
2812 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2813 			retval = DDI_FAILURE;
2814 #ifdef BGE_IPMI_ASF
2815 		if (!bgep->asf_enabled) {
2816 			if (!bge_chip_enable_engine(bgep,
2817 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2818 				retval = DDI_FAILURE;
2819 		} else {
2820 			if (!bge_chip_enable_engine(bgep,
2821 			    RECEIVE_MAC_MODE_REG, 0))
2822 				retval = DDI_FAILURE;
2823 		}
2824 #else
2825 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
2826 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2827 			retval = DDI_FAILURE;
2828 #endif
2829 	}
2830 	return (retval);
2831 }
2832 
2833 /*
2834  * This array defines the sequence of state machine control registers
2835  * in which the <enable> bit must be cleared to bring the chip to a
2836  * clean stop.  Taken from Broadcom document 570X-PG102-R, p116.
2837  */
2838 static bge_regno_t shutdown_engine_regs[] = {
2839 	RECEIVE_MAC_MODE_REG,
2840 	RCV_BD_INITIATOR_MODE_REG,
2841 	RCV_LIST_PLACEMENT_MODE_REG,
2842 	RCV_LIST_SELECTOR_MODE_REG,		/* BCM5704 series only	*/
2843 	RCV_DATA_BD_INITIATOR_MODE_REG,
2844 	RCV_DATA_COMPLETION_MODE_REG,
2845 	RCV_BD_COMPLETION_MODE_REG,
2846 
2847 	SEND_BD_SELECTOR_MODE_REG,
2848 	SEND_BD_INITIATOR_MODE_REG,
2849 	SEND_DATA_INITIATOR_MODE_REG,
2850 	READ_DMA_MODE_REG,
2851 	SEND_DATA_COMPLETION_MODE_REG,
2852 	DMA_COMPLETION_MODE_REG,		/* BCM5704 series only	*/
2853 	SEND_BD_COMPLETION_MODE_REG,
2854 	TRANSMIT_MAC_MODE_REG,
2855 
2856 	HOST_COALESCE_MODE_REG,
2857 	WRITE_DMA_MODE_REG,
2858 	MBUF_CLUSTER_FREE_MODE_REG,		/* BCM5704 series only	*/
2859 	FTQ_RESET_REG,		/* special - see code	*/
2860 	BUFFER_MANAGER_MODE_REG,		/* BCM5704 series only	*/
2861 	MEMORY_ARBITER_MODE_REG,		/* BCM5704 series only	*/
2862 	BGE_REGNO_NONE		/* terminator		*/
2863 };
2864 
2865 /*
2866  * bge_chip_stop() -- stop all chip processing
2867  *
2868  * If the <fault> parameter is B_TRUE, we're stopping the chip because
2869  * we've detected a problem internally; otherwise, this is a normal
2870  * (clean) stop (at user request i.e. the last STREAM has been closed).
2871  */
2872 void bge_chip_stop(bge_t *bgep, boolean_t fault);
2873 #pragma	no_inline(bge_chip_stop)
2874 
2875 void
2876 bge_chip_stop(bge_t *bgep, boolean_t fault)
2877 {
2878 	bge_regno_t regno;
2879 	bge_regno_t *rbp;
2880 	boolean_t ok;
2881 
2882 	BGE_TRACE(("bge_chip_stop($%p)",
2883 	    (void *)bgep));
2884 
2885 	ASSERT(mutex_owned(bgep->genlock));
2886 
2887 	rbp = shutdown_engine_regs;
2888 	/*
2889 	 * When driver try to shutdown the BCM5705/5788/5721/5751/
2890 	 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
2891 	 * -ory arbiter should not be disabled.
2892 	 */
2893 	for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
2894 			if (DEVICE_5704_SERIES_CHIPSETS(bgep))
2895 				ok &= bge_chip_disable_engine(bgep, regno, 0);
2896 			else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
2897 			    (regno != DMA_COMPLETION_MODE_REG) &&
2898 			    (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
2899 			    (regno != BUFFER_MANAGER_MODE_REG) &&
2900 			    (regno != MEMORY_ARBITER_MODE_REG))
2901 				ok &= bge_chip_disable_engine(bgep,
2902 				    regno, 0);
2903 	}
2904 
2905 	if (!ok && !fault)
2906 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
2907 
2908 	/*
2909 	 * Finally, disable (all) MAC events & clear the MAC status
2910 	 */
2911 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
2912 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
2913 
2914 	/*
2915 	 * if we're stopping the chip because of a detected fault then do
2916 	 * appropriate actions
2917 	 */
2918 	if (fault) {
2919 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
2920 			bgep->bge_chip_state = BGE_CHIP_FAULT;
2921 			if (!bgep->manual_reset)
2922 				ddi_fm_service_impact(bgep->devinfo,
2923 				    DDI_SERVICE_LOST);
2924 			if (bgep->bge_dma_error) {
2925 				/*
2926 				 * need to free buffers in case the fault was
2927 				 * due to a memory error in a buffer - got to
2928 				 * do a fair bit of tidying first
2929 				 */
2930 				if (bgep->progress & PROGRESS_KSTATS) {
2931 					bge_fini_kstats(bgep);
2932 					bgep->progress &= ~PROGRESS_KSTATS;
2933 				}
2934 				if (bgep->progress & PROGRESS_INTR) {
2935 					bge_intr_disable(bgep);
2936 					rw_enter(bgep->errlock, RW_WRITER);
2937 					bge_fini_rings(bgep);
2938 					rw_exit(bgep->errlock);
2939 					bgep->progress &= ~PROGRESS_INTR;
2940 				}
2941 				if (bgep->progress & PROGRESS_BUFS) {
2942 					bge_free_bufs(bgep);
2943 					bgep->progress &= ~PROGRESS_BUFS;
2944 				}
2945 				bgep->bge_dma_error = B_FALSE;
2946 			}
2947 		}
2948 	} else
2949 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
2950 }
2951 
2952 /*
2953  * Poll for completion of chip's ROM firmware; also, at least on the
2954  * first time through, find and return the hardware MAC address, if any.
2955  */
2956 static uint64_t bge_poll_firmware(bge_t *bgep);
2957 #pragma	no_inline(bge_poll_firmware)
2958 
2959 static uint64_t
2960 bge_poll_firmware(bge_t *bgep)
2961 {
2962 	uint64_t magic;
2963 	uint64_t mac;
2964 	uint32_t gen;
2965 	uint32_t i;
2966 
2967 	/*
2968 	 * Step 19: poll for firmware completion (GENCOMM port set
2969 	 * to the ones complement of T3_MAGIC_NUMBER).
2970 	 *
2971 	 * While we're at it, we also read the MAC address register;
2972 	 * at some stage the firmware will load this with the
2973 	 * factory-set value.
2974 	 *
2975 	 * When both the magic number and the MAC address are set,
2976 	 * we're done; but we impose a time limit of one second
2977 	 * (1000*1000us) in case the firmware fails in some fashion
2978 	 * or the SEEPROM that provides that MAC address isn't fitted.
2979 	 *
2980 	 * After the first time through (chip state != INITIAL), we
2981 	 * don't need the MAC address to be set (we've already got it
2982 	 * or not, from the first time), so we don't wait for it, but
2983 	 * we still have to wait for the T3_MAGIC_NUMBER.
2984 	 *
2985 	 * Note: the magic number is only a 32-bit quantity, but the NIC
2986 	 * memory is 64-bit (and big-endian) internally.  Addressing the
2987 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
2988 	 * it work correctly on both big- and little-endian hosts.
2989 	 */
2990 	for (i = 0; i < 1000; ++i) {
2991 		drv_usecwait(1000);
2992 		gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
2993 		if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep))
2994 			drv_usecwait(100000);
2995 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
2996 #ifdef BGE_IPMI_ASF
2997 		if (!bgep->asf_enabled) {
2998 #endif
2999 			if (gen != ~T3_MAGIC_NUMBER)
3000 				continue;
3001 #ifdef BGE_IPMI_ASF
3002 		}
3003 #endif
3004 		if (mac != 0ULL)
3005 			break;
3006 		if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3007 			break;
3008 	}
3009 
3010 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3011 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3012 	    (void *)bgep, gen, i));
3013 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3014 	    mac, magic));
3015 
3016 	return (mac);
3017 }
3018 
3019 /*
3020  * Maximum times of trying to get the NVRAM access lock
3021  * by calling bge_nvmem_acquire()
3022  */
3023 #define	MAX_TRY_NVMEM_ACQUIRE	10000
3024 
3025 #ifdef BGE_IPMI_ASF
3026 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3027 #else
3028 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3029 #endif
3030 #pragma	no_inline(bge_chip_reset)
3031 
3032 int
3033 #ifdef BGE_IPMI_ASF
3034 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3035 #else
3036 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3037 #endif
3038 {
3039 	chip_id_t chipid;
3040 	uint64_t mac;
3041 	uint64_t magic;
3042 	uint32_t modeflags;
3043 	uint32_t mhcr;
3044 	uint32_t sx0;
3045 	uint32_t i, tries;
3046 #ifdef BGE_IPMI_ASF
3047 	uint32_t mailbox;
3048 #endif
3049 	int retval = DDI_SUCCESS;
3050 
3051 	BGE_TRACE(("bge_chip_reset($%p, %d)",
3052 		(void *)bgep, enable_dma));
3053 
3054 	ASSERT(mutex_owned(bgep->genlock));
3055 
3056 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3057 		(void *)bgep, enable_dma, bgep->bge_chip_state));
3058 
3059 	/*
3060 	 * Do we need to stop the chip cleanly before resetting?
3061 	 */
3062 	switch (bgep->bge_chip_state) {
3063 	default:
3064 		_NOTE(NOTREACHED)
3065 		return (DDI_FAILURE);
3066 
3067 	case BGE_CHIP_INITIAL:
3068 	case BGE_CHIP_STOPPED:
3069 	case BGE_CHIP_RESET:
3070 		break;
3071 
3072 	case BGE_CHIP_RUNNING:
3073 	case BGE_CHIP_ERROR:
3074 	case BGE_CHIP_FAULT:
3075 		bge_chip_stop(bgep, B_FALSE);
3076 		break;
3077 	}
3078 
3079 #ifdef BGE_IPMI_ASF
3080 	if (bgep->asf_enabled) {
3081 #ifdef __sparc
3082 		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3083 			MHCR_ENABLE_TAGGED_STATUS_MODE |
3084 			MHCR_MASK_INTERRUPT_MODE |
3085 			MHCR_MASK_PCI_INT_OUTPUT |
3086 			MHCR_CLEAR_INTERRUPT_INTA |
3087 			MHCR_ENABLE_ENDIAN_WORD_SWAP |
3088 			MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3089 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3090 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3091 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3092 			MEMORY_ARBITER_ENABLE);
3093 #endif
3094 		if (asf_mode == ASF_MODE_INIT) {
3095 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3096 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
3097 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3098 		}
3099 	}
3100 #endif
3101 	/*
3102 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3103 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3104 	 *
3105 	 * Before reset Core clock,it is
3106 	 * also required to initialize the Memory Arbiter as specified in step9
3107 	 * and Misc Host Control Register as specified in step-13
3108 	 * Step 4-5: reset Core clock & wait for completion
3109 	 * Steps 6-8: are done by bge_chip_cfg_init()
3110 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3111 	 */
3112 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3113 		retval = DDI_FAILURE;
3114 
3115 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3116 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3117 	    MHCR_MASK_INTERRUPT_MODE |
3118 	    MHCR_MASK_PCI_INT_OUTPUT |
3119 	    MHCR_CLEAR_INTERRUPT_INTA;
3120 #ifdef  _BIG_ENDIAN
3121 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3122 #endif  /* _BIG_ENDIAN */
3123 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3124 #ifdef BGE_IPMI_ASF
3125 	if (bgep->asf_enabled)
3126 		bgep->asf_wordswapped = B_FALSE;
3127 #endif
3128 	/*
3129 	 * NVRAM Corruption Workaround
3130 	 */
3131 	for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3132 		if (bge_nvmem_acquire(bgep) != EAGAIN)
3133 			break;
3134 	if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3135 		BGE_DEBUG(("%s: fail to acquire nvram lock",
3136 			bgep->ifname));
3137 
3138 #ifdef BGE_IPMI_ASF
3139 	if (!bgep->asf_enabled) {
3140 #endif
3141 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3142 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3143 #ifdef BGE_IPMI_ASF
3144 	}
3145 #endif
3146 
3147 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3148 		retval = DDI_FAILURE;
3149 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
3150 
3151 	/*
3152 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
3153 	 * a bit set to avoid a fifo overflow/underflow bug.
3154 	 */
3155 	if ((bgep->chipid.chip_label == 5721) ||
3156 		(bgep->chipid.chip_label == 5751) ||
3157 		(bgep->chipid.chip_label == 5752) ||
3158 		(bgep->chipid.chip_label == 5755) ||
3159 		(bgep->chipid.chip_label == 5789))
3160 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3161 
3162 
3163 	/*
3164 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3165 	 * not be changed.
3166 	 */
3167 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3168 		retval = DDI_FAILURE;
3169 
3170 	/*
3171 	 * Steps 10-11: configure PIO endianness options and
3172 	 * enable indirect register access -- already done
3173 	 * Steps 12-13: enable writing to the PCI state & clock
3174 	 * control registers -- not required; we aren't going to
3175 	 * use those features.
3176 	 * Steps 14-15: Configure DMA endianness options.  See
3177 	 * the comments on the setting of the MHCR above.
3178 	 */
3179 #ifdef	_BIG_ENDIAN
3180 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3181 		    MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3182 #else
3183 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3184 #endif	/* _BIG_ENDIAN */
3185 #ifdef BGE_IPMI_ASF
3186 	if (bgep->asf_enabled)
3187 		modeflags |= MODE_HOST_STACK_UP;
3188 #endif
3189 	bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3190 
3191 #ifdef BGE_IPMI_ASF
3192 	if (bgep->asf_enabled) {
3193 #ifdef __sparc
3194 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3195 			MEMORY_ARBITER_ENABLE |
3196 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3197 #endif
3198 
3199 #ifdef  BGE_NETCONSOLE
3200 		if (!bgep->asf_newhandshake) {
3201 			if ((asf_mode == ASF_MODE_INIT) ||
3202 			(asf_mode == ASF_MODE_POST_INIT)) {
3203 				bge_asf_post_reset_old_mode(bgep,
3204 					BGE_INIT_RESET);
3205 			} else {
3206 				bge_asf_post_reset_old_mode(bgep,
3207 					BGE_SHUTDOWN_RESET);
3208 			}
3209 		}
3210 #endif
3211 
3212 		/* Wait for NVRAM init */
3213 		i = 0;
3214 		drv_usecwait(5000);
3215 		mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3216 
3217 		while ((mailbox != (uint32_t)
3218 			~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3219 			(i < 10000)) {
3220 			drv_usecwait(100);
3221 			mailbox = bge_nic_get32(bgep,
3222 				BGE_FIRMWARE_MAILBOX);
3223 			i++;
3224 		}
3225 
3226 #ifndef BGE_NETCONSOLE
3227 		if (!bgep->asf_newhandshake) {
3228 			if ((asf_mode == ASF_MODE_INIT) ||
3229 				(asf_mode == ASF_MODE_POST_INIT)) {
3230 
3231 				bge_asf_post_reset_old_mode(bgep,
3232 					BGE_INIT_RESET);
3233 			} else {
3234 				bge_asf_post_reset_old_mode(bgep,
3235 					BGE_SHUTDOWN_RESET);
3236 			}
3237 		}
3238 #endif
3239 	}
3240 #endif
3241 	/*
3242 	 * Steps 16-17: poll for firmware completion
3243 	 */
3244 	mac = bge_poll_firmware(bgep);
3245 
3246 	/*
3247 	 * Step 18: enable external memory -- doesn't apply.
3248 	 *
3249 	 * However we take the opportunity to set the MLCR anyway, as
3250 	 * this register also controls the SEEPROM auto-access method
3251 	 * which we may want to use later ...
3252 	 *
3253 	 * The proper value here depends on the way the chip is wired
3254 	 * into the circuit board, as this register *also* controls which
3255 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
3256 	 * values driven onto those pins!
3257 	 *
3258 	 * See also step 74 in the PRM ...
3259 	 */
3260 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3261 	    bgep->chipid.bge_mlcr_default);
3262 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3263 
3264 	/*
3265 	 * Step 20: clear the Ethernet MAC mode register
3266 	 */
3267 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3268 
3269 	/*
3270 	 * Step 21: restore cache-line-size, latency timer, and
3271 	 * subsystem ID registers to their original values (not
3272 	 * those read into the local structure <chipid>, 'cos
3273 	 * that was after they were cleared by the RESET).
3274 	 *
3275 	 * Note: the Subsystem Vendor/Device ID registers are not
3276 	 * directly writable in config space, so we use the shadow
3277 	 * copy in "Page Zero" of register space to restore them
3278 	 * both in one go ...
3279 	 */
3280 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3281 		bgep->chipid.clsize);
3282 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3283 		bgep->chipid.latency);
3284 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3285 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
3286 
3287 	/*
3288 	 * The SEND INDEX registers should be reset to zero by the
3289 	 * global chip reset; if they're not, there'll be trouble
3290 	 * later on.
3291 	 */
3292 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3293 	if (sx0 != 0) {
3294 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3295 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3296 		retval = DDI_FAILURE;
3297 	}
3298 
3299 	/* Enable MSI code */
3300 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3301 		bge_reg_set32(bgep, MSI_MODE_REG,
3302 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3303 
3304 	/*
3305 	 * On the first time through, save the factory-set MAC address
3306 	 * (if any).  If bge_poll_firmware() above didn't return one
3307 	 * (from a chip register) consider looking in the attached NV
3308 	 * memory device, if any.  Once we have it, we save it in both
3309 	 * register-image (64-bit) and byte-array forms.  All-zero and
3310 	 * all-one addresses are not valid, and we refuse to stash those.
3311 	 */
3312 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3313 		if (mac == 0ULL)
3314 			mac = bge_get_nvmac(bgep);
3315 		if (mac != 0ULL && mac != ~0ULL) {
3316 			bgep->chipid.hw_mac_addr = mac;
3317 			for (i = ETHERADDRL; i-- != 0; ) {
3318 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3319 				mac >>= 8;
3320 			}
3321 			bgep->chipid.vendor_addr.set = B_TRUE;
3322 		}
3323 	}
3324 
3325 #ifdef BGE_IPMI_ASF
3326 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
3327 		if (asf_mode != ASF_MODE_NONE) {
3328 			if ((asf_mode == ASF_MODE_INIT) ||
3329 				(asf_mode == ASF_MODE_POST_INIT)) {
3330 
3331 				bge_asf_post_reset_new_mode(bgep,
3332 					BGE_INIT_RESET);
3333 			} else {
3334 				bge_asf_post_reset_new_mode(bgep,
3335 					BGE_SHUTDOWN_RESET);
3336 			}
3337 		}
3338 	}
3339 #endif
3340 
3341 	/*
3342 	 * Record the new state
3343 	 */
3344 	bgep->chip_resets += 1;
3345 	bgep->bge_chip_state = BGE_CHIP_RESET;
3346 	return (retval);
3347 }
3348 
3349 /*
3350  * bge_chip_start() -- start the chip transmitting and/or receiving,
3351  * including enabling interrupts
3352  */
3353 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3354 #pragma	no_inline(bge_chip_start)
3355 
3356 int
3357 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3358 {
3359 	uint32_t coalmode;
3360 	uint32_t ledctl;
3361 	uint32_t mtu;
3362 	uint32_t maxring;
3363 	uint32_t stats_mask;
3364 	uint32_t dma_wrprio;
3365 	uint64_t ring;
3366 	int retval = DDI_SUCCESS;
3367 
3368 	BGE_TRACE(("bge_chip_start($%p)",
3369 	    (void *)bgep));
3370 
3371 	ASSERT(mutex_owned(bgep->genlock));
3372 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3373 
3374 	/*
3375 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3376 	 * The document specifies 95 separate steps to fully
3377 	 * initialise the chip!!!!
3378 	 *
3379 	 * The reset code above has already got us as far as step
3380 	 * 21, so we continue with ...
3381 	 *
3382 	 * Step 22: clear the MAC statistics block
3383 	 * (0x0300-0x0aff in NIC-local memory)
3384 	 */
3385 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3386 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3387 		    NIC_MEM_STATISTICS_SIZE);
3388 
3389 	/*
3390 	 * Step 23: clear the status block (in host memory)
3391 	 */
3392 	DMA_ZERO(bgep->status_block);
3393 
3394 	/*
3395 	 * Step 24: set DMA read/write control register
3396 	 */
3397 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3398 	    bgep->chipid.bge_dma_rwctrl);
3399 
3400 	/*
3401 	 * Step 25: Configure DMA endianness -- already done (16/17)
3402 	 * Step 26: Configure Host-Based Send Rings
3403 	 * Step 27: Indicate Host Stack Up
3404 	 */
3405 	bge_reg_set32(bgep, MODE_CONTROL_REG,
3406 	    MODE_HOST_SEND_BDS |
3407 	    MODE_HOST_STACK_UP);
3408 
3409 	/*
3410 	 * Step 28: Configure checksum options:
3411 	 *	Solaris supports the hardware default checksum options.
3412 	 *
3413 	 *	Workaround for Incorrect pseudo-header checksum calculation.
3414 	 */
3415 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3416 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3417 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
3418 
3419 	/*
3420 	 * Step 29: configure Timer Prescaler.  The value is always the
3421 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3422 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
3423 	 * for the whole chip!
3424 	 */
3425 	bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT);
3426 
3427 	/*
3428 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3429 	 *
3430 	 * If the mbuf_length is specified as 0, we just leave these at
3431 	 * their hardware defaults, rather than explicitly setting them.
3432 	 * As the Broadcom HRM,driver better not change the parameters
3433 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3434 	 */
3435 	if ((bgep->chipid.mbuf_length != 0) &&
3436 	    (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3437 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3438 			    bgep->chipid.mbuf_base);
3439 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3440 			    bgep->chipid.mbuf_length);
3441 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3442 			    DMAD_POOL_BASE_DEFAULT);
3443 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3444 			    DMAD_POOL_LENGTH_DEFAULT);
3445 	}
3446 
3447 	/*
3448 	 * Step 32: configure MAC memory pool watermarks
3449 	 */
3450 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3451 	    bgep->chipid.mbuf_lo_water_rdma);
3452 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3453 	    bgep->chipid.mbuf_lo_water_rmac);
3454 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
3455 	    bgep->chipid.mbuf_hi_water);
3456 
3457 	/*
3458 	 * Step 33: configure DMA resource watermarks
3459 	 */
3460 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3461 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3462 		    bge_dmad_lo_water);
3463 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3464 		    bge_dmad_hi_water);
3465 	}
3466 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3467 
3468 	/*
3469 	 * Steps 34-36: enable buffer manager & internal h/w queues
3470 	 */
3471 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3472 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3473 		retval = DDI_FAILURE;
3474 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3475 		retval = DDI_FAILURE;
3476 
3477 	/*
3478 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3479 	 */
3480 	bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3481 	    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3482 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3483 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3484 		    &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3485 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3486 		    &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3487 	}
3488 
3489 	/*
3490 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3491 	 */
3492 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3493 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3494 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3495 		    bge_replenish_jumbo);
3496 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3497 		    bge_replenish_mini);
3498 	}
3499 
3500 	/*
3501 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
3502 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3503 	 */
3504 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3505 		maxring = BGE_SEND_RINGS_MAX;
3506 	else
3507 		maxring = BGE_SEND_RINGS_MAX_5705;
3508 	for (ring = 0; ring < maxring; ++ring) {
3509 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3510 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3511 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3512 		    &bgep->send[ring].hw_rcb);
3513 	}
3514 
3515 	/*
3516 	 * Steps 44-45: initialise Receive Return Rings
3517 	 * (0x0200-0x02ff in NIC-local memory)
3518 	 */
3519 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3520 		maxring = BGE_RECV_RINGS_MAX;
3521 	else
3522 		maxring = BGE_RECV_RINGS_MAX_5705;
3523 	for (ring = 0; ring < maxring; ++ring)
3524 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3525 		    &bgep->recv[ring].hw_rcb);
3526 
3527 	/*
3528 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3529 	 */
3530 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3531 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3532 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3533 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3534 	}
3535 	/*
3536 	 * Step 47: configure the MAC unicast address
3537 	 * Step 48: configure the random backoff seed
3538 	 * Step 96: set up multicast filters
3539 	 */
3540 #ifdef BGE_IPMI_ASF
3541 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3542 #else
3543 	if (bge_chip_sync(bgep) == DDI_FAILURE)
3544 #endif
3545 		retval = DDI_FAILURE;
3546 
3547 	/*
3548 	 * Step 49: configure the MTU
3549 	 */
3550 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3551 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3552 
3553 	/*
3554 	 * Step 50: configure the IPG et al
3555 	 */
3556 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3557 
3558 	/*
3559 	 * Step 51: configure the default Rx Return Ring
3560 	 */
3561 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3562 
3563 	/*
3564 	 * Steps 52-54: configure Receive List Placement,
3565 	 * and enable Receive List Placement Statistics
3566 	 */
3567 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3568 	    RCV_LP_CONFIG(bgep->chipid.rx_rings));
3569 	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
3570 	case MHCR_CHIP_ASIC_REV_5700:
3571 	case MHCR_CHIP_ASIC_REV_5701:
3572 	case MHCR_CHIP_ASIC_REV_5703:
3573 	case MHCR_CHIP_ASIC_REV_5704:
3574 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3575 		break;
3576 	case MHCR_CHIP_ASIC_REV_5705:
3577 		break;
3578 	default:
3579 		stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
3580 		stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
3581 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3582 		break;
3583 	}
3584 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3585 
3586 	if (bgep->chipid.rx_rings > 1)
3587 		bge_init_recv_rule(bgep);
3588 
3589 	/*
3590 	 * Steps 55-56: enable Send Data Initiator Statistics
3591 	 */
3592 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3593 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3594 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3595 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3596 	} else {
3597 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3598 		    SEND_INIT_STATS_ENABLE);
3599 	}
3600 	/*
3601 	 * Steps 57-58: stop (?) the Host Coalescing Engine
3602 	 */
3603 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3604 		retval = DDI_FAILURE;
3605 
3606 	/*
3607 	 * Steps 59-62: initialise Host Coalescing parameters
3608 	 */
3609 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm);
3610 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm);
3611 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm);
3612 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm);
3613 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3614 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3615 		    bge_tx_count_intr);
3616 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3617 		    bge_tx_ticks_intr);
3618 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3619 		    bge_rx_count_intr);
3620 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3621 		    bge_rx_ticks_intr);
3622 	}
3623 
3624 	/*
3625 	 * Steps 63-64: initialise status block & statistics
3626 	 * host memory addresses
3627 	 * The statistic block does not exist in some chipsets
3628 	 * Step 65: initialise Statistics Coalescing Tick Counter
3629 	 */
3630 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
3631 	    bgep->status_block.cookie.dmac_laddress);
3632 
3633 	/*
3634 	 * Steps 66-67: initialise status block & statistics
3635 	 * NIC-local memory addresses
3636 	 */
3637 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3638 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
3639 		    bgep->statistics.cookie.dmac_laddress);
3640 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3641 		    STATISTICS_TICKS_DEFAULT);
3642 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3643 		    NIC_MEM_STATUS_BLOCK);
3644 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
3645 		    NIC_MEM_STATISTICS);
3646 	}
3647 
3648 	/*
3649 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
3650 	 * Completion Engine, the Receive List Placement Engine, and the
3651 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
3652 	 * and BCM5715.
3653 	 */
3654 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
3655 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
3656 		coalmode = COALESCE_64_BYTE_STATUS;
3657 	else
3658 		coalmode = 0;
3659 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
3660 		retval = DDI_FAILURE;
3661 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
3662 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3663 		retval = DDI_FAILURE;
3664 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
3665 		retval = DDI_FAILURE;
3666 
3667 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3668 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
3669 		    STATE_MACHINE_ATTN_ENABLE_BIT))
3670 			retval = DDI_FAILURE;
3671 
3672 	/*
3673 	 * Step 72: Enable MAC DMA engines
3674 	 * Step 73: Clear & enable MAC statistics
3675 	 */
3676 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3677 	    ETHERNET_MODE_ENABLE_FHDE |
3678 	    ETHERNET_MODE_ENABLE_RDE |
3679 	    ETHERNET_MODE_ENABLE_TDE);
3680 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3681 	    ETHERNET_MODE_ENABLE_TX_STATS |
3682 	    ETHERNET_MODE_ENABLE_RX_STATS |
3683 	    ETHERNET_MODE_CLEAR_TX_STATS |
3684 	    ETHERNET_MODE_CLEAR_RX_STATS);
3685 
3686 	/*
3687 	 * Step 74: configure the MLCR (Miscellaneous Local Control
3688 	 * Register); not required, as we set up the MLCR in step 10
3689 	 * (part of the reset code) above.
3690 	 *
3691 	 * Step 75: clear Interrupt Mailbox 0
3692 	 */
3693 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
3694 
3695 	/*
3696 	 * Steps 76-87: Gentlemen, start your engines ...
3697 	 *
3698 	 * Enable the DMA Completion Engine, the Write DMA Engine,
3699 	 * the Read DMA Engine, Receive Data Completion Engine,
3700 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
3701 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
3702 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
3703 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
3704 	 *
3705 	 * Beware exhaust fumes?
3706 	 */
3707 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3708 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
3709 			retval = DDI_FAILURE;
3710 	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
3711 	    ALL_DMA_ATTN_BITS;
3712 	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3713 	    MHCR_CHIP_ASIC_REV_5755) {
3714 		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
3715 	}
3716 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
3717 	    dma_wrprio))
3718 		retval = DDI_FAILURE;
3719 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
3720 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
3721 		retval = DDI_FAILURE;
3722 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
3723 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3724 		retval = DDI_FAILURE;
3725 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3726 		if (!bge_chip_enable_engine(bgep,
3727 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
3728 			retval = DDI_FAILURE;
3729 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
3730 		retval = DDI_FAILURE;
3731 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
3732 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3733 		retval = DDI_FAILURE;
3734 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
3735 	    RCV_BD_DISABLED_RING_ATTN))
3736 		retval = DDI_FAILURE;
3737 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
3738 	    RCV_DATA_BD_ILL_RING_ATTN))
3739 		retval = DDI_FAILURE;
3740 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
3741 		retval = DDI_FAILURE;
3742 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
3743 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3744 		retval = DDI_FAILURE;
3745 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
3746 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3747 		retval = DDI_FAILURE;
3748 
3749 	/*
3750 	 * Step 88: download firmware -- doesn't apply
3751 	 * Steps 89-90: enable Transmit & Receive MAC Engines
3752 	 */
3753 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3754 		retval = DDI_FAILURE;
3755 #ifdef BGE_IPMI_ASF
3756 	if (!bgep->asf_enabled) {
3757 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3758 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3759 			retval = DDI_FAILURE;
3760 	} else {
3761 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
3762 			retval = DDI_FAILURE;
3763 	}
3764 #else
3765 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3766 	    RECEIVE_MODE_KEEP_VLAN_TAG))
3767 		retval = DDI_FAILURE;
3768 #endif
3769 
3770 	/*
3771 	 * Step 91: disable auto-polling of PHY status
3772 	 */
3773 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
3774 
3775 	/*
3776 	 * Step 92: configure D0 power state (not required)
3777 	 * Step 93: initialise LED control register ()
3778 	 */
3779 	ledctl = LED_CONTROL_DEFAULT;
3780 	switch (bgep->chipid.device) {
3781 	case DEVICE_ID_5700:
3782 	case DEVICE_ID_5700x:
3783 	case DEVICE_ID_5701:
3784 		/*
3785 		 * Switch to 5700 (MAC) mode on these older chips
3786 		 */
3787 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
3788 		ledctl |= LED_CONTROL_LED_MODE_5700;
3789 		break;
3790 
3791 	default:
3792 		break;
3793 	}
3794 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
3795 
3796 	/*
3797 	 * Step 94: activate link
3798 	 */
3799 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3800 
3801 	/*
3802 	 * Step 95: set up physical layer (PHY/SerDes)
3803 	 * restart autoneg (if required)
3804 	 */
3805 	if (reset_phys)
3806 		if (bge_phys_update(bgep) == DDI_FAILURE)
3807 			retval = DDI_FAILURE;
3808 
3809 	/*
3810 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
3811 	 */
3812 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
3813 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
3814 		    bgep->buff[ring].rf_next);
3815 
3816 	/*
3817 	 * MSI bits:The least significant MSI 16-bit word.
3818 	 * ISR will be triggered different.
3819 	 */
3820 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3821 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
3822 
3823 	/*
3824 	 * Extra step (DSG): select which interrupts are enabled
3825 	 *
3826 	 * Program the Ethernet MAC engine to signal attention on
3827 	 * Link Change events, then enable interrupts on MAC, DMA,
3828 	 * and FLOW attention signals.
3829 	 */
3830 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
3831 	    ETHERNET_EVENT_LINK_INT |
3832 	    ETHERNET_STATUS_PCS_ERROR_INT);
3833 #ifdef BGE_IPMI_ASF
3834 	if (bgep->asf_enabled) {
3835 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3836 		    MODE_INT_ON_FLOW_ATTN |
3837 		    MODE_INT_ON_DMA_ATTN |
3838 		    MODE_HOST_STACK_UP|
3839 		    MODE_INT_ON_MAC_ATTN);
3840 	} else {
3841 #endif
3842 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3843 		    MODE_INT_ON_FLOW_ATTN |
3844 		    MODE_INT_ON_DMA_ATTN |
3845 		    MODE_INT_ON_MAC_ATTN);
3846 #ifdef BGE_IPMI_ASF
3847 	}
3848 #endif
3849 
3850 	/*
3851 	 * Step 97: enable PCI interrupts!!!
3852 	 */
3853 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3854 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
3855 		    MHCR_MASK_PCI_INT_OUTPUT);
3856 
3857 	/*
3858 	 * All done!
3859 	 */
3860 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
3861 	return (retval);
3862 }
3863 
3864 
3865 /*
3866  * ========== Hardware interrupt handler ==========
3867  */
3868 
3869 #undef	BGE_DBG
3870 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
3871 
3872 /*
3873  * Sync the status block, then atomically clear the specified bits in
3874  * the <flags-and-tag> field of the status block.
3875  * the <flags> word of the status block, returning the value of the
3876  * <tag> and the <flags> before the bits were cleared.
3877  */
3878 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
3879 #pragma	inline(bge_status_sync)
3880 
3881 static int
3882 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
3883 {
3884 	bge_status_t *bsp;
3885 	int retval;
3886 
3887 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
3888 	    (void *)bgep, bits));
3889 
3890 	ASSERT(bgep->bge_guard == BGE_GUARD);
3891 
3892 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
3893 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
3894 	if (retval != DDI_FM_OK)
3895 		return (retval);
3896 
3897 	bsp = DMA_VPTR(bgep->status_block);
3898 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
3899 
3900 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
3901 	    (void *)bgep, bits, *flags));
3902 
3903 	return (retval);
3904 }
3905 
3906 void bge_wake_factotum(bge_t *bgep);
3907 #pragma	inline(bge_wake_factotum)
3908 
3909 void
3910 bge_wake_factotum(bge_t *bgep)
3911 {
3912 	mutex_enter(bgep->softintrlock);
3913 	if (bgep->factotum_flag == 0) {
3914 		bgep->factotum_flag = 1;
3915 		ddi_trigger_softintr(bgep->factotum_id);
3916 	}
3917 	mutex_exit(bgep->softintrlock);
3918 }
3919 
3920 /*
3921  *	bge_intr() -- handle chip interrupts
3922  */
3923 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
3924 #pragma	no_inline(bge_intr)
3925 
3926 uint_t
3927 bge_intr(caddr_t arg1, caddr_t arg2)
3928 {
3929 	bge_t *bgep = (void *)arg1;		/* private device info	*/
3930 	bge_status_t *bsp;
3931 	uint64_t flags;
3932 	uint32_t regval;
3933 	uint_t result;
3934 	int retval, loop_cnt = 0;
3935 
3936 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
3937 
3938 	/*
3939 	 * GLD v2 checks that s/w setup is complete before passing
3940 	 * interrupts to this routine, thus eliminating the old
3941 	 * (and well-known) race condition around ddi_add_intr()
3942 	 */
3943 	ASSERT(bgep->progress & PROGRESS_HWINT);
3944 
3945 	result = DDI_INTR_UNCLAIMED;
3946 	mutex_enter(bgep->genlock);
3947 
3948 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
3949 		/*
3950 		 * Check whether chip's says it's asserting #INTA;
3951 		 * if not, don't process or claim the interrupt.
3952 		 *
3953 		 * Note that the PCI signal is active low, so the
3954 		 * bit is *zero* when the interrupt is asserted.
3955 		 */
3956 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
3957 		if (regval & MLCR_INTA_STATE) {
3958 			if (bge_check_acc_handle(bgep, bgep->io_handle)
3959 			    != DDI_FM_OK)
3960 				goto chip_stop;
3961 			mutex_exit(bgep->genlock);
3962 			return (result);
3963 		}
3964 
3965 		/*
3966 		 * Block further PCI interrupts ...
3967 		 */
3968 		bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
3969 		    MHCR_MASK_PCI_INT_OUTPUT);
3970 
3971 	} else {
3972 		/*
3973 		 * Check MSI status
3974 		 */
3975 		regval = bge_reg_get32(bgep, MSI_STATUS_REG);
3976 		if (regval & MSI_ERROR_ATTENTION) {
3977 			BGE_REPORT((bgep, "msi error attention,"
3978 			    " status=0x%x", regval));
3979 			bge_reg_put32(bgep, MSI_STATUS_REG, regval);
3980 		}
3981 	}
3982 
3983 	result = DDI_INTR_CLAIMED;
3984 
3985 	BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
3986 
3987 	/*
3988 	 * Sync the status block and grab the flags-n-tag from it.
3989 	 * We count the number of interrupts where there doesn't
3990 	 * seem to have been a DMA update of the status block; if
3991 	 * it *has* been updated, the counter will be cleared in
3992 	 * the while() loop below ...
3993 	 */
3994 	bgep->missed_dmas += 1;
3995 	bsp = DMA_VPTR(bgep->status_block);
3996 	for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
3997 		if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
3998 			/*
3999 			 * bge_chip_stop() may have freed dma area etc
4000 			 * while we were in this interrupt handler -
4001 			 * better not call bge_status_sync()
4002 			 */
4003 			(void) bge_check_acc_handle(bgep,
4004 			    bgep->io_handle);
4005 			mutex_exit(bgep->genlock);
4006 			return (DDI_INTR_CLAIMED);
4007 		}
4008 		retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
4009 		    &flags);
4010 		if (retval != DDI_FM_OK) {
4011 			bgep->bge_dma_error = B_TRUE;
4012 			goto chip_stop;
4013 		}
4014 
4015 		if (!(flags & STATUS_FLAG_UPDATED))
4016 			break;
4017 
4018 		/*
4019 		 * Tell the chip that we're processing the interrupt
4020 		 */
4021 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4022 		    INTERRUPT_MBOX_DISABLE(flags));
4023 		if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4024 		    DDI_FM_OK)
4025 			goto chip_stop;
4026 
4027 		/*
4028 		 * Drop the mutex while we:
4029 		 * 	Receive any newly-arrived packets
4030 		 *	Recycle any newly-finished send buffers
4031 		 */
4032 		bgep->bge_intr_running = B_TRUE;
4033 		mutex_exit(bgep->genlock);
4034 		bge_receive(bgep, bsp);
4035 		bge_recycle(bgep, bsp);
4036 		mutex_enter(bgep->genlock);
4037 		bgep->bge_intr_running = B_FALSE;
4038 
4039 		/*
4040 		 * Tell the chip we've finished processing, and
4041 		 * give it the tag that we got from the status
4042 		 * block earlier, so that it knows just how far
4043 		 * we've gone.  If it's got more for us to do,
4044 		 * it will now update the status block and try
4045 		 * to assert an interrupt (but we've got the
4046 		 * #INTA blocked at present).  If we see the
4047 		 * update, we'll loop around to do some more.
4048 		 * Eventually we'll get out of here ...
4049 		 */
4050 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4051 		    INTERRUPT_MBOX_ENABLE(flags));
4052 		if (bgep->chipid.pci_type == BGE_PCI_E)
4053 			(void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4054 		bgep->missed_dmas = 0;
4055 	}
4056 
4057 	/*
4058 	 * Check for exceptional conditions that we need to handle
4059 	 *
4060 	 * Link status changed
4061 	 * Status block not updated
4062 	 */
4063 	if (flags & STATUS_FLAG_LINK_CHANGED)
4064 		bge_wake_factotum(bgep);
4065 
4066 	if (bgep->missed_dmas) {
4067 		/*
4068 		 * Probably due to the internal status tag not
4069 		 * being reset.  Force a status block update now;
4070 		 * this should ensure that we get an update and
4071 		 * a new interrupt.  After that, we should be in
4072 		 * sync again ...
4073 		 */
4074 		BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4075 		    "not updated?", flags));
4076 		bgep->missed_updates++;
4077 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4078 		    COALESCE_NOW);
4079 
4080 		if (bgep->missed_dmas >= bge_dma_miss_limit) {
4081 			/*
4082 			 * If this happens multiple times in a row,
4083 			 * it means DMA is just not working.  Maybe
4084 			 * the chip's failed, or maybe there's a
4085 			 * problem on the PCI bus or in the host-PCI
4086 			 * bridge (Tomatillo).
4087 			 *
4088 			 * At all events, we want to stop further
4089 			 * interrupts and let the recovery code take
4090 			 * over to see whether anything can be done
4091 			 * about it ...
4092 			 */
4093 			bge_fm_ereport(bgep,
4094 			    DDI_FM_DEVICE_BADINT_LIMIT);
4095 			goto chip_stop;
4096 		}
4097 	}
4098 
4099 	/*
4100 	 * Reenable assertion of #INTA, unless there's a DMA fault
4101 	 */
4102 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4103 		bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4104 		    MHCR_MASK_PCI_INT_OUTPUT);
4105 		if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4106 		    DDI_FM_OK)
4107 			goto chip_stop;
4108 	}
4109 
4110 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4111 		goto chip_stop;
4112 
4113 	mutex_exit(bgep->genlock);
4114 	return (result);
4115 
4116 chip_stop:
4117 #ifdef BGE_IPMI_ASF
4118 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4119 		/*
4120 		 * We must stop ASF heart beat before
4121 		 * bge_chip_stop(), otherwise some
4122 		 * computers (ex. IBM HS20 blade
4123 		 * server) may crash.
4124 		 */
4125 		bge_asf_update_status(bgep);
4126 		bge_asf_stop_timer(bgep);
4127 		bgep->asf_status = ASF_STAT_STOP;
4128 
4129 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4130 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4131 	}
4132 #endif
4133 	bge_chip_stop(bgep, B_TRUE);
4134 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
4135 	mutex_exit(bgep->genlock);
4136 	return (result);
4137 }
4138 
4139 /*
4140  * ========== Factotum, implemented as a softint handler ==========
4141  */
4142 
4143 #undef	BGE_DBG
4144 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
4145 
4146 static void bge_factotum_error_handler(bge_t *bgep);
4147 #pragma	no_inline(bge_factotum_error_handler)
4148 
4149 static void
4150 bge_factotum_error_handler(bge_t *bgep)
4151 {
4152 	uint32_t flow;
4153 	uint32_t rdma;
4154 	uint32_t wdma;
4155 	uint32_t tmac;
4156 	uint32_t rmac;
4157 	uint32_t rxrs;
4158 	uint32_t txrs = 0;
4159 
4160 	ASSERT(mutex_owned(bgep->genlock));
4161 
4162 	/*
4163 	 * Read all the registers that show the possible
4164 	 * reasons for the ERROR bit to be asserted
4165 	 */
4166 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4167 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4168 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4169 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4170 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4171 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4172 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4173 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4174 
4175 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4176 	    (void *)bgep, flow, rdma, wdma));
4177 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4178 	    (void *)bgep, tmac, rmac, rxrs, txrs));
4179 
4180 	/*
4181 	 * For now, just clear all the errors ...
4182 	 */
4183 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4184 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4185 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4186 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4187 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4188 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4189 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4190 }
4191 
4192 /*
4193  * Handler for hardware link state change.
4194  *
4195  * When this routine is called, the hardware link state has changed
4196  * and the new state is reflected in the param_* variables.  Here
4197  * we must update the softstate and reprogram the MAC to match.
4198  */
4199 static void bge_factotum_link_handler(bge_t *bgep);
4200 #pragma	no_inline(bge_factotum_link_handler)
4201 
4202 static void
4203 bge_factotum_link_handler(bge_t *bgep)
4204 {
4205 	ASSERT(mutex_owned(bgep->genlock));
4206 
4207 	/*
4208 	 * Update the s/w link_state
4209 	 */
4210 	if (bgep->param_link_up)
4211 		bgep->link_state = LINK_STATE_UP;
4212 	else
4213 		bgep->link_state = LINK_STATE_DOWN;
4214 
4215 	/*
4216 	 * Reprogram the MAC modes to match
4217 	 */
4218 	bge_sync_mac_modes(bgep);
4219 }
4220 
4221 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4222 #pragma	no_inline(bge_factotum_link_check)
4223 
4224 static boolean_t
4225 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4226 {
4227 	boolean_t check;
4228 	uint64_t flags;
4229 	uint32_t tmac_status;
4230 
4231 	ASSERT(mutex_owned(bgep->genlock));
4232 
4233 	/*
4234 	 * Get & clear the writable status bits in the Tx status register
4235 	 * (some bits are write-1-to-clear, others are just readonly).
4236 	 */
4237 	tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4238 	bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4239 
4240 	/*
4241 	 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4242 	 */
4243 	*dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4244 	    STATUS_FLAG_LINK_CHANGED, &flags);
4245 	if (*dma_state != DDI_FM_OK)
4246 		return (B_FALSE);
4247 
4248 	/*
4249 	 * Clear any errors flagged in the status block ...
4250 	 */
4251 	if (flags & STATUS_FLAG_ERROR)
4252 		bge_factotum_error_handler(bgep);
4253 
4254 	/*
4255 	 * We need to check the link status if:
4256 	 *	the status block says there's been a link change
4257 	 *	or there's any discrepancy between the various
4258 	 *	flags indicating the link state (link_state,
4259 	 *	param_link_up, and the LINK STATE bit in the
4260 	 *	Transmit MAC status register).
4261 	 */
4262 	check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4263 	switch (bgep->link_state) {
4264 	case LINK_STATE_UP:
4265 		check |= (bgep->param_link_up == B_FALSE);
4266 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4267 		break;
4268 
4269 	case LINK_STATE_DOWN:
4270 		check |= (bgep->param_link_up != B_FALSE);
4271 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4272 		break;
4273 
4274 	default:
4275 		check = B_TRUE;
4276 		break;
4277 	}
4278 
4279 	/*
4280 	 * If <check> is false, we're sure the link hasn't changed.
4281 	 * If true, however, it's not yet definitive; we have to call
4282 	 * bge_phys_check() to determine whether the link has settled
4283 	 * into a new state yet ... and if it has, then call the link
4284 	 * state change handler.But when the chip is 5700 in Dell 6650
4285 	 * ,even if check is false, the link may have changed.So we
4286 	 * have to call bge_phys_check() to determine the link state.
4287 	 */
4288 	if (check || bgep->chipid.device == DEVICE_ID_5700) {
4289 		check = bge_phys_check(bgep);
4290 		if (check)
4291 			bge_factotum_link_handler(bgep);
4292 	}
4293 
4294 	return (check);
4295 }
4296 
4297 /*
4298  * Factotum routine to check for Tx stall, using the 'watchdog' counter
4299  */
4300 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4301 #pragma	no_inline(bge_factotum_stall_check)
4302 
4303 static boolean_t
4304 bge_factotum_stall_check(bge_t *bgep)
4305 {
4306 	uint32_t dogval;
4307 
4308 	ASSERT(mutex_owned(bgep->genlock));
4309 
4310 	/*
4311 	 * Specific check for Tx stall ...
4312 	 *
4313 	 * The 'watchdog' counter is incremented whenever a packet
4314 	 * is queued, reset to 1 when some (but not all) buffers
4315 	 * are reclaimed, reset to 0 (disabled) when all buffers
4316 	 * are reclaimed, and shifted left here.  If it exceeds the
4317 	 * threshold value, the chip is assumed to have stalled and
4318 	 * is put into the ERROR state.  The factotum will then reset
4319 	 * it on the next pass.
4320 	 *
4321 	 * All of which should ensure that we don't get into a state
4322 	 * where packets are left pending indefinitely!
4323 	 */
4324 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4325 	if (dogval < bge_watchdog_count)
4326 		return (B_FALSE);
4327 
4328 #if !defined(BGE_NETCONSOLE)
4329 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4330 #endif
4331 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4332 	return (B_TRUE);
4333 }
4334 
4335 /*
4336  * The factotum is woken up when there's something to do that we'd rather
4337  * not do from inside a hardware interrupt handler or high-level cyclic.
4338  * Its two main tasks are:
4339  *	reset & restart the chip after an error
4340  *	check the link status whenever necessary
4341  */
4342 uint_t bge_chip_factotum(caddr_t arg);
4343 #pragma	no_inline(bge_chip_factotum)
4344 
4345 uint_t
4346 bge_chip_factotum(caddr_t arg)
4347 {
4348 	bge_t *bgep;
4349 	uint_t result;
4350 	boolean_t error;
4351 	boolean_t linkchg;
4352 	int dma_state;
4353 
4354 	bgep = (void *)arg;
4355 
4356 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4357 
4358 	mutex_enter(bgep->softintrlock);
4359 	if (bgep->factotum_flag == 0) {
4360 		mutex_exit(bgep->softintrlock);
4361 		return (DDI_INTR_UNCLAIMED);
4362 	}
4363 	bgep->factotum_flag = 0;
4364 	mutex_exit(bgep->softintrlock);
4365 
4366 	result = DDI_INTR_CLAIMED;
4367 	error = B_FALSE;
4368 	linkchg = B_FALSE;
4369 
4370 	mutex_enter(bgep->genlock);
4371 	switch (bgep->bge_chip_state) {
4372 	default:
4373 		break;
4374 
4375 	case BGE_CHIP_RUNNING:
4376 		linkchg = bge_factotum_link_check(bgep, &dma_state);
4377 		error = bge_factotum_stall_check(bgep);
4378 		if (dma_state != DDI_FM_OK) {
4379 			bgep->bge_dma_error = B_TRUE;
4380 			error = B_TRUE;
4381 		}
4382 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4383 			error = B_TRUE;
4384 		if (error)
4385 			bgep->bge_chip_state = BGE_CHIP_ERROR;
4386 		break;
4387 
4388 	case BGE_CHIP_ERROR:
4389 		error = B_TRUE;
4390 		break;
4391 
4392 	case BGE_CHIP_FAULT:
4393 		/*
4394 		 * Fault detected, time to reset ...
4395 		 */
4396 		if (bge_autorecover) {
4397 			if (!(bgep->progress & PROGRESS_BUFS)) {
4398 				/*
4399 				 * if we can't allocate the ring buffers,
4400 				 * try later
4401 				 */
4402 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4403 					mutex_exit(bgep->genlock);
4404 					return (result);
4405 				}
4406 				bgep->progress |= PROGRESS_BUFS;
4407 			}
4408 			if (!(bgep->progress & PROGRESS_INTR)) {
4409 				bge_init_rings(bgep);
4410 				bge_intr_enable(bgep);
4411 				bgep->progress |= PROGRESS_INTR;
4412 			}
4413 			if (!(bgep->progress & PROGRESS_KSTATS)) {
4414 				bge_init_kstats(bgep,
4415 				    ddi_get_instance(bgep->devinfo));
4416 				bgep->progress |= PROGRESS_KSTATS;
4417 			}
4418 
4419 			BGE_REPORT((bgep, "automatic recovery activated"));
4420 
4421 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4422 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4423 				error = B_TRUE;
4424 			}
4425 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4426 			    DDI_FM_OK) {
4427 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4428 				error = B_TRUE;
4429 			}
4430 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4431 			    DDI_FM_OK) {
4432 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4433 				error = B_TRUE;
4434 			}
4435 			if (error == B_FALSE) {
4436 #ifdef BGE_IPMI_ASF
4437 				if (bgep->asf_enabled &&
4438 				    bgep->asf_status != ASF_STAT_RUN) {
4439 					bgep->asf_timeout_id = timeout(
4440 					    bge_asf_heartbeat, (void *)bgep,
4441 					    drv_usectohz(
4442 					    BGE_ASF_HEARTBEAT_INTERVAL));
4443 					bgep->asf_status = ASF_STAT_RUN;
4444 				}
4445 #endif
4446 				if (!bgep->manual_reset) {
4447 					ddi_fm_service_impact(bgep->devinfo,
4448 					    DDI_SERVICE_RESTORED);
4449 				}
4450 			}
4451 		}
4452 		break;
4453 	}
4454 
4455 
4456 	/*
4457 	 * If an error is detected, stop the chip now, marking it as
4458 	 * faulty, so that it will be reset next time through ...
4459 	 *
4460 	 * Note that if intr_running is set, then bge_intr() has dropped
4461 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4462 	 * this point so have to wait until the next time the factotum runs.
4463 	 */
4464 	if (error && !bgep->bge_intr_running) {
4465 #ifdef BGE_IPMI_ASF
4466 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4467 			/*
4468 			 * We must stop ASF heart beat before bge_chip_stop(),
4469 			 * otherwise some computers (ex. IBM HS20 blade server)
4470 			 * may crash.
4471 			 */
4472 			bge_asf_update_status(bgep);
4473 			bge_asf_stop_timer(bgep);
4474 			bgep->asf_status = ASF_STAT_STOP;
4475 
4476 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4477 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4478 		}
4479 #endif
4480 		bge_chip_stop(bgep, B_TRUE);
4481 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
4482 	}
4483 	mutex_exit(bgep->genlock);
4484 
4485 	/*
4486 	 * If the link state changed, tell the world about it.
4487 	 * Note: can't do this while still holding the mutex.
4488 	 */
4489 	if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
4490 	    bgep->link_state != LINK_STATE_UNKNOWN)
4491 		linkchg = B_TRUE;
4492 	else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
4493 	    bgep->link_state == LINK_STATE_DOWN)
4494 		linkchg = B_FALSE;
4495 
4496 	if (linkchg) {
4497 		mac_link_update(bgep->mh, bgep->link_state);
4498 		bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
4499 	}
4500 	if (bgep->manual_reset) {
4501 		bgep->manual_reset = B_FALSE;
4502 	}
4503 
4504 	return (result);
4505 }
4506 
4507 /*
4508  * High-level cyclic handler
4509  *
4510  * This routine schedules a (low-level) softint callback to the
4511  * factotum, and prods the chip to update the status block (which
4512  * will cause a hardware interrupt when complete).
4513  */
4514 void bge_chip_cyclic(void *arg);
4515 #pragma	no_inline(bge_chip_cyclic)
4516 
4517 void
4518 bge_chip_cyclic(void *arg)
4519 {
4520 	bge_t *bgep;
4521 
4522 	bgep = arg;
4523 
4524 	switch (bgep->bge_chip_state) {
4525 	default:
4526 		return;
4527 
4528 	case BGE_CHIP_RUNNING:
4529 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4530 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4531 			ddi_fm_service_impact(bgep->devinfo,
4532 			    DDI_SERVICE_UNAFFECTED);
4533 
4534 		if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
4535 			bgep->link_update_timer++;
4536 
4537 		break;
4538 
4539 	case BGE_CHIP_FAULT:
4540 	case BGE_CHIP_ERROR:
4541 		break;
4542 	}
4543 
4544 	bge_wake_factotum(bgep);
4545 }
4546 
4547 
4548 /*
4549  * ========== Ioctl subfunctions ==========
4550  */
4551 
4552 #undef	BGE_DBG
4553 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
4554 
4555 #if	BGE_DEBUGGING || BGE_DO_PPIO
4556 
4557 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4558 #pragma	no_inline(bge_chip_peek_cfg)
4559 
4560 static void
4561 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4562 {
4563 	uint64_t regval;
4564 	uint64_t regno;
4565 
4566 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4567 	    (void *)bgep, (void *)ppd));
4568 
4569 	regno = ppd->pp_acc_offset;
4570 
4571 	switch (ppd->pp_acc_size) {
4572 	case 1:
4573 		regval = pci_config_get8(bgep->cfg_handle, regno);
4574 		break;
4575 
4576 	case 2:
4577 		regval = pci_config_get16(bgep->cfg_handle, regno);
4578 		break;
4579 
4580 	case 4:
4581 		regval = pci_config_get32(bgep->cfg_handle, regno);
4582 		break;
4583 
4584 	case 8:
4585 		regval = pci_config_get64(bgep->cfg_handle, regno);
4586 		break;
4587 	}
4588 
4589 	ppd->pp_acc_data = regval;
4590 }
4591 
4592 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4593 #pragma	no_inline(bge_chip_poke_cfg)
4594 
4595 static void
4596 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4597 {
4598 	uint64_t regval;
4599 	uint64_t regno;
4600 
4601 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
4602 	    (void *)bgep, (void *)ppd));
4603 
4604 	regno = ppd->pp_acc_offset;
4605 	regval = ppd->pp_acc_data;
4606 
4607 	switch (ppd->pp_acc_size) {
4608 	case 1:
4609 		pci_config_put8(bgep->cfg_handle, regno, regval);
4610 		break;
4611 
4612 	case 2:
4613 		pci_config_put16(bgep->cfg_handle, regno, regval);
4614 		break;
4615 
4616 	case 4:
4617 		pci_config_put32(bgep->cfg_handle, regno, regval);
4618 		break;
4619 
4620 	case 8:
4621 		pci_config_put64(bgep->cfg_handle, regno, regval);
4622 		break;
4623 	}
4624 }
4625 
4626 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4627 #pragma	no_inline(bge_chip_peek_reg)
4628 
4629 static void
4630 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4631 {
4632 	uint64_t regval;
4633 	void *regaddr;
4634 
4635 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
4636 	    (void *)bgep, (void *)ppd));
4637 
4638 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4639 
4640 	switch (ppd->pp_acc_size) {
4641 	case 1:
4642 		regval = ddi_get8(bgep->io_handle, regaddr);
4643 		break;
4644 
4645 	case 2:
4646 		regval = ddi_get16(bgep->io_handle, regaddr);
4647 		break;
4648 
4649 	case 4:
4650 		regval = ddi_get32(bgep->io_handle, regaddr);
4651 		break;
4652 
4653 	case 8:
4654 		regval = ddi_get64(bgep->io_handle, regaddr);
4655 		break;
4656 	}
4657 
4658 	ppd->pp_acc_data = regval;
4659 }
4660 
4661 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4662 #pragma	no_inline(bge_chip_peek_reg)
4663 
4664 static void
4665 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4666 {
4667 	uint64_t regval;
4668 	void *regaddr;
4669 
4670 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
4671 	    (void *)bgep, (void *)ppd));
4672 
4673 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4674 	regval = ppd->pp_acc_data;
4675 
4676 	switch (ppd->pp_acc_size) {
4677 	case 1:
4678 		ddi_put8(bgep->io_handle, regaddr, regval);
4679 		break;
4680 
4681 	case 2:
4682 		ddi_put16(bgep->io_handle, regaddr, regval);
4683 		break;
4684 
4685 	case 4:
4686 		ddi_put32(bgep->io_handle, regaddr, regval);
4687 		break;
4688 
4689 	case 8:
4690 		ddi_put64(bgep->io_handle, regaddr, regval);
4691 		break;
4692 	}
4693 	BGE_PCICHK(bgep);
4694 }
4695 
4696 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4697 #pragma	no_inline(bge_chip_peek_nic)
4698 
4699 static void
4700 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4701 {
4702 	uint64_t regoff;
4703 	uint64_t regval;
4704 	void *regaddr;
4705 
4706 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
4707 	    (void *)bgep, (void *)ppd));
4708 
4709 	regoff = ppd->pp_acc_offset;
4710 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4711 	regoff &= MWBAR_GRANULE_MASK;
4712 	regoff += NIC_MEM_WINDOW_OFFSET;
4713 	regaddr = PIO_ADDR(bgep, regoff);
4714 
4715 	switch (ppd->pp_acc_size) {
4716 	case 1:
4717 		regval = ddi_get8(bgep->io_handle, regaddr);
4718 		break;
4719 
4720 	case 2:
4721 		regval = ddi_get16(bgep->io_handle, regaddr);
4722 		break;
4723 
4724 	case 4:
4725 		regval = ddi_get32(bgep->io_handle, regaddr);
4726 		break;
4727 
4728 	case 8:
4729 		regval = ddi_get64(bgep->io_handle, regaddr);
4730 		break;
4731 	}
4732 
4733 	ppd->pp_acc_data = regval;
4734 }
4735 
4736 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4737 #pragma	no_inline(bge_chip_poke_nic)
4738 
4739 static void
4740 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4741 {
4742 	uint64_t regoff;
4743 	uint64_t regval;
4744 	void *regaddr;
4745 
4746 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
4747 	    (void *)bgep, (void *)ppd));
4748 
4749 	regoff = ppd->pp_acc_offset;
4750 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4751 	regoff &= MWBAR_GRANULE_MASK;
4752 	regoff += NIC_MEM_WINDOW_OFFSET;
4753 	regaddr = PIO_ADDR(bgep, regoff);
4754 	regval = ppd->pp_acc_data;
4755 
4756 	switch (ppd->pp_acc_size) {
4757 	case 1:
4758 		ddi_put8(bgep->io_handle, regaddr, regval);
4759 		break;
4760 
4761 	case 2:
4762 		ddi_put16(bgep->io_handle, regaddr, regval);
4763 		break;
4764 
4765 	case 4:
4766 		ddi_put32(bgep->io_handle, regaddr, regval);
4767 		break;
4768 
4769 	case 8:
4770 		ddi_put64(bgep->io_handle, regaddr, regval);
4771 		break;
4772 	}
4773 	BGE_PCICHK(bgep);
4774 }
4775 
4776 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
4777 #pragma	no_inline(bge_chip_peek_mii)
4778 
4779 static void
4780 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
4781 {
4782 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
4783 	    (void *)bgep, (void *)ppd));
4784 
4785 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
4786 }
4787 
4788 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
4789 #pragma	no_inline(bge_chip_poke_mii)
4790 
4791 static void
4792 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
4793 {
4794 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
4795 	    (void *)bgep, (void *)ppd));
4796 
4797 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
4798 }
4799 
4800 #if	BGE_SEE_IO32
4801 
4802 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
4803 #pragma	no_inline(bge_chip_peek_seeprom)
4804 
4805 static void
4806 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
4807 {
4808 	uint32_t data;
4809 	int err;
4810 
4811 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
4812 	    (void *)bgep, (void *)ppd));
4813 
4814 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
4815 	ppd->pp_acc_data = err ? ~0ull : data;
4816 }
4817 
4818 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
4819 #pragma	no_inline(bge_chip_poke_seeprom)
4820 
4821 static void
4822 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
4823 {
4824 	uint32_t data;
4825 
4826 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
4827 	    (void *)bgep, (void *)ppd));
4828 
4829 	data = ppd->pp_acc_data;
4830 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
4831 }
4832 #endif	/* BGE_SEE_IO32 */
4833 
4834 #if	BGE_FLASH_IO32
4835 
4836 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
4837 #pragma	no_inline(bge_chip_peek_flash)
4838 
4839 static void
4840 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
4841 {
4842 	uint32_t data;
4843 	int err;
4844 
4845 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
4846 	    (void *)bgep, (void *)ppd));
4847 
4848 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
4849 	ppd->pp_acc_data = err ? ~0ull : data;
4850 }
4851 
4852 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
4853 #pragma	no_inline(bge_chip_poke_flash)
4854 
4855 static void
4856 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
4857 {
4858 	uint32_t data;
4859 
4860 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
4861 	    (void *)bgep, (void *)ppd));
4862 
4863 	data = ppd->pp_acc_data;
4864 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
4865 	    ppd->pp_acc_offset, &data);
4866 }
4867 #endif	/* BGE_FLASH_IO32 */
4868 
4869 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
4870 #pragma	no_inline(bge_chip_peek_mem)
4871 
4872 static void
4873 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
4874 {
4875 	uint64_t regval;
4876 	void *vaddr;
4877 
4878 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
4879 	    (void *)bgep, (void *)ppd));
4880 
4881 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4882 
4883 	switch (ppd->pp_acc_size) {
4884 	case 1:
4885 		regval = *(uint8_t *)vaddr;
4886 		break;
4887 
4888 	case 2:
4889 		regval = *(uint16_t *)vaddr;
4890 		break;
4891 
4892 	case 4:
4893 		regval = *(uint32_t *)vaddr;
4894 		break;
4895 
4896 	case 8:
4897 		regval = *(uint64_t *)vaddr;
4898 		break;
4899 	}
4900 
4901 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
4902 	    (void *)bgep, (void *)ppd, regval, vaddr));
4903 
4904 	ppd->pp_acc_data = regval;
4905 }
4906 
4907 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
4908 #pragma	no_inline(bge_chip_poke_mem)
4909 
4910 static void
4911 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
4912 {
4913 	uint64_t regval;
4914 	void *vaddr;
4915 
4916 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
4917 	    (void *)bgep, (void *)ppd));
4918 
4919 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4920 	regval = ppd->pp_acc_data;
4921 
4922 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
4923 	    (void *)bgep, (void *)ppd, regval, vaddr));
4924 
4925 	switch (ppd->pp_acc_size) {
4926 	case 1:
4927 		*(uint8_t *)vaddr = (uint8_t)regval;
4928 		break;
4929 
4930 	case 2:
4931 		*(uint16_t *)vaddr = (uint16_t)regval;
4932 		break;
4933 
4934 	case 4:
4935 		*(uint32_t *)vaddr = (uint32_t)regval;
4936 		break;
4937 
4938 	case 8:
4939 		*(uint64_t *)vaddr = (uint64_t)regval;
4940 		break;
4941 	}
4942 }
4943 
4944 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
4945 					struct iocblk *iocp);
4946 #pragma	no_inline(bge_pp_ioctl)
4947 
4948 static enum ioc_reply
4949 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
4950 {
4951 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
4952 	bge_peekpoke_t *ppd;
4953 	dma_area_t *areap;
4954 	uint64_t sizemask;
4955 	uint64_t mem_va;
4956 	uint64_t maxoff;
4957 	boolean_t peek;
4958 
4959 	switch (cmd) {
4960 	default:
4961 		/* NOTREACHED */
4962 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
4963 		return (IOC_INVAL);
4964 
4965 	case BGE_PEEK:
4966 		peek = B_TRUE;
4967 		break;
4968 
4969 	case BGE_POKE:
4970 		peek = B_FALSE;
4971 		break;
4972 	}
4973 
4974 	/*
4975 	 * Validate format of ioctl
4976 	 */
4977 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
4978 		return (IOC_INVAL);
4979 	if (mp->b_cont == NULL)
4980 		return (IOC_INVAL);
4981 	ppd = (void *)mp->b_cont->b_rptr;
4982 
4983 	/*
4984 	 * Validate request parameters
4985 	 */
4986 	switch (ppd->pp_acc_space) {
4987 	default:
4988 		return (IOC_INVAL);
4989 
4990 	case BGE_PP_SPACE_CFG:
4991 		/*
4992 		 * Config space
4993 		 */
4994 		sizemask = 8|4|2|1;
4995 		mem_va = 0;
4996 		maxoff = PCI_CONF_HDR_SIZE;
4997 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
4998 		break;
4999 
5000 	case BGE_PP_SPACE_REG:
5001 		/*
5002 		 * Memory-mapped I/O space
5003 		 */
5004 		sizemask = 8|4|2|1;
5005 		mem_va = 0;
5006 		maxoff = RIAAR_REGISTER_MAX;
5007 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
5008 		break;
5009 
5010 	case BGE_PP_SPACE_NIC:
5011 		/*
5012 		 * NIC on-chip memory
5013 		 */
5014 		sizemask = 8|4|2|1;
5015 		mem_va = 0;
5016 		maxoff = MWBAR_ONCHIP_MAX;
5017 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
5018 		break;
5019 
5020 	case BGE_PP_SPACE_MII:
5021 		/*
5022 		 * PHY's MII registers
5023 		 * NB: all PHY registers are two bytes, but the
5024 		 * addresses increment in ones (word addressing).
5025 		 * So we scale the address here, then undo the
5026 		 * transformation inside the peek/poke functions.
5027 		 */
5028 		ppd->pp_acc_offset *= 2;
5029 		sizemask = 2;
5030 		mem_va = 0;
5031 		maxoff = (MII_MAXREG+1)*2;
5032 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5033 		break;
5034 
5035 #if	BGE_SEE_IO32
5036 	case BGE_PP_SPACE_SEEPROM:
5037 		/*
5038 		 * Attached SEEPROM(s), if any.
5039 		 * NB: we use the high-order bits of the 'address' as
5040 		 * a device select to accommodate multiple SEEPROMS,
5041 		 * If each one is the maximum size (64kbytes), this
5042 		 * makes them appear contiguous.  Otherwise, there may
5043 		 * be holes in the mapping.  ENxS doesn't have any
5044 		 * SEEPROMs anyway ...
5045 		 */
5046 		sizemask = 4;
5047 		mem_va = 0;
5048 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5049 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5050 		break;
5051 #endif	/* BGE_SEE_IO32 */
5052 
5053 #if	BGE_FLASH_IO32
5054 	case BGE_PP_SPACE_FLASH:
5055 		/*
5056 		 * Attached Flash device (if any); a maximum of one device
5057 		 * is currently supported.  But it can be up to 1MB (unlike
5058 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
5059 		 */
5060 		sizemask = 4;
5061 		mem_va = 0;
5062 		maxoff = NVM_FLASH_ADDR_MASK;
5063 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5064 		break;
5065 #endif	/* BGE_FLASH_IO32 */
5066 
5067 	case BGE_PP_SPACE_BGE:
5068 		/*
5069 		 * BGE data structure!
5070 		 */
5071 		sizemask = 8|4|2|1;
5072 		mem_va = (uintptr_t)bgep;
5073 		maxoff = sizeof (*bgep);
5074 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5075 		break;
5076 
5077 	case BGE_PP_SPACE_STATUS:
5078 	case BGE_PP_SPACE_STATISTICS:
5079 	case BGE_PP_SPACE_TXDESC:
5080 	case BGE_PP_SPACE_TXBUFF:
5081 	case BGE_PP_SPACE_RXDESC:
5082 	case BGE_PP_SPACE_RXBUFF:
5083 		/*
5084 		 * Various DMA_AREAs
5085 		 */
5086 		switch (ppd->pp_acc_space) {
5087 		case BGE_PP_SPACE_TXDESC:
5088 			areap = &bgep->tx_desc;
5089 			break;
5090 		case BGE_PP_SPACE_TXBUFF:
5091 			areap = &bgep->tx_buff[0];
5092 			break;
5093 		case BGE_PP_SPACE_RXDESC:
5094 			areap = &bgep->rx_desc[0];
5095 			break;
5096 		case BGE_PP_SPACE_RXBUFF:
5097 			areap = &bgep->rx_buff[0];
5098 			break;
5099 		case BGE_PP_SPACE_STATUS:
5100 			areap = &bgep->status_block;
5101 			break;
5102 		case BGE_PP_SPACE_STATISTICS:
5103 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5104 				areap = &bgep->statistics;
5105 			break;
5106 		}
5107 
5108 		sizemask = 8|4|2|1;
5109 		mem_va = (uintptr_t)areap->mem_va;
5110 		maxoff = areap->alength;
5111 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5112 		break;
5113 	}
5114 
5115 	switch (ppd->pp_acc_size) {
5116 	default:
5117 		return (IOC_INVAL);
5118 
5119 	case 8:
5120 	case 4:
5121 	case 2:
5122 	case 1:
5123 		if ((ppd->pp_acc_size & sizemask) == 0)
5124 			return (IOC_INVAL);
5125 		break;
5126 	}
5127 
5128 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5129 		return (IOC_INVAL);
5130 
5131 	if (ppd->pp_acc_offset >= maxoff)
5132 		return (IOC_INVAL);
5133 
5134 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5135 		return (IOC_INVAL);
5136 
5137 	/*
5138 	 * All OK - go do it!
5139 	 */
5140 	ppd->pp_acc_offset += mem_va;
5141 	(*ppfn)(bgep, ppd);
5142 	return (peek ? IOC_REPLY : IOC_ACK);
5143 }
5144 
5145 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5146 					struct iocblk *iocp);
5147 #pragma	no_inline(bge_diag_ioctl)
5148 
5149 static enum ioc_reply
5150 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5151 {
5152 	ASSERT(mutex_owned(bgep->genlock));
5153 
5154 	switch (cmd) {
5155 	default:
5156 		/* NOTREACHED */
5157 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5158 		return (IOC_INVAL);
5159 
5160 	case BGE_DIAG:
5161 		/*
5162 		 * Currently a no-op
5163 		 */
5164 		return (IOC_ACK);
5165 
5166 	case BGE_PEEK:
5167 	case BGE_POKE:
5168 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5169 
5170 	case BGE_PHY_RESET:
5171 		return (IOC_RESTART_ACK);
5172 
5173 	case BGE_SOFT_RESET:
5174 	case BGE_HARD_RESET:
5175 		/*
5176 		 * Reset and reinitialise the 570x hardware
5177 		 */
5178 		bgep->bge_chip_state = BGE_CHIP_FAULT;
5179 		ddi_trigger_softintr(bgep->factotum_id);
5180 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5181 		return (IOC_ACK);
5182 	}
5183 
5184 	/* NOTREACHED */
5185 }
5186 
5187 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5188 
5189 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5190 				    struct iocblk *iocp);
5191 #pragma	no_inline(bge_mii_ioctl)
5192 
5193 static enum ioc_reply
5194 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5195 {
5196 	struct bge_mii_rw *miirwp;
5197 
5198 	/*
5199 	 * Validate format of ioctl
5200 	 */
5201 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5202 		return (IOC_INVAL);
5203 	if (mp->b_cont == NULL)
5204 		return (IOC_INVAL);
5205 	miirwp = (void *)mp->b_cont->b_rptr;
5206 
5207 	/*
5208 	 * Validate request parameters ...
5209 	 */
5210 	if (miirwp->mii_reg > MII_MAXREG)
5211 		return (IOC_INVAL);
5212 
5213 	switch (cmd) {
5214 	default:
5215 		/* NOTREACHED */
5216 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5217 		return (IOC_INVAL);
5218 
5219 	case BGE_MII_READ:
5220 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5221 		return (IOC_REPLY);
5222 
5223 	case BGE_MII_WRITE:
5224 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5225 		return (IOC_ACK);
5226 	}
5227 
5228 	/* NOTREACHED */
5229 }
5230 
5231 #if	BGE_SEE_IO32
5232 
5233 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5234 				    struct iocblk *iocp);
5235 #pragma	no_inline(bge_see_ioctl)
5236 
5237 static enum ioc_reply
5238 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5239 {
5240 	struct bge_see_rw *seerwp;
5241 
5242 	/*
5243 	 * Validate format of ioctl
5244 	 */
5245 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
5246 		return (IOC_INVAL);
5247 	if (mp->b_cont == NULL)
5248 		return (IOC_INVAL);
5249 	seerwp = (void *)mp->b_cont->b_rptr;
5250 
5251 	/*
5252 	 * Validate request parameters ...
5253 	 */
5254 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5255 		return (IOC_INVAL);
5256 
5257 	switch (cmd) {
5258 	default:
5259 		/* NOTREACHED */
5260 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5261 		return (IOC_INVAL);
5262 
5263 	case BGE_SEE_READ:
5264 	case BGE_SEE_WRITE:
5265 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5266 		    seerwp->see_addr, &seerwp->see_data);
5267 		return (IOC_REPLY);
5268 	}
5269 
5270 	/* NOTREACHED */
5271 }
5272 
5273 #endif	/* BGE_SEE_IO32 */
5274 
5275 #if	BGE_FLASH_IO32
5276 
5277 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5278 				    struct iocblk *iocp);
5279 #pragma	no_inline(bge_flash_ioctl)
5280 
5281 static enum ioc_reply
5282 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5283 {
5284 	struct bge_flash_rw *flashrwp;
5285 
5286 	/*
5287 	 * Validate format of ioctl
5288 	 */
5289 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5290 		return (IOC_INVAL);
5291 	if (mp->b_cont == NULL)
5292 		return (IOC_INVAL);
5293 	flashrwp = (void *)mp->b_cont->b_rptr;
5294 
5295 	/*
5296 	 * Validate request parameters ...
5297 	 */
5298 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5299 		return (IOC_INVAL);
5300 
5301 	switch (cmd) {
5302 	default:
5303 		/* NOTREACHED */
5304 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5305 		return (IOC_INVAL);
5306 
5307 	case BGE_FLASH_READ:
5308 	case BGE_FLASH_WRITE:
5309 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5310 		    flashrwp->flash_addr, &flashrwp->flash_data);
5311 		return (IOC_REPLY);
5312 	}
5313 
5314 	/* NOTREACHED */
5315 }
5316 
5317 #endif	/* BGE_FLASH_IO32 */
5318 
5319 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5320 				struct iocblk *iocp);
5321 #pragma	no_inline(bge_chip_ioctl)
5322 
5323 enum ioc_reply
5324 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5325 {
5326 	int cmd;
5327 
5328 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5329 	    (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5330 
5331 	ASSERT(mutex_owned(bgep->genlock));
5332 
5333 	cmd = iocp->ioc_cmd;
5334 	switch (cmd) {
5335 	default:
5336 		/* NOTREACHED */
5337 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5338 		return (IOC_INVAL);
5339 
5340 	case BGE_DIAG:
5341 	case BGE_PEEK:
5342 	case BGE_POKE:
5343 	case BGE_PHY_RESET:
5344 	case BGE_SOFT_RESET:
5345 	case BGE_HARD_RESET:
5346 #if	BGE_DEBUGGING || BGE_DO_PPIO
5347 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5348 #else
5349 		return (IOC_INVAL);
5350 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5351 
5352 	case BGE_MII_READ:
5353 	case BGE_MII_WRITE:
5354 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5355 
5356 #if	BGE_SEE_IO32
5357 	case BGE_SEE_READ:
5358 	case BGE_SEE_WRITE:
5359 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
5360 #endif	/* BGE_SEE_IO32 */
5361 
5362 #if	BGE_FLASH_IO32
5363 	case BGE_FLASH_READ:
5364 	case BGE_FLASH_WRITE:
5365 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5366 #endif	/* BGE_FLASH_IO32 */
5367 	}
5368 
5369 	/* NOTREACHED */
5370 }
5371 
5372 void
5373 bge_chip_blank(void *arg, time_t ticks, uint_t count)
5374 {
5375 	bge_t *bgep = arg;
5376 
5377 	mutex_enter(bgep->genlock);
5378 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5379 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5380 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5381 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5382 	mutex_exit(bgep->genlock);
5383 }
5384 
5385 #ifdef BGE_IPMI_ASF
5386 
5387 uint32_t
5388 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5389 {
5390 	uint32_t data;
5391 
5392 #ifndef __sparc
5393 	if (!bgep->asf_wordswapped) {
5394 		/* a workaround word swap error */
5395 		if (addr & 4)
5396 			addr = addr - 4;
5397 		else
5398 			addr = addr + 4;
5399 	}
5400 #endif
5401 
5402 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5403 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5404 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5405 
5406 	data = LE_32(data);
5407 	return (data);
5408 }
5409 
5410 void
5411 bge_asf_update_status(bge_t *bgep)
5412 {
5413 	uint32_t event;
5414 
5415 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5416 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5417 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
5418 
5419 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5420 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5421 }
5422 
5423 
5424 /*
5425  * The driver is supposed to notify ASF that the OS is still running
5426  * every three seconds, otherwise the management server may attempt
5427  * to reboot the machine.  If it hasn't actually failed, this is
5428  * not a desirable result.  However, this isn't running as a real-time
5429  * thread, and even if it were, it might not be able to generate the
5430  * heartbeat in a timely manner due to system load.  As it isn't a
5431  * significant strain on the machine, we will set the interval to half
5432  * of the required value.
5433  */
5434 void
5435 bge_asf_heartbeat(void *arg)
5436 {
5437 	bge_t *bgep = (bge_t *)arg;
5438 
5439 	mutex_enter(bgep->genlock);
5440 	bge_asf_update_status((bge_t *)bgep);
5441 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5442 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5443 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5444 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5445 	mutex_exit(bgep->genlock);
5446 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5447 	    drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5448 }
5449 
5450 
5451 void
5452 bge_asf_stop_timer(bge_t *bgep)
5453 {
5454 	timeout_id_t tmp_id = 0;
5455 
5456 	while ((bgep->asf_timeout_id != 0) &&
5457 	    (tmp_id != bgep->asf_timeout_id)) {
5458 		tmp_id = bgep->asf_timeout_id;
5459 		(void) untimeout(tmp_id);
5460 	}
5461 	bgep->asf_timeout_id = 0;
5462 }
5463 
5464 
5465 
5466 /*
5467  * This function should be placed at the earliest position of bge_attach().
5468  */
5469 void
5470 bge_asf_get_config(bge_t *bgep)
5471 {
5472 	uint32_t nicsig;
5473 	uint32_t niccfg;
5474 
5475 	bgep->asf_enabled = B_FALSE;
5476 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5477 	if (nicsig == BGE_NIC_DATA_SIG) {
5478 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5479 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5480 			/*
5481 			 * Here, we don't consider BAXTER, because BGE haven't
5482 			 * supported BAXTER (that is 5752). Also, as I know,
5483 			 * BAXTER doesn't support ASF feature.
5484 			 */
5485 			bgep->asf_enabled = B_TRUE;
5486 		else
5487 			bgep->asf_enabled = B_FALSE;
5488 	} else
5489 		bgep->asf_enabled = B_FALSE;
5490 }
5491 
5492 
5493 void
5494 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5495 {
5496 	uint32_t tries;
5497 	uint32_t event;
5498 
5499 	ASSERT(bgep->asf_enabled);
5500 
5501 	/* Issues "pause firmware" command and wait for ACK */
5502 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5503 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5504 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5505 
5506 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5507 	tries = 0;
5508 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5509 		drv_usecwait(1);
5510 		tries ++;
5511 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5512 	}
5513 
5514 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5515 	    BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5516 
5517 	if (bgep->asf_newhandshake) {
5518 		switch (mode) {
5519 		case BGE_INIT_RESET:
5520 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5521 			    BGE_DRV_STATE_START);
5522 			break;
5523 		case BGE_SHUTDOWN_RESET:
5524 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5525 			    BGE_DRV_STATE_UNLOAD);
5526 			break;
5527 		case BGE_SUSPEND_RESET:
5528 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5529 			    BGE_DRV_STATE_SUSPEND);
5530 			break;
5531 		default:
5532 			break;
5533 		}
5534 	}
5535 }
5536 
5537 
5538 void
5539 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5540 {
5541 	switch (mode) {
5542 	case BGE_INIT_RESET:
5543 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5544 		    BGE_DRV_STATE_START);
5545 		break;
5546 	case BGE_SHUTDOWN_RESET:
5547 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5548 		    BGE_DRV_STATE_UNLOAD);
5549 		break;
5550 	case BGE_SUSPEND_RESET:
5551 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5552 		    BGE_DRV_STATE_SUSPEND);
5553 		break;
5554 	default:
5555 		break;
5556 	}
5557 }
5558 
5559 
5560 void
5561 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5562 {
5563 	switch (mode) {
5564 	case BGE_INIT_RESET:
5565 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5566 		    BGE_DRV_STATE_START_DONE);
5567 		break;
5568 	case BGE_SHUTDOWN_RESET:
5569 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5570 		    BGE_DRV_STATE_UNLOAD_DONE);
5571 		break;
5572 	default:
5573 		break;
5574 	}
5575 }
5576 
5577 #endif /* BGE_IPMI_ASF */
5578