1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * bge_intr_max_loop controls the maximum loop number within bge_intr. 164 * When loading NIC with heavy network traffic, it is useful. 165 * Increasing this value could have positive effect to throughput, 166 * but it might also increase ticks of a bge ISR stick on CPU, which might 167 * lead to bad UI interactive experience. So tune this with caution. 168 */ 169 static int bge_intr_max_loop = 1; 170 171 /* 172 * ========== Low-level chip & ring buffer manipulation ========== 173 */ 174 175 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 176 177 178 /* 179 * Config space read-modify-write routines 180 */ 181 182 #if BGE_CFG_IO8 183 184 /* 185 * 8- and 16-bit set/clr operations are not used; all the config registers 186 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 187 * code here, though, in case we ever find that we do want it after all ... 188 */ 189 190 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 191 #pragma inline(bge_cfg_set8) 192 193 static void 194 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 195 { 196 uint8_t regval; 197 198 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 199 (void *)bgep, regno, bits)); 200 201 regval = pci_config_get8(bgep->cfg_handle, regno); 202 203 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 204 (void *)bgep, regno, bits, regval, regval | bits)); 205 206 regval |= bits; 207 pci_config_put8(bgep->cfg_handle, regno, regval); 208 } 209 210 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 211 #pragma inline(bge_cfg_clr8) 212 213 static void 214 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 215 { 216 uint8_t regval; 217 218 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 219 (void *)bgep, regno, bits)); 220 221 regval = pci_config_get8(bgep->cfg_handle, regno); 222 223 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 224 (void *)bgep, regno, bits, regval, regval & ~bits)); 225 226 regval &= ~bits; 227 pci_config_put8(bgep->cfg_handle, regno, regval); 228 } 229 230 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 231 #pragma inline(bge_cfg_set16) 232 233 static void 234 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 235 { 236 uint16_t regval; 237 238 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 239 (void *)bgep, regno, bits)); 240 241 regval = pci_config_get16(bgep->cfg_handle, regno); 242 243 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 244 (void *)bgep, regno, bits, regval, regval | bits)); 245 246 regval |= bits; 247 pci_config_put16(bgep->cfg_handle, regno, regval); 248 } 249 250 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 251 #pragma inline(bge_cfg_clr16) 252 253 static void 254 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 255 { 256 uint16_t regval; 257 258 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 259 (void *)bgep, regno, bits)); 260 261 regval = pci_config_get16(bgep->cfg_handle, regno); 262 263 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 264 (void *)bgep, regno, bits, regval, regval & ~bits)); 265 266 regval &= ~bits; 267 pci_config_put16(bgep->cfg_handle, regno, regval); 268 } 269 270 #endif /* BGE_CFG_IO8 */ 271 272 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 273 #pragma inline(bge_cfg_set32) 274 275 static void 276 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 277 { 278 uint32_t regval; 279 280 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 281 (void *)bgep, regno, bits)); 282 283 regval = pci_config_get32(bgep->cfg_handle, regno); 284 285 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 286 (void *)bgep, regno, bits, regval, regval | bits)); 287 288 regval |= bits; 289 pci_config_put32(bgep->cfg_handle, regno, regval); 290 } 291 292 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 293 #pragma inline(bge_cfg_clr32) 294 295 static void 296 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 297 { 298 uint32_t regval; 299 300 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 301 (void *)bgep, regno, bits)); 302 303 regval = pci_config_get32(bgep->cfg_handle, regno); 304 305 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 306 (void *)bgep, regno, bits, regval, regval & ~bits)); 307 308 regval &= ~bits; 309 pci_config_put32(bgep->cfg_handle, regno, regval); 310 } 311 312 #if BGE_IND_IO32 313 314 /* 315 * Indirect access to registers & RISC scratchpads, using config space 316 * accesses only. 317 * 318 * This isn't currently used, but someday we might want to use it for 319 * restoring the Subsystem Device/Vendor registers (which aren't directly 320 * writable in Config Space), or for downloading firmware into the RISCs 321 * 322 * In any case there are endian issues to be resolved before this code is 323 * enabled; the bizarre way that bytes get twisted by this chip AND by 324 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 325 * it's been thoroughly tested for all access sizes on all supported 326 * architectures (SPARC *and* x86!). 327 */ 328 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 329 #pragma inline(bge_ind_get32) 330 331 uint32_t 332 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 333 { 334 uint32_t val; 335 336 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 337 338 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 339 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 340 341 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 342 (void *)bgep, regno, val)); 343 344 val = LE_32(val); 345 346 return (val); 347 } 348 349 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 350 #pragma inline(bge_ind_put32) 351 352 void 353 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 354 { 355 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 356 (void *)bgep, regno, val)); 357 358 val = LE_32(val); 359 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 360 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 361 } 362 363 #endif /* BGE_IND_IO32 */ 364 365 #if BGE_DEBUGGING 366 367 static void bge_pci_check(bge_t *bgep); 368 #pragma no_inline(bge_pci_check) 369 370 static void 371 bge_pci_check(bge_t *bgep) 372 { 373 uint16_t pcistatus; 374 375 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 376 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 377 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 378 (void *)bgep, pcistatus)); 379 } 380 381 #endif /* BGE_DEBUGGING */ 382 383 /* 384 * Perform first-stage chip (re-)initialisation, using only config-space 385 * accesses: 386 * 387 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 388 * returning the data in the structure pointed to by <idp>. 389 * + Configure the target-mode endianness (swap) options. 390 * + Disable interrupts and enable Memory Space accesses. 391 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 392 * 393 * This sequence is adapted from Broadcom document 570X-PG102-R, 394 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 395 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 396 * 397 * This function MUST be called before any non-config-space accesses 398 * are made; on this first call <enable_dma> is B_FALSE, and it 399 * effectively performs steps 3-1(!) of the initialisation sequence 400 * (the rest are not required but should be harmless). 401 * 402 * It MUST also be called after a chip reset, as this disables 403 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 404 * it is effectively performing steps 6-8. 405 */ 406 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 407 #pragma no_inline(bge_chip_cfg_init) 408 409 void 410 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 411 { 412 ddi_acc_handle_t handle; 413 uint16_t command; 414 uint32_t mhcr; 415 uint16_t value16; 416 int i; 417 418 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 419 (void *)bgep, (void *)cidp, enable_dma)); 420 421 /* 422 * Step 3: save PCI cache line size and subsystem vendor ID 423 * 424 * Read all the config-space registers that characterise the 425 * chip, specifically vendor/device/revision/subsystem vendor 426 * and subsystem device id. We expect (but don't check) that 427 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 428 * 429 * Also save all bus-transaction related registers (cache-line 430 * size, bus-grant/latency parameters, etc). Some of these are 431 * cleared by reset, so we'll have to restore them later. This 432 * comes from the Broadcom document 570X-PG102-R ... 433 * 434 * Note: Broadcom document 570X-PG102-R seems to be in error 435 * here w.r.t. the offsets of the Subsystem Vendor ID and 436 * Subsystem (Device) ID registers, which are the opposite way 437 * round according to the PCI standard. For good measure, we 438 * save/restore both anyway. 439 */ 440 handle = bgep->cfg_handle; 441 442 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 443 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 444 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 445 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 446 447 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 448 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 449 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 450 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 451 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 452 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 453 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 454 455 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 456 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 457 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 458 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 459 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 460 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 461 cidp->vendor, cidp->device, cidp->revision)); 462 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 463 cidp->subven, cidp->subdev, cidp->asic_rev)); 464 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 465 cidp->clsize, cidp->latency, cidp->command)); 466 467 /* 468 * Step 2 (also step 6): disable and clear interrupts. 469 * Steps 11-13: configure PIO endianness options, and enable 470 * indirect register access. We'll also select any other 471 * options controlled by the MHCR (e.g. tagged status, mask 472 * interrupt mode) at this stage ... 473 * 474 * Note: internally, the chip is 64-bit and BIG-endian, but 475 * since it talks to the host over a (LITTLE-endian) PCI bus, 476 * it normally swaps bytes around at the PCI interface. 477 * However, the PCI host bridge on SPARC systems normally 478 * swaps the byte lanes around too, since SPARCs are also 479 * BIG-endian. So it turns out that on SPARC, the right 480 * option is to tell the chip to swap (and the host bridge 481 * will swap back again), whereas on x86 we ask the chip 482 * NOT to swap, so the natural little-endianness of the 483 * PCI bus is assumed. Then the only thing that doesn't 484 * automatically work right is access to an 8-byte register 485 * by a little-endian host; but we don't want to set the 486 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 487 * accesses don't go where expected ;-( So we live with 488 * that, and perform word-swaps in software in the few cases 489 * where a chip register is defined as an 8-byte value -- 490 * see the code below for details ... 491 * 492 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 493 * very clear in the register description in the PRM, but 494 * Broadcom document 570X-PG104-R page 248 explains a little 495 * more (under "Broadcom Mask Mode"). The bit changes the way 496 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 497 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 498 * way as the 5700 did, which isn't very convenient. Setting 499 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 500 * bit do just what its name says -- MASK the PCI #INTA output 501 * (i.e. deassert the signal at the pin) leaving all internal 502 * state unchanged. This is much more convenient for our 503 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 504 * 505 * Note: the inconvenient semantics of the interrupt mailbox 506 * (nonzero disables and acknowledges/clears the interrupt, 507 * zero enables AND CLEARS it) would make race conditions 508 * likely in the interrupt handler: 509 * 510 * (1) acknowledge & disable interrupts 511 * (2) while (more to do) 512 * process packets 513 * (3) enable interrupts -- also clears pending 514 * 515 * If the chip received more packets and internally generated 516 * an interrupt between the check at (2) and the mbox write 517 * at (3), this interrupt would be lost :-( 518 * 519 * The best way to avoid this is to use TAGGED STATUS mode, 520 * where the chip includes a unique tag in each status block 521 * update, and the host, when re-enabling interrupts, passes 522 * the last tag it saw back to the chip; then the chip can 523 * see whether the host is truly up to date, and regenerate 524 * its interrupt if not. 525 */ 526 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 527 MHCR_ENABLE_TAGGED_STATUS_MODE | 528 MHCR_MASK_INTERRUPT_MODE | 529 MHCR_CLEAR_INTERRUPT_INTA; 530 531 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 532 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 533 534 #ifdef _BIG_ENDIAN 535 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 536 #endif /* _BIG_ENDIAN */ 537 538 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 539 540 #ifdef BGE_IPMI_ASF 541 bgep->asf_wordswapped = B_FALSE; 542 #endif 543 /* 544 * Step 1 (also step 7): Enable PCI Memory Space accesses 545 * Disable Memory Write/Invalidate 546 * Enable or disable Bus Mastering 547 * 548 * Note that all other bits are taken from the original value saved 549 * the first time through here, rather than from the current register 550 * value, 'cos that will have been cleared by a soft RESET since. 551 * In this way we preserve the OBP/nexus-parent's preferred settings 552 * of the parity-error and system-error enable bits across multiple 553 * chip RESETs. 554 */ 555 command = bgep->chipid.command | PCI_COMM_MAE; 556 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 557 if (enable_dma) 558 command |= PCI_COMM_ME; 559 /* 560 * on BCM5714 revision A0, false parity error gets generated 561 * due to a logic bug. Provide a workaround by disabling parity 562 * error. 563 */ 564 if (((cidp->device == DEVICE_ID_5714C) || 565 (cidp->device == DEVICE_ID_5714S)) && 566 (cidp->revision == REVISION_ID_5714_A0)) { 567 command &= ~PCI_COMM_PARITY_DETECT; 568 } 569 pci_config_put16(handle, PCI_CONF_COMM, command); 570 571 /* 572 * On some PCI-E device, there were instances when 573 * the device was still link training. 574 */ 575 if (bgep->chipid.pci_type == BGE_PCI_E) { 576 i = 0; 577 value16 = pci_config_get16(handle, PCI_CONF_COMM); 578 while ((value16 != command) && (i < 100)) { 579 drv_usecwait(200); 580 value16 = pci_config_get16(handle, PCI_CONF_COMM); 581 ++i; 582 } 583 } 584 585 /* 586 * Clear any remaining error status bits 587 */ 588 pci_config_put16(handle, PCI_CONF_STAT, ~0); 589 590 /* 591 * Do following if and only if the device is NOT BCM5714C OR 592 * BCM5715C 593 */ 594 if (!((cidp->device == DEVICE_ID_5714C) || 595 (cidp->device == DEVICE_ID_5715C))) { 596 /* 597 * Make sure these indirect-access registers are sane 598 * rather than random after power-up or reset 599 */ 600 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 601 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 602 } 603 /* 604 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 605 */ 606 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 607 608 if (cidp->pci_type == BGE_PCI_E) 609 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 610 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 611 } 612 613 #ifdef __amd64 614 /* 615 * Distinguish CPU types 616 * 617 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 618 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 619 * for PCI-Express based network interface card. This is the work-around 620 * for those nics. 621 */ 622 static boolean_t bge_get_em64t_type(void); 623 #pragma inline(bge_get_em64t_type) 624 625 static boolean_t 626 bge_get_em64t_type(void) 627 { 628 629 return (x86_vendor == X86_VENDOR_Intel); 630 } 631 #endif 632 633 /* 634 * Operating register get/set access routines 635 */ 636 637 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 638 #pragma inline(bge_reg_get32) 639 640 uint32_t 641 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 642 { 643 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 644 (void *)bgep, regno)); 645 646 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 647 } 648 649 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 650 #pragma inline(bge_reg_put32) 651 652 void 653 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 654 { 655 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 656 (void *)bgep, regno, data)); 657 658 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 659 BGE_PCICHK(bgep); 660 } 661 662 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 663 #pragma inline(bge_reg_set32) 664 665 void 666 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 667 { 668 uint32_t regval; 669 670 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 671 (void *)bgep, regno, bits)); 672 673 regval = bge_reg_get32(bgep, regno); 674 regval |= bits; 675 bge_reg_put32(bgep, regno, regval); 676 } 677 678 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 679 #pragma inline(bge_reg_clr32) 680 681 void 682 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 683 { 684 uint32_t regval; 685 686 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 687 (void *)bgep, regno, bits)); 688 689 regval = bge_reg_get32(bgep, regno); 690 regval &= ~bits; 691 bge_reg_put32(bgep, regno, regval); 692 } 693 694 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 695 #pragma inline(bge_reg_get64) 696 697 static uint64_t 698 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 699 { 700 uint64_t regval; 701 702 #ifdef __amd64 703 if (bge_get_em64t_type()) { 704 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 705 regval <<= 32; 706 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 707 } else { 708 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 709 } 710 #else 711 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 712 #endif 713 714 #ifdef _LITTLE_ENDIAN 715 regval = (regval >> 32) | (regval << 32); 716 #endif /* _LITTLE_ENDIAN */ 717 718 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 719 (void *)bgep, regno, regval)); 720 721 return (regval); 722 } 723 724 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 725 #pragma inline(bge_reg_put64) 726 727 static void 728 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 729 { 730 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 731 (void *)bgep, regno, data)); 732 733 #ifdef _LITTLE_ENDIAN 734 data = ((data >> 32) | (data << 32)); 735 #endif /* _LITTLE_ENDIAN */ 736 737 #ifdef __amd64 738 if (bge_get_em64t_type()) { 739 ddi_put32(bgep->io_handle, 740 PIO_ADDR(bgep, regno), (uint32_t)data); 741 BGE_PCICHK(bgep); 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 744 745 } else { 746 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 747 } 748 #else 749 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 750 #endif 751 752 BGE_PCICHK(bgep); 753 } 754 755 /* 756 * The DDI doesn't provide get/put functions for 128 bit data 757 * so we put RCBs out as two 64-bit chunks instead. 758 */ 759 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 760 #pragma inline(bge_reg_putrcb) 761 762 static void 763 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 764 { 765 uint64_t *p; 766 767 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 768 (void *)bgep, addr, rcbp->host_ring_addr, 769 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 770 771 ASSERT((addr % sizeof (*rcbp)) == 0); 772 773 p = (void *)rcbp; 774 bge_reg_put64(bgep, addr, *p++); 775 bge_reg_put64(bgep, addr+8, *p); 776 } 777 778 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 779 #pragma inline(bge_mbx_put) 780 781 void 782 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 783 { 784 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 785 (void *)bgep, regno, data)); 786 787 /* 788 * Mailbox registers are nominally 64 bits on the 5701, but 789 * the MSW isn't used. On the 5703, they're only 32 bits 790 * anyway. So here we just write the lower(!) 32 bits - 791 * remembering that the chip is big-endian, even though the 792 * PCI bus is little-endian ... 793 */ 794 #ifdef _BIG_ENDIAN 795 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 796 #else 797 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 798 #endif /* _BIG_ENDIAN */ 799 BGE_PCICHK(bgep); 800 } 801 802 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 803 #pragma inline(bge_mbx_get) 804 805 uint32_t 806 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 807 { 808 uint32_t val32; 809 810 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 811 (void *)bgep, regno)); 812 813 #ifdef _BIG_ENDIAN 814 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 815 #else 816 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 817 #endif /* _BIG_ENDIAN */ 818 BGE_PCICHK(bgep); 819 820 return (val32); 821 } 822 823 824 #if BGE_DEBUGGING 825 826 void bge_led_mark(bge_t *bgep); 827 #pragma no_inline(bge_led_mark) 828 829 void 830 bge_led_mark(bge_t *bgep) 831 { 832 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 833 LED_CONTROL_1000MBPS_LED | 834 LED_CONTROL_100MBPS_LED | 835 LED_CONTROL_10MBPS_LED; 836 837 /* 838 * Blink all three LINK LEDs on simultaneously, then all off, 839 * then restore to automatic hardware control. This is used 840 * in laboratory testing to trigger a logic analyser or scope. 841 */ 842 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 843 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 844 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 845 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 846 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 847 } 848 849 #endif /* BGE_DEBUGGING */ 850 851 /* 852 * NIC on-chip memory access routines 853 * 854 * Only 32K of NIC memory is visible at a time, controlled by the 855 * Memory Window Base Address Register (in PCI config space). Once 856 * this is set, the 32K region of NIC-local memory that it refers 857 * to can be directly addressed in the upper 32K of the 64K of PCI 858 * memory space used for the device. 859 */ 860 861 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 862 #pragma inline(bge_nic_setwin) 863 864 static void 865 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 866 { 867 chip_id_t *cidp; 868 869 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 870 (void *)bgep, base)); 871 872 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 873 874 /* 875 * Don't do repeated zero data writes, 876 * if the device is BCM5714C/15C. 877 */ 878 cidp = &bgep->chipid; 879 if ((cidp->device == DEVICE_ID_5714C) || 880 (cidp->device == DEVICE_ID_5715C)) { 881 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 882 return; 883 /* Adjust lastWriteZeroData */ 884 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 885 B_TRUE : B_FALSE); 886 } 887 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 888 } 889 890 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 891 #pragma inline(bge_nic_get32) 892 893 static uint32_t 894 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 895 { 896 uint32_t data; 897 898 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 899 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 900 /* workaround for word swap error */ 901 if (addr & 4) 902 addr = addr - 4; 903 else 904 addr = addr + 4; 905 } 906 #endif 907 908 #ifdef __sparc 909 data = bge_nic_read32(bgep, addr); 910 #else 911 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 912 addr &= MWBAR_GRANULE_MASK; 913 addr += NIC_MEM_WINDOW_OFFSET; 914 915 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 916 #endif 917 918 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 919 (void *)bgep, addr, data)); 920 921 return (data); 922 } 923 924 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 925 #pragma inline(bge_nic_put32) 926 927 void 928 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 929 { 930 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 931 (void *)bgep, addr, data)); 932 933 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 934 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 935 /* workaround for word swap error */ 936 if (addr & 4) 937 addr = addr - 4; 938 else 939 addr = addr + 4; 940 } 941 #endif 942 943 #ifdef __sparc 944 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 945 data = LE_32(data); 946 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 947 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 948 #else 949 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 950 addr &= MWBAR_GRANULE_MASK; 951 addr += NIC_MEM_WINDOW_OFFSET; 952 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 953 BGE_PCICHK(bgep); 954 #endif 955 } 956 957 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 958 #pragma inline(bge_nic_get64) 959 960 static uint64_t 961 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 962 { 963 uint64_t data; 964 965 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 966 addr &= MWBAR_GRANULE_MASK; 967 addr += NIC_MEM_WINDOW_OFFSET; 968 969 #ifdef __amd64 970 if (bge_get_em64t_type()) { 971 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 972 data <<= 32; 973 data |= ddi_get32(bgep->io_handle, 974 PIO_ADDR(bgep, addr + 4)); 975 } else { 976 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 977 } 978 #else 979 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 980 #endif 981 982 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 983 (void *)bgep, addr, data)); 984 985 return (data); 986 } 987 988 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 989 #pragma inline(bge_nic_put64) 990 991 static void 992 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 993 { 994 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 995 (void *)bgep, addr, data)); 996 997 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 998 addr &= MWBAR_GRANULE_MASK; 999 addr += NIC_MEM_WINDOW_OFFSET; 1000 1001 #ifdef __amd64 1002 if (bge_get_em64t_type()) { 1003 ddi_put32(bgep->io_handle, 1004 PIO_ADDR(bgep, addr), (uint32_t)data); 1005 BGE_PCICHK(bgep); 1006 ddi_put32(bgep->io_handle, 1007 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 1008 } else { 1009 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1010 } 1011 #else 1012 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1013 #endif 1014 1015 BGE_PCICHK(bgep); 1016 } 1017 1018 /* 1019 * The DDI doesn't provide get/put functions for 128 bit data 1020 * so we put RCBs out as two 64-bit chunks instead. 1021 */ 1022 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1023 #pragma inline(bge_nic_putrcb) 1024 1025 static void 1026 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1027 { 1028 uint64_t *p; 1029 1030 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1031 (void *)bgep, addr, rcbp->host_ring_addr, 1032 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1033 1034 ASSERT((addr % sizeof (*rcbp)) == 0); 1035 1036 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1037 addr &= MWBAR_GRANULE_MASK; 1038 addr += NIC_MEM_WINDOW_OFFSET; 1039 1040 p = (void *)rcbp; 1041 #ifdef __amd64 1042 if (bge_get_em64t_type()) { 1043 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1044 (uint32_t)(*p)); 1045 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1046 (uint32_t)(*p >> 32)); 1047 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1048 (uint32_t)(*(p + 1))); 1049 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1050 (uint32_t)(*p >> 32)); 1051 1052 } else { 1053 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1054 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1055 } 1056 #else 1057 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1058 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1059 #endif 1060 1061 BGE_PCICHK(bgep); 1062 } 1063 1064 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1065 #pragma inline(bge_nic_zero) 1066 1067 static void 1068 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1069 { 1070 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1071 (void *)bgep, addr, nbytes)); 1072 1073 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1074 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1075 1076 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1077 addr &= MWBAR_GRANULE_MASK; 1078 addr += NIC_MEM_WINDOW_OFFSET; 1079 1080 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1081 nbytes, 1, DDI_DATA_SZ08_ACC); 1082 BGE_PCICHK(bgep); 1083 } 1084 1085 /* 1086 * MII (PHY) register get/set access routines 1087 * 1088 * These use the chip's MII auto-access method, controlled by the 1089 * MII Communication register at 0x044c, so the CPU doesn't have 1090 * to fiddle with the individual bits. 1091 */ 1092 1093 #undef BGE_DBG 1094 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1095 1096 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1097 uint16_t data, uint32_t cmd); 1098 #pragma no_inline(bge_mii_access) 1099 1100 static uint16_t 1101 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1102 { 1103 uint32_t timeout; 1104 uint32_t regval1; 1105 uint32_t regval2; 1106 1107 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1108 (void *)bgep, regno, data, cmd)); 1109 1110 ASSERT(mutex_owned(bgep->genlock)); 1111 1112 /* 1113 * Assemble the command ... 1114 */ 1115 cmd |= data << MI_COMMS_DATA_SHIFT; 1116 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1117 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1118 cmd |= MI_COMMS_START; 1119 1120 /* 1121 * Wait for any command already in progress ... 1122 * 1123 * Note: this *shouldn't* ever find that there is a command 1124 * in progress, because we already hold the <genlock> mutex. 1125 * Nonetheless, we have sometimes seen the MI_COMMS_START 1126 * bit set here -- it seems that the chip can initiate MII 1127 * accesses internally, even with polling OFF. 1128 */ 1129 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1130 for (timeout = 100; ; ) { 1131 if ((regval2 & MI_COMMS_START) == 0) { 1132 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1133 break; 1134 } 1135 if (--timeout == 0) 1136 break; 1137 drv_usecwait(10); 1138 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1139 } 1140 1141 if (timeout == 0) 1142 return ((uint16_t)~0u); 1143 1144 if (timeout != 100) 1145 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1146 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1147 cmd, 10*(100-timeout), regval1, regval2)); 1148 1149 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1150 for (timeout = 1000; ; ) { 1151 if ((regval1 & MI_COMMS_START) == 0) 1152 break; 1153 if (--timeout == 0) 1154 break; 1155 drv_usecwait(10); 1156 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1157 } 1158 1159 /* 1160 * Drop out early if the READ FAILED bit is set -- this chip 1161 * could be a 5703/4S, with a SerDes instead of a PHY! 1162 */ 1163 if (regval2 & MI_COMMS_READ_FAILED) 1164 return ((uint16_t)~0u); 1165 1166 if (timeout == 0) 1167 return ((uint16_t)~0u); 1168 1169 /* 1170 * The PRM says to wait 5us after seeing the START bit clear 1171 * and then re-read the register to get the final value of the 1172 * data field, in order to avoid a race condition where the 1173 * START bit is clear but the data field isn't yet valid. 1174 * 1175 * Note: we don't actually seem to be encounter this race; 1176 * except when the START bit is seen set again (see below), 1177 * the data field doesn't change during this 5us interval. 1178 */ 1179 drv_usecwait(5); 1180 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1181 1182 /* 1183 * Unfortunately, when following the PRMs instructions above, 1184 * we have occasionally seen the START bit set again(!) in the 1185 * value read after the 5us delay. This seems to be due to the 1186 * chip autonomously starting another MII access internally. 1187 * In such cases, the command/data/etc fields relate to the 1188 * internal command, rather than the one that we thought had 1189 * just finished. So in this case, we fall back to returning 1190 * the data from the original read that showed START clear. 1191 */ 1192 if (regval2 & MI_COMMS_START) { 1193 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1194 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1195 cmd, regval1, regval2)); 1196 regval2 = regval1; 1197 } 1198 1199 if (regval2 & MI_COMMS_START) 1200 return ((uint16_t)~0u); 1201 1202 if (regval2 & MI_COMMS_READ_FAILED) 1203 return ((uint16_t)~0u); 1204 1205 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1206 } 1207 1208 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1209 #pragma no_inline(bge_mii_get16) 1210 1211 uint16_t 1212 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1213 { 1214 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1215 (void *)bgep, regno)); 1216 1217 ASSERT(mutex_owned(bgep->genlock)); 1218 1219 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1220 } 1221 1222 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1223 #pragma no_inline(bge_mii_put16) 1224 1225 void 1226 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1227 { 1228 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1229 (void *)bgep, regno, data)); 1230 1231 ASSERT(mutex_owned(bgep->genlock)); 1232 1233 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1234 } 1235 1236 #undef BGE_DBG 1237 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1238 1239 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1240 1241 /* 1242 * Basic SEEPROM get/set access routine 1243 * 1244 * This uses the chip's SEEPROM auto-access method, controlled by the 1245 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1246 * doesn't have to fiddle with the individual bits. 1247 * 1248 * The caller should hold <genlock> and *also* have already acquired 1249 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1250 * 1251 * Return value: 1252 * 0 on success, 1253 * ENODATA on access timeout (maybe retryable: device may just be busy) 1254 * EPROTO on other h/w or s/w errors. 1255 * 1256 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1257 * from a (successful) SEEPROM_ACCESS_READ. 1258 */ 1259 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1260 uint32_t *dp); 1261 #pragma no_inline(bge_seeprom_access) 1262 1263 static int 1264 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1265 { 1266 uint32_t tries; 1267 uint32_t regval; 1268 1269 ASSERT(mutex_owned(bgep->genlock)); 1270 1271 /* 1272 * On the newer chips that support both SEEPROM & Flash, we need 1273 * to specifically enable SEEPROM access (Flash is the default). 1274 * On older chips, we don't; SEEPROM is the only NVtype supported, 1275 * and the NVM control registers don't exist ... 1276 */ 1277 switch (bgep->chipid.nvtype) { 1278 case BGE_NVTYPE_NONE: 1279 case BGE_NVTYPE_UNKNOWN: 1280 _NOTE(NOTREACHED) 1281 case BGE_NVTYPE_SEEPROM: 1282 break; 1283 1284 case BGE_NVTYPE_LEGACY_SEEPROM: 1285 case BGE_NVTYPE_UNBUFFERED_FLASH: 1286 case BGE_NVTYPE_BUFFERED_FLASH: 1287 default: 1288 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1289 NVM_CFG1_LEGACY_SEEPROM_MODE); 1290 break; 1291 } 1292 1293 /* 1294 * Check there's no command in progress. 1295 * 1296 * Note: this *shouldn't* ever find that there is a command 1297 * in progress, because we already hold the <genlock> mutex. 1298 * Also, to ensure we don't have a conflict with the chip's 1299 * internal firmware or a process accessing the same (shared) 1300 * SEEPROM through the other port of a 5704, we've already 1301 * been through the "software arbitration" protocol. 1302 * So this is just a final consistency check: we shouldn't 1303 * see EITHER the START bit (command started but not complete) 1304 * OR the COMPLETE bit (command completed but not cleared). 1305 */ 1306 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1307 if (regval & SEEPROM_ACCESS_START) 1308 return (EPROTO); 1309 if (regval & SEEPROM_ACCESS_COMPLETE) 1310 return (EPROTO); 1311 1312 /* 1313 * Assemble the command ... 1314 */ 1315 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1316 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1317 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1318 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1319 cmd |= SEEPROM_ACCESS_START; 1320 cmd |= SEEPROM_ACCESS_COMPLETE; 1321 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1322 1323 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1324 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1325 1326 /* 1327 * By observation, a successful access takes ~20us on a 5703/4, 1328 * but apparently much longer (up to 1000us) on the obsolescent 1329 * BCM5700/BCM5701. We want to be sure we don't get any false 1330 * timeouts here; but OTOH, we don't want a bogus access to lock 1331 * out interrupts for longer than necessary. So we'll allow up 1332 * to 1000us ... 1333 */ 1334 for (tries = 0; tries < 1000; ++tries) { 1335 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1336 if (regval & SEEPROM_ACCESS_COMPLETE) 1337 break; 1338 drv_usecwait(1); 1339 } 1340 1341 if (regval & SEEPROM_ACCESS_COMPLETE) { 1342 /* 1343 * All OK; read the SEEPROM data register, then write back 1344 * the value read from the address register in order to 1345 * clear the <complete> bit and leave the SEEPROM access 1346 * state machine idle, ready for the next access ... 1347 */ 1348 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1349 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1350 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1351 return (0); 1352 } 1353 1354 /* 1355 * Hmm ... what happened here? 1356 * 1357 * Most likely, the user addressed a non-existent SEEPROM. Or 1358 * maybe the SEEPROM was busy internally (e.g. processing a write) 1359 * and didn't respond to being addressed. Either way, it's left 1360 * the SEEPROM access state machine wedged. So we'll reset it 1361 * before we leave, so it's ready for next time ... 1362 */ 1363 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1364 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1365 return (ENODATA); 1366 } 1367 1368 /* 1369 * Basic Flash get/set access routine 1370 * 1371 * These use the chip's Flash auto-access method, controlled by the 1372 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1373 * fiddle with the individual bits. 1374 * 1375 * The caller should hold <genlock> and *also* have already acquired 1376 * the right to access the Flash, via bge_nvmem_acquire() above. 1377 * 1378 * Return value: 1379 * 0 on success, 1380 * ENODATA on access timeout (maybe retryable: device may just be busy) 1381 * ENODEV if the NVmem device is missing or otherwise unusable 1382 * 1383 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1384 * from a (successful) NVM_FLASH_CMD_RD. 1385 */ 1386 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1387 uint32_t *dp); 1388 #pragma no_inline(bge_flash_access) 1389 1390 static int 1391 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1392 { 1393 uint32_t tries; 1394 uint32_t regval; 1395 1396 ASSERT(mutex_owned(bgep->genlock)); 1397 1398 /* 1399 * On the newer chips that support both SEEPROM & Flash, we need 1400 * to specifically disable SEEPROM access while accessing Flash. 1401 * The older chips don't support Flash, and the NVM registers don't 1402 * exist, so we shouldn't be here at all! 1403 */ 1404 switch (bgep->chipid.nvtype) { 1405 case BGE_NVTYPE_NONE: 1406 case BGE_NVTYPE_UNKNOWN: 1407 _NOTE(NOTREACHED) 1408 case BGE_NVTYPE_SEEPROM: 1409 return (ENODEV); 1410 1411 case BGE_NVTYPE_LEGACY_SEEPROM: 1412 case BGE_NVTYPE_UNBUFFERED_FLASH: 1413 case BGE_NVTYPE_BUFFERED_FLASH: 1414 default: 1415 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1416 NVM_CFG1_LEGACY_SEEPROM_MODE); 1417 break; 1418 } 1419 1420 /* 1421 * Assemble the command ... 1422 */ 1423 addr &= NVM_FLASH_ADDR_MASK; 1424 cmd |= NVM_FLASH_CMD_DOIT; 1425 cmd |= NVM_FLASH_CMD_FIRST; 1426 cmd |= NVM_FLASH_CMD_LAST; 1427 cmd |= NVM_FLASH_CMD_DONE; 1428 1429 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1430 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1431 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1432 1433 /* 1434 * Allow up to 1000ms ... 1435 */ 1436 for (tries = 0; tries < 1000; ++tries) { 1437 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1438 if (regval & NVM_FLASH_CMD_DONE) 1439 break; 1440 drv_usecwait(1); 1441 } 1442 1443 if (regval & NVM_FLASH_CMD_DONE) { 1444 /* 1445 * All OK; read the data from the Flash read register 1446 */ 1447 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1448 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1449 return (0); 1450 } 1451 1452 /* 1453 * Hmm ... what happened here? 1454 * 1455 * Most likely, the user addressed a non-existent Flash. Or 1456 * maybe the Flash was busy internally (e.g. processing a write) 1457 * and didn't respond to being addressed. Either way, there's 1458 * nothing we can here ... 1459 */ 1460 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1461 return (ENODATA); 1462 } 1463 1464 /* 1465 * The next two functions regulate access to the NVram (if fitted). 1466 * 1467 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1468 * (SPI) interface, but they can be accessed through either port. These 1469 * are managed by different instance of this driver and have no software 1470 * state in common. 1471 * 1472 * In addition (and even on a single core chip) the chip's internal 1473 * firmware can access the SEEPROM/Flash, most notably after a RESET 1474 * when it may download code to run internally. 1475 * 1476 * So we need to arbitrate between these various software agents. For 1477 * this purpose, the chip provides the Software Arbitration Register, 1478 * which implements hardware(!) arbitration. 1479 * 1480 * This functionality didn't exist on older (5700/5701) chips, so there's 1481 * nothing we can do by way of arbitration on those; also, if there's no 1482 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1483 * nothing to do. 1484 * 1485 * The internal firmware appears to use Request 0, which is the highest 1486 * priority. So we'd like to use Request 2, leaving one higher and one 1487 * lower for any future developments ... but apparently this doesn't 1488 * always work. So for now, the code uses Request 1 ;-( 1489 */ 1490 1491 #define NVM_READ_REQ NVM_READ_REQ1 1492 #define NVM_RESET_REQ NVM_RESET_REQ1 1493 #define NVM_SET_REQ NVM_SET_REQ1 1494 1495 static void bge_nvmem_relinquish(bge_t *bgep); 1496 #pragma no_inline(bge_nvmem_relinquish) 1497 1498 static void 1499 bge_nvmem_relinquish(bge_t *bgep) 1500 { 1501 ASSERT(mutex_owned(bgep->genlock)); 1502 1503 switch (bgep->chipid.nvtype) { 1504 case BGE_NVTYPE_NONE: 1505 case BGE_NVTYPE_UNKNOWN: 1506 _NOTE(NOTREACHED) 1507 return; 1508 1509 case BGE_NVTYPE_SEEPROM: 1510 /* 1511 * No arbitration performed, no release needed 1512 */ 1513 return; 1514 1515 case BGE_NVTYPE_LEGACY_SEEPROM: 1516 case BGE_NVTYPE_UNBUFFERED_FLASH: 1517 case BGE_NVTYPE_BUFFERED_FLASH: 1518 default: 1519 break; 1520 } 1521 1522 /* 1523 * Our own request should be present (whether or not granted) ... 1524 */ 1525 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1526 1527 /* 1528 * ... this will make it go away. 1529 */ 1530 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1531 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1532 } 1533 1534 /* 1535 * Arbitrate for access to the NVmem, if necessary 1536 * 1537 * Return value: 1538 * 0 on success 1539 * EAGAIN if the device is in use (retryable) 1540 * ENODEV if the NVmem device is missing or otherwise unusable 1541 */ 1542 static int bge_nvmem_acquire(bge_t *bgep); 1543 #pragma no_inline(bge_nvmem_acquire) 1544 1545 static int 1546 bge_nvmem_acquire(bge_t *bgep) 1547 { 1548 uint32_t regval; 1549 uint32_t tries; 1550 1551 ASSERT(mutex_owned(bgep->genlock)); 1552 1553 switch (bgep->chipid.nvtype) { 1554 case BGE_NVTYPE_NONE: 1555 case BGE_NVTYPE_UNKNOWN: 1556 /* 1557 * Access denied: no (recognisable) device fitted 1558 */ 1559 return (ENODEV); 1560 1561 case BGE_NVTYPE_SEEPROM: 1562 /* 1563 * Access granted: no arbitration needed (or possible) 1564 */ 1565 return (0); 1566 1567 case BGE_NVTYPE_LEGACY_SEEPROM: 1568 case BGE_NVTYPE_UNBUFFERED_FLASH: 1569 case BGE_NVTYPE_BUFFERED_FLASH: 1570 default: 1571 /* 1572 * Access conditional: conduct arbitration protocol 1573 */ 1574 break; 1575 } 1576 1577 /* 1578 * We're holding the per-port mutex <genlock>, so no-one other 1579 * thread can be attempting to access the NVmem through *this* 1580 * port. But it could be in use by the *other* port (of a 5704), 1581 * or by the chip's internal firmware, so we have to go through 1582 * the full (hardware) arbitration protocol ... 1583 * 1584 * Note that *because* we're holding <genlock>, the interrupt handler 1585 * won't be able to progress. So we're only willing to spin for a 1586 * fairly short time. Specifically: 1587 * 1588 * We *must* wait long enough for the hardware to resolve all 1589 * requests and determine the winner. Fortunately, this is 1590 * "almost instantaneous", even as observed by GHz CPUs. 1591 * 1592 * A successful access by another Solaris thread (via either 1593 * port) typically takes ~20us. So waiting a bit longer than 1594 * that will give a good chance of success, if the other user 1595 * *is* another thread on the other port. 1596 * 1597 * However, the internal firmware can hold on to the NVmem 1598 * for *much* longer: at least 10 milliseconds just after a 1599 * RESET, and maybe even longer if the NVmem actually contains 1600 * code to download and run on the internal CPUs. 1601 * 1602 * So, we'll allow 50us; if that's not enough then it's up to the 1603 * caller to retry later (hence the choice of return code EAGAIN). 1604 */ 1605 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1606 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1607 1608 for (tries = 0; tries < 50; ++tries) { 1609 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1610 if (regval & NVM_WON_REQ1) 1611 break; 1612 drv_usecwait(1); 1613 } 1614 1615 if (regval & NVM_WON_REQ1) { 1616 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1617 return (0); 1618 } 1619 1620 /* 1621 * Somebody else must be accessing the NVmem, so abandon our 1622 * attempt take control of it. The caller can try again later ... 1623 */ 1624 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1625 bge_nvmem_relinquish(bgep); 1626 return (EAGAIN); 1627 } 1628 1629 /* 1630 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1631 * write protect line in such a way that the NVmem is protected when 1632 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1633 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1634 * 1635 * Note: there's only one set of GPIO pins on a 5704, even though they 1636 * can be accessed through either port. So the chip has to resolve what 1637 * happens if the two ports program a single pin differently ... the rule 1638 * it uses is that if the ports disagree about the *direction* of a pin, 1639 * "output" wins over "input", but if they disagree about its *value* as 1640 * an output, then the pin is TRISTATED instead! In such a case, no-one 1641 * wins, and the external signal does whatever the external circuitry 1642 * defines as the default -- which we've assumed is the PROTECTED state. 1643 * So, we always change GPIO1 back to being an *input* whenever we're not 1644 * specifically using it to unprotect the NVmem. This allows either port 1645 * to update the NVmem, although obviously only one at a time! 1646 * 1647 * The caller should hold <genlock> and *also* have already acquired the 1648 * right to access the NVmem, via bge_nvmem_acquire() above. 1649 */ 1650 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1651 #pragma inline(bge_nvmem_protect) 1652 1653 static void 1654 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1655 { 1656 uint32_t regval; 1657 1658 ASSERT(mutex_owned(bgep->genlock)); 1659 1660 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1661 if (protect) { 1662 regval |= MLCR_MISC_PINS_OUTPUT_1; 1663 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1664 } else { 1665 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1666 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1667 } 1668 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1669 } 1670 1671 /* 1672 * Now put it all together ... 1673 * 1674 * Try to acquire control of the NVmem; if successful, then: 1675 * unprotect it (if we want to write to it) 1676 * perform the requested access 1677 * reprotect it (after a write) 1678 * relinquish control 1679 * 1680 * Return value: 1681 * 0 on success, 1682 * EAGAIN if the device is in use (retryable) 1683 * ENODATA on access timeout (maybe retryable: device may just be busy) 1684 * ENODEV if the NVmem device is missing or otherwise unusable 1685 * EPROTO on other h/w or s/w errors. 1686 */ 1687 static int 1688 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1689 { 1690 int err; 1691 1692 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1693 switch (cmd) { 1694 case BGE_SEE_READ: 1695 err = bge_seeprom_access(bgep, 1696 SEEPROM_ACCESS_READ, addr, dp); 1697 break; 1698 1699 case BGE_SEE_WRITE: 1700 bge_nvmem_protect(bgep, B_FALSE); 1701 err = bge_seeprom_access(bgep, 1702 SEEPROM_ACCESS_WRITE, addr, dp); 1703 bge_nvmem_protect(bgep, B_TRUE); 1704 break; 1705 1706 case BGE_FLASH_READ: 1707 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1708 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1709 bge_reg_set32(bgep, NVM_ACCESS_REG, 1710 NVM_ACCESS_ENABLE); 1711 } 1712 err = bge_flash_access(bgep, 1713 NVM_FLASH_CMD_RD, addr, dp); 1714 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1715 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1716 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1717 NVM_ACCESS_ENABLE); 1718 } 1719 break; 1720 1721 case BGE_FLASH_WRITE: 1722 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1723 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1724 bge_reg_set32(bgep, NVM_ACCESS_REG, 1725 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1726 } 1727 bge_nvmem_protect(bgep, B_FALSE); 1728 err = bge_flash_access(bgep, 1729 NVM_FLASH_CMD_WR, addr, dp); 1730 bge_nvmem_protect(bgep, B_TRUE); 1731 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1732 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1733 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1734 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1735 } 1736 1737 break; 1738 1739 default: 1740 _NOTE(NOTREACHED) 1741 break; 1742 } 1743 bge_nvmem_relinquish(bgep); 1744 } 1745 1746 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1747 return (err); 1748 } 1749 1750 /* 1751 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1752 */ 1753 static uint64_t bge_get_nvmac(bge_t *bgep); 1754 #pragma no_inline(bge_get_nvmac) 1755 1756 static uint64_t 1757 bge_get_nvmac(bge_t *bgep) 1758 { 1759 uint32_t mac_high; 1760 uint32_t mac_low; 1761 uint32_t addr; 1762 uint32_t cmd; 1763 uint64_t mac; 1764 1765 BGE_TRACE(("bge_get_nvmac($%p)", 1766 (void *)bgep)); 1767 1768 switch (bgep->chipid.nvtype) { 1769 case BGE_NVTYPE_NONE: 1770 case BGE_NVTYPE_UNKNOWN: 1771 default: 1772 return (0ULL); 1773 1774 case BGE_NVTYPE_SEEPROM: 1775 case BGE_NVTYPE_LEGACY_SEEPROM: 1776 cmd = BGE_SEE_READ; 1777 break; 1778 1779 case BGE_NVTYPE_UNBUFFERED_FLASH: 1780 case BGE_NVTYPE_BUFFERED_FLASH: 1781 cmd = BGE_FLASH_READ; 1782 break; 1783 } 1784 1785 addr = NVMEM_DATA_MAC_ADDRESS; 1786 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1787 return (0ULL); 1788 addr += 4; 1789 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1790 return (0ULL); 1791 1792 /* 1793 * The Broadcom chip is natively BIG-endian, so that's how the 1794 * MAC address is represented in NVmem. We may need to swap it 1795 * around on a little-endian host ... 1796 */ 1797 #ifdef _BIG_ENDIAN 1798 mac = mac_high; 1799 mac = mac << 32; 1800 mac |= mac_low; 1801 #else 1802 mac = BGE_BSWAP_32(mac_high); 1803 mac = mac << 32; 1804 mac |= BGE_BSWAP_32(mac_low); 1805 #endif /* _BIG_ENDIAN */ 1806 1807 return (mac); 1808 } 1809 1810 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1811 1812 /* 1813 * Dummy version for when we're not supporting NVmem access 1814 */ 1815 static uint64_t bge_get_nvmac(bge_t *bgep); 1816 #pragma inline(bge_get_nvmac) 1817 1818 static uint64_t 1819 bge_get_nvmac(bge_t *bgep) 1820 { 1821 _NOTE(ARGUNUSED(bgep)) 1822 return (0ULL); 1823 } 1824 1825 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1826 1827 /* 1828 * Determine the type of NVmem that is (or may be) attached to this chip, 1829 */ 1830 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1831 #pragma no_inline(bge_nvmem_id) 1832 1833 static enum bge_nvmem_type 1834 bge_nvmem_id(bge_t *bgep) 1835 { 1836 enum bge_nvmem_type nvtype; 1837 uint32_t config1; 1838 1839 BGE_TRACE(("bge_nvmem_id($%p)", 1840 (void *)bgep)); 1841 1842 switch (bgep->chipid.device) { 1843 default: 1844 /* 1845 * We shouldn't get here; it means we don't recognise 1846 * the chip, which means we don't know how to determine 1847 * what sort of NVmem (if any) it has. So we'll say 1848 * NONE, to disable the NVmem access code ... 1849 */ 1850 nvtype = BGE_NVTYPE_NONE; 1851 break; 1852 1853 case DEVICE_ID_5700: 1854 case DEVICE_ID_5700x: 1855 case DEVICE_ID_5701: 1856 /* 1857 * These devices support *only* SEEPROMs 1858 */ 1859 nvtype = BGE_NVTYPE_SEEPROM; 1860 break; 1861 1862 case DEVICE_ID_5702: 1863 case DEVICE_ID_5702fe: 1864 case DEVICE_ID_5703C: 1865 case DEVICE_ID_5703S: 1866 case DEVICE_ID_5704C: 1867 case DEVICE_ID_5704S: 1868 case DEVICE_ID_5704: 1869 case DEVICE_ID_5705M: 1870 case DEVICE_ID_5705C: 1871 case DEVICE_ID_5705_2: 1872 case DEVICE_ID_5706: 1873 case DEVICE_ID_5782: 1874 case DEVICE_ID_5788: 1875 case DEVICE_ID_5789: 1876 case DEVICE_ID_5751: 1877 case DEVICE_ID_5751M: 1878 case DEVICE_ID_5752: 1879 case DEVICE_ID_5752M: 1880 case DEVICE_ID_5754: 1881 case DEVICE_ID_5755: 1882 case DEVICE_ID_5755M: 1883 case DEVICE_ID_5721: 1884 case DEVICE_ID_5714C: 1885 case DEVICE_ID_5714S: 1886 case DEVICE_ID_5715C: 1887 case DEVICE_ID_5715S: 1888 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1889 if (config1 & NVM_CFG1_FLASH_MODE) 1890 if (config1 & NVM_CFG1_BUFFERED_MODE) 1891 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1892 else 1893 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1894 else 1895 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1896 break; 1897 } 1898 1899 return (nvtype); 1900 } 1901 1902 #undef BGE_DBG 1903 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1904 1905 static void 1906 bge_init_recv_rule(bge_t *bgep) 1907 { 1908 bge_recv_rule_t *rulep; 1909 uint32_t i; 1910 1911 /* 1912 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1913 * 1. to direct UDP traffic, set: 1914 * rulep->control = RULE_PROTO_CONTROL; 1915 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1916 * 2. to direct ICMP traffic, set: 1917 * rulep->control = RULE_PROTO_CONTROL; 1918 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1919 * 3. to direct traffic by source ip, set: 1920 * rulep->control = RULE_SIP_CONTROL; 1921 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1922 */ 1923 rulep = bgep->recv_rules; 1924 rulep->control = RULE_PROTO_CONTROL; 1925 rulep->mask_value = RULE_TCP_MASK_VALUE; 1926 1927 /* 1928 * set receive rule registers 1929 */ 1930 rulep = bgep->recv_rules; 1931 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1932 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1933 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1934 } 1935 } 1936 1937 /* 1938 * Using the values captured by bge_chip_cfg_init(), and additional probes 1939 * as required, characterise the chip fully: determine the label by which 1940 * to refer to this chip, the correct settings for various registers, and 1941 * of course whether the device and/or subsystem are supported! 1942 */ 1943 int bge_chip_id_init(bge_t *bgep); 1944 #pragma no_inline(bge_chip_id_init) 1945 1946 int 1947 bge_chip_id_init(bge_t *bgep) 1948 { 1949 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1950 boolean_t sys_ok; 1951 boolean_t dev_ok; 1952 chip_id_t *cidp; 1953 uint32_t subid; 1954 char *devname; 1955 char *sysname; 1956 int *ids; 1957 int err; 1958 uint_t i; 1959 1960 sys_ok = dev_ok = B_FALSE; 1961 cidp = &bgep->chipid; 1962 1963 /* 1964 * Check the PCI device ID to determine the generic chip type and 1965 * select parameters that depend on this. 1966 * 1967 * Note: because the SPARC platforms in general don't fit the 1968 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1969 * as zero - which is why we use <asic_rev> rather than <revision> 1970 * below ... 1971 * 1972 * Note: in general we can't distinguish between the Copper/SerDes 1973 * versions by ID alone, as some Copper devices (e.g. some but not 1974 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1975 * treat them the same here, and the MII code works out the media 1976 * type later on ... 1977 */ 1978 cidp->mbuf_base = bge_mbuf_pool_base; 1979 cidp->mbuf_length = bge_mbuf_pool_len; 1980 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1981 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1982 cidp->pci_type = BGE_PCI_X; 1983 cidp->statistic_type = BGE_STAT_BLK; 1984 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1985 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1986 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1987 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1988 cidp->rx_count_norm = bge_rx_count_norm; 1989 1990 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1991 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1992 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1993 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1994 1995 cidp->msi_enabled = B_FALSE; 1996 1997 switch (cidp->device) { 1998 case DEVICE_ID_5700: 1999 case DEVICE_ID_5700x: 2000 cidp->chip_label = 5700; 2001 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2002 break; 2003 2004 case DEVICE_ID_5701: 2005 cidp->chip_label = 5701; 2006 dev_ok = B_TRUE; 2007 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2008 break; 2009 2010 case DEVICE_ID_5702: 2011 case DEVICE_ID_5702fe: 2012 cidp->chip_label = 5702; 2013 dev_ok = B_TRUE; 2014 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2015 cidp->pci_type = BGE_PCI; 2016 break; 2017 2018 case DEVICE_ID_5703C: 2019 case DEVICE_ID_5703S: 2020 case DEVICE_ID_5703: 2021 /* 2022 * Revision A0 of the 5703/5793 had various errata 2023 * that we can't or don't work around, so it's not 2024 * supported, but all later versions are 2025 */ 2026 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2027 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2028 dev_ok = B_TRUE; 2029 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2030 break; 2031 2032 case DEVICE_ID_5704C: 2033 case DEVICE_ID_5704S: 2034 case DEVICE_ID_5704: 2035 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2036 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2037 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2038 dev_ok = B_TRUE; 2039 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2040 break; 2041 2042 case DEVICE_ID_5705C: 2043 case DEVICE_ID_5705M: 2044 case DEVICE_ID_5705MA3: 2045 case DEVICE_ID_5705F: 2046 case DEVICE_ID_5705_2: 2047 case DEVICE_ID_5754: 2048 if (cidp->device == DEVICE_ID_5754) { 2049 cidp->chip_label = 5754; 2050 cidp->pci_type = BGE_PCI_E; 2051 } else { 2052 cidp->chip_label = 5705; 2053 cidp->pci_type = BGE_PCI; 2054 } 2055 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2056 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2057 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2058 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2059 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2060 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2061 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2062 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2063 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2064 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2065 cidp->statistic_type = BGE_STAT_REG; 2066 dev_ok = B_TRUE; 2067 break; 2068 2069 case DEVICE_ID_5753: 2070 cidp->chip_label = 5753; 2071 cidp->pci_type = BGE_PCI_E; 2072 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2073 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2074 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2075 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2076 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2077 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2078 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2079 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2080 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2081 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2082 cidp->statistic_type = BGE_STAT_REG; 2083 dev_ok = B_TRUE; 2084 break; 2085 2086 case DEVICE_ID_5755: 2087 case DEVICE_ID_5755M: 2088 cidp->chip_label = 5755; 2089 cidp->pci_type = BGE_PCI_E; 2090 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2091 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2092 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2093 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2094 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2095 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2096 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2097 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2098 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2099 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2100 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2101 cidp->statistic_type = BGE_STAT_REG; 2102 dev_ok = B_TRUE; 2103 break; 2104 2105 case DEVICE_ID_5706: 2106 cidp->chip_label = 5706; 2107 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2108 break; 2109 2110 case DEVICE_ID_5782: 2111 /* 2112 * Apart from the label, we treat this as a 5705(?) 2113 */ 2114 cidp->chip_label = 5782; 2115 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2116 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2117 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2118 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2119 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2120 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2121 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2122 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2123 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2124 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2125 cidp->statistic_type = BGE_STAT_REG; 2126 dev_ok = B_TRUE; 2127 break; 2128 2129 case DEVICE_ID_5788: 2130 /* 2131 * Apart from the label, we treat this as a 5705(?) 2132 */ 2133 cidp->chip_label = 5788; 2134 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2135 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2136 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2137 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2138 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2139 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2140 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2141 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2142 cidp->statistic_type = BGE_STAT_REG; 2143 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2144 dev_ok = B_TRUE; 2145 break; 2146 2147 case DEVICE_ID_5714C: 2148 if (cidp->revision >= REVISION_ID_5714_A2) 2149 cidp->msi_enabled = bge_enable_msi; 2150 /* FALLTHRU */ 2151 case DEVICE_ID_5714S: 2152 cidp->chip_label = 5714; 2153 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2154 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2155 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2156 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2157 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2158 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2159 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2160 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2161 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2162 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2163 cidp->pci_type = BGE_PCI_E; 2164 cidp->statistic_type = BGE_STAT_REG; 2165 dev_ok = B_TRUE; 2166 break; 2167 2168 case DEVICE_ID_5715C: 2169 case DEVICE_ID_5715S: 2170 cidp->chip_label = 5715; 2171 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2172 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2173 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2174 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2175 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2176 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2177 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2178 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2179 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2180 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2181 cidp->pci_type = BGE_PCI_E; 2182 cidp->statistic_type = BGE_STAT_REG; 2183 if (cidp->revision >= REVISION_ID_5715_A2) 2184 cidp->msi_enabled = bge_enable_msi; 2185 dev_ok = B_TRUE; 2186 break; 2187 2188 case DEVICE_ID_5721: 2189 cidp->chip_label = 5721; 2190 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2191 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2192 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2193 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2194 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2195 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2196 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2197 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2198 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2199 cidp->pci_type = BGE_PCI_E; 2200 cidp->statistic_type = BGE_STAT_REG; 2201 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2202 dev_ok = B_TRUE; 2203 break; 2204 2205 case DEVICE_ID_5751: 2206 case DEVICE_ID_5751M: 2207 cidp->chip_label = 5751; 2208 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2209 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2210 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2211 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2212 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2213 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2214 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2215 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2216 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2217 cidp->pci_type = BGE_PCI_E; 2218 cidp->statistic_type = BGE_STAT_REG; 2219 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2220 dev_ok = B_TRUE; 2221 break; 2222 2223 case DEVICE_ID_5752: 2224 case DEVICE_ID_5752M: 2225 cidp->chip_label = 5752; 2226 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2227 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2228 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2229 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2230 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2231 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2232 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2233 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2234 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2235 cidp->pci_type = BGE_PCI_E; 2236 cidp->statistic_type = BGE_STAT_REG; 2237 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2238 dev_ok = B_TRUE; 2239 break; 2240 2241 case DEVICE_ID_5789: 2242 cidp->chip_label = 5789; 2243 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2244 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2245 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2246 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2247 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2248 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2249 cidp->pci_type = BGE_PCI_E; 2250 cidp->statistic_type = BGE_STAT_REG; 2251 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2252 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2253 cidp->msi_enabled = B_TRUE; 2254 dev_ok = B_TRUE; 2255 break; 2256 2257 } 2258 2259 /* 2260 * Setup the default jumbo parameter. 2261 */ 2262 cidp->ethmax_size = ETHERMAX; 2263 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2264 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2265 2266 /* 2267 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2268 * setup below jumbo specific parameters. 2269 * 2270 * For BCM5714/5715, there is only one standard receive ring. So the 2271 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2272 * feature is enabled. 2273 */ 2274 if (bge_jumbo_enable && 2275 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2276 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2277 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2278 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2279 cidp->mbuf_lo_water_rdma = 2280 RDMA_MBUF_LOWAT_5714_JUMBO; 2281 cidp->mbuf_lo_water_rmac = 2282 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2283 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2284 cidp->jumbo_slots = 0; 2285 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2286 } else { 2287 cidp->mbuf_lo_water_rdma = 2288 RDMA_MBUF_LOWAT_JUMBO; 2289 cidp->mbuf_lo_water_rmac = 2290 MAC_RX_MBUF_LOWAT_JUMBO; 2291 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2292 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2293 } 2294 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2295 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2296 cidp->ethmax_size = cidp->default_mtu + 2297 sizeof (struct ether_header); 2298 } 2299 2300 /* 2301 * Identify the NV memory type: SEEPROM or Flash? 2302 */ 2303 cidp->nvtype = bge_nvmem_id(bgep); 2304 2305 /* 2306 * Now, we want to check whether this device is part of a 2307 * supported subsystem (e.g., on the motherboard of a Sun 2308 * branded platform). 2309 * 2310 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2311 */ 2312 if (cidp->subven == VENDOR_ID_SUN) 2313 sys_ok = B_TRUE; 2314 2315 /* 2316 * Rule 2: If it's on the list on known subsystems, then it's OK. 2317 * Note: 0x14e41647 should *not* appear in the list, but the code 2318 * doesn't enforce that. 2319 */ 2320 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2321 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2322 if (err == DDI_PROP_SUCCESS) { 2323 /* 2324 * Got the list; scan for a matching subsystem vendor/device 2325 */ 2326 subid = (cidp->subven << 16) | cidp->subdev; 2327 while (i--) 2328 if (ids[i] == subid) 2329 sys_ok = B_TRUE; 2330 ddi_prop_free(ids); 2331 } 2332 2333 /* 2334 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2335 * 2336 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2337 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2338 * we have to check specially for the exact device paths to the 2339 * motherboard devices on those platforms ;-( 2340 * 2341 * Note: we can't just use the "supported-subsystems" mechanism 2342 * above, because the entry would have to be 0x14e41647 -- which 2343 * would then accept *any* plugin card that *didn't* contain a 2344 * (valid) SEEPROM ;-( 2345 */ 2346 sysname = ddi_node_name(ddi_root_node()); 2347 devname = ddi_pathname(bgep->devinfo, buf); 2348 ASSERT(strlen(devname) > 0); 2349 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2350 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2351 sys_ok = B_TRUE; 2352 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2353 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2354 sys_ok = B_TRUE; 2355 2356 /* 2357 * Now check what we've discovered: is this truly a supported 2358 * chip on (the motherboard of) a supported platform? 2359 * 2360 * Possible problems here: 2361 * 1) it's a completely unheard-of chip (e.g. 5761) 2362 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2363 * 3) it's a chip we would support if it were on the motherboard 2364 * of a Sun platform, but this one isn't ;-( 2365 */ 2366 if (cidp->chip_label == 0) 2367 bge_problem(bgep, 2368 "Device 'pci%04x,%04x' not recognized (%d?)", 2369 cidp->vendor, cidp->device, cidp->device); 2370 else if (!dev_ok) 2371 bge_problem(bgep, 2372 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2373 cidp->vendor, cidp->device, cidp->chip_label, 2374 cidp->revision); 2375 #if BGE_DEBUGGING 2376 else if (!sys_ok) 2377 bge_problem(bgep, 2378 "%d-based subsystem 'pci%04x,%04x' not validated", 2379 cidp->chip_label, cidp->subven, cidp->subdev); 2380 #endif 2381 else 2382 cidp->flags |= CHIP_FLAG_SUPPORTED; 2383 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2384 return (EIO); 2385 return (0); 2386 } 2387 2388 void 2389 bge_chip_msi_trig(bge_t *bgep) 2390 { 2391 uint32_t regval; 2392 2393 regval = bgep->param_msi_cnt<<4; 2394 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2395 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2396 } 2397 2398 /* 2399 * Various registers that control the chip's internal engines (state 2400 * machines) have a <reset> and <enable> bits (fortunately, in the 2401 * same place in each such register :-). 2402 * 2403 * To reset the state machine, the <reset> bit must be written with 1; 2404 * it will then read back as 1 while the reset is in progress, but 2405 * self-clear to 0 when the reset completes. 2406 * 2407 * To enable a state machine, one must set the <enable> bit, which 2408 * will continue to read back as 0 until the state machine is running. 2409 * 2410 * To disable a state machine, the <enable> bit must be cleared, but 2411 * it will continue to read back as 1 until the state machine actually 2412 * stops. 2413 * 2414 * This routine implements polling for completion of a reset, enable 2415 * or disable operation, returning B_TRUE on success (bit reached the 2416 * required state) or B_FALSE on timeout (200*100us == 20ms). 2417 */ 2418 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2419 uint32_t mask, uint32_t val); 2420 #pragma no_inline(bge_chip_poll_engine) 2421 2422 static boolean_t 2423 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2424 uint32_t mask, uint32_t val) 2425 { 2426 uint32_t regval; 2427 uint32_t n; 2428 2429 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2430 (void *)bgep, regno, mask, val)); 2431 2432 for (n = 200; n; --n) { 2433 regval = bge_reg_get32(bgep, regno); 2434 if ((regval & mask) == val) 2435 return (B_TRUE); 2436 drv_usecwait(100); 2437 } 2438 2439 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2440 return (B_FALSE); 2441 } 2442 2443 /* 2444 * Various registers that control the chip's internal engines (state 2445 * machines) have a <reset> bit (fortunately, in the same place in 2446 * each such register :-). To reset the state machine, this bit must 2447 * be written with 1; it will then read back as 1 while the reset is 2448 * in progress, but self-clear to 0 when the reset completes. 2449 * 2450 * This code sets the bit, then polls for it to read back as zero. 2451 * The return value is B_TRUE on success (reset bit cleared itself), 2452 * or B_FALSE if the state machine didn't recover :( 2453 * 2454 * NOTE: the Core reset is similar to other resets, except that we 2455 * can't poll for completion, since the Core reset disables memory 2456 * access! So we just have to assume that it will all complete in 2457 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2458 */ 2459 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2460 #pragma no_inline(bge_chip_reset_engine) 2461 2462 static boolean_t 2463 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2464 { 2465 uint32_t regval; 2466 uint32_t val32; 2467 2468 regval = bge_reg_get32(bgep, regno); 2469 2470 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2471 (void *)bgep, regno)); 2472 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2473 regno, regval)); 2474 2475 regval |= STATE_MACHINE_RESET_BIT; 2476 2477 switch (regno) { 2478 case MISC_CONFIG_REG: 2479 /* 2480 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2481 * resetting PCIE block and bringing PCIE link down, bit 29 2482 * in the register needs to be set first, and then set it again 2483 * while the reset bit is written. 2484 * See:P500 of 57xx-PG102-RDS.pdf. 2485 */ 2486 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2487 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2488 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2489 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2490 if (bgep->chipid.pci_type == BGE_PCI_E) { 2491 if (bgep->chipid.asic_rev == 2492 MHCR_CHIP_REV_5751_A0 || 2493 bgep->chipid.asic_rev == 2494 MHCR_CHIP_REV_5721_A0 || 2495 bgep->chipid.asic_rev == 2496 MHCR_CHIP_REV_5755_A0) { 2497 val32 = bge_reg_get32(bgep, 2498 PHY_TEST_CTRL_REG); 2499 if (val32 == (PHY_PCIE_SCRAM_MODE | 2500 PHY_PCIE_LTASS_MODE)) 2501 bge_reg_put32(bgep, 2502 PHY_TEST_CTRL_REG, 2503 PHY_PCIE_SCRAM_MODE); 2504 val32 = pci_config_get32 2505 (bgep->cfg_handle, 2506 PCI_CONF_BGE_CLKCTL); 2507 val32 |= CLKCTL_PCIE_A0_FIX; 2508 pci_config_put32(bgep->cfg_handle, 2509 PCI_CONF_BGE_CLKCTL, val32); 2510 } 2511 bge_reg_set32(bgep, regno, 2512 MISC_CONFIG_GRC_RESET_DISABLE); 2513 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2514 } 2515 } 2516 2517 /* 2518 * Special case - causes Core reset 2519 * 2520 * On SPARC v9 we want to ensure that we don't start 2521 * timing until the I/O access has actually reached 2522 * the chip, otherwise we might make the next access 2523 * too early. And we can't just force the write out 2524 * by following it with a read (even to config space) 2525 * because that would cause the fault we're trying 2526 * to avoid. Hence the need for membar_sync() here. 2527 */ 2528 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2529 #ifdef __sparcv9 2530 membar_sync(); 2531 #endif /* __sparcv9 */ 2532 /* 2533 * On some platforms,system need about 300us for 2534 * link setup. 2535 */ 2536 drv_usecwait(300); 2537 2538 if (bgep->chipid.pci_type == BGE_PCI_E) { 2539 /* PCI-E device need more reset time */ 2540 drv_usecwait(120000); 2541 2542 /* Set PCIE max payload size and clear error status. */ 2543 if ((bgep->chipid.chip_label == 5721) || 2544 (bgep->chipid.chip_label == 5751) || 2545 (bgep->chipid.chip_label == 5752) || 2546 (bgep->chipid.chip_label == 5789)) { 2547 pci_config_put16(bgep->cfg_handle, 2548 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2549 pci_config_put16(bgep->cfg_handle, 2550 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2551 } 2552 } 2553 2554 BGE_PCICHK(bgep); 2555 return (B_TRUE); 2556 2557 default: 2558 bge_reg_put32(bgep, regno, regval); 2559 return (bge_chip_poll_engine(bgep, regno, 2560 STATE_MACHINE_RESET_BIT, 0)); 2561 } 2562 } 2563 2564 /* 2565 * Various registers that control the chip's internal engines (state 2566 * machines) have an <enable> bit (fortunately, in the same place in 2567 * each such register :-). To stop the state machine, this bit must 2568 * be written with 0, then polled to see when the state machine has 2569 * actually stopped. 2570 * 2571 * The return value is B_TRUE on success (enable bit cleared), or 2572 * B_FALSE if the state machine didn't stop :( 2573 */ 2574 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2575 uint32_t morebits); 2576 #pragma no_inline(bge_chip_disable_engine) 2577 2578 static boolean_t 2579 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2580 { 2581 uint32_t regval; 2582 2583 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2584 (void *)bgep, regno, morebits)); 2585 2586 switch (regno) { 2587 case FTQ_RESET_REG: 2588 /* 2589 * For Schumacher's bugfix CR6490108 2590 */ 2591 #ifdef BGE_IPMI_ASF 2592 #ifdef BGE_NETCONSOLE 2593 if (bgep->asf_enabled) 2594 return (B_TRUE); 2595 #endif 2596 #endif 2597 /* 2598 * Not quite like the others; it doesn't 2599 * have an <enable> bit, but instead we 2600 * have to set and then clear all the bits 2601 */ 2602 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2603 drv_usecwait(100); 2604 bge_reg_put32(bgep, regno, 0); 2605 return (B_TRUE); 2606 2607 default: 2608 regval = bge_reg_get32(bgep, regno); 2609 regval &= ~STATE_MACHINE_ENABLE_BIT; 2610 regval &= ~morebits; 2611 bge_reg_put32(bgep, regno, regval); 2612 return (bge_chip_poll_engine(bgep, regno, 2613 STATE_MACHINE_ENABLE_BIT, 0)); 2614 } 2615 } 2616 2617 /* 2618 * Various registers that control the chip's internal engines (state 2619 * machines) have an <enable> bit (fortunately, in the same place in 2620 * each such register :-). To start the state machine, this bit must 2621 * be written with 1, then polled to see when the state machine has 2622 * actually started. 2623 * 2624 * The return value is B_TRUE on success (enable bit set), or 2625 * B_FALSE if the state machine didn't start :( 2626 */ 2627 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2628 uint32_t morebits); 2629 #pragma no_inline(bge_chip_enable_engine) 2630 2631 static boolean_t 2632 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2633 { 2634 uint32_t regval; 2635 2636 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2637 (void *)bgep, regno, morebits)); 2638 2639 switch (regno) { 2640 case FTQ_RESET_REG: 2641 #ifdef BGE_IPMI_ASF 2642 #ifdef BGE_NETCONSOLE 2643 if (bgep->asf_enabled) 2644 return (B_TRUE); 2645 #endif 2646 #endif 2647 /* 2648 * Not quite like the others; it doesn't 2649 * have an <enable> bit, but instead we 2650 * have to set and then clear all the bits 2651 */ 2652 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2653 drv_usecwait(100); 2654 bge_reg_put32(bgep, regno, 0); 2655 return (B_TRUE); 2656 2657 default: 2658 regval = bge_reg_get32(bgep, regno); 2659 regval |= STATE_MACHINE_ENABLE_BIT; 2660 regval |= morebits; 2661 bge_reg_put32(bgep, regno, regval); 2662 return (bge_chip_poll_engine(bgep, regno, 2663 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2664 } 2665 } 2666 2667 /* 2668 * Reprogram the Ethernet, Transmit, and Receive MAC 2669 * modes to match the param_* variables 2670 */ 2671 void bge_sync_mac_modes(bge_t *bgep); 2672 #pragma no_inline(bge_sync_mac_modes) 2673 2674 void 2675 bge_sync_mac_modes(bge_t *bgep) 2676 { 2677 uint32_t macmode; 2678 uint32_t regval; 2679 2680 ASSERT(mutex_owned(bgep->genlock)); 2681 2682 /* 2683 * Reprogram the Ethernet MAC mode ... 2684 */ 2685 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2686 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2687 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2688 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2689 else 2690 macmode |= ETHERNET_MODE_LINK_POLARITY; 2691 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2692 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2693 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2694 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2695 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2696 macmode |= ETHERNET_MODE_PORTMODE_MII; 2697 else 2698 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2699 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2700 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2701 else 2702 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2703 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2704 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2705 else 2706 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2707 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2708 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2709 (void *)bgep, regval, macmode)); 2710 2711 /* 2712 * ... the Transmit MAC mode ... 2713 */ 2714 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2715 if (bgep->param_link_tx_pause) 2716 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2717 else 2718 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2719 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2720 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2721 (void *)bgep, regval, macmode)); 2722 2723 /* 2724 * ... and the Receive MAC mode 2725 */ 2726 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2727 if (bgep->param_link_rx_pause) 2728 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2729 else 2730 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2731 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2732 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2733 (void *)bgep, regval, macmode)); 2734 } 2735 2736 /* 2737 * bge_chip_sync() -- program the chip with the unicast MAC address, 2738 * the multicast hash table, the required level of promiscuity, and 2739 * the current loopback mode ... 2740 */ 2741 #ifdef BGE_IPMI_ASF 2742 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2743 #else 2744 int bge_chip_sync(bge_t *bgep); 2745 #endif 2746 #pragma no_inline(bge_chip_sync) 2747 2748 int 2749 #ifdef BGE_IPMI_ASF 2750 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2751 #else 2752 bge_chip_sync(bge_t *bgep) 2753 #endif 2754 { 2755 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2756 boolean_t promisc; 2757 uint64_t macaddr; 2758 uint32_t fill; 2759 int i, j; 2760 int retval = DDI_SUCCESS; 2761 2762 BGE_TRACE(("bge_chip_sync($%p)", 2763 (void *)bgep)); 2764 2765 ASSERT(mutex_owned(bgep->genlock)); 2766 2767 promisc = B_FALSE; 2768 fill = ~(uint32_t)0; 2769 2770 if (bgep->promisc) 2771 promisc = B_TRUE; 2772 else 2773 fill = (uint32_t)0; 2774 2775 /* 2776 * If the TX/RX MAC engines are already running, we should stop 2777 * them (and reset the RX engine) before changing the parameters. 2778 * If they're not running, this will have no effect ... 2779 * 2780 * NOTE: this is currently disabled by default because stopping 2781 * and restarting the Tx engine may cause an outgoing packet in 2782 * transit to be truncated. Also, stopping and restarting the 2783 * Rx engine seems to not work correctly on the 5705. Testing 2784 * has not (yet!) revealed any problems with NOT stopping and 2785 * restarting these engines (and Broadcom say their drivers don't 2786 * do this), but if it is found to cause problems, this variable 2787 * can be patched to re-enable the old behaviour ... 2788 */ 2789 if (bge_stop_start_on_sync) { 2790 #ifdef BGE_IPMI_ASF 2791 if (!bgep->asf_enabled) { 2792 if (!bge_chip_disable_engine(bgep, 2793 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2794 retval = DDI_FAILURE; 2795 } else { 2796 if (!bge_chip_disable_engine(bgep, 2797 RECEIVE_MAC_MODE_REG, 0)) 2798 retval = DDI_FAILURE; 2799 } 2800 #else 2801 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2802 RECEIVE_MODE_KEEP_VLAN_TAG)) 2803 retval = DDI_FAILURE; 2804 #endif 2805 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2806 retval = DDI_FAILURE; 2807 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2808 retval = DDI_FAILURE; 2809 } 2810 2811 /* 2812 * Reprogram the hashed multicast address table ... 2813 */ 2814 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2815 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2816 2817 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2818 bge_reg_put32(bgep, MAC_HASH_REG(i), 2819 bgep->mcast_hash[i] | fill); 2820 2821 #ifdef BGE_IPMI_ASF 2822 if (!bgep->asf_enabled || !asf_keeplive) { 2823 #endif 2824 /* 2825 * Transform the MAC address(es) from host to chip format, then 2826 * reprogram the transmit random backoff seed and the unicast 2827 * MAC address(es) ... 2828 */ 2829 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2830 for (i = 0, fill = 0, macaddr = 0ull; 2831 i < ETHERADDRL; ++i) { 2832 macaddr <<= 8; 2833 macaddr |= bgep->curr_addr[j].addr[i]; 2834 fill += bgep->curr_addr[j].addr[i]; 2835 } 2836 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2837 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2838 } 2839 2840 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2841 (void *)bgep, macaddr)); 2842 #ifdef BGE_IPMI_ASF 2843 } 2844 #endif 2845 2846 /* 2847 * Set or clear the PROMISCUOUS mode bit 2848 */ 2849 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2850 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2851 2852 /* 2853 * Sync the rest of the MAC modes too ... 2854 */ 2855 bge_sync_mac_modes(bgep); 2856 2857 /* 2858 * Restart RX/TX MAC engines if required ... 2859 */ 2860 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2861 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2862 retval = DDI_FAILURE; 2863 #ifdef BGE_IPMI_ASF 2864 if (!bgep->asf_enabled) { 2865 if (!bge_chip_enable_engine(bgep, 2866 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2867 retval = DDI_FAILURE; 2868 } else { 2869 if (!bge_chip_enable_engine(bgep, 2870 RECEIVE_MAC_MODE_REG, 0)) 2871 retval = DDI_FAILURE; 2872 } 2873 #else 2874 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2875 RECEIVE_MODE_KEEP_VLAN_TAG)) 2876 retval = DDI_FAILURE; 2877 #endif 2878 } 2879 return (retval); 2880 } 2881 2882 /* 2883 * This array defines the sequence of state machine control registers 2884 * in which the <enable> bit must be cleared to bring the chip to a 2885 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2886 */ 2887 static bge_regno_t shutdown_engine_regs[] = { 2888 RECEIVE_MAC_MODE_REG, 2889 RCV_BD_INITIATOR_MODE_REG, 2890 RCV_LIST_PLACEMENT_MODE_REG, 2891 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2892 RCV_DATA_BD_INITIATOR_MODE_REG, 2893 RCV_DATA_COMPLETION_MODE_REG, 2894 RCV_BD_COMPLETION_MODE_REG, 2895 2896 SEND_BD_SELECTOR_MODE_REG, 2897 SEND_BD_INITIATOR_MODE_REG, 2898 SEND_DATA_INITIATOR_MODE_REG, 2899 READ_DMA_MODE_REG, 2900 SEND_DATA_COMPLETION_MODE_REG, 2901 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2902 SEND_BD_COMPLETION_MODE_REG, 2903 TRANSMIT_MAC_MODE_REG, 2904 2905 HOST_COALESCE_MODE_REG, 2906 WRITE_DMA_MODE_REG, 2907 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2908 FTQ_RESET_REG, /* special - see code */ 2909 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2910 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2911 BGE_REGNO_NONE /* terminator */ 2912 }; 2913 2914 /* 2915 * bge_chip_stop() -- stop all chip processing 2916 * 2917 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2918 * we've detected a problem internally; otherwise, this is a normal 2919 * (clean) stop (at user request i.e. the last STREAM has been closed). 2920 */ 2921 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2922 #pragma no_inline(bge_chip_stop) 2923 2924 void 2925 bge_chip_stop(bge_t *bgep, boolean_t fault) 2926 { 2927 bge_regno_t regno; 2928 bge_regno_t *rbp; 2929 boolean_t ok; 2930 2931 BGE_TRACE(("bge_chip_stop($%p)", 2932 (void *)bgep)); 2933 2934 ASSERT(mutex_owned(bgep->genlock)); 2935 2936 rbp = shutdown_engine_regs; 2937 /* 2938 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2939 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2940 * -ory arbiter should not be disabled. 2941 */ 2942 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2943 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2944 ok &= bge_chip_disable_engine(bgep, regno, 0); 2945 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2946 (regno != DMA_COMPLETION_MODE_REG) && 2947 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2948 (regno != BUFFER_MANAGER_MODE_REG) && 2949 (regno != MEMORY_ARBITER_MODE_REG)) 2950 ok &= bge_chip_disable_engine(bgep, 2951 regno, 0); 2952 } 2953 2954 if (!ok && !fault) 2955 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2956 2957 /* 2958 * Finally, disable (all) MAC events & clear the MAC status 2959 */ 2960 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2961 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2962 2963 /* 2964 * if we're stopping the chip because of a detected fault then do 2965 * appropriate actions 2966 */ 2967 if (fault) { 2968 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2969 bgep->bge_chip_state = BGE_CHIP_FAULT; 2970 if (!bgep->manual_reset) 2971 ddi_fm_service_impact(bgep->devinfo, 2972 DDI_SERVICE_LOST); 2973 if (bgep->bge_dma_error) { 2974 /* 2975 * need to free buffers in case the fault was 2976 * due to a memory error in a buffer - got to 2977 * do a fair bit of tidying first 2978 */ 2979 if (bgep->progress & PROGRESS_KSTATS) { 2980 bge_fini_kstats(bgep); 2981 bgep->progress &= ~PROGRESS_KSTATS; 2982 } 2983 if (bgep->progress & PROGRESS_INTR) { 2984 bge_intr_disable(bgep); 2985 rw_enter(bgep->errlock, RW_WRITER); 2986 bge_fini_rings(bgep); 2987 rw_exit(bgep->errlock); 2988 bgep->progress &= ~PROGRESS_INTR; 2989 } 2990 if (bgep->progress & PROGRESS_BUFS) { 2991 bge_free_bufs(bgep); 2992 bgep->progress &= ~PROGRESS_BUFS; 2993 } 2994 bgep->bge_dma_error = B_FALSE; 2995 } 2996 } 2997 } else 2998 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2999 } 3000 3001 /* 3002 * Poll for completion of chip's ROM firmware; also, at least on the 3003 * first time through, find and return the hardware MAC address, if any. 3004 */ 3005 static uint64_t bge_poll_firmware(bge_t *bgep); 3006 #pragma no_inline(bge_poll_firmware) 3007 3008 static uint64_t 3009 bge_poll_firmware(bge_t *bgep) 3010 { 3011 uint64_t magic; 3012 uint64_t mac; 3013 uint32_t gen; 3014 uint32_t i; 3015 3016 /* 3017 * Step 19: poll for firmware completion (GENCOMM port set 3018 * to the ones complement of T3_MAGIC_NUMBER). 3019 * 3020 * While we're at it, we also read the MAC address register; 3021 * at some stage the firmware will load this with the 3022 * factory-set value. 3023 * 3024 * When both the magic number and the MAC address are set, 3025 * we're done; but we impose a time limit of one second 3026 * (1000*1000us) in case the firmware fails in some fashion 3027 * or the SEEPROM that provides that MAC address isn't fitted. 3028 * 3029 * After the first time through (chip state != INITIAL), we 3030 * don't need the MAC address to be set (we've already got it 3031 * or not, from the first time), so we don't wait for it, but 3032 * we still have to wait for the T3_MAGIC_NUMBER. 3033 * 3034 * Note: the magic number is only a 32-bit quantity, but the NIC 3035 * memory is 64-bit (and big-endian) internally. Addressing the 3036 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3037 * it work correctly on both big- and little-endian hosts. 3038 */ 3039 for (i = 0; i < 1000; ++i) { 3040 drv_usecwait(1000); 3041 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3042 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3043 #ifdef BGE_IPMI_ASF 3044 if (!bgep->asf_enabled) { 3045 #endif 3046 if (gen != ~T3_MAGIC_NUMBER) 3047 continue; 3048 #ifdef BGE_IPMI_ASF 3049 } 3050 #endif 3051 if (mac != 0ULL) 3052 break; 3053 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3054 break; 3055 } 3056 3057 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3058 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3059 (void *)bgep, gen, i)); 3060 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3061 mac, magic)); 3062 3063 return (mac); 3064 } 3065 3066 /* 3067 * Maximum times of trying to get the NVRAM access lock 3068 * by calling bge_nvmem_acquire() 3069 */ 3070 #define MAX_TRY_NVMEM_ACQUIRE 10000 3071 3072 #ifdef BGE_IPMI_ASF 3073 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3074 #else 3075 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3076 #endif 3077 #pragma no_inline(bge_chip_reset) 3078 3079 int 3080 #ifdef BGE_IPMI_ASF 3081 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3082 #else 3083 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3084 #endif 3085 { 3086 chip_id_t chipid; 3087 uint64_t mac; 3088 uint64_t magic; 3089 uint32_t modeflags; 3090 uint32_t mhcr; 3091 uint32_t sx0; 3092 uint32_t i, tries; 3093 #ifdef BGE_IPMI_ASF 3094 uint32_t mailbox; 3095 #endif 3096 int retval = DDI_SUCCESS; 3097 3098 BGE_TRACE(("bge_chip_reset($%p, %d)", 3099 (void *)bgep, enable_dma)); 3100 3101 ASSERT(mutex_owned(bgep->genlock)); 3102 3103 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3104 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3105 3106 /* 3107 * Do we need to stop the chip cleanly before resetting? 3108 */ 3109 switch (bgep->bge_chip_state) { 3110 default: 3111 _NOTE(NOTREACHED) 3112 return (DDI_FAILURE); 3113 3114 case BGE_CHIP_INITIAL: 3115 case BGE_CHIP_STOPPED: 3116 case BGE_CHIP_RESET: 3117 break; 3118 3119 case BGE_CHIP_RUNNING: 3120 case BGE_CHIP_ERROR: 3121 case BGE_CHIP_FAULT: 3122 bge_chip_stop(bgep, B_FALSE); 3123 break; 3124 } 3125 3126 #ifdef BGE_IPMI_ASF 3127 if (bgep->asf_enabled) { 3128 #ifdef __sparc 3129 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3130 MHCR_ENABLE_TAGGED_STATUS_MODE | 3131 MHCR_MASK_INTERRUPT_MODE | 3132 MHCR_MASK_PCI_INT_OUTPUT | 3133 MHCR_CLEAR_INTERRUPT_INTA | 3134 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3135 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3136 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3137 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3138 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3139 MEMORY_ARBITER_ENABLE); 3140 #endif 3141 if (asf_mode == ASF_MODE_INIT) { 3142 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3143 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3144 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3145 } 3146 } 3147 #endif 3148 /* 3149 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3150 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3151 * 3152 * Before reset Core clock,it is 3153 * also required to initialize the Memory Arbiter as specified in step9 3154 * and Misc Host Control Register as specified in step-13 3155 * Step 4-5: reset Core clock & wait for completion 3156 * Steps 6-8: are done by bge_chip_cfg_init() 3157 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3158 */ 3159 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3160 retval = DDI_FAILURE; 3161 3162 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3163 MHCR_ENABLE_TAGGED_STATUS_MODE | 3164 MHCR_MASK_INTERRUPT_MODE | 3165 MHCR_MASK_PCI_INT_OUTPUT | 3166 MHCR_CLEAR_INTERRUPT_INTA; 3167 #ifdef _BIG_ENDIAN 3168 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3169 #endif /* _BIG_ENDIAN */ 3170 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3171 #ifdef BGE_IPMI_ASF 3172 if (bgep->asf_enabled) 3173 bgep->asf_wordswapped = B_FALSE; 3174 #endif 3175 /* 3176 * NVRAM Corruption Workaround 3177 */ 3178 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3179 if (bge_nvmem_acquire(bgep) != EAGAIN) 3180 break; 3181 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3182 BGE_DEBUG(("%s: fail to acquire nvram lock", 3183 bgep->ifname)); 3184 3185 #ifdef BGE_IPMI_ASF 3186 if (!bgep->asf_enabled) { 3187 #endif 3188 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3189 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3190 #ifdef BGE_IPMI_ASF 3191 } 3192 #endif 3193 3194 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3195 retval = DDI_FAILURE; 3196 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3197 3198 /* 3199 * Step 8a: This may belong elsewhere, but BCM5721 needs 3200 * a bit set to avoid a fifo overflow/underflow bug. 3201 */ 3202 if ((bgep->chipid.chip_label == 5721) || 3203 (bgep->chipid.chip_label == 5751) || 3204 (bgep->chipid.chip_label == 5752) || 3205 (bgep->chipid.chip_label == 5755) || 3206 (bgep->chipid.chip_label == 5789)) 3207 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3208 3209 3210 /* 3211 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3212 * not be changed. 3213 */ 3214 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3215 retval = DDI_FAILURE; 3216 3217 /* 3218 * Steps 10-11: configure PIO endianness options and 3219 * enable indirect register access -- already done 3220 * Steps 12-13: enable writing to the PCI state & clock 3221 * control registers -- not required; we aren't going to 3222 * use those features. 3223 * Steps 14-15: Configure DMA endianness options. See 3224 * the comments on the setting of the MHCR above. 3225 */ 3226 #ifdef _BIG_ENDIAN 3227 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3228 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3229 #else 3230 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3231 #endif /* _BIG_ENDIAN */ 3232 #ifdef BGE_IPMI_ASF 3233 if (bgep->asf_enabled) 3234 modeflags |= MODE_HOST_STACK_UP; 3235 #endif 3236 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3237 3238 #ifdef BGE_IPMI_ASF 3239 if (bgep->asf_enabled) { 3240 #ifdef __sparc 3241 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3242 MEMORY_ARBITER_ENABLE | 3243 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3244 #endif 3245 3246 #ifdef BGE_NETCONSOLE 3247 if (!bgep->asf_newhandshake) { 3248 if ((asf_mode == ASF_MODE_INIT) || 3249 (asf_mode == ASF_MODE_POST_INIT)) { 3250 bge_asf_post_reset_old_mode(bgep, 3251 BGE_INIT_RESET); 3252 } else { 3253 bge_asf_post_reset_old_mode(bgep, 3254 BGE_SHUTDOWN_RESET); 3255 } 3256 } 3257 #endif 3258 3259 /* Wait for NVRAM init */ 3260 i = 0; 3261 drv_usecwait(5000); 3262 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3263 3264 while ((mailbox != (uint32_t) 3265 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3266 (i < 10000)) { 3267 drv_usecwait(100); 3268 mailbox = bge_nic_get32(bgep, 3269 BGE_FIRMWARE_MAILBOX); 3270 i++; 3271 } 3272 3273 #ifndef BGE_NETCONSOLE 3274 if (!bgep->asf_newhandshake) { 3275 if ((asf_mode == ASF_MODE_INIT) || 3276 (asf_mode == ASF_MODE_POST_INIT)) { 3277 3278 bge_asf_post_reset_old_mode(bgep, 3279 BGE_INIT_RESET); 3280 } else { 3281 bge_asf_post_reset_old_mode(bgep, 3282 BGE_SHUTDOWN_RESET); 3283 } 3284 } 3285 #endif 3286 } 3287 #endif 3288 /* 3289 * Steps 16-17: poll for firmware completion 3290 */ 3291 mac = bge_poll_firmware(bgep); 3292 3293 /* 3294 * Step 18: enable external memory -- doesn't apply. 3295 * 3296 * However we take the opportunity to set the MLCR anyway, as 3297 * this register also controls the SEEPROM auto-access method 3298 * which we may want to use later ... 3299 * 3300 * The proper value here depends on the way the chip is wired 3301 * into the circuit board, as this register *also* controls which 3302 * of the "Miscellaneous I/O" pins are driven as outputs and the 3303 * values driven onto those pins! 3304 * 3305 * See also step 74 in the PRM ... 3306 */ 3307 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3308 bgep->chipid.bge_mlcr_default); 3309 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3310 3311 /* 3312 * Step 20: clear the Ethernet MAC mode register 3313 */ 3314 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3315 3316 /* 3317 * Step 21: restore cache-line-size, latency timer, and 3318 * subsystem ID registers to their original values (not 3319 * those read into the local structure <chipid>, 'cos 3320 * that was after they were cleared by the RESET). 3321 * 3322 * Note: the Subsystem Vendor/Device ID registers are not 3323 * directly writable in config space, so we use the shadow 3324 * copy in "Page Zero" of register space to restore them 3325 * both in one go ... 3326 */ 3327 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3328 bgep->chipid.clsize); 3329 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3330 bgep->chipid.latency); 3331 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3332 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3333 3334 /* 3335 * The SEND INDEX registers should be reset to zero by the 3336 * global chip reset; if they're not, there'll be trouble 3337 * later on. 3338 */ 3339 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3340 if (sx0 != 0) { 3341 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3342 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3343 retval = DDI_FAILURE; 3344 } 3345 3346 /* Enable MSI code */ 3347 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3348 bge_reg_set32(bgep, MSI_MODE_REG, 3349 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3350 3351 /* 3352 * On the first time through, save the factory-set MAC address 3353 * (if any). If bge_poll_firmware() above didn't return one 3354 * (from a chip register) consider looking in the attached NV 3355 * memory device, if any. Once we have it, we save it in both 3356 * register-image (64-bit) and byte-array forms. All-zero and 3357 * all-one addresses are not valid, and we refuse to stash those. 3358 */ 3359 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3360 if (mac == 0ULL) 3361 mac = bge_get_nvmac(bgep); 3362 if (mac != 0ULL && mac != ~0ULL) { 3363 bgep->chipid.hw_mac_addr = mac; 3364 for (i = ETHERADDRL; i-- != 0; ) { 3365 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3366 mac >>= 8; 3367 } 3368 bgep->chipid.vendor_addr.set = B_TRUE; 3369 } 3370 } 3371 3372 #ifdef BGE_IPMI_ASF 3373 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3374 if (asf_mode != ASF_MODE_NONE) { 3375 if ((asf_mode == ASF_MODE_INIT) || 3376 (asf_mode == ASF_MODE_POST_INIT)) { 3377 3378 bge_asf_post_reset_new_mode(bgep, 3379 BGE_INIT_RESET); 3380 } else { 3381 bge_asf_post_reset_new_mode(bgep, 3382 BGE_SHUTDOWN_RESET); 3383 } 3384 } 3385 } 3386 #endif 3387 3388 /* 3389 * Record the new state 3390 */ 3391 bgep->chip_resets += 1; 3392 bgep->bge_chip_state = BGE_CHIP_RESET; 3393 return (retval); 3394 } 3395 3396 /* 3397 * bge_chip_start() -- start the chip transmitting and/or receiving, 3398 * including enabling interrupts 3399 */ 3400 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3401 #pragma no_inline(bge_chip_start) 3402 3403 int 3404 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3405 { 3406 uint32_t coalmode; 3407 uint32_t ledctl; 3408 uint32_t mtu; 3409 uint32_t maxring; 3410 uint32_t stats_mask; 3411 uint32_t dma_wrprio; 3412 uint64_t ring; 3413 int retval = DDI_SUCCESS; 3414 3415 BGE_TRACE(("bge_chip_start($%p)", 3416 (void *)bgep)); 3417 3418 ASSERT(mutex_owned(bgep->genlock)); 3419 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3420 3421 /* 3422 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3423 * The document specifies 95 separate steps to fully 3424 * initialise the chip!!!! 3425 * 3426 * The reset code above has already got us as far as step 3427 * 21, so we continue with ... 3428 * 3429 * Step 22: clear the MAC statistics block 3430 * (0x0300-0x0aff in NIC-local memory) 3431 */ 3432 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3433 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3434 NIC_MEM_STATISTICS_SIZE); 3435 3436 /* 3437 * Step 23: clear the status block (in host memory) 3438 */ 3439 DMA_ZERO(bgep->status_block); 3440 3441 /* 3442 * Step 24: set DMA read/write control register 3443 */ 3444 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3445 bgep->chipid.bge_dma_rwctrl); 3446 3447 /* 3448 * Step 25: Configure DMA endianness -- already done (16/17) 3449 * Step 26: Configure Host-Based Send Rings 3450 * Step 27: Indicate Host Stack Up 3451 */ 3452 bge_reg_set32(bgep, MODE_CONTROL_REG, 3453 MODE_HOST_SEND_BDS | 3454 MODE_HOST_STACK_UP); 3455 3456 /* 3457 * Step 28: Configure checksum options: 3458 * Solaris supports the hardware default checksum options. 3459 * 3460 * Workaround for Incorrect pseudo-header checksum calculation. 3461 */ 3462 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3463 bge_reg_set32(bgep, MODE_CONTROL_REG, 3464 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3465 3466 /* 3467 * Step 29: configure Timer Prescaler. The value is always the 3468 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3469 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3470 * for the whole chip! 3471 */ 3472 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3473 3474 /* 3475 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3476 * 3477 * If the mbuf_length is specified as 0, we just leave these at 3478 * their hardware defaults, rather than explicitly setting them. 3479 * As the Broadcom HRM,driver better not change the parameters 3480 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3481 */ 3482 if ((bgep->chipid.mbuf_length != 0) && 3483 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3484 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3485 bgep->chipid.mbuf_base); 3486 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3487 bgep->chipid.mbuf_length); 3488 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3489 DMAD_POOL_BASE_DEFAULT); 3490 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3491 DMAD_POOL_LENGTH_DEFAULT); 3492 } 3493 3494 /* 3495 * Step 32: configure MAC memory pool watermarks 3496 */ 3497 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3498 bgep->chipid.mbuf_lo_water_rdma); 3499 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3500 bgep->chipid.mbuf_lo_water_rmac); 3501 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3502 bgep->chipid.mbuf_hi_water); 3503 3504 /* 3505 * Step 33: configure DMA resource watermarks 3506 */ 3507 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3508 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3509 bge_dmad_lo_water); 3510 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3511 bge_dmad_hi_water); 3512 } 3513 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3514 3515 /* 3516 * Steps 34-36: enable buffer manager & internal h/w queues 3517 */ 3518 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3519 STATE_MACHINE_ATTN_ENABLE_BIT)) 3520 retval = DDI_FAILURE; 3521 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3522 retval = DDI_FAILURE; 3523 3524 /* 3525 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3526 */ 3527 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3528 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3529 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3530 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3531 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3532 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3533 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3534 } 3535 3536 /* 3537 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3538 */ 3539 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3540 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3541 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3542 bge_replenish_jumbo); 3543 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3544 bge_replenish_mini); 3545 } 3546 3547 /* 3548 * Steps 41-43: clear Send Ring Producer Indices and initialise 3549 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3550 */ 3551 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3552 maxring = BGE_SEND_RINGS_MAX; 3553 else 3554 maxring = BGE_SEND_RINGS_MAX_5705; 3555 for (ring = 0; ring < maxring; ++ring) { 3556 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3557 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3558 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3559 &bgep->send[ring].hw_rcb); 3560 } 3561 3562 /* 3563 * Steps 44-45: initialise Receive Return Rings 3564 * (0x0200-0x02ff in NIC-local memory) 3565 */ 3566 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3567 maxring = BGE_RECV_RINGS_MAX; 3568 else 3569 maxring = BGE_RECV_RINGS_MAX_5705; 3570 for (ring = 0; ring < maxring; ++ring) 3571 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3572 &bgep->recv[ring].hw_rcb); 3573 3574 /* 3575 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3576 */ 3577 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3578 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3579 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3580 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3581 } 3582 /* 3583 * Step 47: configure the MAC unicast address 3584 * Step 48: configure the random backoff seed 3585 * Step 96: set up multicast filters 3586 */ 3587 #ifdef BGE_IPMI_ASF 3588 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3589 #else 3590 if (bge_chip_sync(bgep) == DDI_FAILURE) 3591 #endif 3592 retval = DDI_FAILURE; 3593 3594 /* 3595 * Step 49: configure the MTU 3596 */ 3597 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3598 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3599 3600 /* 3601 * Step 50: configure the IPG et al 3602 */ 3603 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3604 3605 /* 3606 * Step 51: configure the default Rx Return Ring 3607 */ 3608 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3609 3610 /* 3611 * Steps 52-54: configure Receive List Placement, 3612 * and enable Receive List Placement Statistics 3613 */ 3614 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3615 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3616 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3617 case MHCR_CHIP_ASIC_REV_5700: 3618 case MHCR_CHIP_ASIC_REV_5701: 3619 case MHCR_CHIP_ASIC_REV_5703: 3620 case MHCR_CHIP_ASIC_REV_5704: 3621 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3622 break; 3623 case MHCR_CHIP_ASIC_REV_5705: 3624 break; 3625 default: 3626 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3627 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3628 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3629 break; 3630 } 3631 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3632 3633 if (bgep->chipid.rx_rings > 1) 3634 bge_init_recv_rule(bgep); 3635 3636 /* 3637 * Steps 55-56: enable Send Data Initiator Statistics 3638 */ 3639 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3640 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3641 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3642 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3643 } else { 3644 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3645 SEND_INIT_STATS_ENABLE); 3646 } 3647 /* 3648 * Steps 57-58: stop (?) the Host Coalescing Engine 3649 */ 3650 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3651 retval = DDI_FAILURE; 3652 3653 /* 3654 * Steps 59-62: initialise Host Coalescing parameters 3655 */ 3656 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3657 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3658 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3659 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3660 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3661 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3662 bge_tx_count_intr); 3663 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3664 bge_tx_ticks_intr); 3665 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3666 bge_rx_count_intr); 3667 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3668 bge_rx_ticks_intr); 3669 } 3670 3671 /* 3672 * Steps 63-64: initialise status block & statistics 3673 * host memory addresses 3674 * The statistic block does not exist in some chipsets 3675 * Step 65: initialise Statistics Coalescing Tick Counter 3676 */ 3677 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3678 bgep->status_block.cookie.dmac_laddress); 3679 3680 /* 3681 * Steps 66-67: initialise status block & statistics 3682 * NIC-local memory addresses 3683 */ 3684 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3685 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3686 bgep->statistics.cookie.dmac_laddress); 3687 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3688 STATISTICS_TICKS_DEFAULT); 3689 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3690 NIC_MEM_STATUS_BLOCK); 3691 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3692 NIC_MEM_STATISTICS); 3693 } 3694 3695 /* 3696 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3697 * Completion Engine, the Receive List Placement Engine, and the 3698 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3699 * and BCM5715. 3700 */ 3701 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3702 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3703 coalmode = COALESCE_64_BYTE_STATUS; 3704 else 3705 coalmode = 0; 3706 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3707 retval = DDI_FAILURE; 3708 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3709 STATE_MACHINE_ATTN_ENABLE_BIT)) 3710 retval = DDI_FAILURE; 3711 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3712 retval = DDI_FAILURE; 3713 3714 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3715 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3716 STATE_MACHINE_ATTN_ENABLE_BIT)) 3717 retval = DDI_FAILURE; 3718 3719 /* 3720 * Step 72: Enable MAC DMA engines 3721 * Step 73: Clear & enable MAC statistics 3722 */ 3723 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3724 ETHERNET_MODE_ENABLE_FHDE | 3725 ETHERNET_MODE_ENABLE_RDE | 3726 ETHERNET_MODE_ENABLE_TDE); 3727 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3728 ETHERNET_MODE_ENABLE_TX_STATS | 3729 ETHERNET_MODE_ENABLE_RX_STATS | 3730 ETHERNET_MODE_CLEAR_TX_STATS | 3731 ETHERNET_MODE_CLEAR_RX_STATS); 3732 3733 /* 3734 * Step 74: configure the MLCR (Miscellaneous Local Control 3735 * Register); not required, as we set up the MLCR in step 10 3736 * (part of the reset code) above. 3737 * 3738 * Step 75: clear Interrupt Mailbox 0 3739 */ 3740 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3741 3742 /* 3743 * Steps 76-87: Gentlemen, start your engines ... 3744 * 3745 * Enable the DMA Completion Engine, the Write DMA Engine, 3746 * the Read DMA Engine, Receive Data Completion Engine, 3747 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3748 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3749 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3750 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3751 * 3752 * Beware exhaust fumes? 3753 */ 3754 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3755 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3756 retval = DDI_FAILURE; 3757 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3758 ALL_DMA_ATTN_BITS; 3759 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3760 MHCR_CHIP_ASIC_REV_5755) { 3761 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3762 } 3763 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3764 dma_wrprio)) 3765 retval = DDI_FAILURE; 3766 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3767 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3768 retval = DDI_FAILURE; 3769 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3770 STATE_MACHINE_ATTN_ENABLE_BIT)) 3771 retval = DDI_FAILURE; 3772 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3773 if (!bge_chip_enable_engine(bgep, 3774 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3775 retval = DDI_FAILURE; 3776 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3777 retval = DDI_FAILURE; 3778 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3779 STATE_MACHINE_ATTN_ENABLE_BIT)) 3780 retval = DDI_FAILURE; 3781 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3782 RCV_BD_DISABLED_RING_ATTN)) 3783 retval = DDI_FAILURE; 3784 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3785 RCV_DATA_BD_ILL_RING_ATTN)) 3786 retval = DDI_FAILURE; 3787 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3788 retval = DDI_FAILURE; 3789 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3790 STATE_MACHINE_ATTN_ENABLE_BIT)) 3791 retval = DDI_FAILURE; 3792 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3793 STATE_MACHINE_ATTN_ENABLE_BIT)) 3794 retval = DDI_FAILURE; 3795 3796 /* 3797 * Step 88: download firmware -- doesn't apply 3798 * Steps 89-90: enable Transmit & Receive MAC Engines 3799 */ 3800 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3801 retval = DDI_FAILURE; 3802 #ifdef BGE_IPMI_ASF 3803 if (!bgep->asf_enabled) { 3804 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3805 RECEIVE_MODE_KEEP_VLAN_TAG)) 3806 retval = DDI_FAILURE; 3807 } else { 3808 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3809 retval = DDI_FAILURE; 3810 } 3811 #else 3812 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3813 RECEIVE_MODE_KEEP_VLAN_TAG)) 3814 retval = DDI_FAILURE; 3815 #endif 3816 3817 /* 3818 * Step 91: disable auto-polling of PHY status 3819 */ 3820 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3821 3822 /* 3823 * Step 92: configure D0 power state (not required) 3824 * Step 93: initialise LED control register () 3825 */ 3826 ledctl = LED_CONTROL_DEFAULT; 3827 switch (bgep->chipid.device) { 3828 case DEVICE_ID_5700: 3829 case DEVICE_ID_5700x: 3830 case DEVICE_ID_5701: 3831 /* 3832 * Switch to 5700 (MAC) mode on these older chips 3833 */ 3834 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3835 ledctl |= LED_CONTROL_LED_MODE_5700; 3836 break; 3837 3838 default: 3839 break; 3840 } 3841 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3842 3843 /* 3844 * Step 94: activate link 3845 */ 3846 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3847 3848 /* 3849 * Step 95: set up physical layer (PHY/SerDes) 3850 * restart autoneg (if required) 3851 */ 3852 if (reset_phys) 3853 if (bge_phys_update(bgep) == DDI_FAILURE) 3854 retval = DDI_FAILURE; 3855 3856 /* 3857 * Extra step (DSG): hand over all the Receive Buffers to the chip 3858 */ 3859 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3860 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3861 bgep->buff[ring].rf_next); 3862 3863 /* 3864 * MSI bits:The least significant MSI 16-bit word. 3865 * ISR will be triggered different. 3866 */ 3867 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3868 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3869 3870 /* 3871 * Extra step (DSG): select which interrupts are enabled 3872 * 3873 * Program the Ethernet MAC engine to signal attention on 3874 * Link Change events, then enable interrupts on MAC, DMA, 3875 * and FLOW attention signals. 3876 */ 3877 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3878 ETHERNET_EVENT_LINK_INT | 3879 ETHERNET_STATUS_PCS_ERROR_INT); 3880 #ifdef BGE_IPMI_ASF 3881 if (bgep->asf_enabled) { 3882 bge_reg_set32(bgep, MODE_CONTROL_REG, 3883 MODE_INT_ON_FLOW_ATTN | 3884 MODE_INT_ON_DMA_ATTN | 3885 MODE_HOST_STACK_UP| 3886 MODE_INT_ON_MAC_ATTN); 3887 } else { 3888 #endif 3889 bge_reg_set32(bgep, MODE_CONTROL_REG, 3890 MODE_INT_ON_FLOW_ATTN | 3891 MODE_INT_ON_DMA_ATTN | 3892 MODE_INT_ON_MAC_ATTN); 3893 #ifdef BGE_IPMI_ASF 3894 } 3895 #endif 3896 3897 /* 3898 * Step 97: enable PCI interrupts!!! 3899 */ 3900 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3901 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3902 MHCR_MASK_PCI_INT_OUTPUT); 3903 3904 /* 3905 * All done! 3906 */ 3907 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3908 return (retval); 3909 } 3910 3911 3912 /* 3913 * ========== Hardware interrupt handler ========== 3914 */ 3915 3916 #undef BGE_DBG 3917 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3918 3919 /* 3920 * Sync the status block, then atomically clear the specified bits in 3921 * the <flags-and-tag> field of the status block. 3922 * the <flags> word of the status block, returning the value of the 3923 * <tag> and the <flags> before the bits were cleared. 3924 */ 3925 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3926 #pragma inline(bge_status_sync) 3927 3928 static int 3929 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3930 { 3931 bge_status_t *bsp; 3932 int retval; 3933 3934 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3935 (void *)bgep, bits)); 3936 3937 ASSERT(bgep->bge_guard == BGE_GUARD); 3938 3939 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3940 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3941 if (retval != DDI_FM_OK) 3942 return (retval); 3943 3944 bsp = DMA_VPTR(bgep->status_block); 3945 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3946 3947 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3948 (void *)bgep, bits, *flags)); 3949 3950 return (retval); 3951 } 3952 3953 void bge_wake_factotum(bge_t *bgep); 3954 #pragma inline(bge_wake_factotum) 3955 3956 void 3957 bge_wake_factotum(bge_t *bgep) 3958 { 3959 mutex_enter(bgep->softintrlock); 3960 if (bgep->factotum_flag == 0) { 3961 bgep->factotum_flag = 1; 3962 ddi_trigger_softintr(bgep->factotum_id); 3963 } 3964 mutex_exit(bgep->softintrlock); 3965 } 3966 3967 /* 3968 * bge_intr() -- handle chip interrupts 3969 */ 3970 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3971 #pragma no_inline(bge_intr) 3972 3973 uint_t 3974 bge_intr(caddr_t arg1, caddr_t arg2) 3975 { 3976 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3977 bge_status_t *bsp; 3978 uint64_t flags; 3979 uint32_t regval; 3980 uint_t result; 3981 int retval, loop_cnt = 0; 3982 3983 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3984 3985 /* 3986 * GLD v2 checks that s/w setup is complete before passing 3987 * interrupts to this routine, thus eliminating the old 3988 * (and well-known) race condition around ddi_add_intr() 3989 */ 3990 ASSERT(bgep->progress & PROGRESS_HWINT); 3991 3992 result = DDI_INTR_UNCLAIMED; 3993 mutex_enter(bgep->genlock); 3994 3995 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3996 /* 3997 * Check whether chip's says it's asserting #INTA; 3998 * if not, don't process or claim the interrupt. 3999 * 4000 * Note that the PCI signal is active low, so the 4001 * bit is *zero* when the interrupt is asserted. 4002 */ 4003 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4004 if (regval & MLCR_INTA_STATE) { 4005 if (bge_check_acc_handle(bgep, bgep->io_handle) 4006 != DDI_FM_OK) 4007 goto chip_stop; 4008 mutex_exit(bgep->genlock); 4009 return (result); 4010 } 4011 4012 /* 4013 * Block further PCI interrupts ... 4014 */ 4015 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4016 MHCR_MASK_PCI_INT_OUTPUT); 4017 4018 } else { 4019 /* 4020 * Check MSI status 4021 */ 4022 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4023 if (regval & MSI_ERROR_ATTENTION) { 4024 BGE_REPORT((bgep, "msi error attention," 4025 " status=0x%x", regval)); 4026 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4027 } 4028 } 4029 4030 result = DDI_INTR_CLAIMED; 4031 4032 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4033 4034 /* 4035 * Sync the status block and grab the flags-n-tag from it. 4036 * We count the number of interrupts where there doesn't 4037 * seem to have been a DMA update of the status block; if 4038 * it *has* been updated, the counter will be cleared in 4039 * the while() loop below ... 4040 */ 4041 bgep->missed_dmas += 1; 4042 bsp = DMA_VPTR(bgep->status_block); 4043 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4044 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4045 /* 4046 * bge_chip_stop() may have freed dma area etc 4047 * while we were in this interrupt handler - 4048 * better not call bge_status_sync() 4049 */ 4050 (void) bge_check_acc_handle(bgep, 4051 bgep->io_handle); 4052 mutex_exit(bgep->genlock); 4053 return (DDI_INTR_CLAIMED); 4054 } 4055 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4056 &flags); 4057 if (retval != DDI_FM_OK) { 4058 bgep->bge_dma_error = B_TRUE; 4059 goto chip_stop; 4060 } 4061 4062 if (!(flags & STATUS_FLAG_UPDATED)) 4063 break; 4064 4065 /* 4066 * Tell the chip that we're processing the interrupt 4067 */ 4068 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4069 INTERRUPT_MBOX_DISABLE(flags)); 4070 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4071 DDI_FM_OK) 4072 goto chip_stop; 4073 4074 /* 4075 * Drop the mutex while we: 4076 * Receive any newly-arrived packets 4077 * Recycle any newly-finished send buffers 4078 */ 4079 bgep->bge_intr_running = B_TRUE; 4080 mutex_exit(bgep->genlock); 4081 bge_receive(bgep, bsp); 4082 bge_recycle(bgep, bsp); 4083 mutex_enter(bgep->genlock); 4084 bgep->bge_intr_running = B_FALSE; 4085 4086 /* 4087 * Tell the chip we've finished processing, and 4088 * give it the tag that we got from the status 4089 * block earlier, so that it knows just how far 4090 * we've gone. If it's got more for us to do, 4091 * it will now update the status block and try 4092 * to assert an interrupt (but we've got the 4093 * #INTA blocked at present). If we see the 4094 * update, we'll loop around to do some more. 4095 * Eventually we'll get out of here ... 4096 */ 4097 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4098 INTERRUPT_MBOX_ENABLE(flags)); 4099 if (bgep->chipid.pci_type == BGE_PCI_E) 4100 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4101 bgep->missed_dmas = 0; 4102 } 4103 4104 /* 4105 * Check for exceptional conditions that we need to handle 4106 * 4107 * Link status changed 4108 * Status block not updated 4109 */ 4110 if (flags & STATUS_FLAG_LINK_CHANGED) 4111 bge_wake_factotum(bgep); 4112 4113 if (bgep->missed_dmas) { 4114 /* 4115 * Probably due to the internal status tag not 4116 * being reset. Force a status block update now; 4117 * this should ensure that we get an update and 4118 * a new interrupt. After that, we should be in 4119 * sync again ... 4120 */ 4121 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4122 "not updated?", flags)); 4123 bgep->missed_updates++; 4124 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4125 COALESCE_NOW); 4126 4127 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4128 /* 4129 * If this happens multiple times in a row, 4130 * it means DMA is just not working. Maybe 4131 * the chip's failed, or maybe there's a 4132 * problem on the PCI bus or in the host-PCI 4133 * bridge (Tomatillo). 4134 * 4135 * At all events, we want to stop further 4136 * interrupts and let the recovery code take 4137 * over to see whether anything can be done 4138 * about it ... 4139 */ 4140 bge_fm_ereport(bgep, 4141 DDI_FM_DEVICE_BADINT_LIMIT); 4142 goto chip_stop; 4143 } 4144 } 4145 4146 /* 4147 * Reenable assertion of #INTA, unless there's a DMA fault 4148 */ 4149 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4150 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4151 MHCR_MASK_PCI_INT_OUTPUT); 4152 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4153 DDI_FM_OK) 4154 goto chip_stop; 4155 } 4156 4157 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4158 goto chip_stop; 4159 4160 mutex_exit(bgep->genlock); 4161 return (result); 4162 4163 chip_stop: 4164 #ifdef BGE_IPMI_ASF 4165 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4166 /* 4167 * We must stop ASF heart beat before 4168 * bge_chip_stop(), otherwise some 4169 * computers (ex. IBM HS20 blade 4170 * server) may crash. 4171 */ 4172 bge_asf_update_status(bgep); 4173 bge_asf_stop_timer(bgep); 4174 bgep->asf_status = ASF_STAT_STOP; 4175 4176 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4177 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4178 } 4179 #endif 4180 bge_chip_stop(bgep, B_TRUE); 4181 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4182 mutex_exit(bgep->genlock); 4183 return (result); 4184 } 4185 4186 /* 4187 * ========== Factotum, implemented as a softint handler ========== 4188 */ 4189 4190 #undef BGE_DBG 4191 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4192 4193 static void bge_factotum_error_handler(bge_t *bgep); 4194 #pragma no_inline(bge_factotum_error_handler) 4195 4196 static void 4197 bge_factotum_error_handler(bge_t *bgep) 4198 { 4199 uint32_t flow; 4200 uint32_t rdma; 4201 uint32_t wdma; 4202 uint32_t tmac; 4203 uint32_t rmac; 4204 uint32_t rxrs; 4205 uint32_t txrs = 0; 4206 4207 ASSERT(mutex_owned(bgep->genlock)); 4208 4209 /* 4210 * Read all the registers that show the possible 4211 * reasons for the ERROR bit to be asserted 4212 */ 4213 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4214 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4215 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4216 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4217 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4218 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4219 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4220 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4221 4222 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4223 (void *)bgep, flow, rdma, wdma)); 4224 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4225 (void *)bgep, tmac, rmac, rxrs, txrs)); 4226 4227 /* 4228 * For now, just clear all the errors ... 4229 */ 4230 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4231 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4232 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4233 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4234 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4235 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4236 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4237 } 4238 4239 /* 4240 * Handler for hardware link state change. 4241 * 4242 * When this routine is called, the hardware link state has changed 4243 * and the new state is reflected in the param_* variables. Here 4244 * we must update the softstate and reprogram the MAC to match. 4245 */ 4246 static void bge_factotum_link_handler(bge_t *bgep); 4247 #pragma no_inline(bge_factotum_link_handler) 4248 4249 static void 4250 bge_factotum_link_handler(bge_t *bgep) 4251 { 4252 ASSERT(mutex_owned(bgep->genlock)); 4253 4254 /* 4255 * Update the s/w link_state 4256 */ 4257 if (bgep->param_link_up) 4258 bgep->link_state = LINK_STATE_UP; 4259 else 4260 bgep->link_state = LINK_STATE_DOWN; 4261 4262 /* 4263 * Reprogram the MAC modes to match 4264 */ 4265 bge_sync_mac_modes(bgep); 4266 } 4267 4268 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4269 #pragma no_inline(bge_factotum_link_check) 4270 4271 static boolean_t 4272 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4273 { 4274 boolean_t check; 4275 uint64_t flags; 4276 uint32_t tmac_status; 4277 4278 ASSERT(mutex_owned(bgep->genlock)); 4279 4280 /* 4281 * Get & clear the writable status bits in the Tx status register 4282 * (some bits are write-1-to-clear, others are just readonly). 4283 */ 4284 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4285 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4286 4287 /* 4288 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4289 */ 4290 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4291 STATUS_FLAG_LINK_CHANGED, &flags); 4292 if (*dma_state != DDI_FM_OK) 4293 return (B_FALSE); 4294 4295 /* 4296 * Clear any errors flagged in the status block ... 4297 */ 4298 if (flags & STATUS_FLAG_ERROR) 4299 bge_factotum_error_handler(bgep); 4300 4301 /* 4302 * We need to check the link status if: 4303 * the status block says there's been a link change 4304 * or there's any discrepancy between the various 4305 * flags indicating the link state (link_state, 4306 * param_link_up, and the LINK STATE bit in the 4307 * Transmit MAC status register). 4308 */ 4309 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4310 switch (bgep->link_state) { 4311 case LINK_STATE_UP: 4312 check |= (bgep->param_link_up == B_FALSE); 4313 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4314 break; 4315 4316 case LINK_STATE_DOWN: 4317 check |= (bgep->param_link_up != B_FALSE); 4318 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4319 break; 4320 4321 default: 4322 check = B_TRUE; 4323 break; 4324 } 4325 4326 /* 4327 * If <check> is false, we're sure the link hasn't changed. 4328 * If true, however, it's not yet definitive; we have to call 4329 * bge_phys_check() to determine whether the link has settled 4330 * into a new state yet ... and if it has, then call the link 4331 * state change handler.But when the chip is 5700 in Dell 6650 4332 * ,even if check is false, the link may have changed.So we 4333 * have to call bge_phys_check() to determine the link state. 4334 */ 4335 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4336 check = bge_phys_check(bgep); 4337 if (check) 4338 bge_factotum_link_handler(bgep); 4339 } 4340 4341 return (check); 4342 } 4343 4344 /* 4345 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4346 */ 4347 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4348 #pragma no_inline(bge_factotum_stall_check) 4349 4350 static boolean_t 4351 bge_factotum_stall_check(bge_t *bgep) 4352 { 4353 uint32_t dogval; 4354 4355 ASSERT(mutex_owned(bgep->genlock)); 4356 4357 /* 4358 * Specific check for Tx stall ... 4359 * 4360 * The 'watchdog' counter is incremented whenever a packet 4361 * is queued, reset to 1 when some (but not all) buffers 4362 * are reclaimed, reset to 0 (disabled) when all buffers 4363 * are reclaimed, and shifted left here. If it exceeds the 4364 * threshold value, the chip is assumed to have stalled and 4365 * is put into the ERROR state. The factotum will then reset 4366 * it on the next pass. 4367 * 4368 * All of which should ensure that we don't get into a state 4369 * where packets are left pending indefinitely! 4370 */ 4371 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4372 if (dogval < bge_watchdog_count) 4373 return (B_FALSE); 4374 4375 #if !defined(BGE_NETCONSOLE) 4376 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4377 #endif 4378 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4379 return (B_TRUE); 4380 } 4381 4382 /* 4383 * The factotum is woken up when there's something to do that we'd rather 4384 * not do from inside a hardware interrupt handler or high-level cyclic. 4385 * Its two main tasks are: 4386 * reset & restart the chip after an error 4387 * check the link status whenever necessary 4388 */ 4389 uint_t bge_chip_factotum(caddr_t arg); 4390 #pragma no_inline(bge_chip_factotum) 4391 4392 uint_t 4393 bge_chip_factotum(caddr_t arg) 4394 { 4395 bge_t *bgep; 4396 uint_t result; 4397 boolean_t error; 4398 boolean_t linkchg; 4399 int dma_state; 4400 4401 bgep = (bge_t *)arg; 4402 4403 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4404 4405 mutex_enter(bgep->softintrlock); 4406 if (bgep->factotum_flag == 0) { 4407 mutex_exit(bgep->softintrlock); 4408 return (DDI_INTR_UNCLAIMED); 4409 } 4410 bgep->factotum_flag = 0; 4411 mutex_exit(bgep->softintrlock); 4412 4413 result = DDI_INTR_CLAIMED; 4414 error = B_FALSE; 4415 linkchg = B_FALSE; 4416 4417 mutex_enter(bgep->genlock); 4418 switch (bgep->bge_chip_state) { 4419 default: 4420 break; 4421 4422 case BGE_CHIP_RUNNING: 4423 linkchg = bge_factotum_link_check(bgep, &dma_state); 4424 error = bge_factotum_stall_check(bgep); 4425 if (dma_state != DDI_FM_OK) { 4426 bgep->bge_dma_error = B_TRUE; 4427 error = B_TRUE; 4428 } 4429 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4430 error = B_TRUE; 4431 if (error) 4432 bgep->bge_chip_state = BGE_CHIP_ERROR; 4433 break; 4434 4435 case BGE_CHIP_ERROR: 4436 error = B_TRUE; 4437 break; 4438 4439 case BGE_CHIP_FAULT: 4440 /* 4441 * Fault detected, time to reset ... 4442 */ 4443 if (bge_autorecover) { 4444 if (!(bgep->progress & PROGRESS_BUFS)) { 4445 /* 4446 * if we can't allocate the ring buffers, 4447 * try later 4448 */ 4449 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4450 mutex_exit(bgep->genlock); 4451 return (result); 4452 } 4453 bgep->progress |= PROGRESS_BUFS; 4454 } 4455 if (!(bgep->progress & PROGRESS_INTR)) { 4456 bge_init_rings(bgep); 4457 bge_intr_enable(bgep); 4458 bgep->progress |= PROGRESS_INTR; 4459 } 4460 if (!(bgep->progress & PROGRESS_KSTATS)) { 4461 bge_init_kstats(bgep, 4462 ddi_get_instance(bgep->devinfo)); 4463 bgep->progress |= PROGRESS_KSTATS; 4464 } 4465 4466 BGE_REPORT((bgep, "automatic recovery activated")); 4467 4468 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4469 bgep->bge_chip_state = BGE_CHIP_ERROR; 4470 error = B_TRUE; 4471 } 4472 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4473 DDI_FM_OK) { 4474 bgep->bge_chip_state = BGE_CHIP_ERROR; 4475 error = B_TRUE; 4476 } 4477 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4478 DDI_FM_OK) { 4479 bgep->bge_chip_state = BGE_CHIP_ERROR; 4480 error = B_TRUE; 4481 } 4482 if (error == B_FALSE) { 4483 #ifdef BGE_IPMI_ASF 4484 if (bgep->asf_enabled && 4485 bgep->asf_status != ASF_STAT_RUN) { 4486 bgep->asf_timeout_id = timeout( 4487 bge_asf_heartbeat, (void *)bgep, 4488 drv_usectohz( 4489 BGE_ASF_HEARTBEAT_INTERVAL)); 4490 bgep->asf_status = ASF_STAT_RUN; 4491 } 4492 #endif 4493 if (!bgep->manual_reset) { 4494 ddi_fm_service_impact(bgep->devinfo, 4495 DDI_SERVICE_RESTORED); 4496 } 4497 } 4498 } 4499 break; 4500 } 4501 4502 4503 /* 4504 * If an error is detected, stop the chip now, marking it as 4505 * faulty, so that it will be reset next time through ... 4506 * 4507 * Note that if intr_running is set, then bge_intr() has dropped 4508 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4509 * this point so have to wait until the next time the factotum runs. 4510 */ 4511 if (error && !bgep->bge_intr_running) { 4512 #ifdef BGE_IPMI_ASF 4513 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4514 /* 4515 * We must stop ASF heart beat before bge_chip_stop(), 4516 * otherwise some computers (ex. IBM HS20 blade server) 4517 * may crash. 4518 */ 4519 bge_asf_update_status(bgep); 4520 bge_asf_stop_timer(bgep); 4521 bgep->asf_status = ASF_STAT_STOP; 4522 4523 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4524 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4525 } 4526 #endif 4527 bge_chip_stop(bgep, B_TRUE); 4528 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4529 } 4530 mutex_exit(bgep->genlock); 4531 4532 /* 4533 * If the link state changed, tell the world about it. 4534 * Note: can't do this while still holding the mutex. 4535 */ 4536 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4537 bgep->link_state != LINK_STATE_UNKNOWN) 4538 linkchg = B_TRUE; 4539 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4540 bgep->link_state == LINK_STATE_DOWN) 4541 linkchg = B_FALSE; 4542 4543 if (linkchg) { 4544 mac_link_update(bgep->mh, bgep->link_state); 4545 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4546 } 4547 if (bgep->manual_reset) { 4548 bgep->manual_reset = B_FALSE; 4549 } 4550 4551 return (result); 4552 } 4553 4554 /* 4555 * High-level cyclic handler 4556 * 4557 * This routine schedules a (low-level) softint callback to the 4558 * factotum, and prods the chip to update the status block (which 4559 * will cause a hardware interrupt when complete). 4560 */ 4561 void bge_chip_cyclic(void *arg); 4562 #pragma no_inline(bge_chip_cyclic) 4563 4564 void 4565 bge_chip_cyclic(void *arg) 4566 { 4567 bge_t *bgep; 4568 4569 bgep = arg; 4570 4571 switch (bgep->bge_chip_state) { 4572 default: 4573 return; 4574 4575 case BGE_CHIP_RUNNING: 4576 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4577 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4578 ddi_fm_service_impact(bgep->devinfo, 4579 DDI_SERVICE_UNAFFECTED); 4580 4581 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4582 bgep->link_update_timer++; 4583 4584 break; 4585 4586 case BGE_CHIP_FAULT: 4587 case BGE_CHIP_ERROR: 4588 break; 4589 } 4590 4591 bge_wake_factotum(bgep); 4592 } 4593 4594 4595 /* 4596 * ========== Ioctl subfunctions ========== 4597 */ 4598 4599 #undef BGE_DBG 4600 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4601 4602 #if BGE_DEBUGGING || BGE_DO_PPIO 4603 4604 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4605 #pragma no_inline(bge_chip_peek_cfg) 4606 4607 static void 4608 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4609 { 4610 uint64_t regval; 4611 uint64_t regno; 4612 4613 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4614 (void *)bgep, (void *)ppd)); 4615 4616 regno = ppd->pp_acc_offset; 4617 4618 switch (ppd->pp_acc_size) { 4619 case 1: 4620 regval = pci_config_get8(bgep->cfg_handle, regno); 4621 break; 4622 4623 case 2: 4624 regval = pci_config_get16(bgep->cfg_handle, regno); 4625 break; 4626 4627 case 4: 4628 regval = pci_config_get32(bgep->cfg_handle, regno); 4629 break; 4630 4631 case 8: 4632 regval = pci_config_get64(bgep->cfg_handle, regno); 4633 break; 4634 } 4635 4636 ppd->pp_acc_data = regval; 4637 } 4638 4639 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4640 #pragma no_inline(bge_chip_poke_cfg) 4641 4642 static void 4643 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4644 { 4645 uint64_t regval; 4646 uint64_t regno; 4647 4648 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4649 (void *)bgep, (void *)ppd)); 4650 4651 regno = ppd->pp_acc_offset; 4652 regval = ppd->pp_acc_data; 4653 4654 switch (ppd->pp_acc_size) { 4655 case 1: 4656 pci_config_put8(bgep->cfg_handle, regno, regval); 4657 break; 4658 4659 case 2: 4660 pci_config_put16(bgep->cfg_handle, regno, regval); 4661 break; 4662 4663 case 4: 4664 pci_config_put32(bgep->cfg_handle, regno, regval); 4665 break; 4666 4667 case 8: 4668 pci_config_put64(bgep->cfg_handle, regno, regval); 4669 break; 4670 } 4671 } 4672 4673 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4674 #pragma no_inline(bge_chip_peek_reg) 4675 4676 static void 4677 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4678 { 4679 uint64_t regval; 4680 void *regaddr; 4681 4682 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4683 (void *)bgep, (void *)ppd)); 4684 4685 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4686 4687 switch (ppd->pp_acc_size) { 4688 case 1: 4689 regval = ddi_get8(bgep->io_handle, regaddr); 4690 break; 4691 4692 case 2: 4693 regval = ddi_get16(bgep->io_handle, regaddr); 4694 break; 4695 4696 case 4: 4697 regval = ddi_get32(bgep->io_handle, regaddr); 4698 break; 4699 4700 case 8: 4701 regval = ddi_get64(bgep->io_handle, regaddr); 4702 break; 4703 } 4704 4705 ppd->pp_acc_data = regval; 4706 } 4707 4708 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4709 #pragma no_inline(bge_chip_peek_reg) 4710 4711 static void 4712 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4713 { 4714 uint64_t regval; 4715 void *regaddr; 4716 4717 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4718 (void *)bgep, (void *)ppd)); 4719 4720 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4721 regval = ppd->pp_acc_data; 4722 4723 switch (ppd->pp_acc_size) { 4724 case 1: 4725 ddi_put8(bgep->io_handle, regaddr, regval); 4726 break; 4727 4728 case 2: 4729 ddi_put16(bgep->io_handle, regaddr, regval); 4730 break; 4731 4732 case 4: 4733 ddi_put32(bgep->io_handle, regaddr, regval); 4734 break; 4735 4736 case 8: 4737 ddi_put64(bgep->io_handle, regaddr, regval); 4738 break; 4739 } 4740 BGE_PCICHK(bgep); 4741 } 4742 4743 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4744 #pragma no_inline(bge_chip_peek_nic) 4745 4746 static void 4747 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4748 { 4749 uint64_t regoff; 4750 uint64_t regval; 4751 void *regaddr; 4752 4753 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4754 (void *)bgep, (void *)ppd)); 4755 4756 regoff = ppd->pp_acc_offset; 4757 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4758 regoff &= MWBAR_GRANULE_MASK; 4759 regoff += NIC_MEM_WINDOW_OFFSET; 4760 regaddr = PIO_ADDR(bgep, regoff); 4761 4762 switch (ppd->pp_acc_size) { 4763 case 1: 4764 regval = ddi_get8(bgep->io_handle, regaddr); 4765 break; 4766 4767 case 2: 4768 regval = ddi_get16(bgep->io_handle, regaddr); 4769 break; 4770 4771 case 4: 4772 regval = ddi_get32(bgep->io_handle, regaddr); 4773 break; 4774 4775 case 8: 4776 regval = ddi_get64(bgep->io_handle, regaddr); 4777 break; 4778 } 4779 4780 ppd->pp_acc_data = regval; 4781 } 4782 4783 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4784 #pragma no_inline(bge_chip_poke_nic) 4785 4786 static void 4787 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4788 { 4789 uint64_t regoff; 4790 uint64_t regval; 4791 void *regaddr; 4792 4793 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4794 (void *)bgep, (void *)ppd)); 4795 4796 regoff = ppd->pp_acc_offset; 4797 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4798 regoff &= MWBAR_GRANULE_MASK; 4799 regoff += NIC_MEM_WINDOW_OFFSET; 4800 regaddr = PIO_ADDR(bgep, regoff); 4801 regval = ppd->pp_acc_data; 4802 4803 switch (ppd->pp_acc_size) { 4804 case 1: 4805 ddi_put8(bgep->io_handle, regaddr, regval); 4806 break; 4807 4808 case 2: 4809 ddi_put16(bgep->io_handle, regaddr, regval); 4810 break; 4811 4812 case 4: 4813 ddi_put32(bgep->io_handle, regaddr, regval); 4814 break; 4815 4816 case 8: 4817 ddi_put64(bgep->io_handle, regaddr, regval); 4818 break; 4819 } 4820 BGE_PCICHK(bgep); 4821 } 4822 4823 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4824 #pragma no_inline(bge_chip_peek_mii) 4825 4826 static void 4827 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4828 { 4829 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4830 (void *)bgep, (void *)ppd)); 4831 4832 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4833 } 4834 4835 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4836 #pragma no_inline(bge_chip_poke_mii) 4837 4838 static void 4839 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4840 { 4841 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4842 (void *)bgep, (void *)ppd)); 4843 4844 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4845 } 4846 4847 #if BGE_SEE_IO32 4848 4849 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4850 #pragma no_inline(bge_chip_peek_seeprom) 4851 4852 static void 4853 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4854 { 4855 uint32_t data; 4856 int err; 4857 4858 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4859 (void *)bgep, (void *)ppd)); 4860 4861 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4862 ppd->pp_acc_data = err ? ~0ull : data; 4863 } 4864 4865 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4866 #pragma no_inline(bge_chip_poke_seeprom) 4867 4868 static void 4869 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4870 { 4871 uint32_t data; 4872 4873 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4874 (void *)bgep, (void *)ppd)); 4875 4876 data = ppd->pp_acc_data; 4877 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4878 } 4879 #endif /* BGE_SEE_IO32 */ 4880 4881 #if BGE_FLASH_IO32 4882 4883 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4884 #pragma no_inline(bge_chip_peek_flash) 4885 4886 static void 4887 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4888 { 4889 uint32_t data; 4890 int err; 4891 4892 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4893 (void *)bgep, (void *)ppd)); 4894 4895 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4896 ppd->pp_acc_data = err ? ~0ull : data; 4897 } 4898 4899 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4900 #pragma no_inline(bge_chip_poke_flash) 4901 4902 static void 4903 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4904 { 4905 uint32_t data; 4906 4907 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4908 (void *)bgep, (void *)ppd)); 4909 4910 data = ppd->pp_acc_data; 4911 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4912 ppd->pp_acc_offset, &data); 4913 } 4914 #endif /* BGE_FLASH_IO32 */ 4915 4916 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4917 #pragma no_inline(bge_chip_peek_mem) 4918 4919 static void 4920 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4921 { 4922 uint64_t regval; 4923 void *vaddr; 4924 4925 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4926 (void *)bgep, (void *)ppd)); 4927 4928 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4929 4930 switch (ppd->pp_acc_size) { 4931 case 1: 4932 regval = *(uint8_t *)vaddr; 4933 break; 4934 4935 case 2: 4936 regval = *(uint16_t *)vaddr; 4937 break; 4938 4939 case 4: 4940 regval = *(uint32_t *)vaddr; 4941 break; 4942 4943 case 8: 4944 regval = *(uint64_t *)vaddr; 4945 break; 4946 } 4947 4948 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4949 (void *)bgep, (void *)ppd, regval, vaddr)); 4950 4951 ppd->pp_acc_data = regval; 4952 } 4953 4954 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4955 #pragma no_inline(bge_chip_poke_mem) 4956 4957 static void 4958 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4959 { 4960 uint64_t regval; 4961 void *vaddr; 4962 4963 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4964 (void *)bgep, (void *)ppd)); 4965 4966 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4967 regval = ppd->pp_acc_data; 4968 4969 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4970 (void *)bgep, (void *)ppd, regval, vaddr)); 4971 4972 switch (ppd->pp_acc_size) { 4973 case 1: 4974 *(uint8_t *)vaddr = (uint8_t)regval; 4975 break; 4976 4977 case 2: 4978 *(uint16_t *)vaddr = (uint16_t)regval; 4979 break; 4980 4981 case 4: 4982 *(uint32_t *)vaddr = (uint32_t)regval; 4983 break; 4984 4985 case 8: 4986 *(uint64_t *)vaddr = (uint64_t)regval; 4987 break; 4988 } 4989 } 4990 4991 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4992 struct iocblk *iocp); 4993 #pragma no_inline(bge_pp_ioctl) 4994 4995 static enum ioc_reply 4996 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4997 { 4998 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4999 bge_peekpoke_t *ppd; 5000 dma_area_t *areap; 5001 uint64_t sizemask; 5002 uint64_t mem_va; 5003 uint64_t maxoff; 5004 boolean_t peek; 5005 5006 switch (cmd) { 5007 default: 5008 /* NOTREACHED */ 5009 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5010 return (IOC_INVAL); 5011 5012 case BGE_PEEK: 5013 peek = B_TRUE; 5014 break; 5015 5016 case BGE_POKE: 5017 peek = B_FALSE; 5018 break; 5019 } 5020 5021 /* 5022 * Validate format of ioctl 5023 */ 5024 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5025 return (IOC_INVAL); 5026 if (mp->b_cont == NULL) 5027 return (IOC_INVAL); 5028 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 5029 5030 /* 5031 * Validate request parameters 5032 */ 5033 switch (ppd->pp_acc_space) { 5034 default: 5035 return (IOC_INVAL); 5036 5037 case BGE_PP_SPACE_CFG: 5038 /* 5039 * Config space 5040 */ 5041 sizemask = 8|4|2|1; 5042 mem_va = 0; 5043 maxoff = PCI_CONF_HDR_SIZE; 5044 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5045 break; 5046 5047 case BGE_PP_SPACE_REG: 5048 /* 5049 * Memory-mapped I/O space 5050 */ 5051 sizemask = 8|4|2|1; 5052 mem_va = 0; 5053 maxoff = RIAAR_REGISTER_MAX; 5054 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5055 break; 5056 5057 case BGE_PP_SPACE_NIC: 5058 /* 5059 * NIC on-chip memory 5060 */ 5061 sizemask = 8|4|2|1; 5062 mem_va = 0; 5063 maxoff = MWBAR_ONCHIP_MAX; 5064 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5065 break; 5066 5067 case BGE_PP_SPACE_MII: 5068 /* 5069 * PHY's MII registers 5070 * NB: all PHY registers are two bytes, but the 5071 * addresses increment in ones (word addressing). 5072 * So we scale the address here, then undo the 5073 * transformation inside the peek/poke functions. 5074 */ 5075 ppd->pp_acc_offset *= 2; 5076 sizemask = 2; 5077 mem_va = 0; 5078 maxoff = (MII_MAXREG+1)*2; 5079 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5080 break; 5081 5082 #if BGE_SEE_IO32 5083 case BGE_PP_SPACE_SEEPROM: 5084 /* 5085 * Attached SEEPROM(s), if any. 5086 * NB: we use the high-order bits of the 'address' as 5087 * a device select to accommodate multiple SEEPROMS, 5088 * If each one is the maximum size (64kbytes), this 5089 * makes them appear contiguous. Otherwise, there may 5090 * be holes in the mapping. ENxS doesn't have any 5091 * SEEPROMs anyway ... 5092 */ 5093 sizemask = 4; 5094 mem_va = 0; 5095 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5096 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5097 break; 5098 #endif /* BGE_SEE_IO32 */ 5099 5100 #if BGE_FLASH_IO32 5101 case BGE_PP_SPACE_FLASH: 5102 /* 5103 * Attached Flash device (if any); a maximum of one device 5104 * is currently supported. But it can be up to 1MB (unlike 5105 * the 64k limit on SEEPROMs) so why would you need more ;-) 5106 */ 5107 sizemask = 4; 5108 mem_va = 0; 5109 maxoff = NVM_FLASH_ADDR_MASK; 5110 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5111 break; 5112 #endif /* BGE_FLASH_IO32 */ 5113 5114 case BGE_PP_SPACE_BGE: 5115 /* 5116 * BGE data structure! 5117 */ 5118 sizemask = 8|4|2|1; 5119 mem_va = (uintptr_t)bgep; 5120 maxoff = sizeof (*bgep); 5121 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5122 break; 5123 5124 case BGE_PP_SPACE_STATUS: 5125 case BGE_PP_SPACE_STATISTICS: 5126 case BGE_PP_SPACE_TXDESC: 5127 case BGE_PP_SPACE_TXBUFF: 5128 case BGE_PP_SPACE_RXDESC: 5129 case BGE_PP_SPACE_RXBUFF: 5130 /* 5131 * Various DMA_AREAs 5132 */ 5133 switch (ppd->pp_acc_space) { 5134 case BGE_PP_SPACE_TXDESC: 5135 areap = &bgep->tx_desc; 5136 break; 5137 case BGE_PP_SPACE_TXBUFF: 5138 areap = &bgep->tx_buff[0]; 5139 break; 5140 case BGE_PP_SPACE_RXDESC: 5141 areap = &bgep->rx_desc[0]; 5142 break; 5143 case BGE_PP_SPACE_RXBUFF: 5144 areap = &bgep->rx_buff[0]; 5145 break; 5146 case BGE_PP_SPACE_STATUS: 5147 areap = &bgep->status_block; 5148 break; 5149 case BGE_PP_SPACE_STATISTICS: 5150 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5151 areap = &bgep->statistics; 5152 break; 5153 } 5154 5155 sizemask = 8|4|2|1; 5156 mem_va = (uintptr_t)areap->mem_va; 5157 maxoff = areap->alength; 5158 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5159 break; 5160 } 5161 5162 switch (ppd->pp_acc_size) { 5163 default: 5164 return (IOC_INVAL); 5165 5166 case 8: 5167 case 4: 5168 case 2: 5169 case 1: 5170 if ((ppd->pp_acc_size & sizemask) == 0) 5171 return (IOC_INVAL); 5172 break; 5173 } 5174 5175 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5176 return (IOC_INVAL); 5177 5178 if (ppd->pp_acc_offset >= maxoff) 5179 return (IOC_INVAL); 5180 5181 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5182 return (IOC_INVAL); 5183 5184 /* 5185 * All OK - go do it! 5186 */ 5187 ppd->pp_acc_offset += mem_va; 5188 (*ppfn)(bgep, ppd); 5189 return (peek ? IOC_REPLY : IOC_ACK); 5190 } 5191 5192 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5193 struct iocblk *iocp); 5194 #pragma no_inline(bge_diag_ioctl) 5195 5196 static enum ioc_reply 5197 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5198 { 5199 ASSERT(mutex_owned(bgep->genlock)); 5200 5201 switch (cmd) { 5202 default: 5203 /* NOTREACHED */ 5204 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5205 return (IOC_INVAL); 5206 5207 case BGE_DIAG: 5208 /* 5209 * Currently a no-op 5210 */ 5211 return (IOC_ACK); 5212 5213 case BGE_PEEK: 5214 case BGE_POKE: 5215 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5216 5217 case BGE_PHY_RESET: 5218 return (IOC_RESTART_ACK); 5219 5220 case BGE_SOFT_RESET: 5221 case BGE_HARD_RESET: 5222 /* 5223 * Reset and reinitialise the 570x hardware 5224 */ 5225 bgep->bge_chip_state = BGE_CHIP_FAULT; 5226 ddi_trigger_softintr(bgep->factotum_id); 5227 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5228 return (IOC_ACK); 5229 } 5230 5231 /* NOTREACHED */ 5232 } 5233 5234 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5235 5236 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5237 struct iocblk *iocp); 5238 #pragma no_inline(bge_mii_ioctl) 5239 5240 static enum ioc_reply 5241 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5242 { 5243 struct bge_mii_rw *miirwp; 5244 5245 /* 5246 * Validate format of ioctl 5247 */ 5248 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5249 return (IOC_INVAL); 5250 if (mp->b_cont == NULL) 5251 return (IOC_INVAL); 5252 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5253 5254 /* 5255 * Validate request parameters ... 5256 */ 5257 if (miirwp->mii_reg > MII_MAXREG) 5258 return (IOC_INVAL); 5259 5260 switch (cmd) { 5261 default: 5262 /* NOTREACHED */ 5263 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5264 return (IOC_INVAL); 5265 5266 case BGE_MII_READ: 5267 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5268 return (IOC_REPLY); 5269 5270 case BGE_MII_WRITE: 5271 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5272 return (IOC_ACK); 5273 } 5274 5275 /* NOTREACHED */ 5276 } 5277 5278 #if BGE_SEE_IO32 5279 5280 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5281 struct iocblk *iocp); 5282 #pragma no_inline(bge_see_ioctl) 5283 5284 static enum ioc_reply 5285 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5286 { 5287 struct bge_see_rw *seerwp; 5288 5289 /* 5290 * Validate format of ioctl 5291 */ 5292 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5293 return (IOC_INVAL); 5294 if (mp->b_cont == NULL) 5295 return (IOC_INVAL); 5296 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5297 5298 /* 5299 * Validate request parameters ... 5300 */ 5301 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5302 return (IOC_INVAL); 5303 5304 switch (cmd) { 5305 default: 5306 /* NOTREACHED */ 5307 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5308 return (IOC_INVAL); 5309 5310 case BGE_SEE_READ: 5311 case BGE_SEE_WRITE: 5312 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5313 seerwp->see_addr, &seerwp->see_data); 5314 return (IOC_REPLY); 5315 } 5316 5317 /* NOTREACHED */ 5318 } 5319 5320 #endif /* BGE_SEE_IO32 */ 5321 5322 #if BGE_FLASH_IO32 5323 5324 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5325 struct iocblk *iocp); 5326 #pragma no_inline(bge_flash_ioctl) 5327 5328 static enum ioc_reply 5329 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5330 { 5331 struct bge_flash_rw *flashrwp; 5332 5333 /* 5334 * Validate format of ioctl 5335 */ 5336 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5337 return (IOC_INVAL); 5338 if (mp->b_cont == NULL) 5339 return (IOC_INVAL); 5340 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5341 5342 /* 5343 * Validate request parameters ... 5344 */ 5345 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5346 return (IOC_INVAL); 5347 5348 switch (cmd) { 5349 default: 5350 /* NOTREACHED */ 5351 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5352 return (IOC_INVAL); 5353 5354 case BGE_FLASH_READ: 5355 case BGE_FLASH_WRITE: 5356 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5357 flashrwp->flash_addr, &flashrwp->flash_data); 5358 return (IOC_REPLY); 5359 } 5360 5361 /* NOTREACHED */ 5362 } 5363 5364 #endif /* BGE_FLASH_IO32 */ 5365 5366 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5367 struct iocblk *iocp); 5368 #pragma no_inline(bge_chip_ioctl) 5369 5370 enum ioc_reply 5371 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5372 { 5373 int cmd; 5374 5375 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5376 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5377 5378 ASSERT(mutex_owned(bgep->genlock)); 5379 5380 cmd = iocp->ioc_cmd; 5381 switch (cmd) { 5382 default: 5383 /* NOTREACHED */ 5384 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5385 return (IOC_INVAL); 5386 5387 case BGE_DIAG: 5388 case BGE_PEEK: 5389 case BGE_POKE: 5390 case BGE_PHY_RESET: 5391 case BGE_SOFT_RESET: 5392 case BGE_HARD_RESET: 5393 #if BGE_DEBUGGING || BGE_DO_PPIO 5394 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5395 #else 5396 return (IOC_INVAL); 5397 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5398 5399 case BGE_MII_READ: 5400 case BGE_MII_WRITE: 5401 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5402 5403 #if BGE_SEE_IO32 5404 case BGE_SEE_READ: 5405 case BGE_SEE_WRITE: 5406 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5407 #endif /* BGE_SEE_IO32 */ 5408 5409 #if BGE_FLASH_IO32 5410 case BGE_FLASH_READ: 5411 case BGE_FLASH_WRITE: 5412 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5413 #endif /* BGE_FLASH_IO32 */ 5414 } 5415 5416 /* NOTREACHED */ 5417 } 5418 5419 void 5420 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5421 { 5422 bge_t *bgep = arg; 5423 5424 mutex_enter(bgep->genlock); 5425 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5426 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5427 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5428 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5429 mutex_exit(bgep->genlock); 5430 } 5431 5432 #ifdef BGE_IPMI_ASF 5433 5434 uint32_t 5435 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5436 { 5437 uint32_t data; 5438 5439 #ifndef __sparc 5440 if (!bgep->asf_wordswapped) { 5441 /* a workaround word swap error */ 5442 if (addr & 4) 5443 addr = addr - 4; 5444 else 5445 addr = addr + 4; 5446 } 5447 #endif 5448 5449 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5450 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5451 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5452 5453 data = LE_32(data); 5454 return (data); 5455 } 5456 5457 void 5458 bge_asf_update_status(bge_t *bgep) 5459 { 5460 uint32_t event; 5461 5462 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5463 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5464 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5465 5466 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5467 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5468 } 5469 5470 5471 /* 5472 * The driver is supposed to notify ASF that the OS is still running 5473 * every three seconds, otherwise the management server may attempt 5474 * to reboot the machine. If it hasn't actually failed, this is 5475 * not a desirable result. However, this isn't running as a real-time 5476 * thread, and even if it were, it might not be able to generate the 5477 * heartbeat in a timely manner due to system load. As it isn't a 5478 * significant strain on the machine, we will set the interval to half 5479 * of the required value. 5480 */ 5481 void 5482 bge_asf_heartbeat(void *arg) 5483 { 5484 bge_t *bgep = (bge_t *)arg; 5485 5486 mutex_enter(bgep->genlock); 5487 bge_asf_update_status((bge_t *)bgep); 5488 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5489 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5490 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5491 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5492 mutex_exit(bgep->genlock); 5493 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5494 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5495 } 5496 5497 5498 void 5499 bge_asf_stop_timer(bge_t *bgep) 5500 { 5501 timeout_id_t tmp_id = 0; 5502 5503 while ((bgep->asf_timeout_id != 0) && 5504 (tmp_id != bgep->asf_timeout_id)) { 5505 tmp_id = bgep->asf_timeout_id; 5506 (void) untimeout(tmp_id); 5507 } 5508 bgep->asf_timeout_id = 0; 5509 } 5510 5511 5512 5513 /* 5514 * This function should be placed at the earliest position of bge_attach(). 5515 */ 5516 void 5517 bge_asf_get_config(bge_t *bgep) 5518 { 5519 uint32_t nicsig; 5520 uint32_t niccfg; 5521 5522 bgep->asf_enabled = B_FALSE; 5523 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5524 if (nicsig == BGE_NIC_DATA_SIG) { 5525 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5526 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5527 /* 5528 * Here, we don't consider BAXTER, because BGE haven't 5529 * supported BAXTER (that is 5752). Also, as I know, 5530 * BAXTER doesn't support ASF feature. 5531 */ 5532 bgep->asf_enabled = B_TRUE; 5533 else 5534 bgep->asf_enabled = B_FALSE; 5535 } else 5536 bgep->asf_enabled = B_FALSE; 5537 } 5538 5539 5540 void 5541 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5542 { 5543 uint32_t tries; 5544 uint32_t event; 5545 5546 ASSERT(bgep->asf_enabled); 5547 5548 /* Issues "pause firmware" command and wait for ACK */ 5549 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5550 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5551 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5552 5553 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5554 tries = 0; 5555 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5556 drv_usecwait(1); 5557 tries ++; 5558 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5559 } 5560 5561 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5562 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5563 5564 if (bgep->asf_newhandshake) { 5565 switch (mode) { 5566 case BGE_INIT_RESET: 5567 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5568 BGE_DRV_STATE_START); 5569 break; 5570 case BGE_SHUTDOWN_RESET: 5571 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5572 BGE_DRV_STATE_UNLOAD); 5573 break; 5574 case BGE_SUSPEND_RESET: 5575 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5576 BGE_DRV_STATE_SUSPEND); 5577 break; 5578 default: 5579 break; 5580 } 5581 } 5582 } 5583 5584 5585 void 5586 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5587 { 5588 switch (mode) { 5589 case BGE_INIT_RESET: 5590 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5591 BGE_DRV_STATE_START); 5592 break; 5593 case BGE_SHUTDOWN_RESET: 5594 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5595 BGE_DRV_STATE_UNLOAD); 5596 break; 5597 case BGE_SUSPEND_RESET: 5598 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5599 BGE_DRV_STATE_SUSPEND); 5600 break; 5601 default: 5602 break; 5603 } 5604 } 5605 5606 5607 void 5608 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5609 { 5610 switch (mode) { 5611 case BGE_INIT_RESET: 5612 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5613 BGE_DRV_STATE_START_DONE); 5614 break; 5615 case BGE_SHUTDOWN_RESET: 5616 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5617 BGE_DRV_STATE_UNLOAD_DONE); 5618 break; 5619 default: 5620 break; 5621 } 5622 } 5623 5624 #endif /* BGE_IPMI_ASF */ 5625