1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * bge_intr_max_loop controls the maximum loop number within bge_intr. 164 * When loading NIC with heavy network traffic, it is useful. 165 * Increasing this value could have positive effect to throughput, 166 * but it might also increase ticks of a bge ISR stick on CPU, which might 167 * lead to bad UI interactive experience. So tune this with caution. 168 */ 169 static int bge_intr_max_loop = 1; 170 171 /* 172 * ========== Low-level chip & ring buffer manipulation ========== 173 */ 174 175 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 176 177 178 /* 179 * Config space read-modify-write routines 180 */ 181 182 #if BGE_CFG_IO8 183 184 /* 185 * 8- and 16-bit set/clr operations are not used; all the config registers 186 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 187 * code here, though, in case we ever find that we do want it after all ... 188 */ 189 190 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 191 #pragma inline(bge_cfg_set8) 192 193 static void 194 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 195 { 196 uint8_t regval; 197 198 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 199 (void *)bgep, regno, bits)); 200 201 regval = pci_config_get8(bgep->cfg_handle, regno); 202 203 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 204 (void *)bgep, regno, bits, regval, regval | bits)); 205 206 regval |= bits; 207 pci_config_put8(bgep->cfg_handle, regno, regval); 208 } 209 210 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 211 #pragma inline(bge_cfg_clr8) 212 213 static void 214 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 215 { 216 uint8_t regval; 217 218 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 219 (void *)bgep, regno, bits)); 220 221 regval = pci_config_get8(bgep->cfg_handle, regno); 222 223 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 224 (void *)bgep, regno, bits, regval, regval & ~bits)); 225 226 regval &= ~bits; 227 pci_config_put8(bgep->cfg_handle, regno, regval); 228 } 229 230 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 231 #pragma inline(bge_cfg_set16) 232 233 static void 234 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 235 { 236 uint16_t regval; 237 238 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 239 (void *)bgep, regno, bits)); 240 241 regval = pci_config_get16(bgep->cfg_handle, regno); 242 243 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 244 (void *)bgep, regno, bits, regval, regval | bits)); 245 246 regval |= bits; 247 pci_config_put16(bgep->cfg_handle, regno, regval); 248 } 249 250 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 251 #pragma inline(bge_cfg_clr16) 252 253 static void 254 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 255 { 256 uint16_t regval; 257 258 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 259 (void *)bgep, regno, bits)); 260 261 regval = pci_config_get16(bgep->cfg_handle, regno); 262 263 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 264 (void *)bgep, regno, bits, regval, regval & ~bits)); 265 266 regval &= ~bits; 267 pci_config_put16(bgep->cfg_handle, regno, regval); 268 } 269 270 #endif /* BGE_CFG_IO8 */ 271 272 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 273 #pragma inline(bge_cfg_set32) 274 275 static void 276 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 277 { 278 uint32_t regval; 279 280 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 281 (void *)bgep, regno, bits)); 282 283 regval = pci_config_get32(bgep->cfg_handle, regno); 284 285 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 286 (void *)bgep, regno, bits, regval, regval | bits)); 287 288 regval |= bits; 289 pci_config_put32(bgep->cfg_handle, regno, regval); 290 } 291 292 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 293 #pragma inline(bge_cfg_clr32) 294 295 static void 296 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 297 { 298 uint32_t regval; 299 300 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 301 (void *)bgep, regno, bits)); 302 303 regval = pci_config_get32(bgep->cfg_handle, regno); 304 305 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 306 (void *)bgep, regno, bits, regval, regval & ~bits)); 307 308 regval &= ~bits; 309 pci_config_put32(bgep->cfg_handle, regno, regval); 310 } 311 312 #if BGE_IND_IO32 313 314 /* 315 * Indirect access to registers & RISC scratchpads, using config space 316 * accesses only. 317 * 318 * This isn't currently used, but someday we might want to use it for 319 * restoring the Subsystem Device/Vendor registers (which aren't directly 320 * writable in Config Space), or for downloading firmware into the RISCs 321 * 322 * In any case there are endian issues to be resolved before this code is 323 * enabled; the bizarre way that bytes get twisted by this chip AND by 324 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 325 * it's been thoroughly tested for all access sizes on all supported 326 * architectures (SPARC *and* x86!). 327 */ 328 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 329 #pragma inline(bge_ind_get32) 330 331 uint32_t 332 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 333 { 334 uint32_t val; 335 336 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 337 338 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 339 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 340 341 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 342 (void *)bgep, regno, val)); 343 344 val = LE_32(val); 345 346 return (val); 347 } 348 349 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 350 #pragma inline(bge_ind_put32) 351 352 void 353 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 354 { 355 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 356 (void *)bgep, regno, val)); 357 358 val = LE_32(val); 359 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 360 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 361 } 362 363 #endif /* BGE_IND_IO32 */ 364 365 #if BGE_DEBUGGING 366 367 static void bge_pci_check(bge_t *bgep); 368 #pragma no_inline(bge_pci_check) 369 370 static void 371 bge_pci_check(bge_t *bgep) 372 { 373 uint16_t pcistatus; 374 375 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 376 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 377 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 378 (void *)bgep, pcistatus)); 379 } 380 381 #endif /* BGE_DEBUGGING */ 382 383 /* 384 * Perform first-stage chip (re-)initialisation, using only config-space 385 * accesses: 386 * 387 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 388 * returning the data in the structure pointed to by <idp>. 389 * + Configure the target-mode endianness (swap) options. 390 * + Disable interrupts and enable Memory Space accesses. 391 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 392 * 393 * This sequence is adapted from Broadcom document 570X-PG102-R, 394 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 395 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 396 * 397 * This function MUST be called before any non-config-space accesses 398 * are made; on this first call <enable_dma> is B_FALSE, and it 399 * effectively performs steps 3-1(!) of the initialisation sequence 400 * (the rest are not required but should be harmless). 401 * 402 * It MUST also be called after a chip reset, as this disables 403 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 404 * it is effectively performing steps 6-8. 405 */ 406 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 407 #pragma no_inline(bge_chip_cfg_init) 408 409 void 410 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 411 { 412 ddi_acc_handle_t handle; 413 uint16_t command; 414 uint32_t mhcr; 415 uint16_t value16; 416 int i; 417 418 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 419 (void *)bgep, (void *)cidp, enable_dma)); 420 421 /* 422 * Step 3: save PCI cache line size and subsystem vendor ID 423 * 424 * Read all the config-space registers that characterise the 425 * chip, specifically vendor/device/revision/subsystem vendor 426 * and subsystem device id. We expect (but don't check) that 427 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 428 * 429 * Also save all bus-transaction related registers (cache-line 430 * size, bus-grant/latency parameters, etc). Some of these are 431 * cleared by reset, so we'll have to restore them later. This 432 * comes from the Broadcom document 570X-PG102-R ... 433 * 434 * Note: Broadcom document 570X-PG102-R seems to be in error 435 * here w.r.t. the offsets of the Subsystem Vendor ID and 436 * Subsystem (Device) ID registers, which are the opposite way 437 * round according to the PCI standard. For good measure, we 438 * save/restore both anyway. 439 */ 440 handle = bgep->cfg_handle; 441 442 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 443 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 444 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 445 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 446 447 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 448 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 449 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 450 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 451 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 452 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 453 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 454 455 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 456 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 457 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 458 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 459 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 460 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 461 cidp->vendor, cidp->device, cidp->revision)); 462 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 463 cidp->subven, cidp->subdev, cidp->asic_rev)); 464 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 465 cidp->clsize, cidp->latency, cidp->command)); 466 467 /* 468 * Step 2 (also step 6): disable and clear interrupts. 469 * Steps 11-13: configure PIO endianness options, and enable 470 * indirect register access. We'll also select any other 471 * options controlled by the MHCR (e.g. tagged status, mask 472 * interrupt mode) at this stage ... 473 * 474 * Note: internally, the chip is 64-bit and BIG-endian, but 475 * since it talks to the host over a (LITTLE-endian) PCI bus, 476 * it normally swaps bytes around at the PCI interface. 477 * However, the PCI host bridge on SPARC systems normally 478 * swaps the byte lanes around too, since SPARCs are also 479 * BIG-endian. So it turns out that on SPARC, the right 480 * option is to tell the chip to swap (and the host bridge 481 * will swap back again), whereas on x86 we ask the chip 482 * NOT to swap, so the natural little-endianness of the 483 * PCI bus is assumed. Then the only thing that doesn't 484 * automatically work right is access to an 8-byte register 485 * by a little-endian host; but we don't want to set the 486 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 487 * accesses don't go where expected ;-( So we live with 488 * that, and perform word-swaps in software in the few cases 489 * where a chip register is defined as an 8-byte value -- 490 * see the code below for details ... 491 * 492 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 493 * very clear in the register description in the PRM, but 494 * Broadcom document 570X-PG104-R page 248 explains a little 495 * more (under "Broadcom Mask Mode"). The bit changes the way 496 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 497 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 498 * way as the 5700 did, which isn't very convenient. Setting 499 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 500 * bit do just what its name says -- MASK the PCI #INTA output 501 * (i.e. deassert the signal at the pin) leaving all internal 502 * state unchanged. This is much more convenient for our 503 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 504 * 505 * Note: the inconvenient semantics of the interrupt mailbox 506 * (nonzero disables and acknowledges/clears the interrupt, 507 * zero enables AND CLEARS it) would make race conditions 508 * likely in the interrupt handler: 509 * 510 * (1) acknowledge & disable interrupts 511 * (2) while (more to do) 512 * process packets 513 * (3) enable interrupts -- also clears pending 514 * 515 * If the chip received more packets and internally generated 516 * an interrupt between the check at (2) and the mbox write 517 * at (3), this interrupt would be lost :-( 518 * 519 * The best way to avoid this is to use TAGGED STATUS mode, 520 * where the chip includes a unique tag in each status block 521 * update, and the host, when re-enabling interrupts, passes 522 * the last tag it saw back to the chip; then the chip can 523 * see whether the host is truly up to date, and regenerate 524 * its interrupt if not. 525 */ 526 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 527 MHCR_ENABLE_TAGGED_STATUS_MODE | 528 MHCR_MASK_INTERRUPT_MODE | 529 MHCR_CLEAR_INTERRUPT_INTA; 530 531 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 532 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 533 534 #ifdef _BIG_ENDIAN 535 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 536 #endif /* _BIG_ENDIAN */ 537 538 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 539 540 #ifdef BGE_IPMI_ASF 541 bgep->asf_wordswapped = B_FALSE; 542 #endif 543 /* 544 * Step 1 (also step 7): Enable PCI Memory Space accesses 545 * Disable Memory Write/Invalidate 546 * Enable or disable Bus Mastering 547 * 548 * Note that all other bits are taken from the original value saved 549 * the first time through here, rather than from the current register 550 * value, 'cos that will have been cleared by a soft RESET since. 551 * In this way we preserve the OBP/nexus-parent's preferred settings 552 * of the parity-error and system-error enable bits across multiple 553 * chip RESETs. 554 */ 555 command = bgep->chipid.command | PCI_COMM_MAE; 556 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 557 if (enable_dma) 558 command |= PCI_COMM_ME; 559 /* 560 * on BCM5714 revision A0, false parity error gets generated 561 * due to a logic bug. Provide a workaround by disabling parity 562 * error. 563 */ 564 if (((cidp->device == DEVICE_ID_5714C) || 565 (cidp->device == DEVICE_ID_5714S)) && 566 (cidp->revision == REVISION_ID_5714_A0)) { 567 command &= ~PCI_COMM_PARITY_DETECT; 568 } 569 pci_config_put16(handle, PCI_CONF_COMM, command); 570 571 /* 572 * On some PCI-E device, there were instances when 573 * the device was still link training. 574 */ 575 if (bgep->chipid.pci_type == BGE_PCI_E) { 576 i = 0; 577 value16 = pci_config_get16(handle, PCI_CONF_COMM); 578 while ((value16 != command) && (i < 100)) { 579 drv_usecwait(200); 580 value16 = pci_config_get16(handle, PCI_CONF_COMM); 581 ++i; 582 } 583 } 584 585 /* 586 * Clear any remaining error status bits 587 */ 588 pci_config_put16(handle, PCI_CONF_STAT, ~0); 589 590 /* 591 * Do following if and only if the device is NOT BCM5714C OR 592 * BCM5715C 593 */ 594 if (!((cidp->device == DEVICE_ID_5714C) || 595 (cidp->device == DEVICE_ID_5715C))) { 596 /* 597 * Make sure these indirect-access registers are sane 598 * rather than random after power-up or reset 599 */ 600 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 601 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 602 } 603 /* 604 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 605 */ 606 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 607 608 if (cidp->pci_type == BGE_PCI_E) 609 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 610 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 611 } 612 613 #ifdef __amd64 614 /* 615 * Distinguish CPU types 616 * 617 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 618 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 619 * for PCI-Express based network interface card. This is the work-around 620 * for those nics. 621 */ 622 static boolean_t bge_get_em64t_type(void); 623 #pragma inline(bge_get_em64t_type) 624 625 static boolean_t 626 bge_get_em64t_type(void) 627 { 628 629 return (x86_vendor == X86_VENDOR_Intel); 630 } 631 #endif 632 633 /* 634 * Operating register get/set access routines 635 */ 636 637 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 638 #pragma inline(bge_reg_get32) 639 640 uint32_t 641 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 642 { 643 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 644 (void *)bgep, regno)); 645 646 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 647 } 648 649 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 650 #pragma inline(bge_reg_put32) 651 652 void 653 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 654 { 655 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 656 (void *)bgep, regno, data)); 657 658 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 659 BGE_PCICHK(bgep); 660 } 661 662 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 663 #pragma inline(bge_reg_set32) 664 665 void 666 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 667 { 668 uint32_t regval; 669 670 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 671 (void *)bgep, regno, bits)); 672 673 regval = bge_reg_get32(bgep, regno); 674 regval |= bits; 675 bge_reg_put32(bgep, regno, regval); 676 } 677 678 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 679 #pragma inline(bge_reg_clr32) 680 681 void 682 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 683 { 684 uint32_t regval; 685 686 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 687 (void *)bgep, regno, bits)); 688 689 regval = bge_reg_get32(bgep, regno); 690 regval &= ~bits; 691 bge_reg_put32(bgep, regno, regval); 692 } 693 694 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 695 #pragma inline(bge_reg_get64) 696 697 static uint64_t 698 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 699 { 700 uint64_t regval; 701 702 #ifdef __amd64 703 if (bge_get_em64t_type()) { 704 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 705 regval <<= 32; 706 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 707 } else { 708 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 709 } 710 #else 711 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 712 #endif 713 714 #ifdef _LITTLE_ENDIAN 715 regval = (regval >> 32) | (regval << 32); 716 #endif /* _LITTLE_ENDIAN */ 717 718 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 719 (void *)bgep, regno, regval)); 720 721 return (regval); 722 } 723 724 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 725 #pragma inline(bge_reg_put64) 726 727 static void 728 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 729 { 730 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 731 (void *)bgep, regno, data)); 732 733 #ifdef _LITTLE_ENDIAN 734 data = ((data >> 32) | (data << 32)); 735 #endif /* _LITTLE_ENDIAN */ 736 737 #ifdef __amd64 738 if (bge_get_em64t_type()) { 739 ddi_put32(bgep->io_handle, 740 PIO_ADDR(bgep, regno), (uint32_t)data); 741 BGE_PCICHK(bgep); 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 744 745 } else { 746 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 747 } 748 #else 749 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 750 #endif 751 752 BGE_PCICHK(bgep); 753 } 754 755 /* 756 * The DDI doesn't provide get/put functions for 128 bit data 757 * so we put RCBs out as two 64-bit chunks instead. 758 */ 759 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 760 #pragma inline(bge_reg_putrcb) 761 762 static void 763 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 764 { 765 uint64_t *p; 766 767 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 768 (void *)bgep, addr, rcbp->host_ring_addr, 769 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 770 771 ASSERT((addr % sizeof (*rcbp)) == 0); 772 773 p = (void *)rcbp; 774 bge_reg_put64(bgep, addr, *p++); 775 bge_reg_put64(bgep, addr+8, *p); 776 } 777 778 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 779 #pragma inline(bge_mbx_put) 780 781 void 782 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 783 { 784 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 785 (void *)bgep, regno, data)); 786 787 /* 788 * Mailbox registers are nominally 64 bits on the 5701, but 789 * the MSW isn't used. On the 5703, they're only 32 bits 790 * anyway. So here we just write the lower(!) 32 bits - 791 * remembering that the chip is big-endian, even though the 792 * PCI bus is little-endian ... 793 */ 794 #ifdef _BIG_ENDIAN 795 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 796 #else 797 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 798 #endif /* _BIG_ENDIAN */ 799 BGE_PCICHK(bgep); 800 } 801 802 #if BGE_DEBUGGING 803 804 void bge_led_mark(bge_t *bgep); 805 #pragma no_inline(bge_led_mark) 806 807 void 808 bge_led_mark(bge_t *bgep) 809 { 810 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 811 LED_CONTROL_1000MBPS_LED | 812 LED_CONTROL_100MBPS_LED | 813 LED_CONTROL_10MBPS_LED; 814 815 /* 816 * Blink all three LINK LEDs on simultaneously, then all off, 817 * then restore to automatic hardware control. This is used 818 * in laboratory testing to trigger a logic analyser or scope. 819 */ 820 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 821 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 822 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 823 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 824 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 825 } 826 827 #endif /* BGE_DEBUGGING */ 828 829 /* 830 * NIC on-chip memory access routines 831 * 832 * Only 32K of NIC memory is visible at a time, controlled by the 833 * Memory Window Base Address Register (in PCI config space). Once 834 * this is set, the 32K region of NIC-local memory that it refers 835 * to can be directly addressed in the upper 32K of the 64K of PCI 836 * memory space used for the device. 837 */ 838 839 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 840 #pragma inline(bge_nic_setwin) 841 842 static void 843 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 844 { 845 chip_id_t *cidp; 846 847 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 848 (void *)bgep, base)); 849 850 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 851 852 /* 853 * Don't do repeated zero data writes, 854 * if the device is BCM5714C/15C. 855 */ 856 cidp = &bgep->chipid; 857 if ((cidp->device == DEVICE_ID_5714C) || 858 (cidp->device == DEVICE_ID_5715C)) { 859 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 860 return; 861 /* Adjust lastWriteZeroData */ 862 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 863 B_TRUE : B_FALSE); 864 } 865 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 866 } 867 868 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 869 #pragma inline(bge_nic_get32) 870 871 static uint32_t 872 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 873 { 874 uint32_t data; 875 876 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 877 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 878 /* workaround for word swap error */ 879 if (addr & 4) 880 addr = addr - 4; 881 else 882 addr = addr + 4; 883 } 884 #endif 885 886 #ifdef __sparc 887 data = bge_nic_read32(bgep, addr); 888 #else 889 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 890 addr &= MWBAR_GRANULE_MASK; 891 addr += NIC_MEM_WINDOW_OFFSET; 892 893 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 894 #endif 895 896 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 897 (void *)bgep, addr, data)); 898 899 return (data); 900 } 901 902 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 903 #pragma inline(bge_nic_put32) 904 905 void 906 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 907 { 908 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 909 (void *)bgep, addr, data)); 910 911 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 912 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 913 /* workaround for word swap error */ 914 if (addr & 4) 915 addr = addr - 4; 916 else 917 addr = addr + 4; 918 } 919 #endif 920 921 #ifdef __sparc 922 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 923 data = LE_32(data); 924 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 925 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 926 #else 927 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 928 addr &= MWBAR_GRANULE_MASK; 929 addr += NIC_MEM_WINDOW_OFFSET; 930 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 931 BGE_PCICHK(bgep); 932 #endif 933 } 934 935 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 936 #pragma inline(bge_nic_get64) 937 938 static uint64_t 939 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 940 { 941 uint64_t data; 942 943 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 944 addr &= MWBAR_GRANULE_MASK; 945 addr += NIC_MEM_WINDOW_OFFSET; 946 947 #ifdef __amd64 948 if (bge_get_em64t_type()) { 949 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 950 data <<= 32; 951 data |= ddi_get32(bgep->io_handle, 952 PIO_ADDR(bgep, addr + 4)); 953 } else { 954 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 955 } 956 #else 957 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 958 #endif 959 960 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 961 (void *)bgep, addr, data)); 962 963 return (data); 964 } 965 966 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 967 #pragma inline(bge_nic_put64) 968 969 static void 970 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 971 { 972 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 973 (void *)bgep, addr, data)); 974 975 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 976 addr &= MWBAR_GRANULE_MASK; 977 addr += NIC_MEM_WINDOW_OFFSET; 978 979 #ifdef __amd64 980 if (bge_get_em64t_type()) { 981 ddi_put32(bgep->io_handle, 982 PIO_ADDR(bgep, addr), (uint32_t)data); 983 BGE_PCICHK(bgep); 984 ddi_put32(bgep->io_handle, 985 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 986 } else { 987 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 988 } 989 #else 990 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 991 #endif 992 993 BGE_PCICHK(bgep); 994 } 995 996 /* 997 * The DDI doesn't provide get/put functions for 128 bit data 998 * so we put RCBs out as two 64-bit chunks instead. 999 */ 1000 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1001 #pragma inline(bge_nic_putrcb) 1002 1003 static void 1004 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1005 { 1006 uint64_t *p; 1007 1008 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1009 (void *)bgep, addr, rcbp->host_ring_addr, 1010 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1011 1012 ASSERT((addr % sizeof (*rcbp)) == 0); 1013 1014 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1015 addr &= MWBAR_GRANULE_MASK; 1016 addr += NIC_MEM_WINDOW_OFFSET; 1017 1018 p = (void *)rcbp; 1019 #ifdef __amd64 1020 if (bge_get_em64t_type()) { 1021 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1022 (uint32_t)(*p)); 1023 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1024 (uint32_t)(*p >> 32)); 1025 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1026 (uint32_t)(*(p + 1))); 1027 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1028 (uint32_t)(*p >> 32)); 1029 1030 } else { 1031 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1032 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1033 } 1034 #else 1035 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1036 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1037 #endif 1038 1039 BGE_PCICHK(bgep); 1040 } 1041 1042 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1043 #pragma inline(bge_nic_zero) 1044 1045 static void 1046 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1047 { 1048 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1049 (void *)bgep, addr, nbytes)); 1050 1051 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1052 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1053 1054 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1055 addr &= MWBAR_GRANULE_MASK; 1056 addr += NIC_MEM_WINDOW_OFFSET; 1057 1058 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1059 nbytes, 1, DDI_DATA_SZ08_ACC); 1060 BGE_PCICHK(bgep); 1061 } 1062 1063 /* 1064 * MII (PHY) register get/set access routines 1065 * 1066 * These use the chip's MII auto-access method, controlled by the 1067 * MII Communication register at 0x044c, so the CPU doesn't have 1068 * to fiddle with the individual bits. 1069 */ 1070 1071 #undef BGE_DBG 1072 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1073 1074 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1075 uint16_t data, uint32_t cmd); 1076 #pragma no_inline(bge_mii_access) 1077 1078 static uint16_t 1079 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1080 { 1081 uint32_t timeout; 1082 uint32_t regval1; 1083 uint32_t regval2; 1084 1085 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1086 (void *)bgep, regno, data, cmd)); 1087 1088 ASSERT(mutex_owned(bgep->genlock)); 1089 1090 /* 1091 * Assemble the command ... 1092 */ 1093 cmd |= data << MI_COMMS_DATA_SHIFT; 1094 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1095 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1096 cmd |= MI_COMMS_START; 1097 1098 /* 1099 * Wait for any command already in progress ... 1100 * 1101 * Note: this *shouldn't* ever find that there is a command 1102 * in progress, because we already hold the <genlock> mutex. 1103 * Nonetheless, we have sometimes seen the MI_COMMS_START 1104 * bit set here -- it seems that the chip can initiate MII 1105 * accesses internally, even with polling OFF. 1106 */ 1107 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1108 for (timeout = 100; ; ) { 1109 if ((regval2 & MI_COMMS_START) == 0) { 1110 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1111 break; 1112 } 1113 if (--timeout == 0) 1114 break; 1115 drv_usecwait(10); 1116 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1117 } 1118 1119 if (timeout == 0) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout != 100) 1123 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1124 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1125 cmd, 10*(100-timeout), regval1, regval2)); 1126 1127 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1128 for (timeout = 1000; ; ) { 1129 if ((regval1 & MI_COMMS_START) == 0) 1130 break; 1131 if (--timeout == 0) 1132 break; 1133 drv_usecwait(10); 1134 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1135 } 1136 1137 /* 1138 * Drop out early if the READ FAILED bit is set -- this chip 1139 * could be a 5703/4S, with a SerDes instead of a PHY! 1140 */ 1141 if (regval2 & MI_COMMS_READ_FAILED) 1142 return ((uint16_t)~0u); 1143 1144 if (timeout == 0) 1145 return ((uint16_t)~0u); 1146 1147 /* 1148 * The PRM says to wait 5us after seeing the START bit clear 1149 * and then re-read the register to get the final value of the 1150 * data field, in order to avoid a race condition where the 1151 * START bit is clear but the data field isn't yet valid. 1152 * 1153 * Note: we don't actually seem to be encounter this race; 1154 * except when the START bit is seen set again (see below), 1155 * the data field doesn't change during this 5us interval. 1156 */ 1157 drv_usecwait(5); 1158 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1159 1160 /* 1161 * Unfortunately, when following the PRMs instructions above, 1162 * we have occasionally seen the START bit set again(!) in the 1163 * value read after the 5us delay. This seems to be due to the 1164 * chip autonomously starting another MII access internally. 1165 * In such cases, the command/data/etc fields relate to the 1166 * internal command, rather than the one that we thought had 1167 * just finished. So in this case, we fall back to returning 1168 * the data from the original read that showed START clear. 1169 */ 1170 if (regval2 & MI_COMMS_START) { 1171 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1172 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1173 cmd, regval1, regval2)); 1174 regval2 = regval1; 1175 } 1176 1177 if (regval2 & MI_COMMS_START) 1178 return ((uint16_t)~0u); 1179 1180 if (regval2 & MI_COMMS_READ_FAILED) 1181 return ((uint16_t)~0u); 1182 1183 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1184 } 1185 1186 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1187 #pragma no_inline(bge_mii_get16) 1188 1189 uint16_t 1190 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1191 { 1192 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1193 (void *)bgep, regno)); 1194 1195 ASSERT(mutex_owned(bgep->genlock)); 1196 1197 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1198 } 1199 1200 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1201 #pragma no_inline(bge_mii_put16) 1202 1203 void 1204 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1205 { 1206 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1207 (void *)bgep, regno, data)); 1208 1209 ASSERT(mutex_owned(bgep->genlock)); 1210 1211 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1212 } 1213 1214 #undef BGE_DBG 1215 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1216 1217 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1218 1219 /* 1220 * Basic SEEPROM get/set access routine 1221 * 1222 * This uses the chip's SEEPROM auto-access method, controlled by the 1223 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1224 * doesn't have to fiddle with the individual bits. 1225 * 1226 * The caller should hold <genlock> and *also* have already acquired 1227 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1228 * 1229 * Return value: 1230 * 0 on success, 1231 * ENODATA on access timeout (maybe retryable: device may just be busy) 1232 * EPROTO on other h/w or s/w errors. 1233 * 1234 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1235 * from a (successful) SEEPROM_ACCESS_READ. 1236 */ 1237 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1238 uint32_t *dp); 1239 #pragma no_inline(bge_seeprom_access) 1240 1241 static int 1242 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1243 { 1244 uint32_t tries; 1245 uint32_t regval; 1246 1247 ASSERT(mutex_owned(bgep->genlock)); 1248 1249 /* 1250 * On the newer chips that support both SEEPROM & Flash, we need 1251 * to specifically enable SEEPROM access (Flash is the default). 1252 * On older chips, we don't; SEEPROM is the only NVtype supported, 1253 * and the NVM control registers don't exist ... 1254 */ 1255 switch (bgep->chipid.nvtype) { 1256 case BGE_NVTYPE_NONE: 1257 case BGE_NVTYPE_UNKNOWN: 1258 _NOTE(NOTREACHED) 1259 case BGE_NVTYPE_SEEPROM: 1260 break; 1261 1262 case BGE_NVTYPE_LEGACY_SEEPROM: 1263 case BGE_NVTYPE_UNBUFFERED_FLASH: 1264 case BGE_NVTYPE_BUFFERED_FLASH: 1265 default: 1266 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1267 NVM_CFG1_LEGACY_SEEPROM_MODE); 1268 break; 1269 } 1270 1271 /* 1272 * Check there's no command in progress. 1273 * 1274 * Note: this *shouldn't* ever find that there is a command 1275 * in progress, because we already hold the <genlock> mutex. 1276 * Also, to ensure we don't have a conflict with the chip's 1277 * internal firmware or a process accessing the same (shared) 1278 * SEEPROM through the other port of a 5704, we've already 1279 * been through the "software arbitration" protocol. 1280 * So this is just a final consistency check: we shouldn't 1281 * see EITHER the START bit (command started but not complete) 1282 * OR the COMPLETE bit (command completed but not cleared). 1283 */ 1284 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1285 if (regval & SEEPROM_ACCESS_START) 1286 return (EPROTO); 1287 if (regval & SEEPROM_ACCESS_COMPLETE) 1288 return (EPROTO); 1289 1290 /* 1291 * Assemble the command ... 1292 */ 1293 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1294 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1295 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1296 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1297 cmd |= SEEPROM_ACCESS_START; 1298 cmd |= SEEPROM_ACCESS_COMPLETE; 1299 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1300 1301 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1302 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1303 1304 /* 1305 * By observation, a successful access takes ~20us on a 5703/4, 1306 * but apparently much longer (up to 1000us) on the obsolescent 1307 * BCM5700/BCM5701. We want to be sure we don't get any false 1308 * timeouts here; but OTOH, we don't want a bogus access to lock 1309 * out interrupts for longer than necessary. So we'll allow up 1310 * to 1000us ... 1311 */ 1312 for (tries = 0; tries < 1000; ++tries) { 1313 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1314 if (regval & SEEPROM_ACCESS_COMPLETE) 1315 break; 1316 drv_usecwait(1); 1317 } 1318 1319 if (regval & SEEPROM_ACCESS_COMPLETE) { 1320 /* 1321 * All OK; read the SEEPROM data register, then write back 1322 * the value read from the address register in order to 1323 * clear the <complete> bit and leave the SEEPROM access 1324 * state machine idle, ready for the next access ... 1325 */ 1326 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1327 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1328 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1329 return (0); 1330 } 1331 1332 /* 1333 * Hmm ... what happened here? 1334 * 1335 * Most likely, the user addressed a non-existent SEEPROM. Or 1336 * maybe the SEEPROM was busy internally (e.g. processing a write) 1337 * and didn't respond to being addressed. Either way, it's left 1338 * the SEEPROM access state machine wedged. So we'll reset it 1339 * before we leave, so it's ready for next time ... 1340 */ 1341 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1342 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1343 return (ENODATA); 1344 } 1345 1346 /* 1347 * Basic Flash get/set access routine 1348 * 1349 * These use the chip's Flash auto-access method, controlled by the 1350 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1351 * fiddle with the individual bits. 1352 * 1353 * The caller should hold <genlock> and *also* have already acquired 1354 * the right to access the Flash, via bge_nvmem_acquire() above. 1355 * 1356 * Return value: 1357 * 0 on success, 1358 * ENODATA on access timeout (maybe retryable: device may just be busy) 1359 * ENODEV if the NVmem device is missing or otherwise unusable 1360 * 1361 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1362 * from a (successful) NVM_FLASH_CMD_RD. 1363 */ 1364 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1365 uint32_t *dp); 1366 #pragma no_inline(bge_flash_access) 1367 1368 static int 1369 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1370 { 1371 uint32_t tries; 1372 uint32_t regval; 1373 1374 ASSERT(mutex_owned(bgep->genlock)); 1375 1376 /* 1377 * On the newer chips that support both SEEPROM & Flash, we need 1378 * to specifically disable SEEPROM access while accessing Flash. 1379 * The older chips don't support Flash, and the NVM registers don't 1380 * exist, so we shouldn't be here at all! 1381 */ 1382 switch (bgep->chipid.nvtype) { 1383 case BGE_NVTYPE_NONE: 1384 case BGE_NVTYPE_UNKNOWN: 1385 _NOTE(NOTREACHED) 1386 case BGE_NVTYPE_SEEPROM: 1387 return (ENODEV); 1388 1389 case BGE_NVTYPE_LEGACY_SEEPROM: 1390 case BGE_NVTYPE_UNBUFFERED_FLASH: 1391 case BGE_NVTYPE_BUFFERED_FLASH: 1392 default: 1393 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1394 NVM_CFG1_LEGACY_SEEPROM_MODE); 1395 break; 1396 } 1397 1398 /* 1399 * Assemble the command ... 1400 */ 1401 addr &= NVM_FLASH_ADDR_MASK; 1402 cmd |= NVM_FLASH_CMD_DOIT; 1403 cmd |= NVM_FLASH_CMD_FIRST; 1404 cmd |= NVM_FLASH_CMD_LAST; 1405 cmd |= NVM_FLASH_CMD_DONE; 1406 1407 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1408 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1409 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1410 1411 /* 1412 * Allow up to 1000ms ... 1413 */ 1414 for (tries = 0; tries < 1000; ++tries) { 1415 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1416 if (regval & NVM_FLASH_CMD_DONE) 1417 break; 1418 drv_usecwait(1); 1419 } 1420 1421 if (regval & NVM_FLASH_CMD_DONE) { 1422 /* 1423 * All OK; read the data from the Flash read register 1424 */ 1425 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1426 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1427 return (0); 1428 } 1429 1430 /* 1431 * Hmm ... what happened here? 1432 * 1433 * Most likely, the user addressed a non-existent Flash. Or 1434 * maybe the Flash was busy internally (e.g. processing a write) 1435 * and didn't respond to being addressed. Either way, there's 1436 * nothing we can here ... 1437 */ 1438 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1439 return (ENODATA); 1440 } 1441 1442 /* 1443 * The next two functions regulate access to the NVram (if fitted). 1444 * 1445 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1446 * (SPI) interface, but they can be accessed through either port. These 1447 * are managed by different instance of this driver and have no software 1448 * state in common. 1449 * 1450 * In addition (and even on a single core chip) the chip's internal 1451 * firmware can access the SEEPROM/Flash, most notably after a RESET 1452 * when it may download code to run internally. 1453 * 1454 * So we need to arbitrate between these various software agents. For 1455 * this purpose, the chip provides the Software Arbitration Register, 1456 * which implements hardware(!) arbitration. 1457 * 1458 * This functionality didn't exist on older (5700/5701) chips, so there's 1459 * nothing we can do by way of arbitration on those; also, if there's no 1460 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1461 * nothing to do. 1462 * 1463 * The internal firmware appears to use Request 0, which is the highest 1464 * priority. So we'd like to use Request 2, leaving one higher and one 1465 * lower for any future developments ... but apparently this doesn't 1466 * always work. So for now, the code uses Request 1 ;-( 1467 */ 1468 1469 #define NVM_READ_REQ NVM_READ_REQ1 1470 #define NVM_RESET_REQ NVM_RESET_REQ1 1471 #define NVM_SET_REQ NVM_SET_REQ1 1472 1473 static void bge_nvmem_relinquish(bge_t *bgep); 1474 #pragma no_inline(bge_nvmem_relinquish) 1475 1476 static void 1477 bge_nvmem_relinquish(bge_t *bgep) 1478 { 1479 ASSERT(mutex_owned(bgep->genlock)); 1480 1481 switch (bgep->chipid.nvtype) { 1482 case BGE_NVTYPE_NONE: 1483 case BGE_NVTYPE_UNKNOWN: 1484 _NOTE(NOTREACHED) 1485 return; 1486 1487 case BGE_NVTYPE_SEEPROM: 1488 /* 1489 * No arbitration performed, no release needed 1490 */ 1491 return; 1492 1493 case BGE_NVTYPE_LEGACY_SEEPROM: 1494 case BGE_NVTYPE_UNBUFFERED_FLASH: 1495 case BGE_NVTYPE_BUFFERED_FLASH: 1496 default: 1497 break; 1498 } 1499 1500 /* 1501 * Our own request should be present (whether or not granted) ... 1502 */ 1503 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1504 1505 /* 1506 * ... this will make it go away. 1507 */ 1508 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1509 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1510 } 1511 1512 /* 1513 * Arbitrate for access to the NVmem, if necessary 1514 * 1515 * Return value: 1516 * 0 on success 1517 * EAGAIN if the device is in use (retryable) 1518 * ENODEV if the NVmem device is missing or otherwise unusable 1519 */ 1520 static int bge_nvmem_acquire(bge_t *bgep); 1521 #pragma no_inline(bge_nvmem_acquire) 1522 1523 static int 1524 bge_nvmem_acquire(bge_t *bgep) 1525 { 1526 uint32_t regval; 1527 uint32_t tries; 1528 1529 ASSERT(mutex_owned(bgep->genlock)); 1530 1531 switch (bgep->chipid.nvtype) { 1532 case BGE_NVTYPE_NONE: 1533 case BGE_NVTYPE_UNKNOWN: 1534 /* 1535 * Access denied: no (recognisable) device fitted 1536 */ 1537 return (ENODEV); 1538 1539 case BGE_NVTYPE_SEEPROM: 1540 /* 1541 * Access granted: no arbitration needed (or possible) 1542 */ 1543 return (0); 1544 1545 case BGE_NVTYPE_LEGACY_SEEPROM: 1546 case BGE_NVTYPE_UNBUFFERED_FLASH: 1547 case BGE_NVTYPE_BUFFERED_FLASH: 1548 default: 1549 /* 1550 * Access conditional: conduct arbitration protocol 1551 */ 1552 break; 1553 } 1554 1555 /* 1556 * We're holding the per-port mutex <genlock>, so no-one other 1557 * thread can be attempting to access the NVmem through *this* 1558 * port. But it could be in use by the *other* port (of a 5704), 1559 * or by the chip's internal firmware, so we have to go through 1560 * the full (hardware) arbitration protocol ... 1561 * 1562 * Note that *because* we're holding <genlock>, the interrupt handler 1563 * won't be able to progress. So we're only willing to spin for a 1564 * fairly short time. Specifically: 1565 * 1566 * We *must* wait long enough for the hardware to resolve all 1567 * requests and determine the winner. Fortunately, this is 1568 * "almost instantaneous", even as observed by GHz CPUs. 1569 * 1570 * A successful access by another Solaris thread (via either 1571 * port) typically takes ~20us. So waiting a bit longer than 1572 * that will give a good chance of success, if the other user 1573 * *is* another thread on the other port. 1574 * 1575 * However, the internal firmware can hold on to the NVmem 1576 * for *much* longer: at least 10 milliseconds just after a 1577 * RESET, and maybe even longer if the NVmem actually contains 1578 * code to download and run on the internal CPUs. 1579 * 1580 * So, we'll allow 50us; if that's not enough then it's up to the 1581 * caller to retry later (hence the choice of return code EAGAIN). 1582 */ 1583 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1584 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1585 1586 for (tries = 0; tries < 50; ++tries) { 1587 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1588 if (regval & NVM_WON_REQ1) 1589 break; 1590 drv_usecwait(1); 1591 } 1592 1593 if (regval & NVM_WON_REQ1) { 1594 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1595 return (0); 1596 } 1597 1598 /* 1599 * Somebody else must be accessing the NVmem, so abandon our 1600 * attempt take control of it. The caller can try again later ... 1601 */ 1602 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1603 bge_nvmem_relinquish(bgep); 1604 return (EAGAIN); 1605 } 1606 1607 /* 1608 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1609 * write protect line in such a way that the NVmem is protected when 1610 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1611 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1612 * 1613 * Note: there's only one set of GPIO pins on a 5704, even though they 1614 * can be accessed through either port. So the chip has to resolve what 1615 * happens if the two ports program a single pin differently ... the rule 1616 * it uses is that if the ports disagree about the *direction* of a pin, 1617 * "output" wins over "input", but if they disagree about its *value* as 1618 * an output, then the pin is TRISTATED instead! In such a case, no-one 1619 * wins, and the external signal does whatever the external circuitry 1620 * defines as the default -- which we've assumed is the PROTECTED state. 1621 * So, we always change GPIO1 back to being an *input* whenever we're not 1622 * specifically using it to unprotect the NVmem. This allows either port 1623 * to update the NVmem, although obviously only one at a time! 1624 * 1625 * The caller should hold <genlock> and *also* have already acquired the 1626 * right to access the NVmem, via bge_nvmem_acquire() above. 1627 */ 1628 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1629 #pragma inline(bge_nvmem_protect) 1630 1631 static void 1632 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1633 { 1634 uint32_t regval; 1635 1636 ASSERT(mutex_owned(bgep->genlock)); 1637 1638 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1639 if (protect) { 1640 regval |= MLCR_MISC_PINS_OUTPUT_1; 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1642 } else { 1643 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1644 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1645 } 1646 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1647 } 1648 1649 /* 1650 * Now put it all together ... 1651 * 1652 * Try to acquire control of the NVmem; if successful, then: 1653 * unprotect it (if we want to write to it) 1654 * perform the requested access 1655 * reprotect it (after a write) 1656 * relinquish control 1657 * 1658 * Return value: 1659 * 0 on success, 1660 * EAGAIN if the device is in use (retryable) 1661 * ENODATA on access timeout (maybe retryable: device may just be busy) 1662 * ENODEV if the NVmem device is missing or otherwise unusable 1663 * EPROTO on other h/w or s/w errors. 1664 */ 1665 static int 1666 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1667 { 1668 int err; 1669 1670 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1671 switch (cmd) { 1672 case BGE_SEE_READ: 1673 err = bge_seeprom_access(bgep, 1674 SEEPROM_ACCESS_READ, addr, dp); 1675 break; 1676 1677 case BGE_SEE_WRITE: 1678 bge_nvmem_protect(bgep, B_FALSE); 1679 err = bge_seeprom_access(bgep, 1680 SEEPROM_ACCESS_WRITE, addr, dp); 1681 bge_nvmem_protect(bgep, B_TRUE); 1682 break; 1683 1684 case BGE_FLASH_READ: 1685 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1686 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1687 bge_reg_set32(bgep, NVM_ACCESS_REG, 1688 NVM_ACCESS_ENABLE); 1689 } 1690 err = bge_flash_access(bgep, 1691 NVM_FLASH_CMD_RD, addr, dp); 1692 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1702 bge_reg_set32(bgep, NVM_ACCESS_REG, 1703 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1704 } 1705 bge_nvmem_protect(bgep, B_FALSE); 1706 err = bge_flash_access(bgep, 1707 NVM_FLASH_CMD_WR, addr, dp); 1708 bge_nvmem_protect(bgep, B_TRUE); 1709 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1710 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1711 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1712 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1713 } 1714 1715 break; 1716 1717 default: 1718 _NOTE(NOTREACHED) 1719 break; 1720 } 1721 bge_nvmem_relinquish(bgep); 1722 } 1723 1724 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1725 return (err); 1726 } 1727 1728 /* 1729 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1730 */ 1731 static uint64_t bge_get_nvmac(bge_t *bgep); 1732 #pragma no_inline(bge_get_nvmac) 1733 1734 static uint64_t 1735 bge_get_nvmac(bge_t *bgep) 1736 { 1737 uint32_t mac_high; 1738 uint32_t mac_low; 1739 uint32_t addr; 1740 uint32_t cmd; 1741 uint64_t mac; 1742 1743 BGE_TRACE(("bge_get_nvmac($%p)", 1744 (void *)bgep)); 1745 1746 switch (bgep->chipid.nvtype) { 1747 case BGE_NVTYPE_NONE: 1748 case BGE_NVTYPE_UNKNOWN: 1749 default: 1750 return (0ULL); 1751 1752 case BGE_NVTYPE_SEEPROM: 1753 case BGE_NVTYPE_LEGACY_SEEPROM: 1754 cmd = BGE_SEE_READ; 1755 break; 1756 1757 case BGE_NVTYPE_UNBUFFERED_FLASH: 1758 case BGE_NVTYPE_BUFFERED_FLASH: 1759 cmd = BGE_FLASH_READ; 1760 break; 1761 } 1762 1763 addr = NVMEM_DATA_MAC_ADDRESS; 1764 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1765 return (0ULL); 1766 addr += 4; 1767 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1768 return (0ULL); 1769 1770 /* 1771 * The Broadcom chip is natively BIG-endian, so that's how the 1772 * MAC address is represented in NVmem. We may need to swap it 1773 * around on a little-endian host ... 1774 */ 1775 #ifdef _BIG_ENDIAN 1776 mac = mac_high; 1777 mac = mac << 32; 1778 mac |= mac_low; 1779 #else 1780 mac = BGE_BSWAP_32(mac_high); 1781 mac = mac << 32; 1782 mac |= BGE_BSWAP_32(mac_low); 1783 #endif /* _BIG_ENDIAN */ 1784 1785 return (mac); 1786 } 1787 1788 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1789 1790 /* 1791 * Dummy version for when we're not supporting NVmem access 1792 */ 1793 static uint64_t bge_get_nvmac(bge_t *bgep); 1794 #pragma inline(bge_get_nvmac) 1795 1796 static uint64_t 1797 bge_get_nvmac(bge_t *bgep) 1798 { 1799 _NOTE(ARGUNUSED(bgep)) 1800 return (0ULL); 1801 } 1802 1803 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1804 1805 /* 1806 * Determine the type of NVmem that is (or may be) attached to this chip, 1807 */ 1808 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1809 #pragma no_inline(bge_nvmem_id) 1810 1811 static enum bge_nvmem_type 1812 bge_nvmem_id(bge_t *bgep) 1813 { 1814 enum bge_nvmem_type nvtype; 1815 uint32_t config1; 1816 1817 BGE_TRACE(("bge_nvmem_id($%p)", 1818 (void *)bgep)); 1819 1820 switch (bgep->chipid.device) { 1821 default: 1822 /* 1823 * We shouldn't get here; it means we don't recognise 1824 * the chip, which means we don't know how to determine 1825 * what sort of NVmem (if any) it has. So we'll say 1826 * NONE, to disable the NVmem access code ... 1827 */ 1828 nvtype = BGE_NVTYPE_NONE; 1829 break; 1830 1831 case DEVICE_ID_5700: 1832 case DEVICE_ID_5700x: 1833 case DEVICE_ID_5701: 1834 /* 1835 * These devices support *only* SEEPROMs 1836 */ 1837 nvtype = BGE_NVTYPE_SEEPROM; 1838 break; 1839 1840 case DEVICE_ID_5702: 1841 case DEVICE_ID_5702fe: 1842 case DEVICE_ID_5703C: 1843 case DEVICE_ID_5703S: 1844 case DEVICE_ID_5704C: 1845 case DEVICE_ID_5704S: 1846 case DEVICE_ID_5704: 1847 case DEVICE_ID_5705M: 1848 case DEVICE_ID_5705C: 1849 case DEVICE_ID_5705_2: 1850 case DEVICE_ID_5706: 1851 case DEVICE_ID_5782: 1852 case DEVICE_ID_5788: 1853 case DEVICE_ID_5789: 1854 case DEVICE_ID_5751: 1855 case DEVICE_ID_5751M: 1856 case DEVICE_ID_5752: 1857 case DEVICE_ID_5752M: 1858 case DEVICE_ID_5754: 1859 case DEVICE_ID_5755: 1860 case DEVICE_ID_5721: 1861 case DEVICE_ID_5714C: 1862 case DEVICE_ID_5714S: 1863 case DEVICE_ID_5715C: 1864 case DEVICE_ID_5715S: 1865 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1866 if (config1 & NVM_CFG1_FLASH_MODE) 1867 if (config1 & NVM_CFG1_BUFFERED_MODE) 1868 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1869 else 1870 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1871 else 1872 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1873 break; 1874 } 1875 1876 return (nvtype); 1877 } 1878 1879 #undef BGE_DBG 1880 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1881 1882 static void 1883 bge_init_recv_rule(bge_t *bgep) 1884 { 1885 bge_recv_rule_t *rulep; 1886 uint32_t i; 1887 1888 /* 1889 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1890 * 1. to direct UDP traffic, set: 1891 * rulep->control = RULE_PROTO_CONTROL; 1892 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1893 * 2. to direct ICMP traffic, set: 1894 * rulep->control = RULE_PROTO_CONTROL; 1895 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1896 * 3. to direct traffic by source ip, set: 1897 * rulep->control = RULE_SIP_CONTROL; 1898 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1899 */ 1900 rulep = bgep->recv_rules; 1901 rulep->control = RULE_PROTO_CONTROL; 1902 rulep->mask_value = RULE_TCP_MASK_VALUE; 1903 1904 /* 1905 * set receive rule registers 1906 */ 1907 rulep = bgep->recv_rules; 1908 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1909 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1910 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1911 } 1912 } 1913 1914 /* 1915 * Using the values captured by bge_chip_cfg_init(), and additional probes 1916 * as required, characterise the chip fully: determine the label by which 1917 * to refer to this chip, the correct settings for various registers, and 1918 * of course whether the device and/or subsystem are supported! 1919 */ 1920 int bge_chip_id_init(bge_t *bgep); 1921 #pragma no_inline(bge_chip_id_init) 1922 1923 int 1924 bge_chip_id_init(bge_t *bgep) 1925 { 1926 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1927 boolean_t sys_ok; 1928 boolean_t dev_ok; 1929 chip_id_t *cidp; 1930 uint32_t subid; 1931 char *devname; 1932 char *sysname; 1933 int *ids; 1934 int err; 1935 uint_t i; 1936 1937 sys_ok = dev_ok = B_FALSE; 1938 cidp = &bgep->chipid; 1939 1940 /* 1941 * Check the PCI device ID to determine the generic chip type and 1942 * select parameters that depend on this. 1943 * 1944 * Note: because the SPARC platforms in general don't fit the 1945 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1946 * as zero - which is why we use <asic_rev> rather than <revision> 1947 * below ... 1948 * 1949 * Note: in general we can't distinguish between the Copper/SerDes 1950 * versions by ID alone, as some Copper devices (e.g. some but not 1951 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1952 * treat them the same here, and the MII code works out the media 1953 * type later on ... 1954 */ 1955 cidp->mbuf_base = bge_mbuf_pool_base; 1956 cidp->mbuf_length = bge_mbuf_pool_len; 1957 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1958 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1959 cidp->pci_type = BGE_PCI_X; 1960 cidp->statistic_type = BGE_STAT_BLK; 1961 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1962 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1963 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1964 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1965 cidp->rx_count_norm = bge_rx_count_norm; 1966 1967 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1968 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1969 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1970 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1971 1972 cidp->msi_enabled = B_FALSE; 1973 1974 switch (cidp->device) { 1975 case DEVICE_ID_5700: 1976 case DEVICE_ID_5700x: 1977 cidp->chip_label = 5700; 1978 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1979 break; 1980 1981 case DEVICE_ID_5701: 1982 cidp->chip_label = 5701; 1983 dev_ok = B_TRUE; 1984 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1985 break; 1986 1987 case DEVICE_ID_5702: 1988 case DEVICE_ID_5702fe: 1989 cidp->chip_label = 5702; 1990 dev_ok = B_TRUE; 1991 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1992 cidp->pci_type = BGE_PCI; 1993 break; 1994 1995 case DEVICE_ID_5703C: 1996 case DEVICE_ID_5703S: 1997 case DEVICE_ID_5703: 1998 /* 1999 * Revision A0 of the 5703/5793 had various errata 2000 * that we can't or don't work around, so it's not 2001 * supported, but all later versions are 2002 */ 2003 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2004 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2005 dev_ok = B_TRUE; 2006 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2007 break; 2008 2009 case DEVICE_ID_5704C: 2010 case DEVICE_ID_5704S: 2011 case DEVICE_ID_5704: 2012 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2013 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2014 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2015 dev_ok = B_TRUE; 2016 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2017 break; 2018 2019 case DEVICE_ID_5705C: 2020 case DEVICE_ID_5705M: 2021 case DEVICE_ID_5705MA3: 2022 case DEVICE_ID_5705F: 2023 case DEVICE_ID_5705_2: 2024 case DEVICE_ID_5754: 2025 if (cidp->device == DEVICE_ID_5754) { 2026 cidp->chip_label = 5754; 2027 cidp->pci_type = BGE_PCI_E; 2028 } else { 2029 cidp->chip_label = 5705; 2030 cidp->pci_type = BGE_PCI; 2031 } 2032 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2033 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2034 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2035 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2036 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2037 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2038 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2039 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2040 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2041 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2042 cidp->statistic_type = BGE_STAT_REG; 2043 dev_ok = B_TRUE; 2044 break; 2045 2046 case DEVICE_ID_5753: 2047 cidp->chip_label = 5753; 2048 cidp->pci_type = BGE_PCI_E; 2049 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2050 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2051 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2052 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2053 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2054 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2055 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2056 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2057 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2058 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2059 cidp->statistic_type = BGE_STAT_REG; 2060 dev_ok = B_TRUE; 2061 break; 2062 2063 case DEVICE_ID_5755: 2064 cidp->chip_label = 5755; 2065 cidp->pci_type = BGE_PCI_E; 2066 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2067 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2068 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2069 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2070 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2071 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2072 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2073 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2074 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2075 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2076 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2077 cidp->statistic_type = BGE_STAT_REG; 2078 dev_ok = B_TRUE; 2079 break; 2080 2081 case DEVICE_ID_5706: 2082 cidp->chip_label = 5706; 2083 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2084 break; 2085 2086 case DEVICE_ID_5782: 2087 /* 2088 * Apart from the label, we treat this as a 5705(?) 2089 */ 2090 cidp->chip_label = 5782; 2091 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2092 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2093 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2094 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2095 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2096 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2097 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2098 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2099 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2100 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2101 cidp->statistic_type = BGE_STAT_REG; 2102 dev_ok = B_TRUE; 2103 break; 2104 2105 case DEVICE_ID_5788: 2106 /* 2107 * Apart from the label, we treat this as a 5705(?) 2108 */ 2109 cidp->chip_label = 5788; 2110 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2111 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2112 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2113 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2114 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2115 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2116 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2117 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2118 cidp->statistic_type = BGE_STAT_REG; 2119 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2120 dev_ok = B_TRUE; 2121 break; 2122 2123 case DEVICE_ID_5714C: 2124 if (cidp->revision >= REVISION_ID_5714_A2) 2125 cidp->msi_enabled = bge_enable_msi; 2126 /* FALLTHRU */ 2127 case DEVICE_ID_5714S: 2128 cidp->chip_label = 5714; 2129 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2130 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2131 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2132 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2133 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2134 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2135 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2136 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2137 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2138 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2139 cidp->pci_type = BGE_PCI_E; 2140 cidp->statistic_type = BGE_STAT_REG; 2141 dev_ok = B_TRUE; 2142 break; 2143 2144 case DEVICE_ID_5715C: 2145 case DEVICE_ID_5715S: 2146 cidp->chip_label = 5715; 2147 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2148 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2149 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2150 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2151 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2152 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2153 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2154 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2155 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2156 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2157 cidp->pci_type = BGE_PCI_E; 2158 cidp->statistic_type = BGE_STAT_REG; 2159 if (cidp->revision >= REVISION_ID_5715_A2) 2160 cidp->msi_enabled = bge_enable_msi; 2161 dev_ok = B_TRUE; 2162 break; 2163 2164 case DEVICE_ID_5721: 2165 cidp->chip_label = 5721; 2166 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2167 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2168 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2169 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2170 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2171 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2172 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2173 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2174 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2175 cidp->pci_type = BGE_PCI_E; 2176 cidp->statistic_type = BGE_STAT_REG; 2177 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2178 dev_ok = B_TRUE; 2179 break; 2180 2181 case DEVICE_ID_5751: 2182 case DEVICE_ID_5751M: 2183 cidp->chip_label = 5751; 2184 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2185 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2186 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2187 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2188 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2189 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2190 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2191 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2192 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2193 cidp->pci_type = BGE_PCI_E; 2194 cidp->statistic_type = BGE_STAT_REG; 2195 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2196 dev_ok = B_TRUE; 2197 break; 2198 2199 case DEVICE_ID_5752: 2200 case DEVICE_ID_5752M: 2201 cidp->chip_label = 5752; 2202 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2203 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2204 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2205 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2206 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2207 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2208 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2209 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2210 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2211 cidp->pci_type = BGE_PCI_E; 2212 cidp->statistic_type = BGE_STAT_REG; 2213 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2214 dev_ok = B_TRUE; 2215 break; 2216 2217 case DEVICE_ID_5789: 2218 cidp->chip_label = 5789; 2219 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2220 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2221 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2222 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2223 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2224 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2225 cidp->pci_type = BGE_PCI_E; 2226 cidp->statistic_type = BGE_STAT_REG; 2227 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2228 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2229 cidp->msi_enabled = B_TRUE; 2230 dev_ok = B_TRUE; 2231 break; 2232 2233 } 2234 2235 /* 2236 * Setup the default jumbo parameter. 2237 */ 2238 cidp->ethmax_size = ETHERMAX; 2239 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2240 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2241 2242 /* 2243 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2244 * setup below jumbo specific parameters. 2245 * 2246 * For BCM5714/5715, there is only one standard receive ring. So the 2247 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2248 * feature is enabled. 2249 */ 2250 if (bge_jumbo_enable && 2251 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2252 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2253 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2254 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2255 cidp->mbuf_lo_water_rdma = 2256 RDMA_MBUF_LOWAT_5714_JUMBO; 2257 cidp->mbuf_lo_water_rmac = 2258 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2259 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2260 cidp->jumbo_slots = 0; 2261 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2262 } else { 2263 cidp->mbuf_lo_water_rdma = 2264 RDMA_MBUF_LOWAT_JUMBO; 2265 cidp->mbuf_lo_water_rmac = 2266 MAC_RX_MBUF_LOWAT_JUMBO; 2267 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2268 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2269 } 2270 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2271 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2272 cidp->ethmax_size = cidp->default_mtu + 2273 sizeof (struct ether_header); 2274 } 2275 2276 /* 2277 * Identify the NV memory type: SEEPROM or Flash? 2278 */ 2279 cidp->nvtype = bge_nvmem_id(bgep); 2280 2281 /* 2282 * Now, we want to check whether this device is part of a 2283 * supported subsystem (e.g., on the motherboard of a Sun 2284 * branded platform). 2285 * 2286 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2287 */ 2288 if (cidp->subven == VENDOR_ID_SUN) 2289 sys_ok = B_TRUE; 2290 2291 /* 2292 * Rule 2: If it's on the list on known subsystems, then it's OK. 2293 * Note: 0x14e41647 should *not* appear in the list, but the code 2294 * doesn't enforce that. 2295 */ 2296 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2297 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2298 if (err == DDI_PROP_SUCCESS) { 2299 /* 2300 * Got the list; scan for a matching subsystem vendor/device 2301 */ 2302 subid = (cidp->subven << 16) | cidp->subdev; 2303 while (i--) 2304 if (ids[i] == subid) 2305 sys_ok = B_TRUE; 2306 ddi_prop_free(ids); 2307 } 2308 2309 /* 2310 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2311 * 2312 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2313 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2314 * we have to check specially for the exact device paths to the 2315 * motherboard devices on those platforms ;-( 2316 * 2317 * Note: we can't just use the "supported-subsystems" mechanism 2318 * above, because the entry would have to be 0x14e41647 -- which 2319 * would then accept *any* plugin card that *didn't* contain a 2320 * (valid) SEEPROM ;-( 2321 */ 2322 sysname = ddi_node_name(ddi_root_node()); 2323 devname = ddi_pathname(bgep->devinfo, buf); 2324 ASSERT(strlen(devname) > 0); 2325 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2326 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2327 sys_ok = B_TRUE; 2328 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2329 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2330 sys_ok = B_TRUE; 2331 2332 /* 2333 * Now check what we've discovered: is this truly a supported 2334 * chip on (the motherboard of) a supported platform? 2335 * 2336 * Possible problems here: 2337 * 1) it's a completely unheard-of chip (e.g. 5761) 2338 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2339 * 3) it's a chip we would support if it were on the motherboard 2340 * of a Sun platform, but this one isn't ;-( 2341 */ 2342 if (cidp->chip_label == 0) 2343 bge_problem(bgep, 2344 "Device 'pci%04x,%04x' not recognized (%d?)", 2345 cidp->vendor, cidp->device, cidp->device); 2346 else if (!dev_ok) 2347 bge_problem(bgep, 2348 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2349 cidp->vendor, cidp->device, cidp->chip_label, 2350 cidp->revision); 2351 #if BGE_DEBUGGING 2352 else if (!sys_ok) 2353 bge_problem(bgep, 2354 "%d-based subsystem 'pci%04x,%04x' not validated", 2355 cidp->chip_label, cidp->subven, cidp->subdev); 2356 #endif 2357 else 2358 cidp->flags |= CHIP_FLAG_SUPPORTED; 2359 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2360 return (EIO); 2361 return (0); 2362 } 2363 2364 void 2365 bge_chip_msi_trig(bge_t *bgep) 2366 { 2367 uint32_t regval; 2368 2369 regval = bgep->param_msi_cnt<<4; 2370 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2371 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2372 } 2373 2374 /* 2375 * Various registers that control the chip's internal engines (state 2376 * machines) have a <reset> and <enable> bits (fortunately, in the 2377 * same place in each such register :-). 2378 * 2379 * To reset the state machine, the <reset> bit must be written with 1; 2380 * it will then read back as 1 while the reset is in progress, but 2381 * self-clear to 0 when the reset completes. 2382 * 2383 * To enable a state machine, one must set the <enable> bit, which 2384 * will continue to read back as 0 until the state machine is running. 2385 * 2386 * To disable a state machine, the <enable> bit must be cleared, but 2387 * it will continue to read back as 1 until the state machine actually 2388 * stops. 2389 * 2390 * This routine implements polling for completion of a reset, enable 2391 * or disable operation, returning B_TRUE on success (bit reached the 2392 * required state) or B_FALSE on timeout (200*100us == 20ms). 2393 */ 2394 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2395 uint32_t mask, uint32_t val); 2396 #pragma no_inline(bge_chip_poll_engine) 2397 2398 static boolean_t 2399 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2400 uint32_t mask, uint32_t val) 2401 { 2402 uint32_t regval; 2403 uint32_t n; 2404 2405 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2406 (void *)bgep, regno, mask, val)); 2407 2408 for (n = 200; n; --n) { 2409 regval = bge_reg_get32(bgep, regno); 2410 if ((regval & mask) == val) 2411 return (B_TRUE); 2412 drv_usecwait(100); 2413 } 2414 2415 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2416 return (B_FALSE); 2417 } 2418 2419 /* 2420 * Various registers that control the chip's internal engines (state 2421 * machines) have a <reset> bit (fortunately, in the same place in 2422 * each such register :-). To reset the state machine, this bit must 2423 * be written with 1; it will then read back as 1 while the reset is 2424 * in progress, but self-clear to 0 when the reset completes. 2425 * 2426 * This code sets the bit, then polls for it to read back as zero. 2427 * The return value is B_TRUE on success (reset bit cleared itself), 2428 * or B_FALSE if the state machine didn't recover :( 2429 * 2430 * NOTE: the Core reset is similar to other resets, except that we 2431 * can't poll for completion, since the Core reset disables memory 2432 * access! So we just have to assume that it will all complete in 2433 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2434 */ 2435 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2436 #pragma no_inline(bge_chip_reset_engine) 2437 2438 static boolean_t 2439 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2440 { 2441 uint32_t regval; 2442 uint32_t val32; 2443 2444 regval = bge_reg_get32(bgep, regno); 2445 2446 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2447 (void *)bgep, regno)); 2448 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2449 regno, regval)); 2450 2451 regval |= STATE_MACHINE_RESET_BIT; 2452 2453 switch (regno) { 2454 case MISC_CONFIG_REG: 2455 /* 2456 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2457 * resetting PCIE block and bringing PCIE link down, bit 29 2458 * in the register needs to be set first, and then set it again 2459 * while the reset bit is written. 2460 * See:P500 of 57xx-PG102-RDS.pdf. 2461 */ 2462 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2463 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2464 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2465 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2466 if (bgep->chipid.pci_type == BGE_PCI_E) { 2467 if (bgep->chipid.asic_rev == 2468 MHCR_CHIP_REV_5751_A0 || 2469 bgep->chipid.asic_rev == 2470 MHCR_CHIP_REV_5721_A0 || 2471 bgep->chipid.asic_rev == 2472 MHCR_CHIP_REV_5755_A0) { 2473 val32 = bge_reg_get32(bgep, 2474 PHY_TEST_CTRL_REG); 2475 if (val32 == (PHY_PCIE_SCRAM_MODE | 2476 PHY_PCIE_LTASS_MODE)) 2477 bge_reg_put32(bgep, 2478 PHY_TEST_CTRL_REG, 2479 PHY_PCIE_SCRAM_MODE); 2480 val32 = pci_config_get32 2481 (bgep->cfg_handle, 2482 PCI_CONF_BGE_CLKCTL); 2483 val32 |= CLKCTL_PCIE_A0_FIX; 2484 pci_config_put32(bgep->cfg_handle, 2485 PCI_CONF_BGE_CLKCTL, val32); 2486 } 2487 bge_reg_set32(bgep, regno, 2488 MISC_CONFIG_GRC_RESET_DISABLE); 2489 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2490 } 2491 } 2492 2493 /* 2494 * Special case - causes Core reset 2495 * 2496 * On SPARC v9 we want to ensure that we don't start 2497 * timing until the I/O access has actually reached 2498 * the chip, otherwise we might make the next access 2499 * too early. And we can't just force the write out 2500 * by following it with a read (even to config space) 2501 * because that would cause the fault we're trying 2502 * to avoid. Hence the need for membar_sync() here. 2503 */ 2504 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2505 #ifdef __sparcv9 2506 membar_sync(); 2507 #endif /* __sparcv9 */ 2508 /* 2509 * On some platforms,system need about 300us for 2510 * link setup. 2511 */ 2512 drv_usecwait(300); 2513 2514 if (bgep->chipid.pci_type == BGE_PCI_E) { 2515 /* PCI-E device need more reset time */ 2516 drv_usecwait(120000); 2517 2518 /* Set PCIE max payload size and clear error status. */ 2519 if ((bgep->chipid.chip_label == 5721) || 2520 (bgep->chipid.chip_label == 5751) || 2521 (bgep->chipid.chip_label == 5752) || 2522 (bgep->chipid.chip_label == 5789)) { 2523 pci_config_put16(bgep->cfg_handle, 2524 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2525 pci_config_put16(bgep->cfg_handle, 2526 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2527 } 2528 } 2529 2530 BGE_PCICHK(bgep); 2531 return (B_TRUE); 2532 2533 default: 2534 bge_reg_put32(bgep, regno, regval); 2535 return (bge_chip_poll_engine(bgep, regno, 2536 STATE_MACHINE_RESET_BIT, 0)); 2537 } 2538 } 2539 2540 /* 2541 * Various registers that control the chip's internal engines (state 2542 * machines) have an <enable> bit (fortunately, in the same place in 2543 * each such register :-). To stop the state machine, this bit must 2544 * be written with 0, then polled to see when the state machine has 2545 * actually stopped. 2546 * 2547 * The return value is B_TRUE on success (enable bit cleared), or 2548 * B_FALSE if the state machine didn't stop :( 2549 */ 2550 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2551 uint32_t morebits); 2552 #pragma no_inline(bge_chip_disable_engine) 2553 2554 static boolean_t 2555 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2556 { 2557 uint32_t regval; 2558 2559 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2560 (void *)bgep, regno, morebits)); 2561 2562 switch (regno) { 2563 case FTQ_RESET_REG: 2564 /* 2565 * For Schumacher's bugfix CR6490108 2566 */ 2567 #ifdef BGE_IPMI_ASF 2568 #ifdef BGE_NETCONSOLE 2569 if (bgep->asf_enabled) 2570 return (B_TRUE); 2571 #endif 2572 #endif 2573 /* 2574 * Not quite like the others; it doesn't 2575 * have an <enable> bit, but instead we 2576 * have to set and then clear all the bits 2577 */ 2578 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2579 drv_usecwait(100); 2580 bge_reg_put32(bgep, regno, 0); 2581 return (B_TRUE); 2582 2583 default: 2584 regval = bge_reg_get32(bgep, regno); 2585 regval &= ~STATE_MACHINE_ENABLE_BIT; 2586 regval &= ~morebits; 2587 bge_reg_put32(bgep, regno, regval); 2588 return (bge_chip_poll_engine(bgep, regno, 2589 STATE_MACHINE_ENABLE_BIT, 0)); 2590 } 2591 } 2592 2593 /* 2594 * Various registers that control the chip's internal engines (state 2595 * machines) have an <enable> bit (fortunately, in the same place in 2596 * each such register :-). To start the state machine, this bit must 2597 * be written with 1, then polled to see when the state machine has 2598 * actually started. 2599 * 2600 * The return value is B_TRUE on success (enable bit set), or 2601 * B_FALSE if the state machine didn't start :( 2602 */ 2603 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2604 uint32_t morebits); 2605 #pragma no_inline(bge_chip_enable_engine) 2606 2607 static boolean_t 2608 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2609 { 2610 uint32_t regval; 2611 2612 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2613 (void *)bgep, regno, morebits)); 2614 2615 switch (regno) { 2616 case FTQ_RESET_REG: 2617 #ifdef BGE_IPMI_ASF 2618 #ifdef BGE_NETCONSOLE 2619 if (bgep->asf_enabled) 2620 return (B_TRUE); 2621 #endif 2622 #endif 2623 /* 2624 * Not quite like the others; it doesn't 2625 * have an <enable> bit, but instead we 2626 * have to set and then clear all the bits 2627 */ 2628 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2629 drv_usecwait(100); 2630 bge_reg_put32(bgep, regno, 0); 2631 return (B_TRUE); 2632 2633 default: 2634 regval = bge_reg_get32(bgep, regno); 2635 regval |= STATE_MACHINE_ENABLE_BIT; 2636 regval |= morebits; 2637 bge_reg_put32(bgep, regno, regval); 2638 return (bge_chip_poll_engine(bgep, regno, 2639 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2640 } 2641 } 2642 2643 /* 2644 * Reprogram the Ethernet, Transmit, and Receive MAC 2645 * modes to match the param_* variables 2646 */ 2647 void bge_sync_mac_modes(bge_t *bgep); 2648 #pragma no_inline(bge_sync_mac_modes) 2649 2650 void 2651 bge_sync_mac_modes(bge_t *bgep) 2652 { 2653 uint32_t macmode; 2654 uint32_t regval; 2655 2656 ASSERT(mutex_owned(bgep->genlock)); 2657 2658 /* 2659 * Reprogram the Ethernet MAC mode ... 2660 */ 2661 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2662 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2663 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2664 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2665 else 2666 macmode |= ETHERNET_MODE_LINK_POLARITY; 2667 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2668 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2669 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2670 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2671 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2672 macmode |= ETHERNET_MODE_PORTMODE_MII; 2673 else 2674 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2675 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2676 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2677 else 2678 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2679 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2680 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2681 else 2682 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2683 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2684 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2685 (void *)bgep, regval, macmode)); 2686 2687 /* 2688 * ... the Transmit MAC mode ... 2689 */ 2690 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2691 if (bgep->param_link_tx_pause) 2692 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2693 else 2694 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2695 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2696 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2697 (void *)bgep, regval, macmode)); 2698 2699 /* 2700 * ... and the Receive MAC mode 2701 */ 2702 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2703 if (bgep->param_link_rx_pause) 2704 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2705 else 2706 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2707 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2708 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2709 (void *)bgep, regval, macmode)); 2710 } 2711 2712 /* 2713 * bge_chip_sync() -- program the chip with the unicast MAC address, 2714 * the multicast hash table, the required level of promiscuity, and 2715 * the current loopback mode ... 2716 */ 2717 #ifdef BGE_IPMI_ASF 2718 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2719 #else 2720 int bge_chip_sync(bge_t *bgep); 2721 #endif 2722 #pragma no_inline(bge_chip_sync) 2723 2724 int 2725 #ifdef BGE_IPMI_ASF 2726 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2727 #else 2728 bge_chip_sync(bge_t *bgep) 2729 #endif 2730 { 2731 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2732 boolean_t promisc; 2733 uint64_t macaddr; 2734 uint32_t fill; 2735 int i, j; 2736 int retval = DDI_SUCCESS; 2737 2738 BGE_TRACE(("bge_chip_sync($%p)", 2739 (void *)bgep)); 2740 2741 ASSERT(mutex_owned(bgep->genlock)); 2742 2743 promisc = B_FALSE; 2744 fill = ~(uint32_t)0; 2745 2746 if (bgep->promisc) 2747 promisc = B_TRUE; 2748 else 2749 fill = (uint32_t)0; 2750 2751 /* 2752 * If the TX/RX MAC engines are already running, we should stop 2753 * them (and reset the RX engine) before changing the parameters. 2754 * If they're not running, this will have no effect ... 2755 * 2756 * NOTE: this is currently disabled by default because stopping 2757 * and restarting the Tx engine may cause an outgoing packet in 2758 * transit to be truncated. Also, stopping and restarting the 2759 * Rx engine seems to not work correctly on the 5705. Testing 2760 * has not (yet!) revealed any problems with NOT stopping and 2761 * restarting these engines (and Broadcom say their drivers don't 2762 * do this), but if it is found to cause problems, this variable 2763 * can be patched to re-enable the old behaviour ... 2764 */ 2765 if (bge_stop_start_on_sync) { 2766 #ifdef BGE_IPMI_ASF 2767 if (!bgep->asf_enabled) { 2768 if (!bge_chip_disable_engine(bgep, 2769 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2770 retval = DDI_FAILURE; 2771 } else { 2772 if (!bge_chip_disable_engine(bgep, 2773 RECEIVE_MAC_MODE_REG, 0)) 2774 retval = DDI_FAILURE; 2775 } 2776 #else 2777 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2778 RECEIVE_MODE_KEEP_VLAN_TAG)) 2779 retval = DDI_FAILURE; 2780 #endif 2781 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2782 retval = DDI_FAILURE; 2783 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2784 retval = DDI_FAILURE; 2785 } 2786 2787 /* 2788 * Reprogram the hashed multicast address table ... 2789 */ 2790 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2791 bge_reg_put32(bgep, MAC_HASH_REG(i), 2792 bgep->mcast_hash[i] | fill); 2793 2794 #ifdef BGE_IPMI_ASF 2795 if (!bgep->asf_enabled || !asf_keeplive) { 2796 #endif 2797 /* 2798 * Transform the MAC address(es) from host to chip format, then 2799 * reprogram the transmit random backoff seed and the unicast 2800 * MAC address(es) ... 2801 */ 2802 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2803 for (i = 0, fill = 0, macaddr = 0ull; 2804 i < ETHERADDRL; ++i) { 2805 macaddr <<= 8; 2806 macaddr |= bgep->curr_addr[j].addr[i]; 2807 fill += bgep->curr_addr[j].addr[i]; 2808 } 2809 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2810 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2811 } 2812 2813 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2814 (void *)bgep, macaddr)); 2815 #ifdef BGE_IPMI_ASF 2816 } 2817 #endif 2818 2819 /* 2820 * Set or clear the PROMISCUOUS mode bit 2821 */ 2822 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2823 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2824 2825 /* 2826 * Sync the rest of the MAC modes too ... 2827 */ 2828 bge_sync_mac_modes(bgep); 2829 2830 /* 2831 * Restart RX/TX MAC engines if required ... 2832 */ 2833 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2834 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2835 retval = DDI_FAILURE; 2836 #ifdef BGE_IPMI_ASF 2837 if (!bgep->asf_enabled) { 2838 if (!bge_chip_enable_engine(bgep, 2839 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2840 retval = DDI_FAILURE; 2841 } else { 2842 if (!bge_chip_enable_engine(bgep, 2843 RECEIVE_MAC_MODE_REG, 0)) 2844 retval = DDI_FAILURE; 2845 } 2846 #else 2847 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2848 RECEIVE_MODE_KEEP_VLAN_TAG)) 2849 retval = DDI_FAILURE; 2850 #endif 2851 } 2852 return (retval); 2853 } 2854 2855 /* 2856 * This array defines the sequence of state machine control registers 2857 * in which the <enable> bit must be cleared to bring the chip to a 2858 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2859 */ 2860 static bge_regno_t shutdown_engine_regs[] = { 2861 RECEIVE_MAC_MODE_REG, 2862 RCV_BD_INITIATOR_MODE_REG, 2863 RCV_LIST_PLACEMENT_MODE_REG, 2864 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2865 RCV_DATA_BD_INITIATOR_MODE_REG, 2866 RCV_DATA_COMPLETION_MODE_REG, 2867 RCV_BD_COMPLETION_MODE_REG, 2868 2869 SEND_BD_SELECTOR_MODE_REG, 2870 SEND_BD_INITIATOR_MODE_REG, 2871 SEND_DATA_INITIATOR_MODE_REG, 2872 READ_DMA_MODE_REG, 2873 SEND_DATA_COMPLETION_MODE_REG, 2874 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2875 SEND_BD_COMPLETION_MODE_REG, 2876 TRANSMIT_MAC_MODE_REG, 2877 2878 HOST_COALESCE_MODE_REG, 2879 WRITE_DMA_MODE_REG, 2880 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2881 FTQ_RESET_REG, /* special - see code */ 2882 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2883 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2884 BGE_REGNO_NONE /* terminator */ 2885 }; 2886 2887 /* 2888 * bge_chip_stop() -- stop all chip processing 2889 * 2890 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2891 * we've detected a problem internally; otherwise, this is a normal 2892 * (clean) stop (at user request i.e. the last STREAM has been closed). 2893 */ 2894 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2895 #pragma no_inline(bge_chip_stop) 2896 2897 void 2898 bge_chip_stop(bge_t *bgep, boolean_t fault) 2899 { 2900 bge_regno_t regno; 2901 bge_regno_t *rbp; 2902 boolean_t ok; 2903 2904 BGE_TRACE(("bge_chip_stop($%p)", 2905 (void *)bgep)); 2906 2907 ASSERT(mutex_owned(bgep->genlock)); 2908 2909 rbp = shutdown_engine_regs; 2910 /* 2911 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2912 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2913 * -ory arbiter should not be disabled. 2914 */ 2915 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2916 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2917 ok &= bge_chip_disable_engine(bgep, regno, 0); 2918 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2919 (regno != DMA_COMPLETION_MODE_REG) && 2920 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2921 (regno != BUFFER_MANAGER_MODE_REG) && 2922 (regno != MEMORY_ARBITER_MODE_REG)) 2923 ok &= bge_chip_disable_engine(bgep, 2924 regno, 0); 2925 } 2926 2927 if (!ok && !fault) 2928 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2929 2930 /* 2931 * Finally, disable (all) MAC events & clear the MAC status 2932 */ 2933 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2934 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2935 2936 /* 2937 * if we're stopping the chip because of a detected fault then do 2938 * appropriate actions 2939 */ 2940 if (fault) { 2941 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2942 bgep->bge_chip_state = BGE_CHIP_FAULT; 2943 if (!bgep->manual_reset) 2944 ddi_fm_service_impact(bgep->devinfo, 2945 DDI_SERVICE_LOST); 2946 if (bgep->bge_dma_error) { 2947 /* 2948 * need to free buffers in case the fault was 2949 * due to a memory error in a buffer - got to 2950 * do a fair bit of tidying first 2951 */ 2952 if (bgep->progress & PROGRESS_KSTATS) { 2953 bge_fini_kstats(bgep); 2954 bgep->progress &= ~PROGRESS_KSTATS; 2955 } 2956 if (bgep->progress & PROGRESS_INTR) { 2957 bge_intr_disable(bgep); 2958 rw_enter(bgep->errlock, RW_WRITER); 2959 bge_fini_rings(bgep); 2960 rw_exit(bgep->errlock); 2961 bgep->progress &= ~PROGRESS_INTR; 2962 } 2963 if (bgep->progress & PROGRESS_BUFS) { 2964 bge_free_bufs(bgep); 2965 bgep->progress &= ~PROGRESS_BUFS; 2966 } 2967 bgep->bge_dma_error = B_FALSE; 2968 } 2969 } 2970 } else 2971 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2972 } 2973 2974 /* 2975 * Poll for completion of chip's ROM firmware; also, at least on the 2976 * first time through, find and return the hardware MAC address, if any. 2977 */ 2978 static uint64_t bge_poll_firmware(bge_t *bgep); 2979 #pragma no_inline(bge_poll_firmware) 2980 2981 static uint64_t 2982 bge_poll_firmware(bge_t *bgep) 2983 { 2984 uint64_t magic; 2985 uint64_t mac; 2986 uint32_t gen; 2987 uint32_t i; 2988 2989 /* 2990 * Step 19: poll for firmware completion (GENCOMM port set 2991 * to the ones complement of T3_MAGIC_NUMBER). 2992 * 2993 * While we're at it, we also read the MAC address register; 2994 * at some stage the firmware will load this with the 2995 * factory-set value. 2996 * 2997 * When both the magic number and the MAC address are set, 2998 * we're done; but we impose a time limit of one second 2999 * (1000*1000us) in case the firmware fails in some fashion 3000 * or the SEEPROM that provides that MAC address isn't fitted. 3001 * 3002 * After the first time through (chip state != INITIAL), we 3003 * don't need the MAC address to be set (we've already got it 3004 * or not, from the first time), so we don't wait for it, but 3005 * we still have to wait for the T3_MAGIC_NUMBER. 3006 * 3007 * Note: the magic number is only a 32-bit quantity, but the NIC 3008 * memory is 64-bit (and big-endian) internally. Addressing the 3009 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3010 * it work correctly on both big- and little-endian hosts. 3011 */ 3012 for (i = 0; i < 1000; ++i) { 3013 drv_usecwait(1000); 3014 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3015 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3016 #ifdef BGE_IPMI_ASF 3017 if (!bgep->asf_enabled) { 3018 #endif 3019 if (gen != ~T3_MAGIC_NUMBER) 3020 continue; 3021 #ifdef BGE_IPMI_ASF 3022 } 3023 #endif 3024 if (mac != 0ULL) 3025 break; 3026 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3027 break; 3028 } 3029 3030 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3031 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3032 (void *)bgep, gen, i)); 3033 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3034 mac, magic)); 3035 3036 return (mac); 3037 } 3038 3039 /* 3040 * Maximum times of trying to get the NVRAM access lock 3041 * by calling bge_nvmem_acquire() 3042 */ 3043 #define MAX_TRY_NVMEM_ACQUIRE 10000 3044 3045 #ifdef BGE_IPMI_ASF 3046 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3047 #else 3048 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3049 #endif 3050 #pragma no_inline(bge_chip_reset) 3051 3052 int 3053 #ifdef BGE_IPMI_ASF 3054 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3055 #else 3056 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3057 #endif 3058 { 3059 chip_id_t chipid; 3060 uint64_t mac; 3061 uint64_t magic; 3062 uint32_t modeflags; 3063 uint32_t mhcr; 3064 uint32_t sx0; 3065 uint32_t i, tries; 3066 #ifdef BGE_IPMI_ASF 3067 uint32_t mailbox; 3068 #endif 3069 int retval = DDI_SUCCESS; 3070 3071 BGE_TRACE(("bge_chip_reset($%p, %d)", 3072 (void *)bgep, enable_dma)); 3073 3074 ASSERT(mutex_owned(bgep->genlock)); 3075 3076 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3077 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3078 3079 /* 3080 * Do we need to stop the chip cleanly before resetting? 3081 */ 3082 switch (bgep->bge_chip_state) { 3083 default: 3084 _NOTE(NOTREACHED) 3085 return (DDI_FAILURE); 3086 3087 case BGE_CHIP_INITIAL: 3088 case BGE_CHIP_STOPPED: 3089 case BGE_CHIP_RESET: 3090 break; 3091 3092 case BGE_CHIP_RUNNING: 3093 case BGE_CHIP_ERROR: 3094 case BGE_CHIP_FAULT: 3095 bge_chip_stop(bgep, B_FALSE); 3096 break; 3097 } 3098 3099 #ifdef BGE_IPMI_ASF 3100 if (bgep->asf_enabled) { 3101 #ifdef __sparc 3102 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3103 MHCR_ENABLE_TAGGED_STATUS_MODE | 3104 MHCR_MASK_INTERRUPT_MODE | 3105 MHCR_MASK_PCI_INT_OUTPUT | 3106 MHCR_CLEAR_INTERRUPT_INTA | 3107 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3108 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3109 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3110 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3111 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3112 MEMORY_ARBITER_ENABLE); 3113 #endif 3114 if (asf_mode == ASF_MODE_INIT) { 3115 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3116 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3117 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3118 } 3119 } 3120 #endif 3121 /* 3122 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3123 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3124 * 3125 * Before reset Core clock,it is 3126 * also required to initialize the Memory Arbiter as specified in step9 3127 * and Misc Host Control Register as specified in step-13 3128 * Step 4-5: reset Core clock & wait for completion 3129 * Steps 6-8: are done by bge_chip_cfg_init() 3130 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3131 */ 3132 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3133 retval = DDI_FAILURE; 3134 3135 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3136 MHCR_ENABLE_TAGGED_STATUS_MODE | 3137 MHCR_MASK_INTERRUPT_MODE | 3138 MHCR_MASK_PCI_INT_OUTPUT | 3139 MHCR_CLEAR_INTERRUPT_INTA; 3140 #ifdef _BIG_ENDIAN 3141 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3142 #endif /* _BIG_ENDIAN */ 3143 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3144 #ifdef BGE_IPMI_ASF 3145 if (bgep->asf_enabled) 3146 bgep->asf_wordswapped = B_FALSE; 3147 #endif 3148 /* 3149 * NVRAM Corruption Workaround 3150 */ 3151 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3152 if (bge_nvmem_acquire(bgep) != EAGAIN) 3153 break; 3154 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3155 BGE_DEBUG(("%s: fail to acquire nvram lock", 3156 bgep->ifname)); 3157 3158 #ifdef BGE_IPMI_ASF 3159 if (!bgep->asf_enabled) { 3160 #endif 3161 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3162 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3163 #ifdef BGE_IPMI_ASF 3164 } 3165 #endif 3166 3167 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3168 retval = DDI_FAILURE; 3169 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3170 3171 /* 3172 * Step 8a: This may belong elsewhere, but BCM5721 needs 3173 * a bit set to avoid a fifo overflow/underflow bug. 3174 */ 3175 if ((bgep->chipid.chip_label == 5721) || 3176 (bgep->chipid.chip_label == 5751) || 3177 (bgep->chipid.chip_label == 5752) || 3178 (bgep->chipid.chip_label == 5755) || 3179 (bgep->chipid.chip_label == 5789)) 3180 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3181 3182 3183 /* 3184 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3185 * not be changed. 3186 */ 3187 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3188 retval = DDI_FAILURE; 3189 3190 /* 3191 * Steps 10-11: configure PIO endianness options and 3192 * enable indirect register access -- already done 3193 * Steps 12-13: enable writing to the PCI state & clock 3194 * control registers -- not required; we aren't going to 3195 * use those features. 3196 * Steps 14-15: Configure DMA endianness options. See 3197 * the comments on the setting of the MHCR above. 3198 */ 3199 #ifdef _BIG_ENDIAN 3200 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3201 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3202 #else 3203 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3204 #endif /* _BIG_ENDIAN */ 3205 #ifdef BGE_IPMI_ASF 3206 if (bgep->asf_enabled) 3207 modeflags |= MODE_HOST_STACK_UP; 3208 #endif 3209 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3210 3211 #ifdef BGE_IPMI_ASF 3212 if (bgep->asf_enabled) { 3213 #ifdef __sparc 3214 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3215 MEMORY_ARBITER_ENABLE | 3216 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3217 #endif 3218 3219 #ifdef BGE_NETCONSOLE 3220 if (!bgep->asf_newhandshake) { 3221 if ((asf_mode == ASF_MODE_INIT) || 3222 (asf_mode == ASF_MODE_POST_INIT)) { 3223 bge_asf_post_reset_old_mode(bgep, 3224 BGE_INIT_RESET); 3225 } else { 3226 bge_asf_post_reset_old_mode(bgep, 3227 BGE_SHUTDOWN_RESET); 3228 } 3229 } 3230 #endif 3231 3232 /* Wait for NVRAM init */ 3233 i = 0; 3234 drv_usecwait(5000); 3235 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3236 3237 while ((mailbox != (uint32_t) 3238 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3239 (i < 10000)) { 3240 drv_usecwait(100); 3241 mailbox = bge_nic_get32(bgep, 3242 BGE_FIRMWARE_MAILBOX); 3243 i++; 3244 } 3245 3246 #ifndef BGE_NETCONSOLE 3247 if (!bgep->asf_newhandshake) { 3248 if ((asf_mode == ASF_MODE_INIT) || 3249 (asf_mode == ASF_MODE_POST_INIT)) { 3250 3251 bge_asf_post_reset_old_mode(bgep, 3252 BGE_INIT_RESET); 3253 } else { 3254 bge_asf_post_reset_old_mode(bgep, 3255 BGE_SHUTDOWN_RESET); 3256 } 3257 } 3258 #endif 3259 } 3260 #endif 3261 /* 3262 * Steps 16-17: poll for firmware completion 3263 */ 3264 mac = bge_poll_firmware(bgep); 3265 3266 /* 3267 * Step 18: enable external memory -- doesn't apply. 3268 * 3269 * However we take the opportunity to set the MLCR anyway, as 3270 * this register also controls the SEEPROM auto-access method 3271 * which we may want to use later ... 3272 * 3273 * The proper value here depends on the way the chip is wired 3274 * into the circuit board, as this register *also* controls which 3275 * of the "Miscellaneous I/O" pins are driven as outputs and the 3276 * values driven onto those pins! 3277 * 3278 * See also step 74 in the PRM ... 3279 */ 3280 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3281 bgep->chipid.bge_mlcr_default); 3282 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3283 3284 /* 3285 * Step 20: clear the Ethernet MAC mode register 3286 */ 3287 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3288 3289 /* 3290 * Step 21: restore cache-line-size, latency timer, and 3291 * subsystem ID registers to their original values (not 3292 * those read into the local structure <chipid>, 'cos 3293 * that was after they were cleared by the RESET). 3294 * 3295 * Note: the Subsystem Vendor/Device ID registers are not 3296 * directly writable in config space, so we use the shadow 3297 * copy in "Page Zero" of register space to restore them 3298 * both in one go ... 3299 */ 3300 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3301 bgep->chipid.clsize); 3302 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3303 bgep->chipid.latency); 3304 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3305 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3306 3307 /* 3308 * The SEND INDEX registers should be reset to zero by the 3309 * global chip reset; if they're not, there'll be trouble 3310 * later on. 3311 */ 3312 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3313 if (sx0 != 0) { 3314 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3315 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3316 retval = DDI_FAILURE; 3317 } 3318 3319 /* Enable MSI code */ 3320 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3321 bge_reg_set32(bgep, MSI_MODE_REG, 3322 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3323 3324 /* 3325 * On the first time through, save the factory-set MAC address 3326 * (if any). If bge_poll_firmware() above didn't return one 3327 * (from a chip register) consider looking in the attached NV 3328 * memory device, if any. Once we have it, we save it in both 3329 * register-image (64-bit) and byte-array forms. All-zero and 3330 * all-one addresses are not valid, and we refuse to stash those. 3331 */ 3332 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3333 if (mac == 0ULL) 3334 mac = bge_get_nvmac(bgep); 3335 if (mac != 0ULL && mac != ~0ULL) { 3336 bgep->chipid.hw_mac_addr = mac; 3337 for (i = ETHERADDRL; i-- != 0; ) { 3338 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3339 mac >>= 8; 3340 } 3341 bgep->chipid.vendor_addr.set = B_TRUE; 3342 } 3343 } 3344 3345 #ifdef BGE_IPMI_ASF 3346 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3347 if (asf_mode != ASF_MODE_NONE) { 3348 if ((asf_mode == ASF_MODE_INIT) || 3349 (asf_mode == ASF_MODE_POST_INIT)) { 3350 3351 bge_asf_post_reset_new_mode(bgep, 3352 BGE_INIT_RESET); 3353 } else { 3354 bge_asf_post_reset_new_mode(bgep, 3355 BGE_SHUTDOWN_RESET); 3356 } 3357 } 3358 } 3359 #endif 3360 3361 /* 3362 * Record the new state 3363 */ 3364 bgep->chip_resets += 1; 3365 bgep->bge_chip_state = BGE_CHIP_RESET; 3366 return (retval); 3367 } 3368 3369 /* 3370 * bge_chip_start() -- start the chip transmitting and/or receiving, 3371 * including enabling interrupts 3372 */ 3373 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3374 #pragma no_inline(bge_chip_start) 3375 3376 int 3377 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3378 { 3379 uint32_t coalmode; 3380 uint32_t ledctl; 3381 uint32_t mtu; 3382 uint32_t maxring; 3383 uint32_t stats_mask; 3384 uint32_t dma_wrprio; 3385 uint64_t ring; 3386 int retval = DDI_SUCCESS; 3387 3388 BGE_TRACE(("bge_chip_start($%p)", 3389 (void *)bgep)); 3390 3391 ASSERT(mutex_owned(bgep->genlock)); 3392 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3393 3394 /* 3395 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3396 * The document specifies 95 separate steps to fully 3397 * initialise the chip!!!! 3398 * 3399 * The reset code above has already got us as far as step 3400 * 21, so we continue with ... 3401 * 3402 * Step 22: clear the MAC statistics block 3403 * (0x0300-0x0aff in NIC-local memory) 3404 */ 3405 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3406 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3407 NIC_MEM_STATISTICS_SIZE); 3408 3409 /* 3410 * Step 23: clear the status block (in host memory) 3411 */ 3412 DMA_ZERO(bgep->status_block); 3413 3414 /* 3415 * Step 24: set DMA read/write control register 3416 */ 3417 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3418 bgep->chipid.bge_dma_rwctrl); 3419 3420 /* 3421 * Step 25: Configure DMA endianness -- already done (16/17) 3422 * Step 26: Configure Host-Based Send Rings 3423 * Step 27: Indicate Host Stack Up 3424 */ 3425 bge_reg_set32(bgep, MODE_CONTROL_REG, 3426 MODE_HOST_SEND_BDS | 3427 MODE_HOST_STACK_UP); 3428 3429 /* 3430 * Step 28: Configure checksum options: 3431 * Solaris supports the hardware default checksum options. 3432 * 3433 * Workaround for Incorrect pseudo-header checksum calculation. 3434 */ 3435 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3436 bge_reg_set32(bgep, MODE_CONTROL_REG, 3437 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3438 3439 /* 3440 * Step 29: configure Timer Prescaler. The value is always the 3441 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3442 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3443 * for the whole chip! 3444 */ 3445 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3446 3447 /* 3448 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3449 * 3450 * If the mbuf_length is specified as 0, we just leave these at 3451 * their hardware defaults, rather than explicitly setting them. 3452 * As the Broadcom HRM,driver better not change the parameters 3453 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3454 */ 3455 if ((bgep->chipid.mbuf_length != 0) && 3456 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3457 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3458 bgep->chipid.mbuf_base); 3459 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3460 bgep->chipid.mbuf_length); 3461 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3462 DMAD_POOL_BASE_DEFAULT); 3463 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3464 DMAD_POOL_LENGTH_DEFAULT); 3465 } 3466 3467 /* 3468 * Step 32: configure MAC memory pool watermarks 3469 */ 3470 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3471 bgep->chipid.mbuf_lo_water_rdma); 3472 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3473 bgep->chipid.mbuf_lo_water_rmac); 3474 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3475 bgep->chipid.mbuf_hi_water); 3476 3477 /* 3478 * Step 33: configure DMA resource watermarks 3479 */ 3480 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3481 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3482 bge_dmad_lo_water); 3483 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3484 bge_dmad_hi_water); 3485 } 3486 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3487 3488 /* 3489 * Steps 34-36: enable buffer manager & internal h/w queues 3490 */ 3491 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3492 STATE_MACHINE_ATTN_ENABLE_BIT)) 3493 retval = DDI_FAILURE; 3494 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3495 retval = DDI_FAILURE; 3496 3497 /* 3498 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3499 */ 3500 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3501 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3502 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3503 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3504 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3505 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3506 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3507 } 3508 3509 /* 3510 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3511 */ 3512 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3513 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3514 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3515 bge_replenish_jumbo); 3516 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3517 bge_replenish_mini); 3518 } 3519 3520 /* 3521 * Steps 41-43: clear Send Ring Producer Indices and initialise 3522 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3523 */ 3524 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3525 maxring = BGE_SEND_RINGS_MAX; 3526 else 3527 maxring = BGE_SEND_RINGS_MAX_5705; 3528 for (ring = 0; ring < maxring; ++ring) { 3529 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3530 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3531 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3532 &bgep->send[ring].hw_rcb); 3533 } 3534 3535 /* 3536 * Steps 44-45: initialise Receive Return Rings 3537 * (0x0200-0x02ff in NIC-local memory) 3538 */ 3539 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3540 maxring = BGE_RECV_RINGS_MAX; 3541 else 3542 maxring = BGE_RECV_RINGS_MAX_5705; 3543 for (ring = 0; ring < maxring; ++ring) 3544 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3545 &bgep->recv[ring].hw_rcb); 3546 3547 /* 3548 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3549 */ 3550 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3551 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3552 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3553 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3554 } 3555 /* 3556 * Step 47: configure the MAC unicast address 3557 * Step 48: configure the random backoff seed 3558 * Step 96: set up multicast filters 3559 */ 3560 #ifdef BGE_IPMI_ASF 3561 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3562 #else 3563 if (bge_chip_sync(bgep) == DDI_FAILURE) 3564 #endif 3565 retval = DDI_FAILURE; 3566 3567 /* 3568 * Step 49: configure the MTU 3569 */ 3570 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3571 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3572 3573 /* 3574 * Step 50: configure the IPG et al 3575 */ 3576 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3577 3578 /* 3579 * Step 51: configure the default Rx Return Ring 3580 */ 3581 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3582 3583 /* 3584 * Steps 52-54: configure Receive List Placement, 3585 * and enable Receive List Placement Statistics 3586 */ 3587 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3588 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3589 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3590 case MHCR_CHIP_ASIC_REV_5700: 3591 case MHCR_CHIP_ASIC_REV_5701: 3592 case MHCR_CHIP_ASIC_REV_5703: 3593 case MHCR_CHIP_ASIC_REV_5704: 3594 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3595 break; 3596 case MHCR_CHIP_ASIC_REV_5705: 3597 break; 3598 default: 3599 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3600 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3601 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3602 break; 3603 } 3604 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3605 3606 if (bgep->chipid.rx_rings > 1) 3607 bge_init_recv_rule(bgep); 3608 3609 /* 3610 * Steps 55-56: enable Send Data Initiator Statistics 3611 */ 3612 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3613 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3614 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3615 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3616 } else { 3617 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3618 SEND_INIT_STATS_ENABLE); 3619 } 3620 /* 3621 * Steps 57-58: stop (?) the Host Coalescing Engine 3622 */ 3623 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3624 retval = DDI_FAILURE; 3625 3626 /* 3627 * Steps 59-62: initialise Host Coalescing parameters 3628 */ 3629 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3630 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3631 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3632 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3633 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3634 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3635 bge_tx_count_intr); 3636 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3637 bge_tx_ticks_intr); 3638 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3639 bge_rx_count_intr); 3640 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3641 bge_rx_ticks_intr); 3642 } 3643 3644 /* 3645 * Steps 63-64: initialise status block & statistics 3646 * host memory addresses 3647 * The statistic block does not exist in some chipsets 3648 * Step 65: initialise Statistics Coalescing Tick Counter 3649 */ 3650 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3651 bgep->status_block.cookie.dmac_laddress); 3652 3653 /* 3654 * Steps 66-67: initialise status block & statistics 3655 * NIC-local memory addresses 3656 */ 3657 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3658 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3659 bgep->statistics.cookie.dmac_laddress); 3660 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3661 STATISTICS_TICKS_DEFAULT); 3662 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3663 NIC_MEM_STATUS_BLOCK); 3664 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3665 NIC_MEM_STATISTICS); 3666 } 3667 3668 /* 3669 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3670 * Completion Engine, the Receive List Placement Engine, and the 3671 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3672 * and BCM5715. 3673 */ 3674 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3675 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3676 coalmode = COALESCE_64_BYTE_STATUS; 3677 else 3678 coalmode = 0; 3679 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3680 retval = DDI_FAILURE; 3681 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3682 STATE_MACHINE_ATTN_ENABLE_BIT)) 3683 retval = DDI_FAILURE; 3684 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3685 retval = DDI_FAILURE; 3686 3687 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3688 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3689 STATE_MACHINE_ATTN_ENABLE_BIT)) 3690 retval = DDI_FAILURE; 3691 3692 /* 3693 * Step 72: Enable MAC DMA engines 3694 * Step 73: Clear & enable MAC statistics 3695 */ 3696 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3697 ETHERNET_MODE_ENABLE_FHDE | 3698 ETHERNET_MODE_ENABLE_RDE | 3699 ETHERNET_MODE_ENABLE_TDE); 3700 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3701 ETHERNET_MODE_ENABLE_TX_STATS | 3702 ETHERNET_MODE_ENABLE_RX_STATS | 3703 ETHERNET_MODE_CLEAR_TX_STATS | 3704 ETHERNET_MODE_CLEAR_RX_STATS); 3705 3706 /* 3707 * Step 74: configure the MLCR (Miscellaneous Local Control 3708 * Register); not required, as we set up the MLCR in step 10 3709 * (part of the reset code) above. 3710 * 3711 * Step 75: clear Interrupt Mailbox 0 3712 */ 3713 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3714 3715 /* 3716 * Steps 76-87: Gentlemen, start your engines ... 3717 * 3718 * Enable the DMA Completion Engine, the Write DMA Engine, 3719 * the Read DMA Engine, Receive Data Completion Engine, 3720 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3721 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3722 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3723 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3724 * 3725 * Beware exhaust fumes? 3726 */ 3727 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3728 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3729 retval = DDI_FAILURE; 3730 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3731 ALL_DMA_ATTN_BITS; 3732 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3733 MHCR_CHIP_ASIC_REV_5755) { 3734 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3735 } 3736 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3737 dma_wrprio)) 3738 retval = DDI_FAILURE; 3739 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3740 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3741 retval = DDI_FAILURE; 3742 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3743 STATE_MACHINE_ATTN_ENABLE_BIT)) 3744 retval = DDI_FAILURE; 3745 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3746 if (!bge_chip_enable_engine(bgep, 3747 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3748 retval = DDI_FAILURE; 3749 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3750 retval = DDI_FAILURE; 3751 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3752 STATE_MACHINE_ATTN_ENABLE_BIT)) 3753 retval = DDI_FAILURE; 3754 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3755 RCV_BD_DISABLED_RING_ATTN)) 3756 retval = DDI_FAILURE; 3757 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3758 RCV_DATA_BD_ILL_RING_ATTN)) 3759 retval = DDI_FAILURE; 3760 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3761 retval = DDI_FAILURE; 3762 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3763 STATE_MACHINE_ATTN_ENABLE_BIT)) 3764 retval = DDI_FAILURE; 3765 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3766 STATE_MACHINE_ATTN_ENABLE_BIT)) 3767 retval = DDI_FAILURE; 3768 3769 /* 3770 * Step 88: download firmware -- doesn't apply 3771 * Steps 89-90: enable Transmit & Receive MAC Engines 3772 */ 3773 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3774 retval = DDI_FAILURE; 3775 #ifdef BGE_IPMI_ASF 3776 if (!bgep->asf_enabled) { 3777 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3778 RECEIVE_MODE_KEEP_VLAN_TAG)) 3779 retval = DDI_FAILURE; 3780 } else { 3781 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3782 retval = DDI_FAILURE; 3783 } 3784 #else 3785 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3786 RECEIVE_MODE_KEEP_VLAN_TAG)) 3787 retval = DDI_FAILURE; 3788 #endif 3789 3790 /* 3791 * Step 91: disable auto-polling of PHY status 3792 */ 3793 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3794 3795 /* 3796 * Step 92: configure D0 power state (not required) 3797 * Step 93: initialise LED control register () 3798 */ 3799 ledctl = LED_CONTROL_DEFAULT; 3800 switch (bgep->chipid.device) { 3801 case DEVICE_ID_5700: 3802 case DEVICE_ID_5700x: 3803 case DEVICE_ID_5701: 3804 /* 3805 * Switch to 5700 (MAC) mode on these older chips 3806 */ 3807 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3808 ledctl |= LED_CONTROL_LED_MODE_5700; 3809 break; 3810 3811 default: 3812 break; 3813 } 3814 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3815 3816 /* 3817 * Step 94: activate link 3818 */ 3819 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3820 3821 /* 3822 * Step 95: set up physical layer (PHY/SerDes) 3823 * restart autoneg (if required) 3824 */ 3825 if (reset_phys) 3826 if (bge_phys_update(bgep) == DDI_FAILURE) 3827 retval = DDI_FAILURE; 3828 3829 /* 3830 * Extra step (DSG): hand over all the Receive Buffers to the chip 3831 */ 3832 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3833 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3834 bgep->buff[ring].rf_next); 3835 3836 /* 3837 * MSI bits:The least significant MSI 16-bit word. 3838 * ISR will be triggered different. 3839 */ 3840 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3841 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3842 3843 /* 3844 * Extra step (DSG): select which interrupts are enabled 3845 * 3846 * Program the Ethernet MAC engine to signal attention on 3847 * Link Change events, then enable interrupts on MAC, DMA, 3848 * and FLOW attention signals. 3849 */ 3850 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3851 ETHERNET_EVENT_LINK_INT | 3852 ETHERNET_STATUS_PCS_ERROR_INT); 3853 #ifdef BGE_IPMI_ASF 3854 if (bgep->asf_enabled) { 3855 bge_reg_set32(bgep, MODE_CONTROL_REG, 3856 MODE_INT_ON_FLOW_ATTN | 3857 MODE_INT_ON_DMA_ATTN | 3858 MODE_HOST_STACK_UP| 3859 MODE_INT_ON_MAC_ATTN); 3860 } else { 3861 #endif 3862 bge_reg_set32(bgep, MODE_CONTROL_REG, 3863 MODE_INT_ON_FLOW_ATTN | 3864 MODE_INT_ON_DMA_ATTN | 3865 MODE_INT_ON_MAC_ATTN); 3866 #ifdef BGE_IPMI_ASF 3867 } 3868 #endif 3869 3870 /* 3871 * Step 97: enable PCI interrupts!!! 3872 */ 3873 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3874 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3875 MHCR_MASK_PCI_INT_OUTPUT); 3876 3877 /* 3878 * All done! 3879 */ 3880 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3881 return (retval); 3882 } 3883 3884 3885 /* 3886 * ========== Hardware interrupt handler ========== 3887 */ 3888 3889 #undef BGE_DBG 3890 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3891 3892 /* 3893 * Sync the status block, then atomically clear the specified bits in 3894 * the <flags-and-tag> field of the status block. 3895 * the <flags> word of the status block, returning the value of the 3896 * <tag> and the <flags> before the bits were cleared. 3897 */ 3898 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3899 #pragma inline(bge_status_sync) 3900 3901 static int 3902 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3903 { 3904 bge_status_t *bsp; 3905 int retval; 3906 3907 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3908 (void *)bgep, bits)); 3909 3910 ASSERT(bgep->bge_guard == BGE_GUARD); 3911 3912 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3913 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3914 if (retval != DDI_FM_OK) 3915 return (retval); 3916 3917 bsp = DMA_VPTR(bgep->status_block); 3918 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3919 3920 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3921 (void *)bgep, bits, *flags)); 3922 3923 return (retval); 3924 } 3925 3926 void bge_wake_factotum(bge_t *bgep); 3927 #pragma inline(bge_wake_factotum) 3928 3929 void 3930 bge_wake_factotum(bge_t *bgep) 3931 { 3932 mutex_enter(bgep->softintrlock); 3933 if (bgep->factotum_flag == 0) { 3934 bgep->factotum_flag = 1; 3935 ddi_trigger_softintr(bgep->factotum_id); 3936 } 3937 mutex_exit(bgep->softintrlock); 3938 } 3939 3940 /* 3941 * bge_intr() -- handle chip interrupts 3942 */ 3943 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3944 #pragma no_inline(bge_intr) 3945 3946 uint_t 3947 bge_intr(caddr_t arg1, caddr_t arg2) 3948 { 3949 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3950 bge_status_t *bsp; 3951 uint64_t flags; 3952 uint32_t regval; 3953 uint_t result; 3954 int retval, loop_cnt = 0; 3955 3956 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3957 3958 /* 3959 * GLD v2 checks that s/w setup is complete before passing 3960 * interrupts to this routine, thus eliminating the old 3961 * (and well-known) race condition around ddi_add_intr() 3962 */ 3963 ASSERT(bgep->progress & PROGRESS_HWINT); 3964 3965 result = DDI_INTR_UNCLAIMED; 3966 mutex_enter(bgep->genlock); 3967 3968 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3969 /* 3970 * Check whether chip's says it's asserting #INTA; 3971 * if not, don't process or claim the interrupt. 3972 * 3973 * Note that the PCI signal is active low, so the 3974 * bit is *zero* when the interrupt is asserted. 3975 */ 3976 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3977 if (regval & MLCR_INTA_STATE) { 3978 if (bge_check_acc_handle(bgep, bgep->io_handle) 3979 != DDI_FM_OK) 3980 goto chip_stop; 3981 mutex_exit(bgep->genlock); 3982 return (result); 3983 } 3984 3985 /* 3986 * Block further PCI interrupts ... 3987 */ 3988 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3989 MHCR_MASK_PCI_INT_OUTPUT); 3990 3991 } else { 3992 /* 3993 * Check MSI status 3994 */ 3995 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3996 if (regval & MSI_ERROR_ATTENTION) { 3997 BGE_REPORT((bgep, "msi error attention," 3998 " status=0x%x", regval)); 3999 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4000 } 4001 } 4002 4003 result = DDI_INTR_CLAIMED; 4004 4005 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4006 4007 /* 4008 * Sync the status block and grab the flags-n-tag from it. 4009 * We count the number of interrupts where there doesn't 4010 * seem to have been a DMA update of the status block; if 4011 * it *has* been updated, the counter will be cleared in 4012 * the while() loop below ... 4013 */ 4014 bgep->missed_dmas += 1; 4015 bsp = DMA_VPTR(bgep->status_block); 4016 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4017 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4018 /* 4019 * bge_chip_stop() may have freed dma area etc 4020 * while we were in this interrupt handler - 4021 * better not call bge_status_sync() 4022 */ 4023 (void) bge_check_acc_handle(bgep, 4024 bgep->io_handle); 4025 mutex_exit(bgep->genlock); 4026 return (DDI_INTR_CLAIMED); 4027 } 4028 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4029 &flags); 4030 if (retval != DDI_FM_OK) { 4031 bgep->bge_dma_error = B_TRUE; 4032 goto chip_stop; 4033 } 4034 4035 if (!(flags & STATUS_FLAG_UPDATED)) 4036 break; 4037 4038 /* 4039 * Tell the chip that we're processing the interrupt 4040 */ 4041 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4042 INTERRUPT_MBOX_DISABLE(flags)); 4043 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4044 DDI_FM_OK) 4045 goto chip_stop; 4046 4047 /* 4048 * Drop the mutex while we: 4049 * Receive any newly-arrived packets 4050 * Recycle any newly-finished send buffers 4051 */ 4052 bgep->bge_intr_running = B_TRUE; 4053 mutex_exit(bgep->genlock); 4054 bge_receive(bgep, bsp); 4055 bge_recycle(bgep, bsp); 4056 mutex_enter(bgep->genlock); 4057 bgep->bge_intr_running = B_FALSE; 4058 4059 /* 4060 * Tell the chip we've finished processing, and 4061 * give it the tag that we got from the status 4062 * block earlier, so that it knows just how far 4063 * we've gone. If it's got more for us to do, 4064 * it will now update the status block and try 4065 * to assert an interrupt (but we've got the 4066 * #INTA blocked at present). If we see the 4067 * update, we'll loop around to do some more. 4068 * Eventually we'll get out of here ... 4069 */ 4070 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4071 INTERRUPT_MBOX_ENABLE(flags)); 4072 bgep->missed_dmas = 0; 4073 } 4074 4075 /* 4076 * Check for exceptional conditions that we need to handle 4077 * 4078 * Link status changed 4079 * Status block not updated 4080 */ 4081 if (flags & STATUS_FLAG_LINK_CHANGED) 4082 bge_wake_factotum(bgep); 4083 4084 if (bgep->missed_dmas) { 4085 /* 4086 * Probably due to the internal status tag not 4087 * being reset. Force a status block update now; 4088 * this should ensure that we get an update and 4089 * a new interrupt. After that, we should be in 4090 * sync again ... 4091 */ 4092 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4093 "not updated?", flags)); 4094 bgep->missed_updates++; 4095 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4096 COALESCE_NOW); 4097 4098 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4099 /* 4100 * If this happens multiple times in a row, 4101 * it means DMA is just not working. Maybe 4102 * the chip's failed, or maybe there's a 4103 * problem on the PCI bus or in the host-PCI 4104 * bridge (Tomatillo). 4105 * 4106 * At all events, we want to stop further 4107 * interrupts and let the recovery code take 4108 * over to see whether anything can be done 4109 * about it ... 4110 */ 4111 bge_fm_ereport(bgep, 4112 DDI_FM_DEVICE_BADINT_LIMIT); 4113 goto chip_stop; 4114 } 4115 } 4116 4117 /* 4118 * Reenable assertion of #INTA, unless there's a DMA fault 4119 */ 4120 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4121 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4122 MHCR_MASK_PCI_INT_OUTPUT); 4123 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4124 DDI_FM_OK) 4125 goto chip_stop; 4126 } 4127 4128 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4129 goto chip_stop; 4130 4131 mutex_exit(bgep->genlock); 4132 return (result); 4133 4134 chip_stop: 4135 #ifdef BGE_IPMI_ASF 4136 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4137 /* 4138 * We must stop ASF heart beat before 4139 * bge_chip_stop(), otherwise some 4140 * computers (ex. IBM HS20 blade 4141 * server) may crash. 4142 */ 4143 bge_asf_update_status(bgep); 4144 bge_asf_stop_timer(bgep); 4145 bgep->asf_status = ASF_STAT_STOP; 4146 4147 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4148 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4149 } 4150 #endif 4151 bge_chip_stop(bgep, B_TRUE); 4152 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4153 mutex_exit(bgep->genlock); 4154 return (result); 4155 } 4156 4157 /* 4158 * ========== Factotum, implemented as a softint handler ========== 4159 */ 4160 4161 #undef BGE_DBG 4162 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4163 4164 static void bge_factotum_error_handler(bge_t *bgep); 4165 #pragma no_inline(bge_factotum_error_handler) 4166 4167 static void 4168 bge_factotum_error_handler(bge_t *bgep) 4169 { 4170 uint32_t flow; 4171 uint32_t rdma; 4172 uint32_t wdma; 4173 uint32_t tmac; 4174 uint32_t rmac; 4175 uint32_t rxrs; 4176 uint32_t txrs = 0; 4177 4178 ASSERT(mutex_owned(bgep->genlock)); 4179 4180 /* 4181 * Read all the registers that show the possible 4182 * reasons for the ERROR bit to be asserted 4183 */ 4184 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4185 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4186 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4187 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4188 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4189 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4190 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4191 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4192 4193 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4194 (void *)bgep, flow, rdma, wdma)); 4195 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4196 (void *)bgep, tmac, rmac, rxrs, txrs)); 4197 4198 /* 4199 * For now, just clear all the errors ... 4200 */ 4201 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4202 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4203 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4204 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4205 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4206 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4207 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4208 } 4209 4210 /* 4211 * Handler for hardware link state change. 4212 * 4213 * When this routine is called, the hardware link state has changed 4214 * and the new state is reflected in the param_* variables. Here 4215 * we must update the softstate and reprogram the MAC to match. 4216 */ 4217 static void bge_factotum_link_handler(bge_t *bgep); 4218 #pragma no_inline(bge_factotum_link_handler) 4219 4220 static void 4221 bge_factotum_link_handler(bge_t *bgep) 4222 { 4223 ASSERT(mutex_owned(bgep->genlock)); 4224 4225 /* 4226 * Update the s/w link_state 4227 */ 4228 if (bgep->param_link_up) 4229 bgep->link_state = LINK_STATE_UP; 4230 else 4231 bgep->link_state = LINK_STATE_DOWN; 4232 4233 /* 4234 * Reprogram the MAC modes to match 4235 */ 4236 bge_sync_mac_modes(bgep); 4237 } 4238 4239 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4240 #pragma no_inline(bge_factotum_link_check) 4241 4242 static boolean_t 4243 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4244 { 4245 boolean_t check; 4246 uint64_t flags; 4247 uint32_t tmac_status; 4248 4249 ASSERT(mutex_owned(bgep->genlock)); 4250 4251 /* 4252 * Get & clear the writable status bits in the Tx status register 4253 * (some bits are write-1-to-clear, others are just readonly). 4254 */ 4255 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4256 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4257 4258 /* 4259 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4260 */ 4261 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4262 STATUS_FLAG_LINK_CHANGED, &flags); 4263 if (*dma_state != DDI_FM_OK) 4264 return (B_FALSE); 4265 4266 /* 4267 * Clear any errors flagged in the status block ... 4268 */ 4269 if (flags & STATUS_FLAG_ERROR) 4270 bge_factotum_error_handler(bgep); 4271 4272 /* 4273 * We need to check the link status if: 4274 * the status block says there's been a link change 4275 * or there's any discrepancy between the various 4276 * flags indicating the link state (link_state, 4277 * param_link_up, and the LINK STATE bit in the 4278 * Transmit MAC status register). 4279 */ 4280 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4281 switch (bgep->link_state) { 4282 case LINK_STATE_UP: 4283 check |= (bgep->param_link_up == B_FALSE); 4284 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4285 break; 4286 4287 case LINK_STATE_DOWN: 4288 check |= (bgep->param_link_up != B_FALSE); 4289 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4290 break; 4291 4292 default: 4293 check = B_TRUE; 4294 break; 4295 } 4296 4297 /* 4298 * If <check> is false, we're sure the link hasn't changed. 4299 * If true, however, it's not yet definitive; we have to call 4300 * bge_phys_check() to determine whether the link has settled 4301 * into a new state yet ... and if it has, then call the link 4302 * state change handler.But when the chip is 5700 in Dell 6650 4303 * ,even if check is false, the link may have changed.So we 4304 * have to call bge_phys_check() to determine the link state. 4305 */ 4306 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4307 check = bge_phys_check(bgep); 4308 if (check) 4309 bge_factotum_link_handler(bgep); 4310 } 4311 4312 return (check); 4313 } 4314 4315 /* 4316 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4317 */ 4318 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4319 #pragma no_inline(bge_factotum_stall_check) 4320 4321 static boolean_t 4322 bge_factotum_stall_check(bge_t *bgep) 4323 { 4324 uint32_t dogval; 4325 4326 ASSERT(mutex_owned(bgep->genlock)); 4327 4328 /* 4329 * Specific check for Tx stall ... 4330 * 4331 * The 'watchdog' counter is incremented whenever a packet 4332 * is queued, reset to 1 when some (but not all) buffers 4333 * are reclaimed, reset to 0 (disabled) when all buffers 4334 * are reclaimed, and shifted left here. If it exceeds the 4335 * threshold value, the chip is assumed to have stalled and 4336 * is put into the ERROR state. The factotum will then reset 4337 * it on the next pass. 4338 * 4339 * All of which should ensure that we don't get into a state 4340 * where packets are left pending indefinitely! 4341 */ 4342 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4343 if (dogval < bge_watchdog_count) 4344 return (B_FALSE); 4345 4346 #if !defined(BGE_NETCONSOLE) 4347 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4348 #endif 4349 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4350 return (B_TRUE); 4351 } 4352 4353 /* 4354 * The factotum is woken up when there's something to do that we'd rather 4355 * not do from inside a hardware interrupt handler or high-level cyclic. 4356 * Its two main tasks are: 4357 * reset & restart the chip after an error 4358 * check the link status whenever necessary 4359 */ 4360 uint_t bge_chip_factotum(caddr_t arg); 4361 #pragma no_inline(bge_chip_factotum) 4362 4363 uint_t 4364 bge_chip_factotum(caddr_t arg) 4365 { 4366 bge_t *bgep; 4367 uint_t result; 4368 boolean_t error; 4369 boolean_t linkchg; 4370 int dma_state; 4371 4372 bgep = (bge_t *)arg; 4373 4374 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4375 4376 mutex_enter(bgep->softintrlock); 4377 if (bgep->factotum_flag == 0) { 4378 mutex_exit(bgep->softintrlock); 4379 return (DDI_INTR_UNCLAIMED); 4380 } 4381 bgep->factotum_flag = 0; 4382 mutex_exit(bgep->softintrlock); 4383 4384 result = DDI_INTR_CLAIMED; 4385 error = B_FALSE; 4386 linkchg = B_FALSE; 4387 4388 mutex_enter(bgep->genlock); 4389 switch (bgep->bge_chip_state) { 4390 default: 4391 break; 4392 4393 case BGE_CHIP_RUNNING: 4394 linkchg = bge_factotum_link_check(bgep, &dma_state); 4395 error = bge_factotum_stall_check(bgep); 4396 if (dma_state != DDI_FM_OK) { 4397 bgep->bge_dma_error = B_TRUE; 4398 error = B_TRUE; 4399 } 4400 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4401 error = B_TRUE; 4402 if (error) 4403 bgep->bge_chip_state = BGE_CHIP_ERROR; 4404 break; 4405 4406 case BGE_CHIP_ERROR: 4407 error = B_TRUE; 4408 break; 4409 4410 case BGE_CHIP_FAULT: 4411 /* 4412 * Fault detected, time to reset ... 4413 */ 4414 if (bge_autorecover) { 4415 if (!(bgep->progress & PROGRESS_BUFS)) { 4416 /* 4417 * if we can't allocate the ring buffers, 4418 * try later 4419 */ 4420 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4421 mutex_exit(bgep->genlock); 4422 return (result); 4423 } 4424 bgep->progress |= PROGRESS_BUFS; 4425 } 4426 if (!(bgep->progress & PROGRESS_INTR)) { 4427 bge_init_rings(bgep); 4428 bge_intr_enable(bgep); 4429 bgep->progress |= PROGRESS_INTR; 4430 } 4431 if (!(bgep->progress & PROGRESS_KSTATS)) { 4432 bge_init_kstats(bgep, 4433 ddi_get_instance(bgep->devinfo)); 4434 bgep->progress |= PROGRESS_KSTATS; 4435 } 4436 4437 BGE_REPORT((bgep, "automatic recovery activated")); 4438 4439 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4440 bgep->bge_chip_state = BGE_CHIP_ERROR; 4441 error = B_TRUE; 4442 } 4443 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4444 DDI_FM_OK) { 4445 bgep->bge_chip_state = BGE_CHIP_ERROR; 4446 error = B_TRUE; 4447 } 4448 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4449 DDI_FM_OK) { 4450 bgep->bge_chip_state = BGE_CHIP_ERROR; 4451 error = B_TRUE; 4452 } 4453 if (error == B_FALSE) { 4454 #ifdef BGE_IPMI_ASF 4455 if (bgep->asf_enabled && 4456 bgep->asf_status != ASF_STAT_RUN) { 4457 bgep->asf_timeout_id = timeout( 4458 bge_asf_heartbeat, (void *)bgep, 4459 drv_usectohz( 4460 BGE_ASF_HEARTBEAT_INTERVAL)); 4461 bgep->asf_status = ASF_STAT_RUN; 4462 } 4463 #endif 4464 if (!bgep->manual_reset) { 4465 ddi_fm_service_impact(bgep->devinfo, 4466 DDI_SERVICE_RESTORED); 4467 } 4468 } 4469 } 4470 break; 4471 } 4472 4473 4474 /* 4475 * If an error is detected, stop the chip now, marking it as 4476 * faulty, so that it will be reset next time through ... 4477 * 4478 * Note that if intr_running is set, then bge_intr() has dropped 4479 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4480 * this point so have to wait until the next time the factotum runs. 4481 */ 4482 if (error && !bgep->bge_intr_running) { 4483 #ifdef BGE_IPMI_ASF 4484 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4485 /* 4486 * We must stop ASF heart beat before bge_chip_stop(), 4487 * otherwise some computers (ex. IBM HS20 blade server) 4488 * may crash. 4489 */ 4490 bge_asf_update_status(bgep); 4491 bge_asf_stop_timer(bgep); 4492 bgep->asf_status = ASF_STAT_STOP; 4493 4494 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4495 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4496 } 4497 #endif 4498 bge_chip_stop(bgep, B_TRUE); 4499 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4500 } 4501 mutex_exit(bgep->genlock); 4502 4503 /* 4504 * If the link state changed, tell the world about it. 4505 * Note: can't do this while still holding the mutex. 4506 */ 4507 if (linkchg) 4508 mac_link_update(bgep->mh, bgep->link_state); 4509 if (bgep->manual_reset) { 4510 bgep->manual_reset = B_FALSE; 4511 } 4512 4513 return (result); 4514 } 4515 4516 /* 4517 * High-level cyclic handler 4518 * 4519 * This routine schedules a (low-level) softint callback to the 4520 * factotum, and prods the chip to update the status block (which 4521 * will cause a hardware interrupt when complete). 4522 */ 4523 void bge_chip_cyclic(void *arg); 4524 #pragma no_inline(bge_chip_cyclic) 4525 4526 void 4527 bge_chip_cyclic(void *arg) 4528 { 4529 bge_t *bgep; 4530 4531 bgep = arg; 4532 4533 switch (bgep->bge_chip_state) { 4534 default: 4535 return; 4536 4537 case BGE_CHIP_RUNNING: 4538 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4539 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4540 ddi_fm_service_impact(bgep->devinfo, 4541 DDI_SERVICE_UNAFFECTED); 4542 break; 4543 4544 case BGE_CHIP_FAULT: 4545 case BGE_CHIP_ERROR: 4546 break; 4547 } 4548 4549 bge_wake_factotum(bgep); 4550 } 4551 4552 4553 /* 4554 * ========== Ioctl subfunctions ========== 4555 */ 4556 4557 #undef BGE_DBG 4558 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4559 4560 #if BGE_DEBUGGING || BGE_DO_PPIO 4561 4562 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4563 #pragma no_inline(bge_chip_peek_cfg) 4564 4565 static void 4566 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4567 { 4568 uint64_t regval; 4569 uint64_t regno; 4570 4571 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4572 (void *)bgep, (void *)ppd)); 4573 4574 regno = ppd->pp_acc_offset; 4575 4576 switch (ppd->pp_acc_size) { 4577 case 1: 4578 regval = pci_config_get8(bgep->cfg_handle, regno); 4579 break; 4580 4581 case 2: 4582 regval = pci_config_get16(bgep->cfg_handle, regno); 4583 break; 4584 4585 case 4: 4586 regval = pci_config_get32(bgep->cfg_handle, regno); 4587 break; 4588 4589 case 8: 4590 regval = pci_config_get64(bgep->cfg_handle, regno); 4591 break; 4592 } 4593 4594 ppd->pp_acc_data = regval; 4595 } 4596 4597 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4598 #pragma no_inline(bge_chip_poke_cfg) 4599 4600 static void 4601 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4602 { 4603 uint64_t regval; 4604 uint64_t regno; 4605 4606 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4607 (void *)bgep, (void *)ppd)); 4608 4609 regno = ppd->pp_acc_offset; 4610 regval = ppd->pp_acc_data; 4611 4612 switch (ppd->pp_acc_size) { 4613 case 1: 4614 pci_config_put8(bgep->cfg_handle, regno, regval); 4615 break; 4616 4617 case 2: 4618 pci_config_put16(bgep->cfg_handle, regno, regval); 4619 break; 4620 4621 case 4: 4622 pci_config_put32(bgep->cfg_handle, regno, regval); 4623 break; 4624 4625 case 8: 4626 pci_config_put64(bgep->cfg_handle, regno, regval); 4627 break; 4628 } 4629 } 4630 4631 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4632 #pragma no_inline(bge_chip_peek_reg) 4633 4634 static void 4635 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4636 { 4637 uint64_t regval; 4638 void *regaddr; 4639 4640 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4641 (void *)bgep, (void *)ppd)); 4642 4643 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4644 4645 switch (ppd->pp_acc_size) { 4646 case 1: 4647 regval = ddi_get8(bgep->io_handle, regaddr); 4648 break; 4649 4650 case 2: 4651 regval = ddi_get16(bgep->io_handle, regaddr); 4652 break; 4653 4654 case 4: 4655 regval = ddi_get32(bgep->io_handle, regaddr); 4656 break; 4657 4658 case 8: 4659 regval = ddi_get64(bgep->io_handle, regaddr); 4660 break; 4661 } 4662 4663 ppd->pp_acc_data = regval; 4664 } 4665 4666 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4667 #pragma no_inline(bge_chip_peek_reg) 4668 4669 static void 4670 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4671 { 4672 uint64_t regval; 4673 void *regaddr; 4674 4675 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4676 (void *)bgep, (void *)ppd)); 4677 4678 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4679 regval = ppd->pp_acc_data; 4680 4681 switch (ppd->pp_acc_size) { 4682 case 1: 4683 ddi_put8(bgep->io_handle, regaddr, regval); 4684 break; 4685 4686 case 2: 4687 ddi_put16(bgep->io_handle, regaddr, regval); 4688 break; 4689 4690 case 4: 4691 ddi_put32(bgep->io_handle, regaddr, regval); 4692 break; 4693 4694 case 8: 4695 ddi_put64(bgep->io_handle, regaddr, regval); 4696 break; 4697 } 4698 BGE_PCICHK(bgep); 4699 } 4700 4701 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4702 #pragma no_inline(bge_chip_peek_nic) 4703 4704 static void 4705 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4706 { 4707 uint64_t regoff; 4708 uint64_t regval; 4709 void *regaddr; 4710 4711 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4712 (void *)bgep, (void *)ppd)); 4713 4714 regoff = ppd->pp_acc_offset; 4715 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4716 regoff &= MWBAR_GRANULE_MASK; 4717 regoff += NIC_MEM_WINDOW_OFFSET; 4718 regaddr = PIO_ADDR(bgep, regoff); 4719 4720 switch (ppd->pp_acc_size) { 4721 case 1: 4722 regval = ddi_get8(bgep->io_handle, regaddr); 4723 break; 4724 4725 case 2: 4726 regval = ddi_get16(bgep->io_handle, regaddr); 4727 break; 4728 4729 case 4: 4730 regval = ddi_get32(bgep->io_handle, regaddr); 4731 break; 4732 4733 case 8: 4734 regval = ddi_get64(bgep->io_handle, regaddr); 4735 break; 4736 } 4737 4738 ppd->pp_acc_data = regval; 4739 } 4740 4741 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4742 #pragma no_inline(bge_chip_poke_nic) 4743 4744 static void 4745 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4746 { 4747 uint64_t regoff; 4748 uint64_t regval; 4749 void *regaddr; 4750 4751 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4752 (void *)bgep, (void *)ppd)); 4753 4754 regoff = ppd->pp_acc_offset; 4755 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4756 regoff &= MWBAR_GRANULE_MASK; 4757 regoff += NIC_MEM_WINDOW_OFFSET; 4758 regaddr = PIO_ADDR(bgep, regoff); 4759 regval = ppd->pp_acc_data; 4760 4761 switch (ppd->pp_acc_size) { 4762 case 1: 4763 ddi_put8(bgep->io_handle, regaddr, regval); 4764 break; 4765 4766 case 2: 4767 ddi_put16(bgep->io_handle, regaddr, regval); 4768 break; 4769 4770 case 4: 4771 ddi_put32(bgep->io_handle, regaddr, regval); 4772 break; 4773 4774 case 8: 4775 ddi_put64(bgep->io_handle, regaddr, regval); 4776 break; 4777 } 4778 BGE_PCICHK(bgep); 4779 } 4780 4781 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4782 #pragma no_inline(bge_chip_peek_mii) 4783 4784 static void 4785 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4786 { 4787 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4788 (void *)bgep, (void *)ppd)); 4789 4790 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4791 } 4792 4793 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4794 #pragma no_inline(bge_chip_poke_mii) 4795 4796 static void 4797 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4798 { 4799 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4800 (void *)bgep, (void *)ppd)); 4801 4802 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4803 } 4804 4805 #if BGE_SEE_IO32 4806 4807 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4808 #pragma no_inline(bge_chip_peek_seeprom) 4809 4810 static void 4811 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4812 { 4813 uint32_t data; 4814 int err; 4815 4816 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4817 (void *)bgep, (void *)ppd)); 4818 4819 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4820 ppd->pp_acc_data = err ? ~0ull : data; 4821 } 4822 4823 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4824 #pragma no_inline(bge_chip_poke_seeprom) 4825 4826 static void 4827 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4828 { 4829 uint32_t data; 4830 4831 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4832 (void *)bgep, (void *)ppd)); 4833 4834 data = ppd->pp_acc_data; 4835 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4836 } 4837 #endif /* BGE_SEE_IO32 */ 4838 4839 #if BGE_FLASH_IO32 4840 4841 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4842 #pragma no_inline(bge_chip_peek_flash) 4843 4844 static void 4845 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4846 { 4847 uint32_t data; 4848 int err; 4849 4850 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4851 (void *)bgep, (void *)ppd)); 4852 4853 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4854 ppd->pp_acc_data = err ? ~0ull : data; 4855 } 4856 4857 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4858 #pragma no_inline(bge_chip_poke_flash) 4859 4860 static void 4861 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4862 { 4863 uint32_t data; 4864 4865 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4866 (void *)bgep, (void *)ppd)); 4867 4868 data = ppd->pp_acc_data; 4869 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4870 ppd->pp_acc_offset, &data); 4871 } 4872 #endif /* BGE_FLASH_IO32 */ 4873 4874 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4875 #pragma no_inline(bge_chip_peek_mem) 4876 4877 static void 4878 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4879 { 4880 uint64_t regval; 4881 void *vaddr; 4882 4883 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4884 (void *)bgep, (void *)ppd)); 4885 4886 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4887 4888 switch (ppd->pp_acc_size) { 4889 case 1: 4890 regval = *(uint8_t *)vaddr; 4891 break; 4892 4893 case 2: 4894 regval = *(uint16_t *)vaddr; 4895 break; 4896 4897 case 4: 4898 regval = *(uint32_t *)vaddr; 4899 break; 4900 4901 case 8: 4902 regval = *(uint64_t *)vaddr; 4903 break; 4904 } 4905 4906 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4907 (void *)bgep, (void *)ppd, regval, vaddr)); 4908 4909 ppd->pp_acc_data = regval; 4910 } 4911 4912 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4913 #pragma no_inline(bge_chip_poke_mem) 4914 4915 static void 4916 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4917 { 4918 uint64_t regval; 4919 void *vaddr; 4920 4921 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4922 (void *)bgep, (void *)ppd)); 4923 4924 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4925 regval = ppd->pp_acc_data; 4926 4927 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4928 (void *)bgep, (void *)ppd, regval, vaddr)); 4929 4930 switch (ppd->pp_acc_size) { 4931 case 1: 4932 *(uint8_t *)vaddr = (uint8_t)regval; 4933 break; 4934 4935 case 2: 4936 *(uint16_t *)vaddr = (uint16_t)regval; 4937 break; 4938 4939 case 4: 4940 *(uint32_t *)vaddr = (uint32_t)regval; 4941 break; 4942 4943 case 8: 4944 *(uint64_t *)vaddr = (uint64_t)regval; 4945 break; 4946 } 4947 } 4948 4949 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4950 struct iocblk *iocp); 4951 #pragma no_inline(bge_pp_ioctl) 4952 4953 static enum ioc_reply 4954 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4955 { 4956 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4957 bge_peekpoke_t *ppd; 4958 dma_area_t *areap; 4959 uint64_t sizemask; 4960 uint64_t mem_va; 4961 uint64_t maxoff; 4962 boolean_t peek; 4963 4964 switch (cmd) { 4965 default: 4966 /* NOTREACHED */ 4967 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4968 return (IOC_INVAL); 4969 4970 case BGE_PEEK: 4971 peek = B_TRUE; 4972 break; 4973 4974 case BGE_POKE: 4975 peek = B_FALSE; 4976 break; 4977 } 4978 4979 /* 4980 * Validate format of ioctl 4981 */ 4982 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4983 return (IOC_INVAL); 4984 if (mp->b_cont == NULL) 4985 return (IOC_INVAL); 4986 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4987 4988 /* 4989 * Validate request parameters 4990 */ 4991 switch (ppd->pp_acc_space) { 4992 default: 4993 return (IOC_INVAL); 4994 4995 case BGE_PP_SPACE_CFG: 4996 /* 4997 * Config space 4998 */ 4999 sizemask = 8|4|2|1; 5000 mem_va = 0; 5001 maxoff = PCI_CONF_HDR_SIZE; 5002 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5003 break; 5004 5005 case BGE_PP_SPACE_REG: 5006 /* 5007 * Memory-mapped I/O space 5008 */ 5009 sizemask = 8|4|2|1; 5010 mem_va = 0; 5011 maxoff = RIAAR_REGISTER_MAX; 5012 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5013 break; 5014 5015 case BGE_PP_SPACE_NIC: 5016 /* 5017 * NIC on-chip memory 5018 */ 5019 sizemask = 8|4|2|1; 5020 mem_va = 0; 5021 maxoff = MWBAR_ONCHIP_MAX; 5022 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5023 break; 5024 5025 case BGE_PP_SPACE_MII: 5026 /* 5027 * PHY's MII registers 5028 * NB: all PHY registers are two bytes, but the 5029 * addresses increment in ones (word addressing). 5030 * So we scale the address here, then undo the 5031 * transformation inside the peek/poke functions. 5032 */ 5033 ppd->pp_acc_offset *= 2; 5034 sizemask = 2; 5035 mem_va = 0; 5036 maxoff = (MII_MAXREG+1)*2; 5037 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5038 break; 5039 5040 #if BGE_SEE_IO32 5041 case BGE_PP_SPACE_SEEPROM: 5042 /* 5043 * Attached SEEPROM(s), if any. 5044 * NB: we use the high-order bits of the 'address' as 5045 * a device select to accommodate multiple SEEPROMS, 5046 * If each one is the maximum size (64kbytes), this 5047 * makes them appear contiguous. Otherwise, there may 5048 * be holes in the mapping. ENxS doesn't have any 5049 * SEEPROMs anyway ... 5050 */ 5051 sizemask = 4; 5052 mem_va = 0; 5053 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5054 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5055 break; 5056 #endif /* BGE_SEE_IO32 */ 5057 5058 #if BGE_FLASH_IO32 5059 case BGE_PP_SPACE_FLASH: 5060 /* 5061 * Attached Flash device (if any); a maximum of one device 5062 * is currently supported. But it can be up to 1MB (unlike 5063 * the 64k limit on SEEPROMs) so why would you need more ;-) 5064 */ 5065 sizemask = 4; 5066 mem_va = 0; 5067 maxoff = NVM_FLASH_ADDR_MASK; 5068 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5069 break; 5070 #endif /* BGE_FLASH_IO32 */ 5071 5072 case BGE_PP_SPACE_BGE: 5073 /* 5074 * BGE data structure! 5075 */ 5076 sizemask = 8|4|2|1; 5077 mem_va = (uintptr_t)bgep; 5078 maxoff = sizeof (*bgep); 5079 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5080 break; 5081 5082 case BGE_PP_SPACE_STATUS: 5083 case BGE_PP_SPACE_STATISTICS: 5084 case BGE_PP_SPACE_TXDESC: 5085 case BGE_PP_SPACE_TXBUFF: 5086 case BGE_PP_SPACE_RXDESC: 5087 case BGE_PP_SPACE_RXBUFF: 5088 /* 5089 * Various DMA_AREAs 5090 */ 5091 switch (ppd->pp_acc_space) { 5092 case BGE_PP_SPACE_TXDESC: 5093 areap = &bgep->tx_desc; 5094 break; 5095 case BGE_PP_SPACE_TXBUFF: 5096 areap = &bgep->tx_buff[0]; 5097 break; 5098 case BGE_PP_SPACE_RXDESC: 5099 areap = &bgep->rx_desc[0]; 5100 break; 5101 case BGE_PP_SPACE_RXBUFF: 5102 areap = &bgep->rx_buff[0]; 5103 break; 5104 case BGE_PP_SPACE_STATUS: 5105 areap = &bgep->status_block; 5106 break; 5107 case BGE_PP_SPACE_STATISTICS: 5108 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5109 areap = &bgep->statistics; 5110 break; 5111 } 5112 5113 sizemask = 8|4|2|1; 5114 mem_va = (uintptr_t)areap->mem_va; 5115 maxoff = areap->alength; 5116 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5117 break; 5118 } 5119 5120 switch (ppd->pp_acc_size) { 5121 default: 5122 return (IOC_INVAL); 5123 5124 case 8: 5125 case 4: 5126 case 2: 5127 case 1: 5128 if ((ppd->pp_acc_size & sizemask) == 0) 5129 return (IOC_INVAL); 5130 break; 5131 } 5132 5133 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5134 return (IOC_INVAL); 5135 5136 if (ppd->pp_acc_offset >= maxoff) 5137 return (IOC_INVAL); 5138 5139 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5140 return (IOC_INVAL); 5141 5142 /* 5143 * All OK - go do it! 5144 */ 5145 ppd->pp_acc_offset += mem_va; 5146 (*ppfn)(bgep, ppd); 5147 return (peek ? IOC_REPLY : IOC_ACK); 5148 } 5149 5150 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5151 struct iocblk *iocp); 5152 #pragma no_inline(bge_diag_ioctl) 5153 5154 static enum ioc_reply 5155 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5156 { 5157 ASSERT(mutex_owned(bgep->genlock)); 5158 5159 switch (cmd) { 5160 default: 5161 /* NOTREACHED */ 5162 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5163 return (IOC_INVAL); 5164 5165 case BGE_DIAG: 5166 /* 5167 * Currently a no-op 5168 */ 5169 return (IOC_ACK); 5170 5171 case BGE_PEEK: 5172 case BGE_POKE: 5173 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5174 5175 case BGE_PHY_RESET: 5176 return (IOC_RESTART_ACK); 5177 5178 case BGE_SOFT_RESET: 5179 case BGE_HARD_RESET: 5180 /* 5181 * Reset and reinitialise the 570x hardware 5182 */ 5183 bgep->bge_chip_state = BGE_CHIP_FAULT; 5184 ddi_trigger_softintr(bgep->factotum_id); 5185 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5186 return (IOC_ACK); 5187 } 5188 5189 /* NOTREACHED */ 5190 } 5191 5192 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5193 5194 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5195 struct iocblk *iocp); 5196 #pragma no_inline(bge_mii_ioctl) 5197 5198 static enum ioc_reply 5199 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5200 { 5201 struct bge_mii_rw *miirwp; 5202 5203 /* 5204 * Validate format of ioctl 5205 */ 5206 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5207 return (IOC_INVAL); 5208 if (mp->b_cont == NULL) 5209 return (IOC_INVAL); 5210 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5211 5212 /* 5213 * Validate request parameters ... 5214 */ 5215 if (miirwp->mii_reg > MII_MAXREG) 5216 return (IOC_INVAL); 5217 5218 switch (cmd) { 5219 default: 5220 /* NOTREACHED */ 5221 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5222 return (IOC_INVAL); 5223 5224 case BGE_MII_READ: 5225 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5226 return (IOC_REPLY); 5227 5228 case BGE_MII_WRITE: 5229 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5230 return (IOC_ACK); 5231 } 5232 5233 /* NOTREACHED */ 5234 } 5235 5236 #if BGE_SEE_IO32 5237 5238 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5239 struct iocblk *iocp); 5240 #pragma no_inline(bge_see_ioctl) 5241 5242 static enum ioc_reply 5243 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5244 { 5245 struct bge_see_rw *seerwp; 5246 5247 /* 5248 * Validate format of ioctl 5249 */ 5250 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5251 return (IOC_INVAL); 5252 if (mp->b_cont == NULL) 5253 return (IOC_INVAL); 5254 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5255 5256 /* 5257 * Validate request parameters ... 5258 */ 5259 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5260 return (IOC_INVAL); 5261 5262 switch (cmd) { 5263 default: 5264 /* NOTREACHED */ 5265 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5266 return (IOC_INVAL); 5267 5268 case BGE_SEE_READ: 5269 case BGE_SEE_WRITE: 5270 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5271 seerwp->see_addr, &seerwp->see_data); 5272 return (IOC_REPLY); 5273 } 5274 5275 /* NOTREACHED */ 5276 } 5277 5278 #endif /* BGE_SEE_IO32 */ 5279 5280 #if BGE_FLASH_IO32 5281 5282 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5283 struct iocblk *iocp); 5284 #pragma no_inline(bge_flash_ioctl) 5285 5286 static enum ioc_reply 5287 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5288 { 5289 struct bge_flash_rw *flashrwp; 5290 5291 /* 5292 * Validate format of ioctl 5293 */ 5294 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5295 return (IOC_INVAL); 5296 if (mp->b_cont == NULL) 5297 return (IOC_INVAL); 5298 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5299 5300 /* 5301 * Validate request parameters ... 5302 */ 5303 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5304 return (IOC_INVAL); 5305 5306 switch (cmd) { 5307 default: 5308 /* NOTREACHED */ 5309 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5310 return (IOC_INVAL); 5311 5312 case BGE_FLASH_READ: 5313 case BGE_FLASH_WRITE: 5314 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5315 flashrwp->flash_addr, &flashrwp->flash_data); 5316 return (IOC_REPLY); 5317 } 5318 5319 /* NOTREACHED */ 5320 } 5321 5322 #endif /* BGE_FLASH_IO32 */ 5323 5324 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5325 struct iocblk *iocp); 5326 #pragma no_inline(bge_chip_ioctl) 5327 5328 enum ioc_reply 5329 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5330 { 5331 int cmd; 5332 5333 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5334 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5335 5336 ASSERT(mutex_owned(bgep->genlock)); 5337 5338 cmd = iocp->ioc_cmd; 5339 switch (cmd) { 5340 default: 5341 /* NOTREACHED */ 5342 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5343 return (IOC_INVAL); 5344 5345 case BGE_DIAG: 5346 case BGE_PEEK: 5347 case BGE_POKE: 5348 case BGE_PHY_RESET: 5349 case BGE_SOFT_RESET: 5350 case BGE_HARD_RESET: 5351 #if BGE_DEBUGGING || BGE_DO_PPIO 5352 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5353 #else 5354 return (IOC_INVAL); 5355 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5356 5357 case BGE_MII_READ: 5358 case BGE_MII_WRITE: 5359 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5360 5361 #if BGE_SEE_IO32 5362 case BGE_SEE_READ: 5363 case BGE_SEE_WRITE: 5364 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5365 #endif /* BGE_SEE_IO32 */ 5366 5367 #if BGE_FLASH_IO32 5368 case BGE_FLASH_READ: 5369 case BGE_FLASH_WRITE: 5370 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5371 #endif /* BGE_FLASH_IO32 */ 5372 } 5373 5374 /* NOTREACHED */ 5375 } 5376 5377 void 5378 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5379 { 5380 bge_t *bgep = arg; 5381 5382 mutex_enter(bgep->genlock); 5383 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5384 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5385 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5386 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5387 mutex_exit(bgep->genlock); 5388 } 5389 5390 #ifdef BGE_IPMI_ASF 5391 5392 uint32_t 5393 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5394 { 5395 uint32_t data; 5396 5397 #ifndef __sparc 5398 if (!bgep->asf_wordswapped) { 5399 /* a workaround word swap error */ 5400 if (addr & 4) 5401 addr = addr - 4; 5402 else 5403 addr = addr + 4; 5404 } 5405 #endif 5406 5407 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5408 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5409 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5410 5411 data = LE_32(data); 5412 return (data); 5413 } 5414 5415 void 5416 bge_asf_update_status(bge_t *bgep) 5417 { 5418 uint32_t event; 5419 5420 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5421 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5422 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5423 5424 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5425 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5426 } 5427 5428 5429 /* 5430 * The driver is supposed to notify ASF that the OS is still running 5431 * every three seconds, otherwise the management server may attempt 5432 * to reboot the machine. If it hasn't actually failed, this is 5433 * not a desirable result. However, this isn't running as a real-time 5434 * thread, and even if it were, it might not be able to generate the 5435 * heartbeat in a timely manner due to system load. As it isn't a 5436 * significant strain on the machine, we will set the interval to half 5437 * of the required value. 5438 */ 5439 void 5440 bge_asf_heartbeat(void *arg) 5441 { 5442 bge_t *bgep = (bge_t *)arg; 5443 5444 mutex_enter(bgep->genlock); 5445 bge_asf_update_status((bge_t *)bgep); 5446 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5447 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5448 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5449 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5450 mutex_exit(bgep->genlock); 5451 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5452 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5453 } 5454 5455 5456 void 5457 bge_asf_stop_timer(bge_t *bgep) 5458 { 5459 timeout_id_t tmp_id = 0; 5460 5461 while ((bgep->asf_timeout_id != 0) && 5462 (tmp_id != bgep->asf_timeout_id)) { 5463 tmp_id = bgep->asf_timeout_id; 5464 (void) untimeout(tmp_id); 5465 } 5466 bgep->asf_timeout_id = 0; 5467 } 5468 5469 5470 5471 /* 5472 * This function should be placed at the earliest position of bge_attach(). 5473 */ 5474 void 5475 bge_asf_get_config(bge_t *bgep) 5476 { 5477 uint32_t nicsig; 5478 uint32_t niccfg; 5479 5480 bgep->asf_enabled = B_FALSE; 5481 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5482 if (nicsig == BGE_NIC_DATA_SIG) { 5483 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5484 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5485 /* 5486 * Here, we don't consider BAXTER, because BGE haven't 5487 * supported BAXTER (that is 5752). Also, as I know, 5488 * BAXTER doesn't support ASF feature. 5489 */ 5490 bgep->asf_enabled = B_TRUE; 5491 else 5492 bgep->asf_enabled = B_FALSE; 5493 } else 5494 bgep->asf_enabled = B_FALSE; 5495 } 5496 5497 5498 void 5499 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5500 { 5501 uint32_t tries; 5502 uint32_t event; 5503 5504 ASSERT(bgep->asf_enabled); 5505 5506 /* Issues "pause firmware" command and wait for ACK */ 5507 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5508 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5509 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5510 5511 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5512 tries = 0; 5513 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5514 drv_usecwait(1); 5515 tries ++; 5516 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5517 } 5518 5519 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5520 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5521 5522 if (bgep->asf_newhandshake) { 5523 switch (mode) { 5524 case BGE_INIT_RESET: 5525 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5526 BGE_DRV_STATE_START); 5527 break; 5528 case BGE_SHUTDOWN_RESET: 5529 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5530 BGE_DRV_STATE_UNLOAD); 5531 break; 5532 case BGE_SUSPEND_RESET: 5533 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5534 BGE_DRV_STATE_SUSPEND); 5535 break; 5536 default: 5537 break; 5538 } 5539 } 5540 } 5541 5542 5543 void 5544 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5545 { 5546 switch (mode) { 5547 case BGE_INIT_RESET: 5548 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5549 BGE_DRV_STATE_START); 5550 break; 5551 case BGE_SHUTDOWN_RESET: 5552 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5553 BGE_DRV_STATE_UNLOAD); 5554 break; 5555 case BGE_SUSPEND_RESET: 5556 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5557 BGE_DRV_STATE_SUSPEND); 5558 break; 5559 default: 5560 break; 5561 } 5562 } 5563 5564 5565 void 5566 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5567 { 5568 switch (mode) { 5569 case BGE_INIT_RESET: 5570 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5571 BGE_DRV_STATE_START_DONE); 5572 break; 5573 case BGE_SHUTDOWN_RESET: 5574 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5575 BGE_DRV_STATE_UNLOAD_DONE); 5576 break; 5577 default: 5578 break; 5579 } 5580 } 5581 5582 #endif /* BGE_IPMI_ASF */ 5583