1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transaction related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (e.g. tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 */ 542 command = bgep->chipid.command | PCI_COMM_MAE; 543 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 544 if (enable_dma) 545 command |= PCI_COMM_ME; 546 /* 547 * on BCM5714 revision A0, false parity error gets generated 548 * due to a logic bug. Provide a workaround by disabling parity 549 * error. 550 */ 551 if (((cidp->device == DEVICE_ID_5714C) || 552 (cidp->device == DEVICE_ID_5714S)) && 553 (cidp->revision == REVISION_ID_5714_A0)) { 554 command &= ~PCI_COMM_PARITY_DETECT; 555 } 556 pci_config_put16(handle, PCI_CONF_COMM, command); 557 558 /* 559 * On some PCI-E device, there were instances when 560 * the device was still link training. 561 */ 562 if (bgep->chipid.pci_type == BGE_PCI_E) { 563 i = 0; 564 value16 = pci_config_get16(handle, PCI_CONF_COMM); 565 while ((value16 != command) && (i < 100)) { 566 drv_usecwait(200); 567 value16 = pci_config_get16(handle, PCI_CONF_COMM); 568 ++i; 569 } 570 } 571 572 /* 573 * Clear any remaining error status bits 574 */ 575 pci_config_put16(handle, PCI_CONF_STAT, ~0); 576 577 /* 578 * Do following if and only if the device is NOT BCM5714C OR 579 * BCM5715C 580 */ 581 if (!((cidp->device == DEVICE_ID_5714C) || 582 (cidp->device == DEVICE_ID_5715C))) { 583 /* 584 * Make sure these indirect-access registers are sane 585 * rather than random after power-up or reset 586 */ 587 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 588 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 589 } 590 /* 591 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 592 */ 593 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 594 595 if (cidp->pci_type == BGE_PCI_E) 596 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 597 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 598 } 599 600 #ifdef __amd64 601 /* 602 * Distinguish CPU types 603 * 604 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 605 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 606 * for PCI-Express based network interface card. This is the work-around 607 * for those nics. 608 */ 609 static boolean_t bge_get_em64t_type(void); 610 #pragma inline(bge_get_em64t_type) 611 612 static boolean_t 613 bge_get_em64t_type(void) 614 { 615 616 return (x86_vendor == X86_VENDOR_Intel); 617 } 618 #endif 619 620 /* 621 * Operating register get/set access routines 622 */ 623 624 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 625 #pragma inline(bge_reg_get32) 626 627 uint32_t 628 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 629 { 630 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 631 (void *)bgep, regno)); 632 633 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 634 } 635 636 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 637 #pragma inline(bge_reg_put32) 638 639 void 640 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 641 { 642 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 643 (void *)bgep, regno, data)); 644 645 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 646 BGE_PCICHK(bgep); 647 } 648 649 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 650 #pragma inline(bge_reg_set32) 651 652 void 653 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 654 { 655 uint32_t regval; 656 657 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 658 (void *)bgep, regno, bits)); 659 660 regval = bge_reg_get32(bgep, regno); 661 regval |= bits; 662 bge_reg_put32(bgep, regno, regval); 663 } 664 665 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 666 #pragma inline(bge_reg_clr32) 667 668 void 669 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 670 { 671 uint32_t regval; 672 673 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 674 (void *)bgep, regno, bits)); 675 676 regval = bge_reg_get32(bgep, regno); 677 regval &= ~bits; 678 bge_reg_put32(bgep, regno, regval); 679 } 680 681 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 682 #pragma inline(bge_reg_get64) 683 684 static uint64_t 685 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 686 { 687 uint64_t regval; 688 689 #ifdef __amd64 690 if (bge_get_em64t_type()) { 691 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 692 regval <<= 32; 693 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 } else { 695 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 696 } 697 #else 698 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 699 #endif 700 701 #ifdef _LITTLE_ENDIAN 702 regval = (regval >> 32) | (regval << 32); 703 #endif /* _LITTLE_ENDIAN */ 704 705 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 706 (void *)bgep, regno, regval)); 707 708 return (regval); 709 } 710 711 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 712 #pragma inline(bge_reg_put64) 713 714 static void 715 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 716 { 717 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 718 (void *)bgep, regno, data)); 719 720 #ifdef _LITTLE_ENDIAN 721 data = ((data >> 32) | (data << 32)); 722 #endif /* _LITTLE_ENDIAN */ 723 724 #ifdef __amd64 725 if (bge_get_em64t_type()) { 726 ddi_put32(bgep->io_handle, 727 PIO_ADDR(bgep, regno), (uint32_t)data); 728 BGE_PCICHK(bgep); 729 ddi_put32(bgep->io_handle, 730 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 731 732 } else { 733 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 734 } 735 #else 736 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 737 #endif 738 739 BGE_PCICHK(bgep); 740 } 741 742 /* 743 * The DDI doesn't provide get/put functions for 128 bit data 744 * so we put RCBs out as two 64-bit chunks instead. 745 */ 746 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 747 #pragma inline(bge_reg_putrcb) 748 749 static void 750 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 751 { 752 uint64_t *p; 753 754 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 755 (void *)bgep, addr, rcbp->host_ring_addr, 756 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 757 758 ASSERT((addr % sizeof (*rcbp)) == 0); 759 760 p = (void *)rcbp; 761 bge_reg_put64(bgep, addr, *p++); 762 bge_reg_put64(bgep, addr+8, *p); 763 } 764 765 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 766 #pragma inline(bge_mbx_put) 767 768 void 769 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 770 { 771 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 772 (void *)bgep, regno, data)); 773 774 /* 775 * Mailbox registers are nominally 64 bits on the 5701, but 776 * the MSW isn't used. On the 5703, they're only 32 bits 777 * anyway. So here we just write the lower(!) 32 bits - 778 * remembering that the chip is big-endian, even though the 779 * PCI bus is little-endian ... 780 */ 781 #ifdef _BIG_ENDIAN 782 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 783 #else 784 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 785 #endif /* _BIG_ENDIAN */ 786 BGE_PCICHK(bgep); 787 } 788 789 #if BGE_DEBUGGING 790 791 void bge_led_mark(bge_t *bgep); 792 #pragma no_inline(bge_led_mark) 793 794 void 795 bge_led_mark(bge_t *bgep) 796 { 797 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 798 LED_CONTROL_1000MBPS_LED | 799 LED_CONTROL_100MBPS_LED | 800 LED_CONTROL_10MBPS_LED; 801 802 /* 803 * Blink all three LINK LEDs on simultaneously, then all off, 804 * then restore to automatic hardware control. This is used 805 * in laboratory testing to trigger a logic analyser or scope. 806 */ 807 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 808 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 809 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 810 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 811 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 812 } 813 814 #endif /* BGE_DEBUGGING */ 815 816 /* 817 * NIC on-chip memory access routines 818 * 819 * Only 32K of NIC memory is visible at a time, controlled by the 820 * Memory Window Base Address Register (in PCI config space). Once 821 * this is set, the 32K region of NIC-local memory that it refers 822 * to can be directly addressed in the upper 32K of the 64K of PCI 823 * memory space used for the device. 824 */ 825 826 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 827 #pragma inline(bge_nic_setwin) 828 829 static void 830 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 831 { 832 chip_id_t *cidp; 833 834 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 835 (void *)bgep, base)); 836 837 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 838 839 /* 840 * Don't do repeated zero data writes, 841 * if the device is BCM5714C/15C. 842 */ 843 cidp = &bgep->chipid; 844 if ((cidp->device == DEVICE_ID_5714C) || 845 (cidp->device == DEVICE_ID_5715C)) { 846 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 847 return; 848 /* Adjust lastWriteZeroData */ 849 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 850 B_TRUE : B_FALSE); 851 } 852 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 853 } 854 855 856 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 857 #pragma inline(bge_nic_get32) 858 859 static uint32_t 860 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 861 { 862 uint32_t data; 863 864 #ifdef BGE_IPMI_ASF 865 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 866 /* workaround for word swap error */ 867 if (addr & 4) 868 addr = addr - 4; 869 else 870 addr = addr + 4; 871 } 872 #endif 873 874 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 875 addr &= MWBAR_GRANULE_MASK; 876 addr += NIC_MEM_WINDOW_OFFSET; 877 878 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 879 880 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 881 (void *)bgep, addr, data)); 882 883 return (data); 884 } 885 886 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 887 #pragma inline(bge_nic_put32) 888 889 void 890 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 891 { 892 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 893 (void *)bgep, addr, data)); 894 895 #ifdef BGE_IPMI_ASF 896 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 897 /* workaround for word swap error */ 898 if (addr & 4) 899 addr = addr - 4; 900 else 901 addr = addr + 4; 902 } 903 #endif 904 905 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 906 addr &= MWBAR_GRANULE_MASK; 907 addr += NIC_MEM_WINDOW_OFFSET; 908 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 909 BGE_PCICHK(bgep); 910 } 911 912 913 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 914 #pragma inline(bge_nic_get64) 915 916 static uint64_t 917 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 918 { 919 uint64_t data; 920 921 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 922 addr &= MWBAR_GRANULE_MASK; 923 addr += NIC_MEM_WINDOW_OFFSET; 924 925 #ifdef __amd64 926 if (bge_get_em64t_type()) { 927 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 928 data <<= 32; 929 data |= ddi_get32(bgep->io_handle, 930 PIO_ADDR(bgep, addr + 4)); 931 } else { 932 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 933 } 934 #else 935 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 936 #endif 937 938 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 939 (void *)bgep, addr, data)); 940 941 return (data); 942 } 943 944 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 945 #pragma inline(bge_nic_put64) 946 947 static void 948 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 949 { 950 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 951 (void *)bgep, addr, data)); 952 953 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 954 addr &= MWBAR_GRANULE_MASK; 955 addr += NIC_MEM_WINDOW_OFFSET; 956 957 #ifdef __amd64 958 if (bge_get_em64t_type()) { 959 ddi_put32(bgep->io_handle, 960 PIO_ADDR(bgep, addr), (uint32_t)data); 961 BGE_PCICHK(bgep); 962 ddi_put32(bgep->io_handle, 963 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 966 } 967 #else 968 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 969 #endif 970 971 BGE_PCICHK(bgep); 972 } 973 974 /* 975 * The DDI doesn't provide get/put functions for 128 bit data 976 * so we put RCBs out as two 64-bit chunks instead. 977 */ 978 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 979 #pragma inline(bge_nic_putrcb) 980 981 static void 982 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 983 { 984 uint64_t *p; 985 986 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 987 (void *)bgep, addr, rcbp->host_ring_addr, 988 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 989 990 ASSERT((addr % sizeof (*rcbp)) == 0); 991 992 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 993 addr &= MWBAR_GRANULE_MASK; 994 addr += NIC_MEM_WINDOW_OFFSET; 995 996 p = (void *)rcbp; 997 #ifdef __amd64 998 if (bge_get_em64t_type()) { 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1000 (uint32_t)(*p)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1002 (uint32_t)(*p >> 32)); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1004 (uint32_t)(*(p + 1))); 1005 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1006 (uint32_t)(*p >> 32)); 1007 1008 } else { 1009 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1010 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1011 } 1012 #else 1013 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1014 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1015 #endif 1016 1017 BGE_PCICHK(bgep); 1018 } 1019 1020 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1021 #pragma inline(bge_nic_zero) 1022 1023 static void 1024 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1025 { 1026 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1027 (void *)bgep, addr, nbytes)); 1028 1029 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1030 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1031 1032 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1033 addr &= MWBAR_GRANULE_MASK; 1034 addr += NIC_MEM_WINDOW_OFFSET; 1035 1036 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1037 nbytes, 1, DDI_DATA_SZ08_ACC); 1038 BGE_PCICHK(bgep); 1039 } 1040 1041 /* 1042 * MII (PHY) register get/set access routines 1043 * 1044 * These use the chip's MII auto-access method, controlled by the 1045 * MII Communication register at 0x044c, so the CPU doesn't have 1046 * to fiddle with the individual bits. 1047 */ 1048 1049 #undef BGE_DBG 1050 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1051 1052 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1053 uint16_t data, uint32_t cmd); 1054 #pragma no_inline(bge_mii_access) 1055 1056 static uint16_t 1057 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1058 { 1059 uint32_t timeout; 1060 uint32_t regval1; 1061 uint32_t regval2; 1062 1063 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1064 (void *)bgep, regno, data, cmd)); 1065 1066 ASSERT(mutex_owned(bgep->genlock)); 1067 1068 /* 1069 * Assemble the command ... 1070 */ 1071 cmd |= data << MI_COMMS_DATA_SHIFT; 1072 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1073 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1074 cmd |= MI_COMMS_START; 1075 1076 /* 1077 * Wait for any command already in progress ... 1078 * 1079 * Note: this *shouldn't* ever find that there is a command 1080 * in progress, because we already hold the <genlock> mutex. 1081 * Nonetheless, we have sometimes seen the MI_COMMS_START 1082 * bit set here -- it seems that the chip can initiate MII 1083 * accesses internally, even with polling OFF. 1084 */ 1085 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1086 for (timeout = 100; ; ) { 1087 if ((regval2 & MI_COMMS_START) == 0) { 1088 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1089 break; 1090 } 1091 if (--timeout == 0) 1092 break; 1093 drv_usecwait(10); 1094 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1095 } 1096 1097 if (timeout == 0) 1098 return ((uint16_t)~0u); 1099 1100 if (timeout != 100) 1101 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1102 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1103 cmd, 10*(100-timeout), regval1, regval2)); 1104 1105 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1106 for (timeout = 1000; ; ) { 1107 if ((regval1 & MI_COMMS_START) == 0) 1108 break; 1109 if (--timeout == 0) 1110 break; 1111 drv_usecwait(10); 1112 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1113 } 1114 1115 /* 1116 * Drop out early if the READ FAILED bit is set -- this chip 1117 * could be a 5703/4S, with a SerDes instead of a PHY! 1118 */ 1119 if (regval2 & MI_COMMS_READ_FAILED) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout == 0) 1123 return ((uint16_t)~0u); 1124 1125 /* 1126 * The PRM says to wait 5us after seeing the START bit clear 1127 * and then re-read the register to get the final value of the 1128 * data field, in order to avoid a race condition where the 1129 * START bit is clear but the data field isn't yet valid. 1130 * 1131 * Note: we don't actually seem to be encounter this race; 1132 * except when the START bit is seen set again (see below), 1133 * the data field doesn't change during this 5us interval. 1134 */ 1135 drv_usecwait(5); 1136 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1137 1138 /* 1139 * Unfortunately, when following the PRMs instructions above, 1140 * we have occasionally seen the START bit set again(!) in the 1141 * value read after the 5us delay. This seems to be due to the 1142 * chip autonomously starting another MII access internally. 1143 * In such cases, the command/data/etc fields relate to the 1144 * internal command, rather than the one that we thought had 1145 * just finished. So in this case, we fall back to returning 1146 * the data from the original read that showed START clear. 1147 */ 1148 if (regval2 & MI_COMMS_START) { 1149 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1150 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1151 cmd, regval1, regval2)); 1152 regval2 = regval1; 1153 } 1154 1155 if (regval2 & MI_COMMS_START) 1156 return ((uint16_t)~0u); 1157 1158 if (regval2 & MI_COMMS_READ_FAILED) 1159 return ((uint16_t)~0u); 1160 1161 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1162 } 1163 1164 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1165 #pragma no_inline(bge_mii_get16) 1166 1167 uint16_t 1168 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1169 { 1170 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1171 (void *)bgep, regno)); 1172 1173 ASSERT(mutex_owned(bgep->genlock)); 1174 1175 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1176 } 1177 1178 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1179 #pragma no_inline(bge_mii_put16) 1180 1181 void 1182 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1183 { 1184 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1185 (void *)bgep, regno, data)); 1186 1187 ASSERT(mutex_owned(bgep->genlock)); 1188 1189 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1190 } 1191 1192 #undef BGE_DBG 1193 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1194 1195 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1196 1197 /* 1198 * Basic SEEPROM get/set access routine 1199 * 1200 * This uses the chip's SEEPROM auto-access method, controlled by the 1201 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1202 * doesn't have to fiddle with the individual bits. 1203 * 1204 * The caller should hold <genlock> and *also* have already acquired 1205 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1206 * 1207 * Return value: 1208 * 0 on success, 1209 * ENODATA on access timeout (maybe retryable: device may just be busy) 1210 * EPROTO on other h/w or s/w errors. 1211 * 1212 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1213 * from a (successful) SEEPROM_ACCESS_READ. 1214 */ 1215 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1216 uint32_t *dp); 1217 #pragma no_inline(bge_seeprom_access) 1218 1219 static int 1220 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1221 { 1222 uint32_t tries; 1223 uint32_t regval; 1224 1225 ASSERT(mutex_owned(bgep->genlock)); 1226 1227 /* 1228 * On the newer chips that support both SEEPROM & Flash, we need 1229 * to specifically enable SEEPROM access (Flash is the default). 1230 * On older chips, we don't; SEEPROM is the only NVtype supported, 1231 * and the NVM control registers don't exist ... 1232 */ 1233 switch (bgep->chipid.nvtype) { 1234 case BGE_NVTYPE_NONE: 1235 case BGE_NVTYPE_UNKNOWN: 1236 _NOTE(NOTREACHED) 1237 case BGE_NVTYPE_SEEPROM: 1238 break; 1239 1240 case BGE_NVTYPE_LEGACY_SEEPROM: 1241 case BGE_NVTYPE_UNBUFFERED_FLASH: 1242 case BGE_NVTYPE_BUFFERED_FLASH: 1243 default: 1244 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1245 NVM_CFG1_LEGACY_SEEPROM_MODE); 1246 break; 1247 } 1248 1249 /* 1250 * Check there's no command in progress. 1251 * 1252 * Note: this *shouldn't* ever find that there is a command 1253 * in progress, because we already hold the <genlock> mutex. 1254 * Also, to ensure we don't have a conflict with the chip's 1255 * internal firmware or a process accessing the same (shared) 1256 * SEEPROM through the other port of a 5704, we've already 1257 * been through the "software arbitration" protocol. 1258 * So this is just a final consistency check: we shouldn't 1259 * see EITHER the START bit (command started but not complete) 1260 * OR the COMPLETE bit (command completed but not cleared). 1261 */ 1262 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1263 if (regval & SEEPROM_ACCESS_START) 1264 return (EPROTO); 1265 if (regval & SEEPROM_ACCESS_COMPLETE) 1266 return (EPROTO); 1267 1268 /* 1269 * Assemble the command ... 1270 */ 1271 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1272 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1273 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1274 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1275 cmd |= SEEPROM_ACCESS_START; 1276 cmd |= SEEPROM_ACCESS_COMPLETE; 1277 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1278 1279 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1280 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1281 1282 /* 1283 * By observation, a successful access takes ~20us on a 5703/4, 1284 * but apparently much longer (up to 1000us) on the obsolescent 1285 * BCM5700/BCM5701. We want to be sure we don't get any false 1286 * timeouts here; but OTOH, we don't want a bogus access to lock 1287 * out interrupts for longer than necessary. So we'll allow up 1288 * to 1000us ... 1289 */ 1290 for (tries = 0; tries < 1000; ++tries) { 1291 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1292 if (regval & SEEPROM_ACCESS_COMPLETE) 1293 break; 1294 drv_usecwait(1); 1295 } 1296 1297 if (regval & SEEPROM_ACCESS_COMPLETE) { 1298 /* 1299 * All OK; read the SEEPROM data register, then write back 1300 * the value read from the address register in order to 1301 * clear the <complete> bit and leave the SEEPROM access 1302 * state machine idle, ready for the next access ... 1303 */ 1304 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1305 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1306 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1307 return (0); 1308 } 1309 1310 /* 1311 * Hmm ... what happened here? 1312 * 1313 * Most likely, the user addressed a non-existent SEEPROM. Or 1314 * maybe the SEEPROM was busy internally (e.g. processing a write) 1315 * and didn't respond to being addressed. Either way, it's left 1316 * the SEEPROM access state machine wedged. So we'll reset it 1317 * before we leave, so it's ready for next time ... 1318 */ 1319 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1320 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1321 return (ENODATA); 1322 } 1323 1324 /* 1325 * Basic Flash get/set access routine 1326 * 1327 * These use the chip's Flash auto-access method, controlled by the 1328 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1329 * fiddle with the individual bits. 1330 * 1331 * The caller should hold <genlock> and *also* have already acquired 1332 * the right to access the Flash, via bge_nvmem_acquire() above. 1333 * 1334 * Return value: 1335 * 0 on success, 1336 * ENODATA on access timeout (maybe retryable: device may just be busy) 1337 * ENODEV if the NVmem device is missing or otherwise unusable 1338 * 1339 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1340 * from a (successful) NVM_FLASH_CMD_RD. 1341 */ 1342 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1343 uint32_t *dp); 1344 #pragma no_inline(bge_flash_access) 1345 1346 static int 1347 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1348 { 1349 uint32_t tries; 1350 uint32_t regval; 1351 1352 ASSERT(mutex_owned(bgep->genlock)); 1353 1354 /* 1355 * On the newer chips that support both SEEPROM & Flash, we need 1356 * to specifically disable SEEPROM access while accessing Flash. 1357 * The older chips don't support Flash, and the NVM registers don't 1358 * exist, so we shouldn't be here at all! 1359 */ 1360 switch (bgep->chipid.nvtype) { 1361 case BGE_NVTYPE_NONE: 1362 case BGE_NVTYPE_UNKNOWN: 1363 _NOTE(NOTREACHED) 1364 case BGE_NVTYPE_SEEPROM: 1365 return (ENODEV); 1366 1367 case BGE_NVTYPE_LEGACY_SEEPROM: 1368 case BGE_NVTYPE_UNBUFFERED_FLASH: 1369 case BGE_NVTYPE_BUFFERED_FLASH: 1370 default: 1371 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1372 NVM_CFG1_LEGACY_SEEPROM_MODE); 1373 break; 1374 } 1375 1376 /* 1377 * Assemble the command ... 1378 */ 1379 addr &= NVM_FLASH_ADDR_MASK; 1380 cmd |= NVM_FLASH_CMD_DOIT; 1381 cmd |= NVM_FLASH_CMD_FIRST; 1382 cmd |= NVM_FLASH_CMD_LAST; 1383 cmd |= NVM_FLASH_CMD_DONE; 1384 1385 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1386 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1387 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1388 1389 /* 1390 * Allow up to 1000ms ... 1391 */ 1392 for (tries = 0; tries < 1000; ++tries) { 1393 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1394 if (regval & NVM_FLASH_CMD_DONE) 1395 break; 1396 drv_usecwait(1); 1397 } 1398 1399 if (regval & NVM_FLASH_CMD_DONE) { 1400 /* 1401 * All OK; read the data from the Flash read register 1402 */ 1403 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1404 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1405 return (0); 1406 } 1407 1408 /* 1409 * Hmm ... what happened here? 1410 * 1411 * Most likely, the user addressed a non-existent Flash. Or 1412 * maybe the Flash was busy internally (e.g. processing a write) 1413 * and didn't respond to being addressed. Either way, there's 1414 * nothing we can here ... 1415 */ 1416 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1417 return (ENODATA); 1418 } 1419 1420 /* 1421 * The next two functions regulate access to the NVram (if fitted). 1422 * 1423 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1424 * (SPI) interface, but they can be accessed through either port. These 1425 * are managed by different instance of this driver and have no software 1426 * state in common. 1427 * 1428 * In addition (and even on a single core chip) the chip's internal 1429 * firmware can access the SEEPROM/Flash, most notably after a RESET 1430 * when it may download code to run internally. 1431 * 1432 * So we need to arbitrate between these various software agents. For 1433 * this purpose, the chip provides the Software Arbitration Register, 1434 * which implements hardware(!) arbitration. 1435 * 1436 * This functionality didn't exist on older (5700/5701) chips, so there's 1437 * nothing we can do by way of arbitration on those; also, if there's no 1438 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1439 * nothing to do. 1440 * 1441 * The internal firmware appears to use Request 0, which is the highest 1442 * priority. So we'd like to use Request 2, leaving one higher and one 1443 * lower for any future developments ... but apparently this doesn't 1444 * always work. So for now, the code uses Request 1 ;-( 1445 */ 1446 1447 #define NVM_READ_REQ NVM_READ_REQ1 1448 #define NVM_RESET_REQ NVM_RESET_REQ1 1449 #define NVM_SET_REQ NVM_SET_REQ1 1450 1451 static void bge_nvmem_relinquish(bge_t *bgep); 1452 #pragma no_inline(bge_nvmem_relinquish) 1453 1454 static void 1455 bge_nvmem_relinquish(bge_t *bgep) 1456 { 1457 ASSERT(mutex_owned(bgep->genlock)); 1458 1459 switch (bgep->chipid.nvtype) { 1460 case BGE_NVTYPE_NONE: 1461 case BGE_NVTYPE_UNKNOWN: 1462 _NOTE(NOTREACHED) 1463 return; 1464 1465 case BGE_NVTYPE_SEEPROM: 1466 /* 1467 * No arbitration performed, no release needed 1468 */ 1469 return; 1470 1471 case BGE_NVTYPE_LEGACY_SEEPROM: 1472 case BGE_NVTYPE_UNBUFFERED_FLASH: 1473 case BGE_NVTYPE_BUFFERED_FLASH: 1474 default: 1475 break; 1476 } 1477 1478 /* 1479 * Our own request should be present (whether or not granted) ... 1480 */ 1481 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1482 1483 /* 1484 * ... this will make it go away. 1485 */ 1486 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1487 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1488 } 1489 1490 /* 1491 * Arbitrate for access to the NVmem, if necessary 1492 * 1493 * Return value: 1494 * 0 on success 1495 * EAGAIN if the device is in use (retryable) 1496 * ENODEV if the NVmem device is missing or otherwise unusable 1497 */ 1498 static int bge_nvmem_acquire(bge_t *bgep); 1499 #pragma no_inline(bge_nvmem_acquire) 1500 1501 static int 1502 bge_nvmem_acquire(bge_t *bgep) 1503 { 1504 uint32_t regval; 1505 uint32_t tries; 1506 1507 ASSERT(mutex_owned(bgep->genlock)); 1508 1509 switch (bgep->chipid.nvtype) { 1510 case BGE_NVTYPE_NONE: 1511 case BGE_NVTYPE_UNKNOWN: 1512 /* 1513 * Access denied: no (recognisable) device fitted 1514 */ 1515 return (ENODEV); 1516 1517 case BGE_NVTYPE_SEEPROM: 1518 /* 1519 * Access granted: no arbitration needed (or possible) 1520 */ 1521 return (0); 1522 1523 case BGE_NVTYPE_LEGACY_SEEPROM: 1524 case BGE_NVTYPE_UNBUFFERED_FLASH: 1525 case BGE_NVTYPE_BUFFERED_FLASH: 1526 default: 1527 /* 1528 * Access conditional: conduct arbitration protocol 1529 */ 1530 break; 1531 } 1532 1533 /* 1534 * We're holding the per-port mutex <genlock>, so no-one other 1535 * thread can be attempting to access the NVmem through *this* 1536 * port. But it could be in use by the *other* port (of a 5704), 1537 * or by the chip's internal firmware, so we have to go through 1538 * the full (hardware) arbitration protocol ... 1539 * 1540 * Note that *because* we're holding <genlock>, the interrupt handler 1541 * won't be able to progress. So we're only willing to spin for a 1542 * fairly short time. Specifically: 1543 * 1544 * We *must* wait long enough for the hardware to resolve all 1545 * requests and determine the winner. Fortunately, this is 1546 * "almost instantaneous", even as observed by GHz CPUs. 1547 * 1548 * A successful access by another Solaris thread (via either 1549 * port) typically takes ~20us. So waiting a bit longer than 1550 * that will give a good chance of success, if the other user 1551 * *is* another thread on the other port. 1552 * 1553 * However, the internal firmware can hold on to the NVmem 1554 * for *much* longer: at least 10 milliseconds just after a 1555 * RESET, and maybe even longer if the NVmem actually contains 1556 * code to download and run on the internal CPUs. 1557 * 1558 * So, we'll allow 50us; if that's not enough then it's up to the 1559 * caller to retry later (hence the choice of return code EAGAIN). 1560 */ 1561 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1562 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1563 1564 for (tries = 0; tries < 50; ++tries) { 1565 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1566 if (regval & NVM_WON_REQ1) 1567 break; 1568 drv_usecwait(1); 1569 } 1570 1571 if (regval & NVM_WON_REQ1) { 1572 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1573 return (0); 1574 } 1575 1576 /* 1577 * Somebody else must be accessing the NVmem, so abandon our 1578 * attempt take control of it. The caller can try again later ... 1579 */ 1580 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1581 bge_nvmem_relinquish(bgep); 1582 return (EAGAIN); 1583 } 1584 1585 /* 1586 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1587 * write protect line in such a way that the NVmem is protected when 1588 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1589 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1590 * 1591 * Note: there's only one set of GPIO pins on a 5704, even though they 1592 * can be accessed through either port. So the chip has to resolve what 1593 * happens if the two ports program a single pin differently ... the rule 1594 * it uses is that if the ports disagree about the *direction* of a pin, 1595 * "output" wins over "input", but if they disagree about its *value* as 1596 * an output, then the pin is TRISTATED instead! In such a case, no-one 1597 * wins, and the external signal does whatever the external circuitry 1598 * defines as the default -- which we've assumed is the PROTECTED state. 1599 * So, we always change GPIO1 back to being an *input* whenever we're not 1600 * specifically using it to unprotect the NVmem. This allows either port 1601 * to update the NVmem, although obviously only one at a time! 1602 * 1603 * The caller should hold <genlock> and *also* have already acquired the 1604 * right to access the NVmem, via bge_nvmem_acquire() above. 1605 */ 1606 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1607 #pragma inline(bge_nvmem_protect) 1608 1609 static void 1610 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1611 { 1612 uint32_t regval; 1613 1614 ASSERT(mutex_owned(bgep->genlock)); 1615 1616 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1617 if (protect) { 1618 regval |= MLCR_MISC_PINS_OUTPUT_1; 1619 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1620 } else { 1621 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1622 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1623 } 1624 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1625 } 1626 1627 /* 1628 * Now put it all together ... 1629 * 1630 * Try to acquire control of the NVmem; if successful, then: 1631 * unprotect it (if we want to write to it) 1632 * perform the requested access 1633 * reprotect it (after a write) 1634 * relinquish control 1635 * 1636 * Return value: 1637 * 0 on success, 1638 * EAGAIN if the device is in use (retryable) 1639 * ENODATA on access timeout (maybe retryable: device may just be busy) 1640 * ENODEV if the NVmem device is missing or otherwise unusable 1641 * EPROTO on other h/w or s/w errors. 1642 */ 1643 static int 1644 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1645 { 1646 int err; 1647 1648 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1649 switch (cmd) { 1650 case BGE_SEE_READ: 1651 err = bge_seeprom_access(bgep, 1652 SEEPROM_ACCESS_READ, addr, dp); 1653 break; 1654 1655 case BGE_SEE_WRITE: 1656 bge_nvmem_protect(bgep, B_FALSE); 1657 err = bge_seeprom_access(bgep, 1658 SEEPROM_ACCESS_WRITE, addr, dp); 1659 bge_nvmem_protect(bgep, B_TRUE); 1660 break; 1661 1662 case BGE_FLASH_READ: 1663 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1664 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1665 bge_reg_set32(bgep, NVM_ACCESS_REG, 1666 NVM_ACCESS_ENABLE); 1667 } 1668 err = bge_flash_access(bgep, 1669 NVM_FLASH_CMD_RD, addr, dp); 1670 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1671 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1672 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1673 NVM_ACCESS_ENABLE); 1674 } 1675 break; 1676 1677 case BGE_FLASH_WRITE: 1678 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1679 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1680 bge_reg_set32(bgep, NVM_ACCESS_REG, 1681 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1682 } 1683 bge_nvmem_protect(bgep, B_FALSE); 1684 err = bge_flash_access(bgep, 1685 NVM_FLASH_CMD_WR, addr, dp); 1686 bge_nvmem_protect(bgep, B_TRUE); 1687 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1688 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1689 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1690 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1691 } 1692 1693 break; 1694 1695 default: 1696 _NOTE(NOTREACHED) 1697 break; 1698 } 1699 bge_nvmem_relinquish(bgep); 1700 } 1701 1702 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1703 return (err); 1704 } 1705 1706 /* 1707 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1708 */ 1709 static uint64_t bge_get_nvmac(bge_t *bgep); 1710 #pragma no_inline(bge_get_nvmac) 1711 1712 static uint64_t 1713 bge_get_nvmac(bge_t *bgep) 1714 { 1715 uint32_t mac_high; 1716 uint32_t mac_low; 1717 uint32_t addr; 1718 uint32_t cmd; 1719 uint64_t mac; 1720 1721 BGE_TRACE(("bge_get_nvmac($%p)", 1722 (void *)bgep)); 1723 1724 switch (bgep->chipid.nvtype) { 1725 case BGE_NVTYPE_NONE: 1726 case BGE_NVTYPE_UNKNOWN: 1727 default: 1728 return (0ULL); 1729 1730 case BGE_NVTYPE_SEEPROM: 1731 case BGE_NVTYPE_LEGACY_SEEPROM: 1732 cmd = BGE_SEE_READ; 1733 break; 1734 1735 case BGE_NVTYPE_UNBUFFERED_FLASH: 1736 case BGE_NVTYPE_BUFFERED_FLASH: 1737 cmd = BGE_FLASH_READ; 1738 break; 1739 } 1740 1741 addr = NVMEM_DATA_MAC_ADDRESS; 1742 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1743 return (0ULL); 1744 addr += 4; 1745 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1746 return (0ULL); 1747 1748 /* 1749 * The Broadcom chip is natively BIG-endian, so that's how the 1750 * MAC address is represented in NVmem. We may need to swap it 1751 * around on a little-endian host ... 1752 */ 1753 #ifdef _BIG_ENDIAN 1754 mac = mac_high; 1755 mac = mac << 32; 1756 mac |= mac_low; 1757 #else 1758 mac = BGE_BSWAP_32(mac_high); 1759 mac = mac << 32; 1760 mac |= BGE_BSWAP_32(mac_low); 1761 #endif /* _BIG_ENDIAN */ 1762 1763 return (mac); 1764 } 1765 1766 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1767 1768 /* 1769 * Dummy version for when we're not supporting NVmem access 1770 */ 1771 static uint64_t bge_get_nvmac(bge_t *bgep); 1772 #pragma inline(bge_get_nvmac) 1773 1774 static uint64_t 1775 bge_get_nvmac(bge_t *bgep) 1776 { 1777 _NOTE(ARGUNUSED(bgep)) 1778 return (0ULL); 1779 } 1780 1781 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1782 1783 /* 1784 * Determine the type of NVmem that is (or may be) attached to this chip, 1785 */ 1786 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1787 #pragma no_inline(bge_nvmem_id) 1788 1789 static enum bge_nvmem_type 1790 bge_nvmem_id(bge_t *bgep) 1791 { 1792 enum bge_nvmem_type nvtype; 1793 uint32_t config1; 1794 1795 BGE_TRACE(("bge_nvmem_id($%p)", 1796 (void *)bgep)); 1797 1798 switch (bgep->chipid.device) { 1799 default: 1800 /* 1801 * We shouldn't get here; it means we don't recognise 1802 * the chip, which means we don't know how to determine 1803 * what sort of NVmem (if any) it has. So we'll say 1804 * NONE, to disable the NVmem access code ... 1805 */ 1806 nvtype = BGE_NVTYPE_NONE; 1807 break; 1808 1809 case DEVICE_ID_5700: 1810 case DEVICE_ID_5700x: 1811 case DEVICE_ID_5701: 1812 /* 1813 * These devices support *only* SEEPROMs 1814 */ 1815 nvtype = BGE_NVTYPE_SEEPROM; 1816 break; 1817 1818 case DEVICE_ID_5702: 1819 case DEVICE_ID_5702fe: 1820 case DEVICE_ID_5703C: 1821 case DEVICE_ID_5703S: 1822 case DEVICE_ID_5704C: 1823 case DEVICE_ID_5704S: 1824 case DEVICE_ID_5704: 1825 case DEVICE_ID_5705M: 1826 case DEVICE_ID_5705C: 1827 case DEVICE_ID_5705_2: 1828 case DEVICE_ID_5706: 1829 case DEVICE_ID_5782: 1830 case DEVICE_ID_5788: 1831 case DEVICE_ID_5789: 1832 case DEVICE_ID_5751: 1833 case DEVICE_ID_5751M: 1834 case DEVICE_ID_5752: 1835 case DEVICE_ID_5752M: 1836 case DEVICE_ID_5721: 1837 case DEVICE_ID_5714C: 1838 case DEVICE_ID_5714S: 1839 case DEVICE_ID_5715C: 1840 case DEVICE_ID_5715S: 1841 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1842 if (config1 & NVM_CFG1_FLASH_MODE) 1843 if (config1 & NVM_CFG1_BUFFERED_MODE) 1844 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1845 else 1846 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1847 else 1848 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1849 break; 1850 } 1851 1852 return (nvtype); 1853 } 1854 1855 #undef BGE_DBG 1856 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1857 1858 static void 1859 bge_init_recv_rule(bge_t *bgep) 1860 { 1861 bge_recv_rule_t *rulep; 1862 uint32_t i; 1863 1864 /* 1865 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1866 * 1. to direct UDP traffic, set: 1867 * rulep->control = RULE_PROTO_CONTROL; 1868 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1869 * 2. to direct ICMP traffic, set: 1870 * rulep->control = RULE_PROTO_CONTROL; 1871 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1872 * 3. to direct traffic by source ip, set: 1873 * rulep->control = RULE_SIP_CONTROL; 1874 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1875 */ 1876 rulep = bgep->recv_rules; 1877 rulep->control = RULE_PROTO_CONTROL; 1878 rulep->mask_value = RULE_TCP_MASK_VALUE; 1879 1880 /* 1881 * set receive rule registers 1882 */ 1883 rulep = bgep->recv_rules; 1884 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1885 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1886 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1887 } 1888 } 1889 1890 /* 1891 * Using the values captured by bge_chip_cfg_init(), and additional probes 1892 * as required, characterise the chip fully: determine the label by which 1893 * to refer to this chip, the correct settings for various registers, and 1894 * of course whether the device and/or subsystem are supported! 1895 */ 1896 int bge_chip_id_init(bge_t *bgep); 1897 #pragma no_inline(bge_chip_id_init) 1898 1899 int 1900 bge_chip_id_init(bge_t *bgep) 1901 { 1902 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1903 boolean_t sys_ok; 1904 boolean_t dev_ok; 1905 chip_id_t *cidp; 1906 uint32_t subid; 1907 char *devname; 1908 char *sysname; 1909 int *ids; 1910 int err; 1911 uint_t i; 1912 1913 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1914 1915 sys_ok = dev_ok = B_FALSE; 1916 cidp = &bgep->chipid; 1917 1918 /* 1919 * Check the PCI device ID to determine the generic chip type and 1920 * select parameters that depend on this. 1921 * 1922 * Note: because the SPARC platforms in general don't fit the 1923 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1924 * as zero - which is why we use <asic_rev> rather than <revision> 1925 * below ... 1926 * 1927 * Note: in general we can't distinguish between the Copper/SerDes 1928 * versions by ID alone, as some Copper devices (e.g. some but not 1929 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1930 * treat them the same here, and the MII code works out the media 1931 * type later on ... 1932 */ 1933 cidp->mbuf_base = bge_mbuf_pool_base; 1934 cidp->mbuf_length = bge_mbuf_pool_len; 1935 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1936 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1937 cidp->pci_type = BGE_PCI_X; 1938 cidp->statistic_type = BGE_STAT_BLK; 1939 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1940 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1941 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1942 1943 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1944 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1945 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1946 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1947 1948 cidp->msi_enabled = B_FALSE; 1949 1950 switch (cidp->device) { 1951 case DEVICE_ID_5700: 1952 case DEVICE_ID_5700x: 1953 cidp->chip_label = 5700; 1954 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1955 break; 1956 1957 case DEVICE_ID_5701: 1958 cidp->chip_label = 5701; 1959 dev_ok = B_TRUE; 1960 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1961 break; 1962 1963 case DEVICE_ID_5702: 1964 case DEVICE_ID_5702fe: 1965 cidp->chip_label = 5702; 1966 dev_ok = B_TRUE; 1967 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1968 cidp->pci_type = BGE_PCI; 1969 break; 1970 1971 case DEVICE_ID_5703C: 1972 case DEVICE_ID_5703S: 1973 case DEVICE_ID_5703: 1974 /* 1975 * Revision A0 of the 5703/5793 had various errata 1976 * that we can't or don't work around, so it's not 1977 * supported, but all later versions are 1978 */ 1979 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1980 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1981 dev_ok = B_TRUE; 1982 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1983 break; 1984 1985 case DEVICE_ID_5704C: 1986 case DEVICE_ID_5704S: 1987 case DEVICE_ID_5704: 1988 /* 1989 * Revision A0 of the 5704/5794 had various errata 1990 * but we have workarounds, so it *is* supported. 1991 */ 1992 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1993 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1994 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1995 dev_ok = B_TRUE; 1996 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 1997 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1998 break; 1999 2000 case DEVICE_ID_5705C: 2001 case DEVICE_ID_5705M: 2002 case DEVICE_ID_5705MA3: 2003 case DEVICE_ID_5705F: 2004 case DEVICE_ID_5705_2: 2005 cidp->chip_label = 5705; 2006 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2007 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2008 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2009 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2010 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2011 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2012 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2013 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2014 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2015 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2016 cidp->pci_type = BGE_PCI; 2017 cidp->statistic_type = BGE_STAT_REG; 2018 dev_ok = B_TRUE; 2019 break; 2020 2021 case DEVICE_ID_5706: 2022 cidp->chip_label = 5706; 2023 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2024 break; 2025 2026 case DEVICE_ID_5782: 2027 /* 2028 * Apart from the label, we treat this as a 5705(?) 2029 */ 2030 cidp->chip_label = 5782; 2031 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2032 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2033 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2034 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2035 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2036 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2037 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2038 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2039 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2040 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2041 cidp->statistic_type = BGE_STAT_REG; 2042 dev_ok = B_TRUE; 2043 break; 2044 2045 case DEVICE_ID_5788: 2046 /* 2047 * Apart from the label, we treat this as a 5705(?) 2048 */ 2049 cidp->chip_label = 5788; 2050 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2051 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2052 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2053 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2054 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2055 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2056 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2057 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2058 cidp->statistic_type = BGE_STAT_REG; 2059 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2060 dev_ok = B_TRUE; 2061 break; 2062 2063 case DEVICE_ID_5714C: 2064 if (cidp->revision >= REVISION_ID_5714_A2) 2065 cidp->msi_enabled = bge_enable_msi; 2066 /* FALLTHRU */ 2067 case DEVICE_ID_5714S: 2068 cidp->chip_label = 5714; 2069 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2070 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2071 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2072 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2073 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2074 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2075 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2076 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2077 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2078 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2079 cidp->pci_type = BGE_PCI_E; 2080 cidp->statistic_type = BGE_STAT_REG; 2081 dev_ok = B_TRUE; 2082 break; 2083 2084 case DEVICE_ID_5715C: 2085 case DEVICE_ID_5715S: 2086 cidp->chip_label = 5715; 2087 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2088 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2089 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2090 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2091 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2092 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2093 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2094 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2095 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2096 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2097 cidp->pci_type = BGE_PCI_E; 2098 cidp->statistic_type = BGE_STAT_REG; 2099 if (cidp->revision >= REVISION_ID_5715_A2) 2100 cidp->msi_enabled = bge_enable_msi; 2101 dev_ok = B_TRUE; 2102 break; 2103 2104 case DEVICE_ID_5721: 2105 cidp->chip_label = 5721; 2106 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2107 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2108 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2109 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2110 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2111 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2112 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2113 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2114 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2115 cidp->pci_type = BGE_PCI_E; 2116 cidp->statistic_type = BGE_STAT_REG; 2117 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2118 dev_ok = B_TRUE; 2119 break; 2120 2121 case DEVICE_ID_5751: 2122 case DEVICE_ID_5751M: 2123 cidp->chip_label = 5751; 2124 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2125 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2126 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2127 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2128 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2129 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2130 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2131 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2132 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2133 cidp->pci_type = BGE_PCI_E; 2134 cidp->statistic_type = BGE_STAT_REG; 2135 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2136 dev_ok = B_TRUE; 2137 break; 2138 2139 case DEVICE_ID_5752: 2140 case DEVICE_ID_5752M: 2141 cidp->chip_label = 5752; 2142 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2143 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2144 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2145 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2146 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2147 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2148 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2149 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2150 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2151 cidp->pci_type = BGE_PCI_E; 2152 cidp->statistic_type = BGE_STAT_REG; 2153 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2154 dev_ok = B_TRUE; 2155 break; 2156 2157 case DEVICE_ID_5789: 2158 cidp->chip_label = 5789; 2159 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2160 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2161 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2162 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2163 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2164 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2165 cidp->pci_type = BGE_PCI_E; 2166 cidp->statistic_type = BGE_STAT_REG; 2167 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2168 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2169 cidp->msi_enabled = B_TRUE; 2170 dev_ok = B_TRUE; 2171 break; 2172 2173 } 2174 2175 /* 2176 * Setup the default jumbo parameter. 2177 */ 2178 cidp->ethmax_size = ETHERMAX; 2179 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2180 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2181 2182 /* 2183 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2184 * setup below jumbo specific parameters. 2185 * 2186 * For BCM5714/5715, there is only one standard receive ring. So the 2187 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2188 * feature is enabled. 2189 */ 2190 if (bge_jumbo_enable && 2191 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2192 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2193 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2194 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2195 cidp->mbuf_lo_water_rdma = 2196 RDMA_MBUF_LOWAT_5714_JUMBO; 2197 cidp->mbuf_lo_water_rmac = 2198 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2199 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2200 cidp->jumbo_slots = 0; 2201 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2202 } else { 2203 cidp->mbuf_lo_water_rdma = 2204 RDMA_MBUF_LOWAT_JUMBO; 2205 cidp->mbuf_lo_water_rmac = 2206 MAC_RX_MBUF_LOWAT_JUMBO; 2207 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2208 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2209 } 2210 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2211 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2212 cidp->ethmax_size = cidp->default_mtu + 2213 sizeof (struct ether_header); 2214 } 2215 2216 /* 2217 * Identify the NV memory type: SEEPROM or Flash? 2218 */ 2219 cidp->nvtype = bge_nvmem_id(bgep); 2220 2221 /* 2222 * Now, we want to check whether this device is part of a 2223 * supported subsystem (e.g., on the motherboard of a Sun 2224 * branded platform). 2225 * 2226 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2227 */ 2228 if (cidp->subven == VENDOR_ID_SUN) 2229 sys_ok = B_TRUE; 2230 2231 /* 2232 * Rule 2: If it's on the list on known subsystems, then it's OK. 2233 * Note: 0x14e41647 should *not* appear in the list, but the code 2234 * doesn't enforce that. 2235 */ 2236 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2237 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2238 if (err == DDI_PROP_SUCCESS) { 2239 /* 2240 * Got the list; scan for a matching subsystem vendor/device 2241 */ 2242 subid = (cidp->subven << 16) | cidp->subdev; 2243 while (i--) 2244 if (ids[i] == subid) 2245 sys_ok = B_TRUE; 2246 ddi_prop_free(ids); 2247 } 2248 2249 /* 2250 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2251 * 2252 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2253 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2254 * we have to check specially for the exact device paths to the 2255 * motherboard devices on those platforms ;-( 2256 * 2257 * Note: we can't just use the "supported-subsystems" mechanism 2258 * above, because the entry would have to be 0x14e41647 -- which 2259 * would then accept *any* plugin card that *didn't* contain a 2260 * (valid) SEEPROM ;-( 2261 */ 2262 sysname = ddi_node_name(ddi_root_node()); 2263 devname = ddi_pathname(bgep->devinfo, buf); 2264 ASSERT(strlen(devname) > 0); 2265 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2266 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2267 sys_ok = B_TRUE; 2268 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2269 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2270 sys_ok = B_TRUE; 2271 2272 /* 2273 * Now check what we've discovered: is this truly a supported 2274 * chip on (the motherboard of) a supported platform? 2275 * 2276 * Possible problems here: 2277 * 1) it's a completely unheard-of chip (e.g. 5761) 2278 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2279 * 3) it's a chip we would support if it were on the motherboard 2280 * of a Sun platform, but this one isn't ;-( 2281 */ 2282 if (cidp->chip_label == 0) 2283 bge_problem(bgep, 2284 "Device 'pci%04x,%04x' not recognized (%d?)", 2285 cidp->vendor, cidp->device, cidp->device); 2286 else if (!dev_ok) 2287 bge_problem(bgep, 2288 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2289 cidp->vendor, cidp->device, cidp->chip_label, 2290 cidp->revision); 2291 #if BGE_DEBUGGING 2292 else if (!sys_ok) 2293 bge_problem(bgep, 2294 "%d-based subsystem 'pci%04x,%04x' not validated", 2295 cidp->chip_label, cidp->subven, cidp->subdev); 2296 #endif 2297 else 2298 cidp->flags |= CHIP_FLAG_SUPPORTED; 2299 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2300 return (EIO); 2301 return (0); 2302 } 2303 2304 void 2305 bge_chip_msi_trig(bge_t *bgep) 2306 { 2307 uint32_t regval; 2308 2309 regval = bgep->param_msi_cnt<<4; 2310 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2311 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2312 } 2313 2314 /* 2315 * Various registers that control the chip's internal engines (state 2316 * machines) have a <reset> and <enable> bits (fortunately, in the 2317 * same place in each such register :-). 2318 * 2319 * To reset the state machine, the <reset> bit must be written with 1; 2320 * it will then read back as 1 while the reset is in progress, but 2321 * self-clear to 0 when the reset completes. 2322 * 2323 * To enable a state machine, one must set the <enable> bit, which 2324 * will continue to read back as 0 until the state machine is running. 2325 * 2326 * To disable a state machine, the <enable> bit must be cleared, but 2327 * it will continue to read back as 1 until the state machine actually 2328 * stops. 2329 * 2330 * This routine implements polling for completion of a reset, enable 2331 * or disable operation, returning B_TRUE on success (bit reached the 2332 * required state) or B_FALSE on timeout (200*100us == 20ms). 2333 */ 2334 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2335 uint32_t mask, uint32_t val); 2336 #pragma no_inline(bge_chip_poll_engine) 2337 2338 static boolean_t 2339 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2340 uint32_t mask, uint32_t val) 2341 { 2342 uint32_t regval; 2343 uint32_t n; 2344 2345 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2346 (void *)bgep, regno, mask, val)); 2347 2348 for (n = 200; n; --n) { 2349 regval = bge_reg_get32(bgep, regno); 2350 if ((regval & mask) == val) 2351 return (B_TRUE); 2352 drv_usecwait(100); 2353 } 2354 2355 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2356 return (B_FALSE); 2357 } 2358 2359 /* 2360 * Various registers that control the chip's internal engines (state 2361 * machines) have a <reset> bit (fortunately, in the same place in 2362 * each such register :-). To reset the state machine, this bit must 2363 * be written with 1; it will then read back as 1 while the reset is 2364 * in progress, but self-clear to 0 when the reset completes. 2365 * 2366 * This code sets the bit, then polls for it to read back as zero. 2367 * The return value is B_TRUE on success (reset bit cleared itself), 2368 * or B_FALSE if the state machine didn't recover :( 2369 * 2370 * NOTE: the Core reset is similar to other resets, except that we 2371 * can't poll for completion, since the Core reset disables memory 2372 * access! So we just have to assume that it will all complete in 2373 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2374 */ 2375 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2376 #pragma no_inline(bge_chip_reset_engine) 2377 2378 static boolean_t 2379 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2380 { 2381 uint32_t regval; 2382 uint32_t val32; 2383 2384 regval = bge_reg_get32(bgep, regno); 2385 2386 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2387 (void *)bgep, regno)); 2388 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2389 regno, regval)); 2390 2391 regval |= STATE_MACHINE_RESET_BIT; 2392 2393 switch (regno) { 2394 case MISC_CONFIG_REG: 2395 /* 2396 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2397 * resetting PCIE block and bringing PCIE link down, bit 29 2398 * in the register needs to be set first, and then set it again 2399 * while the reset bit is written. 2400 * See:P500 of 57xx-PG102-RDS.pdf. 2401 */ 2402 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2403 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2404 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2405 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2406 if (bgep->chipid.pci_type == BGE_PCI_E) { 2407 if (bgep->chipid.asic_rev == 2408 MHCR_CHIP_REV_5751_A0 || 2409 bgep->chipid.asic_rev == 2410 MHCR_CHIP_REV_5721_A0) { 2411 val32 = bge_reg_get32(bgep, 2412 PHY_TEST_CTRL_REG); 2413 if (val32 == (PHY_PCIE_SCRAM_MODE | 2414 PHY_PCIE_LTASS_MODE)) 2415 bge_reg_put32(bgep, 2416 PHY_TEST_CTRL_REG, 2417 PHY_PCIE_SCRAM_MODE); 2418 val32 = pci_config_get32 2419 (bgep->cfg_handle, 2420 PCI_CONF_BGE_CLKCTL); 2421 val32 |= CLKCTL_PCIE_A0_FIX; 2422 pci_config_put32(bgep->cfg_handle, 2423 PCI_CONF_BGE_CLKCTL, val32); 2424 } 2425 bge_reg_set32(bgep, regno, 2426 MISC_CONFIG_GRC_RESET_DISABLE); 2427 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2428 } 2429 } 2430 2431 /* 2432 * Special case - causes Core reset 2433 * 2434 * On SPARC v9 we want to ensure that we don't start 2435 * timing until the I/O access has actually reached 2436 * the chip, otherwise we might make the next access 2437 * too early. And we can't just force the write out 2438 * by following it with a read (even to config space) 2439 * because that would cause the fault we're trying 2440 * to avoid. Hence the need for membar_sync() here. 2441 */ 2442 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2443 #ifdef __sparcv9 2444 membar_sync(); 2445 #endif /* __sparcv9 */ 2446 /* 2447 * On some platforms,system need about 300us for 2448 * link setup. 2449 */ 2450 drv_usecwait(300); 2451 2452 if (bgep->chipid.pci_type == BGE_PCI_E) { 2453 /* PCI-E device need more reset time */ 2454 drv_usecwait(120000); 2455 2456 /* Set PCIE max payload size and clear error status. */ 2457 if ((bgep->chipid.chip_label == 5721) || 2458 (bgep->chipid.chip_label == 5751) || 2459 (bgep->chipid.chip_label == 5752) || 2460 (bgep->chipid.chip_label == 5789)) { 2461 pci_config_put16(bgep->cfg_handle, 2462 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2463 pci_config_put16(bgep->cfg_handle, 2464 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2465 } 2466 } 2467 2468 BGE_PCICHK(bgep); 2469 return (B_TRUE); 2470 2471 default: 2472 bge_reg_put32(bgep, regno, regval); 2473 return (bge_chip_poll_engine(bgep, regno, 2474 STATE_MACHINE_RESET_BIT, 0)); 2475 } 2476 } 2477 2478 /* 2479 * Various registers that control the chip's internal engines (state 2480 * machines) have an <enable> bit (fortunately, in the same place in 2481 * each such register :-). To stop the state machine, this bit must 2482 * be written with 0, then polled to see when the state machine has 2483 * actually stopped. 2484 * 2485 * The return value is B_TRUE on success (enable bit cleared), or 2486 * B_FALSE if the state machine didn't stop :( 2487 */ 2488 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2489 uint32_t morebits); 2490 #pragma no_inline(bge_chip_disable_engine) 2491 2492 static boolean_t 2493 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2494 { 2495 uint32_t regval; 2496 2497 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2498 (void *)bgep, regno, morebits)); 2499 2500 switch (regno) { 2501 case FTQ_RESET_REG: 2502 /* 2503 * Not quite like the others; it doesn't 2504 * have an <enable> bit, but instead we 2505 * have to set and then clear all the bits 2506 */ 2507 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2508 drv_usecwait(100); 2509 bge_reg_put32(bgep, regno, 0); 2510 return (B_TRUE); 2511 2512 default: 2513 regval = bge_reg_get32(bgep, regno); 2514 regval &= ~STATE_MACHINE_ENABLE_BIT; 2515 regval &= ~morebits; 2516 bge_reg_put32(bgep, regno, regval); 2517 return (bge_chip_poll_engine(bgep, regno, 2518 STATE_MACHINE_ENABLE_BIT, 0)); 2519 } 2520 } 2521 2522 /* 2523 * Various registers that control the chip's internal engines (state 2524 * machines) have an <enable> bit (fortunately, in the same place in 2525 * each such register :-). To start the state machine, this bit must 2526 * be written with 1, then polled to see when the state machine has 2527 * actually started. 2528 * 2529 * The return value is B_TRUE on success (enable bit set), or 2530 * B_FALSE if the state machine didn't start :( 2531 */ 2532 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2533 uint32_t morebits); 2534 #pragma no_inline(bge_chip_enable_engine) 2535 2536 static boolean_t 2537 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2538 { 2539 uint32_t regval; 2540 2541 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2542 (void *)bgep, regno, morebits)); 2543 2544 switch (regno) { 2545 case FTQ_RESET_REG: 2546 /* 2547 * Not quite like the others; it doesn't 2548 * have an <enable> bit, but instead we 2549 * have to set and then clear all the bits 2550 */ 2551 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2552 drv_usecwait(100); 2553 bge_reg_put32(bgep, regno, 0); 2554 return (B_TRUE); 2555 2556 default: 2557 regval = bge_reg_get32(bgep, regno); 2558 regval |= STATE_MACHINE_ENABLE_BIT; 2559 regval |= morebits; 2560 bge_reg_put32(bgep, regno, regval); 2561 return (bge_chip_poll_engine(bgep, regno, 2562 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2563 } 2564 } 2565 2566 /* 2567 * Reprogram the Ethernet, Transmit, and Receive MAC 2568 * modes to match the param_* variables 2569 */ 2570 static void bge_sync_mac_modes(bge_t *bgep); 2571 #pragma no_inline(bge_sync_mac_modes) 2572 2573 static void 2574 bge_sync_mac_modes(bge_t *bgep) 2575 { 2576 uint32_t macmode; 2577 uint32_t regval; 2578 2579 ASSERT(mutex_owned(bgep->genlock)); 2580 2581 /* 2582 * Reprogram the Ethernet MAC mode ... 2583 */ 2584 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2585 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2586 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2587 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2588 else 2589 macmode |= ETHERNET_MODE_LINK_POLARITY; 2590 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2591 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2592 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2593 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2594 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2595 macmode |= ETHERNET_MODE_PORTMODE_MII; 2596 else 2597 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2598 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2599 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2600 else 2601 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2602 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2603 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2604 else 2605 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2606 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2607 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2608 (void *)bgep, regval, macmode)); 2609 2610 /* 2611 * ... the Transmit MAC mode ... 2612 */ 2613 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2614 if (bgep->param_link_tx_pause) 2615 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2616 else 2617 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2618 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2619 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2620 (void *)bgep, regval, macmode)); 2621 2622 /* 2623 * ... and the Receive MAC mode 2624 */ 2625 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2626 if (bgep->param_link_rx_pause) 2627 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2628 else 2629 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2630 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2631 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2632 (void *)bgep, regval, macmode)); 2633 } 2634 2635 /* 2636 * bge_chip_sync() -- program the chip with the unicast MAC address, 2637 * the multicast hash table, the required level of promiscuity, and 2638 * the current loopback mode ... 2639 */ 2640 #ifdef BGE_IPMI_ASF 2641 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2642 #else 2643 int bge_chip_sync(bge_t *bgep); 2644 #endif 2645 #pragma no_inline(bge_chip_sync) 2646 2647 int 2648 #ifdef BGE_IPMI_ASF 2649 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2650 #else 2651 bge_chip_sync(bge_t *bgep) 2652 #endif 2653 { 2654 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2655 boolean_t promisc; 2656 uint64_t macaddr; 2657 uint32_t fill; 2658 int i, j; 2659 int retval = DDI_SUCCESS; 2660 2661 BGE_TRACE(("bge_chip_sync($%p)", 2662 (void *)bgep)); 2663 2664 ASSERT(mutex_owned(bgep->genlock)); 2665 2666 promisc = B_FALSE; 2667 fill = ~(uint32_t)0; 2668 2669 if (bgep->promisc) 2670 promisc = B_TRUE; 2671 else 2672 fill = (uint32_t)0; 2673 2674 /* 2675 * If the TX/RX MAC engines are already running, we should stop 2676 * them (and reset the RX engine) before changing the parameters. 2677 * If they're not running, this will have no effect ... 2678 * 2679 * NOTE: this is currently disabled by default because stopping 2680 * and restarting the Tx engine may cause an outgoing packet in 2681 * transit to be truncated. Also, stopping and restarting the 2682 * Rx engine seems to not work correctly on the 5705. Testing 2683 * has not (yet!) revealed any problems with NOT stopping and 2684 * restarting these engines (and Broadcom say their drivers don't 2685 * do this), but if it is found to cause problems, this variable 2686 * can be patched to re-enable the old behaviour ... 2687 */ 2688 if (bge_stop_start_on_sync) { 2689 #ifdef BGE_IPMI_ASF 2690 if (!bgep->asf_enabled) { 2691 if (!bge_chip_disable_engine(bgep, 2692 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2693 retval = DDI_FAILURE; 2694 } else { 2695 if (!bge_chip_disable_engine(bgep, 2696 RECEIVE_MAC_MODE_REG, 0)) 2697 retval = DDI_FAILURE; 2698 } 2699 #else 2700 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2701 RECEIVE_MODE_KEEP_VLAN_TAG)) 2702 retval = DDI_FAILURE; 2703 #endif 2704 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2705 retval = DDI_FAILURE; 2706 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2707 retval = DDI_FAILURE; 2708 } 2709 2710 /* 2711 * Reprogram the hashed multicast address table ... 2712 */ 2713 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2714 bge_reg_put32(bgep, MAC_HASH_REG(i), 2715 bgep->mcast_hash[i] | fill); 2716 2717 #ifdef BGE_IPMI_ASF 2718 if (!bgep->asf_enabled || !asf_keeplive) { 2719 #endif 2720 /* 2721 * Transform the MAC address(es) from host to chip format, then 2722 * reprogram the transmit random backoff seed and the unicast 2723 * MAC address(es) ... 2724 */ 2725 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2726 for (i = 0, fill = 0, macaddr = 0ull; 2727 i < ETHERADDRL; ++i) { 2728 macaddr <<= 8; 2729 macaddr |= bgep->curr_addr[j].addr[i]; 2730 fill += bgep->curr_addr[j].addr[i]; 2731 } 2732 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2733 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2734 } 2735 2736 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2737 (void *)bgep, macaddr)); 2738 #ifdef BGE_IPMI_ASF 2739 } 2740 #endif 2741 2742 /* 2743 * Set or clear the PROMISCUOUS mode bit 2744 */ 2745 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2746 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2747 2748 /* 2749 * Sync the rest of the MAC modes too ... 2750 */ 2751 bge_sync_mac_modes(bgep); 2752 2753 /* 2754 * Restart RX/TX MAC engines if required ... 2755 */ 2756 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2757 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2758 retval = DDI_FAILURE; 2759 #ifdef BGE_IPMI_ASF 2760 if (!bgep->asf_enabled) { 2761 if (!bge_chip_enable_engine(bgep, 2762 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2763 retval = DDI_FAILURE; 2764 } else { 2765 if (!bge_chip_enable_engine(bgep, 2766 RECEIVE_MAC_MODE_REG, 0)) 2767 retval = DDI_FAILURE; 2768 } 2769 #else 2770 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2771 RECEIVE_MODE_KEEP_VLAN_TAG)) 2772 retval = DDI_FAILURE; 2773 #endif 2774 } 2775 return (retval); 2776 } 2777 2778 /* 2779 * This array defines the sequence of state machine control registers 2780 * in which the <enable> bit must be cleared to bring the chip to a 2781 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2782 */ 2783 static bge_regno_t shutdown_engine_regs[] = { 2784 RECEIVE_MAC_MODE_REG, 2785 RCV_BD_INITIATOR_MODE_REG, 2786 RCV_LIST_PLACEMENT_MODE_REG, 2787 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2788 RCV_DATA_BD_INITIATOR_MODE_REG, 2789 RCV_DATA_COMPLETION_MODE_REG, 2790 RCV_BD_COMPLETION_MODE_REG, 2791 2792 SEND_BD_SELECTOR_MODE_REG, 2793 SEND_BD_INITIATOR_MODE_REG, 2794 SEND_DATA_INITIATOR_MODE_REG, 2795 READ_DMA_MODE_REG, 2796 SEND_DATA_COMPLETION_MODE_REG, 2797 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2798 SEND_BD_COMPLETION_MODE_REG, 2799 TRANSMIT_MAC_MODE_REG, 2800 2801 HOST_COALESCE_MODE_REG, 2802 WRITE_DMA_MODE_REG, 2803 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2804 FTQ_RESET_REG, /* special - see code */ 2805 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2806 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2807 BGE_REGNO_NONE /* terminator */ 2808 }; 2809 2810 /* 2811 * bge_chip_stop() -- stop all chip processing 2812 * 2813 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2814 * we've detected a problem internally; otherwise, this is a normal 2815 * (clean) stop (at user request i.e. the last STREAM has been closed). 2816 */ 2817 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2818 #pragma no_inline(bge_chip_stop) 2819 2820 void 2821 bge_chip_stop(bge_t *bgep, boolean_t fault) 2822 { 2823 bge_regno_t regno; 2824 bge_regno_t *rbp; 2825 boolean_t ok; 2826 2827 BGE_TRACE(("bge_chip_stop($%p)", 2828 (void *)bgep)); 2829 2830 ASSERT(mutex_owned(bgep->genlock)); 2831 2832 rbp = shutdown_engine_regs; 2833 /* 2834 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2835 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2836 * -ory arbiter should not be disabled. 2837 */ 2838 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2839 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2840 ok &= bge_chip_disable_engine(bgep, regno, 0); 2841 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2842 (regno != DMA_COMPLETION_MODE_REG) && 2843 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2844 (regno != BUFFER_MANAGER_MODE_REG) && 2845 (regno != MEMORY_ARBITER_MODE_REG)) 2846 ok &= bge_chip_disable_engine(bgep, 2847 regno, 0); 2848 } 2849 2850 if (!ok && !fault) 2851 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2852 2853 /* 2854 * Finally, disable (all) MAC events & clear the MAC status 2855 */ 2856 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2857 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2858 2859 /* 2860 * if we're stopping the chip because of a detected fault then do 2861 * appropriate actions 2862 */ 2863 if (fault) { 2864 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2865 bgep->bge_chip_state = BGE_CHIP_FAULT; 2866 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2867 if (bgep->bge_dma_error) { 2868 /* 2869 * need to free buffers in case the fault was 2870 * due to a memory error in a buffer - got to 2871 * do a fair bit of tidying first 2872 */ 2873 if (bgep->progress & PROGRESS_KSTATS) { 2874 bge_fini_kstats(bgep); 2875 bgep->progress &= ~PROGRESS_KSTATS; 2876 } 2877 if (bgep->progress & PROGRESS_INTR) { 2878 bge_intr_disable(bgep); 2879 rw_enter(bgep->errlock, RW_WRITER); 2880 bge_fini_rings(bgep); 2881 rw_exit(bgep->errlock); 2882 bgep->progress &= ~PROGRESS_INTR; 2883 } 2884 if (bgep->progress & PROGRESS_BUFS) { 2885 bge_free_bufs(bgep); 2886 bgep->progress &= ~PROGRESS_BUFS; 2887 } 2888 bgep->bge_dma_error = B_FALSE; 2889 } 2890 } 2891 } else 2892 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2893 } 2894 2895 /* 2896 * Poll for completion of chip's ROM firmware; also, at least on the 2897 * first time through, find and return the hardware MAC address, if any. 2898 */ 2899 static uint64_t bge_poll_firmware(bge_t *bgep); 2900 #pragma no_inline(bge_poll_firmware) 2901 2902 static uint64_t 2903 bge_poll_firmware(bge_t *bgep) 2904 { 2905 uint64_t magic; 2906 uint64_t mac; 2907 uint32_t gen; 2908 uint32_t i; 2909 2910 /* 2911 * Step 19: poll for firmware completion (GENCOMM port set 2912 * to the ones complement of T3_MAGIC_NUMBER). 2913 * 2914 * While we're at it, we also read the MAC address register; 2915 * at some stage the firmware will load this with the 2916 * factory-set value. 2917 * 2918 * When both the magic number and the MAC address are set, 2919 * we're done; but we impose a time limit of one second 2920 * (1000*1000us) in case the firmware fails in some fashion 2921 * or the SEEPROM that provides that MAC address isn't fitted. 2922 * 2923 * After the first time through (chip state != INITIAL), we 2924 * don't need the MAC address to be set (we've already got it 2925 * or not, from the first time), so we don't wait for it, but 2926 * we still have to wait for the T3_MAGIC_NUMBER. 2927 * 2928 * Note: the magic number is only a 32-bit quantity, but the NIC 2929 * memory is 64-bit (and big-endian) internally. Addressing the 2930 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2931 * it work correctly on both big- and little-endian hosts. 2932 */ 2933 for (i = 0; i < 1000; ++i) { 2934 drv_usecwait(1000); 2935 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2936 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2937 #ifdef BGE_IPMI_ASF 2938 if (!bgep->asf_enabled) { 2939 #endif 2940 if (gen != ~T3_MAGIC_NUMBER) 2941 continue; 2942 #ifdef BGE_IPMI_ASF 2943 } 2944 #endif 2945 if (mac != 0ULL) 2946 break; 2947 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2948 break; 2949 } 2950 2951 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2952 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2953 (void *)bgep, gen, i)); 2954 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2955 mac, magic)); 2956 2957 return (mac); 2958 } 2959 2960 #ifdef BGE_IPMI_ASF 2961 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2962 #else 2963 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2964 #endif 2965 #pragma no_inline(bge_chip_reset) 2966 2967 int 2968 #ifdef BGE_IPMI_ASF 2969 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2970 #else 2971 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2972 #endif 2973 { 2974 chip_id_t chipid; 2975 uint64_t mac; 2976 uint64_t magic; 2977 uint32_t modeflags; 2978 uint32_t mhcr; 2979 uint32_t sx0; 2980 uint32_t i; 2981 #ifdef BGE_IPMI_ASF 2982 uint32_t mailbox; 2983 #endif 2984 int retval = DDI_SUCCESS; 2985 2986 BGE_TRACE(("bge_chip_reset($%p, %d)", 2987 (void *)bgep, enable_dma)); 2988 2989 ASSERT(mutex_owned(bgep->genlock)); 2990 2991 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 2992 (void *)bgep, enable_dma, bgep->bge_chip_state)); 2993 2994 /* 2995 * Do we need to stop the chip cleanly before resetting? 2996 */ 2997 switch (bgep->bge_chip_state) { 2998 default: 2999 _NOTE(NOTREACHED) 3000 return (DDI_FAILURE); 3001 3002 case BGE_CHIP_INITIAL: 3003 case BGE_CHIP_STOPPED: 3004 case BGE_CHIP_RESET: 3005 break; 3006 3007 case BGE_CHIP_RUNNING: 3008 case BGE_CHIP_ERROR: 3009 case BGE_CHIP_FAULT: 3010 bge_chip_stop(bgep, B_FALSE); 3011 break; 3012 } 3013 3014 #ifdef BGE_IPMI_ASF 3015 if (bgep->asf_enabled) { 3016 if (asf_mode == ASF_MODE_INIT) { 3017 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3018 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3019 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3020 } 3021 } 3022 #endif 3023 /* 3024 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3025 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3026 * 3027 * Before reset Core clock,it is 3028 * also required to initialize the Memory Arbiter as specified in step9 3029 * and Misc Host Control Register as specified in step-13 3030 * Step 4-5: reset Core clock & wait for completion 3031 * Steps 6-8: are done by bge_chip_cfg_init() 3032 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3033 */ 3034 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3035 retval = DDI_FAILURE; 3036 3037 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3038 MHCR_ENABLE_TAGGED_STATUS_MODE | 3039 MHCR_MASK_INTERRUPT_MODE | 3040 MHCR_MASK_PCI_INT_OUTPUT | 3041 MHCR_CLEAR_INTERRUPT_INTA; 3042 #ifdef _BIG_ENDIAN 3043 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3044 #endif /* _BIG_ENDIAN */ 3045 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3046 #ifdef BGE_IPMI_ASF 3047 if (bgep->asf_enabled) 3048 bgep->asf_wordswapped = B_FALSE; 3049 #endif 3050 /* 3051 * NVRAM Corruption Workaround 3052 */ 3053 for (i = 0; i < 600; i++) 3054 if (bge_nvmem_acquire(bgep) == 0) 3055 break; 3056 if (i >= 600) 3057 BGE_DEBUG(("%s: fail to acquire nvram lock", 3058 bgep->ifname)); 3059 3060 #ifdef BGE_IPMI_ASF 3061 if (!bgep->asf_enabled) { 3062 #endif 3063 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3064 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3065 #ifdef BGE_IPMI_ASF 3066 } 3067 #endif 3068 3069 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3070 retval = DDI_FAILURE; 3071 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3072 3073 /* 3074 * Step 8a: This may belong elsewhere, but BCM5721 needs 3075 * a bit set to avoid a fifo overflow/underflow bug. 3076 */ 3077 if ((bgep->chipid.chip_label == 5721) || 3078 (bgep->chipid.chip_label == 5751) || 3079 (bgep->chipid.chip_label == 5752) || 3080 (bgep->chipid.chip_label == 5789)) 3081 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3082 3083 3084 /* 3085 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3086 * not be changed. 3087 */ 3088 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3089 retval = DDI_FAILURE; 3090 3091 /* 3092 * Steps 10-11: configure PIO endianness options and 3093 * enable indirect register access -- already done 3094 * Steps 12-13: enable writing to the PCI state & clock 3095 * control registers -- not required; we aren't going to 3096 * use those features. 3097 * Steps 14-15: Configure DMA endianness options. See 3098 * the comments on the setting of the MHCR above. 3099 */ 3100 #ifdef _BIG_ENDIAN 3101 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3102 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3103 #else 3104 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3105 #endif /* _BIG_ENDIAN */ 3106 #ifdef BGE_IPMI_ASF 3107 if (bgep->asf_enabled) 3108 modeflags |= MODE_HOST_STACK_UP; 3109 #endif 3110 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3111 3112 #ifdef BGE_IPMI_ASF 3113 if (bgep->asf_enabled) { 3114 if (asf_mode != ASF_MODE_NONE) { 3115 /* Wait for NVRAM init */ 3116 i = 0; 3117 drv_usecwait(5000); 3118 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3119 while ((mailbox != (uint32_t) 3120 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3121 (i < 10000)) { 3122 drv_usecwait(100); 3123 mailbox = bge_nic_get32(bgep, 3124 BGE_FIRMWARE_MAILBOX); 3125 i++; 3126 } 3127 if (!bgep->asf_newhandshake) { 3128 if ((asf_mode == ASF_MODE_INIT) || 3129 (asf_mode == ASF_MODE_POST_INIT)) { 3130 3131 bge_asf_post_reset_old_mode(bgep, 3132 BGE_INIT_RESET); 3133 } else { 3134 bge_asf_post_reset_old_mode(bgep, 3135 BGE_SHUTDOWN_RESET); 3136 } 3137 } 3138 } 3139 } 3140 #endif 3141 /* 3142 * Steps 16-17: poll for firmware completion 3143 */ 3144 mac = bge_poll_firmware(bgep); 3145 3146 /* 3147 * Step 18: enable external memory -- doesn't apply. 3148 * 3149 * However we take the opportunity to set the MLCR anyway, as 3150 * this register also controls the SEEPROM auto-access method 3151 * which we may want to use later ... 3152 * 3153 * The proper value here depends on the way the chip is wired 3154 * into the circuit board, as this register *also* controls which 3155 * of the "Miscellaneous I/O" pins are driven as outputs and the 3156 * values driven onto those pins! 3157 * 3158 * See also step 74 in the PRM ... 3159 */ 3160 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3161 bgep->chipid.bge_mlcr_default); 3162 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3163 3164 /* 3165 * Step 20: clear the Ethernet MAC mode register 3166 */ 3167 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3168 3169 /* 3170 * Step 21: restore cache-line-size, latency timer, and 3171 * subsystem ID registers to their original values (not 3172 * those read into the local structure <chipid>, 'cos 3173 * that was after they were cleared by the RESET). 3174 * 3175 * Note: the Subsystem Vendor/Device ID registers are not 3176 * directly writable in config space, so we use the shadow 3177 * copy in "Page Zero" of register space to restore them 3178 * both in one go ... 3179 */ 3180 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3181 bgep->chipid.clsize); 3182 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3183 bgep->chipid.latency); 3184 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3185 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3186 3187 /* 3188 * The SEND INDEX registers should be reset to zero by the 3189 * global chip reset; if they're not, there'll be trouble 3190 * later on. 3191 */ 3192 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3193 if (sx0 != 0) { 3194 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3195 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3196 retval = DDI_FAILURE; 3197 } 3198 3199 /* Enable MSI code */ 3200 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3201 bge_reg_set32(bgep, MSI_MODE_REG, 3202 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3203 3204 /* 3205 * On the first time through, save the factory-set MAC address 3206 * (if any). If bge_poll_firmware() above didn't return one 3207 * (from a chip register) consider looking in the attached NV 3208 * memory device, if any. Once we have it, we save it in both 3209 * register-image (64-bit) and byte-array forms. All-zero and 3210 * all-one addresses are not valid, and we refuse to stash those. 3211 */ 3212 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3213 if (mac == 0ULL) 3214 mac = bge_get_nvmac(bgep); 3215 if (mac != 0ULL && mac != ~0ULL) { 3216 bgep->chipid.hw_mac_addr = mac; 3217 for (i = ETHERADDRL; i-- != 0; ) { 3218 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3219 mac >>= 8; 3220 } 3221 bgep->chipid.vendor_addr.set = B_TRUE; 3222 } 3223 } 3224 3225 #ifdef BGE_IPMI_ASF 3226 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3227 if (asf_mode != ASF_MODE_NONE) { 3228 if ((asf_mode == ASF_MODE_INIT) || 3229 (asf_mode == ASF_MODE_POST_INIT)) { 3230 3231 bge_asf_post_reset_new_mode(bgep, 3232 BGE_INIT_RESET); 3233 } else { 3234 bge_asf_post_reset_new_mode(bgep, 3235 BGE_SHUTDOWN_RESET); 3236 } 3237 } 3238 } 3239 #endif 3240 3241 /* 3242 * Record the new state 3243 */ 3244 bgep->chip_resets += 1; 3245 bgep->bge_chip_state = BGE_CHIP_RESET; 3246 return (retval); 3247 } 3248 3249 /* 3250 * bge_chip_start() -- start the chip transmitting and/or receiving, 3251 * including enabling interrupts 3252 */ 3253 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3254 #pragma no_inline(bge_chip_start) 3255 3256 int 3257 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3258 { 3259 uint32_t coalmode; 3260 uint32_t ledctl; 3261 uint32_t mtu; 3262 uint32_t maxring; 3263 uint64_t ring; 3264 int retval = DDI_SUCCESS; 3265 3266 BGE_TRACE(("bge_chip_start($%p)", 3267 (void *)bgep)); 3268 3269 ASSERT(mutex_owned(bgep->genlock)); 3270 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3271 3272 /* 3273 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3274 * The document specifies 95 separate steps to fully 3275 * initialise the chip!!!! 3276 * 3277 * The reset code above has already got us as far as step 3278 * 21, so we continue with ... 3279 * 3280 * Step 22: clear the MAC statistics block 3281 * (0x0300-0x0aff in NIC-local memory) 3282 */ 3283 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3284 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3285 NIC_MEM_STATISTICS_SIZE); 3286 3287 /* 3288 * Step 23: clear the status block (in host memory) 3289 */ 3290 DMA_ZERO(bgep->status_block); 3291 3292 /* 3293 * Step 24: set DMA read/write control register 3294 */ 3295 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3296 bgep->chipid.bge_dma_rwctrl); 3297 3298 /* 3299 * Step 25: Configure DMA endianness -- already done (16/17) 3300 * Step 26: Configure Host-Based Send Rings 3301 * Step 27: Indicate Host Stack Up 3302 */ 3303 bge_reg_set32(bgep, MODE_CONTROL_REG, 3304 MODE_HOST_SEND_BDS | 3305 MODE_HOST_STACK_UP); 3306 3307 /* 3308 * Step 28: Configure checksum options: 3309 * Solaris supports the hardware default checksum options. 3310 * 3311 * Workaround for Incorrect pseudo-header checksum calculation. 3312 */ 3313 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3314 bge_reg_set32(bgep, MODE_CONTROL_REG, 3315 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3316 3317 /* 3318 * Step 29: configure Timer Prescaler. The value is always the 3319 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3320 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3321 * for the whole chip! 3322 */ 3323 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3324 3325 /* 3326 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3327 * 3328 * If the mbuf_length is specified as 0, we just leave these at 3329 * their hardware defaults, rather than explicitly setting them. 3330 * As the Broadcom HRM,driver better not change the parameters 3331 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3332 */ 3333 if ((bgep->chipid.mbuf_length != 0) && 3334 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3335 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3336 bgep->chipid.mbuf_base); 3337 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3338 bgep->chipid.mbuf_length); 3339 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3340 DMAD_POOL_BASE_DEFAULT); 3341 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3342 DMAD_POOL_LENGTH_DEFAULT); 3343 } 3344 3345 /* 3346 * Step 32: configure MAC memory pool watermarks 3347 */ 3348 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3349 bgep->chipid.mbuf_lo_water_rdma); 3350 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3351 bgep->chipid.mbuf_lo_water_rmac); 3352 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3353 bgep->chipid.mbuf_hi_water); 3354 3355 /* 3356 * Step 33: configure DMA resource watermarks 3357 */ 3358 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3359 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3360 bge_dmad_lo_water); 3361 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3362 bge_dmad_hi_water); 3363 } 3364 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3365 3366 /* 3367 * Steps 34-36: enable buffer manager & internal h/w queues 3368 */ 3369 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3370 STATE_MACHINE_ATTN_ENABLE_BIT)) 3371 retval = DDI_FAILURE; 3372 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3373 retval = DDI_FAILURE; 3374 3375 /* 3376 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3377 */ 3378 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3379 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3380 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3381 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3382 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3383 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3384 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3385 } 3386 3387 /* 3388 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3389 */ 3390 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3391 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3392 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3393 bge_replenish_jumbo); 3394 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3395 bge_replenish_mini); 3396 } 3397 3398 /* 3399 * Steps 41-43: clear Send Ring Producer Indices and initialise 3400 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3401 */ 3402 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3403 maxring = BGE_SEND_RINGS_MAX; 3404 else 3405 maxring = BGE_SEND_RINGS_MAX_5705; 3406 for (ring = 0; ring < maxring; ++ring) { 3407 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3408 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3409 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3410 &bgep->send[ring].hw_rcb); 3411 } 3412 3413 /* 3414 * Steps 44-45: initialise Receive Return Rings 3415 * (0x0200-0x02ff in NIC-local memory) 3416 */ 3417 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3418 maxring = BGE_RECV_RINGS_MAX; 3419 else 3420 maxring = BGE_RECV_RINGS_MAX_5705; 3421 for (ring = 0; ring < maxring; ++ring) 3422 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3423 &bgep->recv[ring].hw_rcb); 3424 3425 /* 3426 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3427 */ 3428 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3429 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3430 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3431 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3432 } 3433 /* 3434 * Step 47: configure the MAC unicast address 3435 * Step 48: configure the random backoff seed 3436 * Step 96: set up multicast filters 3437 */ 3438 #ifdef BGE_IPMI_ASF 3439 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3440 #else 3441 if (bge_chip_sync(bgep) == DDI_FAILURE) 3442 #endif 3443 retval = DDI_FAILURE; 3444 3445 /* 3446 * Step 49: configure the MTU 3447 */ 3448 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3449 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3450 3451 /* 3452 * Step 50: configure the IPG et al 3453 */ 3454 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3455 3456 /* 3457 * Step 51: configure the default Rx Return Ring 3458 */ 3459 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3460 3461 /* 3462 * Steps 52-54: configure Receive List Placement, 3463 * and enable Receive List Placement Statistics 3464 */ 3465 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3466 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3467 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3468 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3469 3470 if (bgep->chipid.rx_rings > 1) 3471 bge_init_recv_rule(bgep); 3472 3473 /* 3474 * Steps 55-56: enable Send Data Initiator Statistics 3475 */ 3476 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3477 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3478 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3479 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3480 } else { 3481 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3482 SEND_INIT_STATS_ENABLE); 3483 } 3484 /* 3485 * Steps 57-58: stop (?) the Host Coalescing Engine 3486 */ 3487 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3488 retval = DDI_FAILURE; 3489 3490 /* 3491 * Steps 59-62: initialise Host Coalescing parameters 3492 */ 3493 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3494 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3495 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3496 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3497 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3498 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3499 bge_tx_count_intr); 3500 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3501 bge_tx_ticks_intr); 3502 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3503 bge_rx_count_intr); 3504 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3505 bge_rx_ticks_intr); 3506 } 3507 3508 /* 3509 * Steps 63-64: initialise status block & statistics 3510 * host memory addresses 3511 * The statistic block does not exist in some chipsets 3512 * Step 65: initialise Statistics Coalescing Tick Counter 3513 */ 3514 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3515 bgep->status_block.cookie.dmac_laddress); 3516 3517 /* 3518 * Steps 66-67: initialise status block & statistics 3519 * NIC-local memory addresses 3520 */ 3521 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3522 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3523 bgep->statistics.cookie.dmac_laddress); 3524 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3525 STATISTICS_TICKS_DEFAULT); 3526 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3527 NIC_MEM_STATUS_BLOCK); 3528 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3529 NIC_MEM_STATISTICS); 3530 } 3531 3532 /* 3533 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3534 * Completion Engine, the Receive List Placement Engine, and the 3535 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3536 * and BCM5715. 3537 */ 3538 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3539 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3540 coalmode = COALESCE_64_BYTE_STATUS; 3541 else 3542 coalmode = 0; 3543 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3544 retval = DDI_FAILURE; 3545 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3546 STATE_MACHINE_ATTN_ENABLE_BIT)) 3547 retval = DDI_FAILURE; 3548 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3549 retval = DDI_FAILURE; 3550 3551 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3552 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3553 STATE_MACHINE_ATTN_ENABLE_BIT)) 3554 retval = DDI_FAILURE; 3555 3556 /* 3557 * Step 72: Enable MAC DMA engines 3558 * Step 73: Clear & enable MAC statistics 3559 */ 3560 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3561 ETHERNET_MODE_ENABLE_FHDE | 3562 ETHERNET_MODE_ENABLE_RDE | 3563 ETHERNET_MODE_ENABLE_TDE); 3564 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3565 ETHERNET_MODE_ENABLE_TX_STATS | 3566 ETHERNET_MODE_ENABLE_RX_STATS | 3567 ETHERNET_MODE_CLEAR_TX_STATS | 3568 ETHERNET_MODE_CLEAR_RX_STATS); 3569 3570 /* 3571 * Step 74: configure the MLCR (Miscellaneous Local Control 3572 * Register); not required, as we set up the MLCR in step 10 3573 * (part of the reset code) above. 3574 * 3575 * Step 75: clear Interrupt Mailbox 0 3576 */ 3577 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3578 3579 /* 3580 * Steps 76-87: Gentlemen, start your engines ... 3581 * 3582 * Enable the DMA Completion Engine, the Write DMA Engine, 3583 * the Read DMA Engine, Receive Data Completion Engine, 3584 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3585 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3586 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3587 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3588 * 3589 * Beware exhaust fumes? 3590 */ 3591 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3592 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3593 retval = DDI_FAILURE; 3594 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3595 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3596 retval = DDI_FAILURE; 3597 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3598 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3599 retval = DDI_FAILURE; 3600 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3601 STATE_MACHINE_ATTN_ENABLE_BIT)) 3602 retval = DDI_FAILURE; 3603 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3604 if (!bge_chip_enable_engine(bgep, 3605 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3606 retval = DDI_FAILURE; 3607 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3608 retval = DDI_FAILURE; 3609 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3610 STATE_MACHINE_ATTN_ENABLE_BIT)) 3611 retval = DDI_FAILURE; 3612 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3613 RCV_BD_DISABLED_RING_ATTN)) 3614 retval = DDI_FAILURE; 3615 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3616 RCV_DATA_BD_ILL_RING_ATTN)) 3617 retval = DDI_FAILURE; 3618 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3619 retval = DDI_FAILURE; 3620 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3621 STATE_MACHINE_ATTN_ENABLE_BIT)) 3622 retval = DDI_FAILURE; 3623 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3624 STATE_MACHINE_ATTN_ENABLE_BIT)) 3625 retval = DDI_FAILURE; 3626 3627 /* 3628 * Step 88: download firmware -- doesn't apply 3629 * Steps 89-90: enable Transmit & Receive MAC Engines 3630 */ 3631 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3632 retval = DDI_FAILURE; 3633 #ifdef BGE_IPMI_ASF 3634 if (!bgep->asf_enabled) { 3635 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3636 RECEIVE_MODE_KEEP_VLAN_TAG)) 3637 retval = DDI_FAILURE; 3638 } else { 3639 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3640 retval = DDI_FAILURE; 3641 } 3642 #else 3643 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3644 RECEIVE_MODE_KEEP_VLAN_TAG)) 3645 retval = DDI_FAILURE; 3646 #endif 3647 3648 /* 3649 * Step 91: disable auto-polling of PHY status 3650 */ 3651 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3652 3653 /* 3654 * Step 92: configure D0 power state (not required) 3655 * Step 93: initialise LED control register () 3656 */ 3657 ledctl = LED_CONTROL_DEFAULT; 3658 switch (bgep->chipid.device) { 3659 case DEVICE_ID_5700: 3660 case DEVICE_ID_5700x: 3661 case DEVICE_ID_5701: 3662 /* 3663 * Switch to 5700 (MAC) mode on these older chips 3664 */ 3665 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3666 ledctl |= LED_CONTROL_LED_MODE_5700; 3667 break; 3668 3669 default: 3670 break; 3671 } 3672 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3673 3674 /* 3675 * Step 94: activate link 3676 */ 3677 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3678 3679 /* 3680 * Step 95: set up physical layer (PHY/SerDes) 3681 * restart autoneg (if required) 3682 */ 3683 if (reset_phys) 3684 if (bge_phys_update(bgep) == DDI_FAILURE) 3685 retval = DDI_FAILURE; 3686 3687 /* 3688 * Extra step (DSG): hand over all the Receive Buffers to the chip 3689 */ 3690 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3691 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3692 bgep->buff[ring].rf_next); 3693 3694 /* 3695 * MSI bits:The least significant MSI 16-bit word. 3696 * ISR will be triggered different. 3697 */ 3698 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3699 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3700 3701 /* 3702 * Extra step (DSG): select which interrupts are enabled 3703 * 3704 * Program the Ethernet MAC engine to signal attention on 3705 * Link Change events, then enable interrupts on MAC, DMA, 3706 * and FLOW attention signals. 3707 */ 3708 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3709 ETHERNET_EVENT_LINK_INT | 3710 ETHERNET_STATUS_PCS_ERROR_INT); 3711 #ifdef BGE_IPMI_ASF 3712 if (bgep->asf_enabled) { 3713 bge_reg_set32(bgep, MODE_CONTROL_REG, 3714 MODE_INT_ON_FLOW_ATTN | 3715 MODE_INT_ON_DMA_ATTN | 3716 MODE_HOST_STACK_UP| 3717 MODE_INT_ON_MAC_ATTN); 3718 } else { 3719 #endif 3720 bge_reg_set32(bgep, MODE_CONTROL_REG, 3721 MODE_INT_ON_FLOW_ATTN | 3722 MODE_INT_ON_DMA_ATTN | 3723 MODE_INT_ON_MAC_ATTN); 3724 #ifdef BGE_IPMI_ASF 3725 } 3726 #endif 3727 3728 /* 3729 * Step 97: enable PCI interrupts!!! 3730 */ 3731 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3732 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3733 MHCR_MASK_PCI_INT_OUTPUT); 3734 3735 /* 3736 * All done! 3737 */ 3738 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3739 return (retval); 3740 } 3741 3742 3743 /* 3744 * ========== Hardware interrupt handler ========== 3745 */ 3746 3747 #undef BGE_DBG 3748 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3749 3750 /* 3751 * Sync the status block, then atomically clear the specified bits in 3752 * the <flags-and-tag> field of the status block. 3753 * the <flags> word of the status block, returning the value of the 3754 * <tag> and the <flags> before the bits were cleared. 3755 */ 3756 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3757 #pragma inline(bge_status_sync) 3758 3759 static int 3760 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3761 { 3762 bge_status_t *bsp; 3763 int retval; 3764 3765 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3766 (void *)bgep, bits)); 3767 3768 ASSERT(bgep->bge_guard == BGE_GUARD); 3769 3770 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3771 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3772 if (retval != DDI_FM_OK) 3773 return (retval); 3774 3775 bsp = DMA_VPTR(bgep->status_block); 3776 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3777 3778 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3779 (void *)bgep, bits, *flags)); 3780 3781 return (retval); 3782 } 3783 3784 static void bge_wake_factotum(bge_t *bgep); 3785 #pragma inline(bge_wake_factotum) 3786 3787 static void 3788 bge_wake_factotum(bge_t *bgep) 3789 { 3790 mutex_enter(bgep->softintrlock); 3791 if (bgep->factotum_flag == 0) { 3792 bgep->factotum_flag = 1; 3793 ddi_trigger_softintr(bgep->factotum_id); 3794 } 3795 mutex_exit(bgep->softintrlock); 3796 } 3797 3798 /* 3799 * bge_intr() -- handle chip interrupts 3800 */ 3801 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3802 #pragma no_inline(bge_intr) 3803 3804 uint_t 3805 bge_intr(caddr_t arg1, caddr_t arg2) 3806 { 3807 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3808 bge_status_t *bsp; 3809 uint64_t flags; 3810 uint32_t mlcr = 0; 3811 uint_t result; 3812 int retval; 3813 3814 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3815 3816 /* 3817 * GLD v2 checks that s/w setup is complete before passing 3818 * interrupts to this routine, thus eliminating the old 3819 * (and well-known) race condition around ddi_add_intr() 3820 */ 3821 ASSERT(bgep->progress & PROGRESS_HWINT); 3822 3823 /* 3824 * Check whether chip's says it's asserting #INTA; 3825 * if not, don't process or claim the interrupt. 3826 * 3827 * Note that the PCI signal is active low, so the 3828 * bit is *zero* when the interrupt is asserted. 3829 */ 3830 result = DDI_INTR_UNCLAIMED; 3831 mutex_enter(bgep->genlock); 3832 3833 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3834 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3835 3836 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3837 3838 if ((mlcr & MLCR_INTA_STATE) == 0) { 3839 /* 3840 * Block further PCI interrupts ... 3841 */ 3842 result = DDI_INTR_CLAIMED; 3843 3844 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3845 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3846 MHCR_MASK_PCI_INT_OUTPUT); 3847 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 3848 DDI_FM_OK) 3849 goto chip_stop; 3850 } 3851 3852 /* 3853 * Sync the status block and grab the flags-n-tag from it. 3854 * We count the number of interrupts where there doesn't 3855 * seem to have been a DMA update of the status block; if 3856 * it *has* been updated, the counter will be cleared in 3857 * the while() loop below ... 3858 */ 3859 bgep->missed_dmas += 1; 3860 bsp = DMA_VPTR(bgep->status_block); 3861 for (;;) { 3862 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3863 /* 3864 * bge_chip_stop() may have freed dma area etc 3865 * while we were in this interrupt handler - 3866 * better not call bge_status_sync() 3867 */ 3868 (void) bge_check_acc_handle(bgep, 3869 bgep->io_handle); 3870 mutex_exit(bgep->genlock); 3871 return (DDI_INTR_CLAIMED); 3872 } 3873 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3874 &flags); 3875 if (retval != DDI_FM_OK) { 3876 bgep->bge_dma_error = B_TRUE; 3877 goto chip_stop; 3878 } 3879 3880 if (!(flags & STATUS_FLAG_UPDATED)) 3881 break; 3882 3883 /* 3884 * Tell the chip that we're processing the interrupt 3885 */ 3886 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3887 INTERRUPT_MBOX_DISABLE(flags)); 3888 if (bge_check_acc_handle(bgep, bgep->io_handle) != 3889 DDI_FM_OK) 3890 goto chip_stop; 3891 3892 /* 3893 * Drop the mutex while we: 3894 * Receive any newly-arrived packets 3895 * Recycle any newly-finished send buffers 3896 */ 3897 bgep->bge_intr_running = B_TRUE; 3898 mutex_exit(bgep->genlock); 3899 bge_receive(bgep, bsp); 3900 bge_recycle(bgep, bsp); 3901 mutex_enter(bgep->genlock); 3902 bgep->bge_intr_running = B_FALSE; 3903 3904 /* 3905 * Tell the chip we've finished processing, and 3906 * give it the tag that we got from the status 3907 * block earlier, so that it knows just how far 3908 * we've gone. If it's got more for us to do, 3909 * it will now update the status block and try 3910 * to assert an interrupt (but we've got the 3911 * #INTA blocked at present). If we see the 3912 * update, we'll loop around to do some more. 3913 * Eventually we'll get out of here ... 3914 */ 3915 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3916 INTERRUPT_MBOX_ENABLE(flags)); 3917 bgep->missed_dmas = 0; 3918 } 3919 3920 /* 3921 * Check for exceptional conditions that we need to handle 3922 * 3923 * Link status changed 3924 * Status block not updated 3925 */ 3926 if (flags & STATUS_FLAG_LINK_CHANGED) 3927 bge_wake_factotum(bgep); 3928 3929 if (bgep->missed_dmas) { 3930 /* 3931 * Probably due to the internal status tag not 3932 * being reset. Force a status block update now; 3933 * this should ensure that we get an update and 3934 * a new interrupt. After that, we should be in 3935 * sync again ... 3936 */ 3937 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3938 "not updated?", flags)); 3939 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3940 COALESCE_NOW); 3941 3942 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3943 /* 3944 * If this happens multiple times in a row, 3945 * it means DMA is just not working. Maybe 3946 * the chip's failed, or maybe there's a 3947 * problem on the PCI bus or in the host-PCI 3948 * bridge (Tomatillo). 3949 * 3950 * At all events, we want to stop further 3951 * interrupts and let the recovery code take 3952 * over to see whether anything can be done 3953 * about it ... 3954 */ 3955 bge_fm_ereport(bgep, 3956 DDI_FM_DEVICE_BADINT_LIMIT); 3957 goto chip_stop; 3958 } 3959 } 3960 3961 /* 3962 * Reenable assertion of #INTA, unless there's a DMA fault 3963 */ 3964 if (result == DDI_INTR_CLAIMED) { 3965 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3966 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 3967 MHCR_MASK_PCI_INT_OUTPUT); 3968 if (bge_check_acc_handle(bgep, 3969 bgep->cfg_handle) != DDI_FM_OK) 3970 goto chip_stop; 3971 } 3972 } 3973 } 3974 3975 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3976 goto chip_stop; 3977 3978 mutex_exit(bgep->genlock); 3979 return (result); 3980 3981 chip_stop: 3982 #ifdef BGE_IPMI_ASF 3983 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 3984 /* 3985 * We must stop ASF heart beat before 3986 * bge_chip_stop(), otherwise some 3987 * computers (ex. IBM HS20 blade 3988 * server) may crash. 3989 */ 3990 bge_asf_update_status(bgep); 3991 bge_asf_stop_timer(bgep); 3992 bgep->asf_status = ASF_STAT_STOP; 3993 3994 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3995 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 3996 } 3997 #endif 3998 bge_chip_stop(bgep, B_TRUE); 3999 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4000 mutex_exit(bgep->genlock); 4001 return (result); 4002 } 4003 4004 /* 4005 * ========== Factotum, implemented as a softint handler ========== 4006 */ 4007 4008 #undef BGE_DBG 4009 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4010 4011 static void bge_factotum_error_handler(bge_t *bgep); 4012 #pragma no_inline(bge_factotum_error_handler) 4013 4014 static void 4015 bge_factotum_error_handler(bge_t *bgep) 4016 { 4017 uint32_t flow; 4018 uint32_t rdma; 4019 uint32_t wdma; 4020 uint32_t tmac; 4021 uint32_t rmac; 4022 uint32_t rxrs; 4023 uint32_t txrs = 0; 4024 4025 ASSERT(mutex_owned(bgep->genlock)); 4026 4027 /* 4028 * Read all the registers that show the possible 4029 * reasons for the ERROR bit to be asserted 4030 */ 4031 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4032 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4033 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4034 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4035 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4036 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4037 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4038 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4039 4040 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4041 (void *)bgep, flow, rdma, wdma)); 4042 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4043 (void *)bgep, tmac, rmac, rxrs, txrs)); 4044 4045 /* 4046 * For now, just clear all the errors ... 4047 */ 4048 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4049 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4050 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4051 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4052 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4053 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4054 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4055 } 4056 4057 /* 4058 * Handler for hardware link state change. 4059 * 4060 * When this routine is called, the hardware link state has changed 4061 * and the new state is reflected in the param_* variables. Here 4062 * we must update the softstate, reprogram the MAC to match, and 4063 * record the change in the log and/or on the console. 4064 */ 4065 static void bge_factotum_link_handler(bge_t *bgep); 4066 #pragma no_inline(bge_factotum_link_handler) 4067 4068 static void 4069 bge_factotum_link_handler(bge_t *bgep) 4070 { 4071 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4072 const char *msg; 4073 hrtime_t deltat; 4074 4075 ASSERT(mutex_owned(bgep->genlock)); 4076 4077 /* 4078 * Update the s/w link_state 4079 */ 4080 if (bgep->param_link_up) 4081 bgep->link_state = LINK_STATE_UP; 4082 else 4083 bgep->link_state = LINK_STATE_DOWN; 4084 4085 /* 4086 * Reprogram the MAC modes to match 4087 */ 4088 bge_sync_mac_modes(bgep); 4089 4090 /* 4091 * Finally, we have to decide whether to write a message 4092 * on the console or only in the log. If the PHY has 4093 * been reprogrammed (at user request) "recently", then 4094 * the message only goes in the log. Otherwise it's an 4095 * "unexpected" event, and it goes on the console as well. 4096 */ 4097 deltat = bgep->phys_event_time - bgep->phys_write_time; 4098 if (deltat > BGE_LINK_SETTLE_TIME) 4099 msg = ""; 4100 else if (bgep->param_link_up) 4101 msg = bgep->link_up_msg; 4102 else 4103 msg = bgep->link_down_msg; 4104 4105 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4106 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4107 } 4108 4109 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4110 #pragma no_inline(bge_factotum_link_check) 4111 4112 static boolean_t 4113 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4114 { 4115 boolean_t check; 4116 uint64_t flags; 4117 uint32_t tmac_status; 4118 4119 ASSERT(mutex_owned(bgep->genlock)); 4120 4121 /* 4122 * Get & clear the writable status bits in the Tx status register 4123 * (some bits are write-1-to-clear, others are just readonly). 4124 */ 4125 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4126 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4127 4128 /* 4129 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4130 */ 4131 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4132 STATUS_FLAG_LINK_CHANGED, &flags); 4133 if (*dma_state != DDI_FM_OK) 4134 return (B_FALSE); 4135 4136 /* 4137 * Clear any errors flagged in the status block ... 4138 */ 4139 if (flags & STATUS_FLAG_ERROR) 4140 bge_factotum_error_handler(bgep); 4141 4142 /* 4143 * We need to check the link status if: 4144 * the status block says there's been a link change 4145 * or there's any discrepancy between the various 4146 * flags indicating the link state (link_state, 4147 * param_link_up, and the LINK STATE bit in the 4148 * Transmit MAC status register). 4149 */ 4150 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4151 switch (bgep->link_state) { 4152 case LINK_STATE_UP: 4153 check |= (bgep->param_link_up == B_FALSE); 4154 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4155 break; 4156 4157 case LINK_STATE_DOWN: 4158 check |= (bgep->param_link_up != B_FALSE); 4159 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4160 break; 4161 4162 default: 4163 check = B_TRUE; 4164 break; 4165 } 4166 4167 /* 4168 * If <check> is false, we're sure the link hasn't changed. 4169 * If true, however, it's not yet definitive; we have to call 4170 * bge_phys_check() to determine whether the link has settled 4171 * into a new state yet ... and if it has, then call the link 4172 * state change handler.But when the chip is 5700 in Dell 6650 4173 * ,even if check is false, the link may have changed.So we 4174 * have to call bge_phys_check() to determine the link state. 4175 */ 4176 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4177 check = bge_phys_check(bgep); 4178 if (check) 4179 bge_factotum_link_handler(bgep); 4180 } 4181 4182 return (check); 4183 } 4184 4185 /* 4186 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4187 */ 4188 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4189 #pragma no_inline(bge_factotum_stall_check) 4190 4191 static boolean_t 4192 bge_factotum_stall_check(bge_t *bgep) 4193 { 4194 uint32_t dogval; 4195 4196 ASSERT(mutex_owned(bgep->genlock)); 4197 4198 /* 4199 * Specific check for Tx stall ... 4200 * 4201 * The 'watchdog' counter is incremented whenever a packet 4202 * is queued, reset to 1 when some (but not all) buffers 4203 * are reclaimed, reset to 0 (disabled) when all buffers 4204 * are reclaimed, and shifted left here. If it exceeds the 4205 * threshold value, the chip is assumed to have stalled and 4206 * is put into the ERROR state. The factotum will then reset 4207 * it on the next pass. 4208 * 4209 * All of which should ensure that we don't get into a state 4210 * where packets are left pending indefinitely! 4211 */ 4212 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4213 if (dogval < bge_watchdog_count) 4214 return (B_FALSE); 4215 4216 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4217 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4218 return (B_TRUE); 4219 } 4220 4221 /* 4222 * The factotum is woken up when there's something to do that we'd rather 4223 * not do from inside a hardware interrupt handler or high-level cyclic. 4224 * Its two main tasks are: 4225 * reset & restart the chip after an error 4226 * check the link status whenever necessary 4227 */ 4228 uint_t bge_chip_factotum(caddr_t arg); 4229 #pragma no_inline(bge_chip_factotum) 4230 4231 uint_t 4232 bge_chip_factotum(caddr_t arg) 4233 { 4234 bge_t *bgep; 4235 uint_t result; 4236 boolean_t error; 4237 boolean_t linkchg; 4238 int dma_state; 4239 4240 bgep = (bge_t *)arg; 4241 4242 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4243 4244 mutex_enter(bgep->softintrlock); 4245 if (bgep->factotum_flag == 0) { 4246 mutex_exit(bgep->softintrlock); 4247 return (DDI_INTR_UNCLAIMED); 4248 } 4249 bgep->factotum_flag = 0; 4250 mutex_exit(bgep->softintrlock); 4251 4252 result = DDI_INTR_CLAIMED; 4253 error = B_FALSE; 4254 linkchg = B_FALSE; 4255 4256 mutex_enter(bgep->genlock); 4257 switch (bgep->bge_chip_state) { 4258 default: 4259 break; 4260 4261 case BGE_CHIP_RUNNING: 4262 linkchg = bge_factotum_link_check(bgep, &dma_state); 4263 error = bge_factotum_stall_check(bgep); 4264 if (dma_state != DDI_FM_OK) { 4265 bgep->bge_dma_error = B_TRUE; 4266 error = B_TRUE; 4267 } 4268 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4269 error = B_TRUE; 4270 if (error) 4271 bgep->bge_chip_state = BGE_CHIP_ERROR; 4272 break; 4273 4274 case BGE_CHIP_ERROR: 4275 error = B_TRUE; 4276 break; 4277 4278 case BGE_CHIP_FAULT: 4279 /* 4280 * Fault detected, time to reset ... 4281 */ 4282 if (bge_autorecover) { 4283 if (!(bgep->progress & PROGRESS_BUFS)) { 4284 /* 4285 * if we can't allocate the ring buffers, 4286 * try later 4287 */ 4288 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4289 mutex_exit(bgep->genlock); 4290 return (result); 4291 } 4292 bgep->progress |= PROGRESS_BUFS; 4293 } 4294 if (!(bgep->progress & PROGRESS_INTR)) { 4295 bge_init_rings(bgep); 4296 bge_intr_enable(bgep); 4297 bgep->progress |= PROGRESS_INTR; 4298 } 4299 if (!(bgep->progress & PROGRESS_KSTATS)) { 4300 bge_init_kstats(bgep, 4301 ddi_get_instance(bgep->devinfo)); 4302 bgep->progress |= PROGRESS_KSTATS; 4303 } 4304 4305 BGE_REPORT((bgep, "automatic recovery activated")); 4306 4307 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4308 bgep->bge_chip_state = BGE_CHIP_ERROR; 4309 error = B_TRUE; 4310 } 4311 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4312 DDI_FM_OK) { 4313 bgep->bge_chip_state = BGE_CHIP_ERROR; 4314 error = B_TRUE; 4315 } 4316 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4317 DDI_FM_OK) { 4318 bgep->bge_chip_state = BGE_CHIP_ERROR; 4319 error = B_TRUE; 4320 } 4321 if (error == B_FALSE) { 4322 #ifdef BGE_IPMI_ASF 4323 if (bgep->asf_enabled && 4324 bgep->asf_status != ASF_STAT_RUN) { 4325 bgep->asf_timeout_id = timeout( 4326 bge_asf_heartbeat, (void *)bgep, 4327 drv_usectohz( 4328 BGE_ASF_HEARTBEAT_INTERVAL)); 4329 bgep->asf_status = ASF_STAT_RUN; 4330 } 4331 #endif 4332 ddi_fm_service_impact(bgep->devinfo, 4333 DDI_SERVICE_RESTORED); 4334 } 4335 } 4336 break; 4337 } 4338 4339 4340 /* 4341 * If an error is detected, stop the chip now, marking it as 4342 * faulty, so that it will be reset next time through ... 4343 * 4344 * Note that if intr_running is set, then bge_intr() has dropped 4345 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4346 * this point so have to wait until the next time the factotum runs. 4347 */ 4348 if (error && !bgep->bge_intr_running) { 4349 #ifdef BGE_IPMI_ASF 4350 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4351 /* 4352 * We must stop ASF heart beat before bge_chip_stop(), 4353 * otherwise some computers (ex. IBM HS20 blade server) 4354 * may crash. 4355 */ 4356 bge_asf_update_status(bgep); 4357 bge_asf_stop_timer(bgep); 4358 bgep->asf_status = ASF_STAT_STOP; 4359 4360 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4361 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4362 } 4363 #endif 4364 bge_chip_stop(bgep, B_TRUE); 4365 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4366 } 4367 mutex_exit(bgep->genlock); 4368 4369 /* 4370 * If the link state changed, tell the world about it. 4371 * Note: can't do this while still holding the mutex. 4372 */ 4373 if (linkchg) 4374 mac_link_update(bgep->mh, bgep->link_state); 4375 4376 return (result); 4377 } 4378 4379 /* 4380 * High-level cyclic handler 4381 * 4382 * This routine schedules a (low-level) softint callback to the 4383 * factotum, and prods the chip to update the status block (which 4384 * will cause a hardware interrupt when complete). 4385 */ 4386 void bge_chip_cyclic(void *arg); 4387 #pragma no_inline(bge_chip_cyclic) 4388 4389 void 4390 bge_chip_cyclic(void *arg) 4391 { 4392 bge_t *bgep; 4393 4394 bgep = arg; 4395 4396 switch (bgep->bge_chip_state) { 4397 default: 4398 return; 4399 4400 case BGE_CHIP_RUNNING: 4401 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4402 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4403 ddi_fm_service_impact(bgep->devinfo, 4404 DDI_SERVICE_UNAFFECTED); 4405 break; 4406 4407 case BGE_CHIP_FAULT: 4408 case BGE_CHIP_ERROR: 4409 break; 4410 } 4411 4412 bge_wake_factotum(bgep); 4413 } 4414 4415 4416 /* 4417 * ========== Ioctl subfunctions ========== 4418 */ 4419 4420 #undef BGE_DBG 4421 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4422 4423 #if BGE_DEBUGGING || BGE_DO_PPIO 4424 4425 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4426 #pragma no_inline(bge_chip_peek_cfg) 4427 4428 static void 4429 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4430 { 4431 uint64_t regval; 4432 uint64_t regno; 4433 4434 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4435 (void *)bgep, (void *)ppd)); 4436 4437 regno = ppd->pp_acc_offset; 4438 4439 switch (ppd->pp_acc_size) { 4440 case 1: 4441 regval = pci_config_get8(bgep->cfg_handle, regno); 4442 break; 4443 4444 case 2: 4445 regval = pci_config_get16(bgep->cfg_handle, regno); 4446 break; 4447 4448 case 4: 4449 regval = pci_config_get32(bgep->cfg_handle, regno); 4450 break; 4451 4452 case 8: 4453 regval = pci_config_get64(bgep->cfg_handle, regno); 4454 break; 4455 } 4456 4457 ppd->pp_acc_data = regval; 4458 } 4459 4460 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4461 #pragma no_inline(bge_chip_poke_cfg) 4462 4463 static void 4464 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4465 { 4466 uint64_t regval; 4467 uint64_t regno; 4468 4469 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4470 (void *)bgep, (void *)ppd)); 4471 4472 regno = ppd->pp_acc_offset; 4473 regval = ppd->pp_acc_data; 4474 4475 switch (ppd->pp_acc_size) { 4476 case 1: 4477 pci_config_put8(bgep->cfg_handle, regno, regval); 4478 break; 4479 4480 case 2: 4481 pci_config_put16(bgep->cfg_handle, regno, regval); 4482 break; 4483 4484 case 4: 4485 pci_config_put32(bgep->cfg_handle, regno, regval); 4486 break; 4487 4488 case 8: 4489 pci_config_put64(bgep->cfg_handle, regno, regval); 4490 break; 4491 } 4492 } 4493 4494 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4495 #pragma no_inline(bge_chip_peek_reg) 4496 4497 static void 4498 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4499 { 4500 uint64_t regval; 4501 void *regaddr; 4502 4503 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4504 (void *)bgep, (void *)ppd)); 4505 4506 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4507 4508 switch (ppd->pp_acc_size) { 4509 case 1: 4510 regval = ddi_get8(bgep->io_handle, regaddr); 4511 break; 4512 4513 case 2: 4514 regval = ddi_get16(bgep->io_handle, regaddr); 4515 break; 4516 4517 case 4: 4518 regval = ddi_get32(bgep->io_handle, regaddr); 4519 break; 4520 4521 case 8: 4522 regval = ddi_get64(bgep->io_handle, regaddr); 4523 break; 4524 } 4525 4526 ppd->pp_acc_data = regval; 4527 } 4528 4529 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4530 #pragma no_inline(bge_chip_peek_reg) 4531 4532 static void 4533 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4534 { 4535 uint64_t regval; 4536 void *regaddr; 4537 4538 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4539 (void *)bgep, (void *)ppd)); 4540 4541 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4542 regval = ppd->pp_acc_data; 4543 4544 switch (ppd->pp_acc_size) { 4545 case 1: 4546 ddi_put8(bgep->io_handle, regaddr, regval); 4547 break; 4548 4549 case 2: 4550 ddi_put16(bgep->io_handle, regaddr, regval); 4551 break; 4552 4553 case 4: 4554 ddi_put32(bgep->io_handle, regaddr, regval); 4555 break; 4556 4557 case 8: 4558 ddi_put64(bgep->io_handle, regaddr, regval); 4559 break; 4560 } 4561 BGE_PCICHK(bgep); 4562 } 4563 4564 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4565 #pragma no_inline(bge_chip_peek_nic) 4566 4567 static void 4568 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4569 { 4570 uint64_t regoff; 4571 uint64_t regval; 4572 void *regaddr; 4573 4574 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4575 (void *)bgep, (void *)ppd)); 4576 4577 regoff = ppd->pp_acc_offset; 4578 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4579 regoff &= MWBAR_GRANULE_MASK; 4580 regoff += NIC_MEM_WINDOW_OFFSET; 4581 regaddr = PIO_ADDR(bgep, regoff); 4582 4583 switch (ppd->pp_acc_size) { 4584 case 1: 4585 regval = ddi_get8(bgep->io_handle, regaddr); 4586 break; 4587 4588 case 2: 4589 regval = ddi_get16(bgep->io_handle, regaddr); 4590 break; 4591 4592 case 4: 4593 regval = ddi_get32(bgep->io_handle, regaddr); 4594 break; 4595 4596 case 8: 4597 regval = ddi_get64(bgep->io_handle, regaddr); 4598 break; 4599 } 4600 4601 ppd->pp_acc_data = regval; 4602 } 4603 4604 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4605 #pragma no_inline(bge_chip_poke_nic) 4606 4607 static void 4608 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4609 { 4610 uint64_t regoff; 4611 uint64_t regval; 4612 void *regaddr; 4613 4614 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4615 (void *)bgep, (void *)ppd)); 4616 4617 regoff = ppd->pp_acc_offset; 4618 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4619 regoff &= MWBAR_GRANULE_MASK; 4620 regoff += NIC_MEM_WINDOW_OFFSET; 4621 regaddr = PIO_ADDR(bgep, regoff); 4622 regval = ppd->pp_acc_data; 4623 4624 switch (ppd->pp_acc_size) { 4625 case 1: 4626 ddi_put8(bgep->io_handle, regaddr, regval); 4627 break; 4628 4629 case 2: 4630 ddi_put16(bgep->io_handle, regaddr, regval); 4631 break; 4632 4633 case 4: 4634 ddi_put32(bgep->io_handle, regaddr, regval); 4635 break; 4636 4637 case 8: 4638 ddi_put64(bgep->io_handle, regaddr, regval); 4639 break; 4640 } 4641 BGE_PCICHK(bgep); 4642 } 4643 4644 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4645 #pragma no_inline(bge_chip_peek_mii) 4646 4647 static void 4648 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4649 { 4650 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4651 (void *)bgep, (void *)ppd)); 4652 4653 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4654 } 4655 4656 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4657 #pragma no_inline(bge_chip_poke_mii) 4658 4659 static void 4660 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4661 { 4662 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4663 (void *)bgep, (void *)ppd)); 4664 4665 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4666 } 4667 4668 #if BGE_SEE_IO32 4669 4670 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4671 #pragma no_inline(bge_chip_peek_seeprom) 4672 4673 static void 4674 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4675 { 4676 uint32_t data; 4677 int err; 4678 4679 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4680 (void *)bgep, (void *)ppd)); 4681 4682 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4683 ppd->pp_acc_data = err ? ~0ull : data; 4684 } 4685 4686 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4687 #pragma no_inline(bge_chip_poke_seeprom) 4688 4689 static void 4690 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4691 { 4692 uint32_t data; 4693 4694 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4695 (void *)bgep, (void *)ppd)); 4696 4697 data = ppd->pp_acc_data; 4698 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4699 } 4700 #endif /* BGE_SEE_IO32 */ 4701 4702 #if BGE_FLASH_IO32 4703 4704 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4705 #pragma no_inline(bge_chip_peek_flash) 4706 4707 static void 4708 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4709 { 4710 uint32_t data; 4711 int err; 4712 4713 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4714 (void *)bgep, (void *)ppd)); 4715 4716 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4717 ppd->pp_acc_data = err ? ~0ull : data; 4718 } 4719 4720 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4721 #pragma no_inline(bge_chip_poke_flash) 4722 4723 static void 4724 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4725 { 4726 uint32_t data; 4727 4728 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4729 (void *)bgep, (void *)ppd)); 4730 4731 data = ppd->pp_acc_data; 4732 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4733 ppd->pp_acc_offset, &data); 4734 } 4735 #endif /* BGE_FLASH_IO32 */ 4736 4737 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4738 #pragma no_inline(bge_chip_peek_mem) 4739 4740 static void 4741 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4742 { 4743 uint64_t regval; 4744 void *vaddr; 4745 4746 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4747 (void *)bgep, (void *)ppd)); 4748 4749 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4750 4751 switch (ppd->pp_acc_size) { 4752 case 1: 4753 regval = *(uint8_t *)vaddr; 4754 break; 4755 4756 case 2: 4757 regval = *(uint16_t *)vaddr; 4758 break; 4759 4760 case 4: 4761 regval = *(uint32_t *)vaddr; 4762 break; 4763 4764 case 8: 4765 regval = *(uint64_t *)vaddr; 4766 break; 4767 } 4768 4769 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4770 (void *)bgep, (void *)ppd, regval, vaddr)); 4771 4772 ppd->pp_acc_data = regval; 4773 } 4774 4775 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4776 #pragma no_inline(bge_chip_poke_mem) 4777 4778 static void 4779 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4780 { 4781 uint64_t regval; 4782 void *vaddr; 4783 4784 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4785 (void *)bgep, (void *)ppd)); 4786 4787 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4788 regval = ppd->pp_acc_data; 4789 4790 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4791 (void *)bgep, (void *)ppd, regval, vaddr)); 4792 4793 switch (ppd->pp_acc_size) { 4794 case 1: 4795 *(uint8_t *)vaddr = (uint8_t)regval; 4796 break; 4797 4798 case 2: 4799 *(uint16_t *)vaddr = (uint16_t)regval; 4800 break; 4801 4802 case 4: 4803 *(uint32_t *)vaddr = (uint32_t)regval; 4804 break; 4805 4806 case 8: 4807 *(uint64_t *)vaddr = (uint64_t)regval; 4808 break; 4809 } 4810 } 4811 4812 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4813 struct iocblk *iocp); 4814 #pragma no_inline(bge_pp_ioctl) 4815 4816 static enum ioc_reply 4817 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4818 { 4819 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4820 bge_peekpoke_t *ppd; 4821 dma_area_t *areap; 4822 uint64_t sizemask; 4823 uint64_t mem_va; 4824 uint64_t maxoff; 4825 boolean_t peek; 4826 4827 switch (cmd) { 4828 default: 4829 /* NOTREACHED */ 4830 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4831 return (IOC_INVAL); 4832 4833 case BGE_PEEK: 4834 peek = B_TRUE; 4835 break; 4836 4837 case BGE_POKE: 4838 peek = B_FALSE; 4839 break; 4840 } 4841 4842 /* 4843 * Validate format of ioctl 4844 */ 4845 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4846 return (IOC_INVAL); 4847 if (mp->b_cont == NULL) 4848 return (IOC_INVAL); 4849 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4850 4851 /* 4852 * Validate request parameters 4853 */ 4854 switch (ppd->pp_acc_space) { 4855 default: 4856 return (IOC_INVAL); 4857 4858 case BGE_PP_SPACE_CFG: 4859 /* 4860 * Config space 4861 */ 4862 sizemask = 8|4|2|1; 4863 mem_va = 0; 4864 maxoff = PCI_CONF_HDR_SIZE; 4865 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4866 break; 4867 4868 case BGE_PP_SPACE_REG: 4869 /* 4870 * Memory-mapped I/O space 4871 */ 4872 sizemask = 8|4|2|1; 4873 mem_va = 0; 4874 maxoff = RIAAR_REGISTER_MAX; 4875 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4876 break; 4877 4878 case BGE_PP_SPACE_NIC: 4879 /* 4880 * NIC on-chip memory 4881 */ 4882 sizemask = 8|4|2|1; 4883 mem_va = 0; 4884 maxoff = MWBAR_ONCHIP_MAX; 4885 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4886 break; 4887 4888 case BGE_PP_SPACE_MII: 4889 /* 4890 * PHY's MII registers 4891 * NB: all PHY registers are two bytes, but the 4892 * addresses increment in ones (word addressing). 4893 * So we scale the address here, then undo the 4894 * transformation inside the peek/poke functions. 4895 */ 4896 ppd->pp_acc_offset *= 2; 4897 sizemask = 2; 4898 mem_va = 0; 4899 maxoff = (MII_MAXREG+1)*2; 4900 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4901 break; 4902 4903 #if BGE_SEE_IO32 4904 case BGE_PP_SPACE_SEEPROM: 4905 /* 4906 * Attached SEEPROM(s), if any. 4907 * NB: we use the high-order bits of the 'address' as 4908 * a device select to accommodate multiple SEEPROMS, 4909 * If each one is the maximum size (64kbytes), this 4910 * makes them appear contiguous. Otherwise, there may 4911 * be holes in the mapping. ENxS doesn't have any 4912 * SEEPROMs anyway ... 4913 */ 4914 sizemask = 4; 4915 mem_va = 0; 4916 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4917 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4918 break; 4919 #endif /* BGE_SEE_IO32 */ 4920 4921 #if BGE_FLASH_IO32 4922 case BGE_PP_SPACE_FLASH: 4923 /* 4924 * Attached Flash device (if any); a maximum of one device 4925 * is currently supported. But it can be up to 1MB (unlike 4926 * the 64k limit on SEEPROMs) so why would you need more ;-) 4927 */ 4928 sizemask = 4; 4929 mem_va = 0; 4930 maxoff = NVM_FLASH_ADDR_MASK; 4931 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4932 break; 4933 #endif /* BGE_FLASH_IO32 */ 4934 4935 case BGE_PP_SPACE_BGE: 4936 /* 4937 * BGE data structure! 4938 */ 4939 sizemask = 8|4|2|1; 4940 mem_va = (uintptr_t)bgep; 4941 maxoff = sizeof (*bgep); 4942 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4943 break; 4944 4945 case BGE_PP_SPACE_STATUS: 4946 case BGE_PP_SPACE_STATISTICS: 4947 case BGE_PP_SPACE_TXDESC: 4948 case BGE_PP_SPACE_TXBUFF: 4949 case BGE_PP_SPACE_RXDESC: 4950 case BGE_PP_SPACE_RXBUFF: 4951 /* 4952 * Various DMA_AREAs 4953 */ 4954 switch (ppd->pp_acc_space) { 4955 case BGE_PP_SPACE_TXDESC: 4956 areap = &bgep->tx_desc; 4957 break; 4958 case BGE_PP_SPACE_TXBUFF: 4959 areap = &bgep->tx_buff[0]; 4960 break; 4961 case BGE_PP_SPACE_RXDESC: 4962 areap = &bgep->rx_desc[0]; 4963 break; 4964 case BGE_PP_SPACE_RXBUFF: 4965 areap = &bgep->rx_buff[0]; 4966 break; 4967 case BGE_PP_SPACE_STATUS: 4968 areap = &bgep->status_block; 4969 break; 4970 case BGE_PP_SPACE_STATISTICS: 4971 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4972 areap = &bgep->statistics; 4973 break; 4974 } 4975 4976 sizemask = 8|4|2|1; 4977 mem_va = (uintptr_t)areap->mem_va; 4978 maxoff = areap->alength; 4979 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4980 break; 4981 } 4982 4983 switch (ppd->pp_acc_size) { 4984 default: 4985 return (IOC_INVAL); 4986 4987 case 8: 4988 case 4: 4989 case 2: 4990 case 1: 4991 if ((ppd->pp_acc_size & sizemask) == 0) 4992 return (IOC_INVAL); 4993 break; 4994 } 4995 4996 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4997 return (IOC_INVAL); 4998 4999 if (ppd->pp_acc_offset >= maxoff) 5000 return (IOC_INVAL); 5001 5002 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5003 return (IOC_INVAL); 5004 5005 /* 5006 * All OK - go do it! 5007 */ 5008 ppd->pp_acc_offset += mem_va; 5009 (*ppfn)(bgep, ppd); 5010 return (peek ? IOC_REPLY : IOC_ACK); 5011 } 5012 5013 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5014 struct iocblk *iocp); 5015 #pragma no_inline(bge_diag_ioctl) 5016 5017 static enum ioc_reply 5018 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5019 { 5020 ASSERT(mutex_owned(bgep->genlock)); 5021 5022 switch (cmd) { 5023 default: 5024 /* NOTREACHED */ 5025 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5026 return (IOC_INVAL); 5027 5028 case BGE_DIAG: 5029 /* 5030 * Currently a no-op 5031 */ 5032 return (IOC_ACK); 5033 5034 case BGE_PEEK: 5035 case BGE_POKE: 5036 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5037 5038 case BGE_PHY_RESET: 5039 return (IOC_RESTART_ACK); 5040 5041 case BGE_SOFT_RESET: 5042 case BGE_HARD_RESET: 5043 /* 5044 * Reset and reinitialise the 570x hardware 5045 */ 5046 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5047 return (IOC_ACK); 5048 } 5049 5050 /* NOTREACHED */ 5051 } 5052 5053 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5054 5055 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5056 struct iocblk *iocp); 5057 #pragma no_inline(bge_mii_ioctl) 5058 5059 static enum ioc_reply 5060 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5061 { 5062 struct bge_mii_rw *miirwp; 5063 5064 /* 5065 * Validate format of ioctl 5066 */ 5067 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5068 return (IOC_INVAL); 5069 if (mp->b_cont == NULL) 5070 return (IOC_INVAL); 5071 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5072 5073 /* 5074 * Validate request parameters ... 5075 */ 5076 if (miirwp->mii_reg > MII_MAXREG) 5077 return (IOC_INVAL); 5078 5079 switch (cmd) { 5080 default: 5081 /* NOTREACHED */ 5082 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5083 return (IOC_INVAL); 5084 5085 case BGE_MII_READ: 5086 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5087 return (IOC_REPLY); 5088 5089 case BGE_MII_WRITE: 5090 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5091 return (IOC_ACK); 5092 } 5093 5094 /* NOTREACHED */ 5095 } 5096 5097 #if BGE_SEE_IO32 5098 5099 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5100 struct iocblk *iocp); 5101 #pragma no_inline(bge_see_ioctl) 5102 5103 static enum ioc_reply 5104 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5105 { 5106 struct bge_see_rw *seerwp; 5107 5108 /* 5109 * Validate format of ioctl 5110 */ 5111 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5112 return (IOC_INVAL); 5113 if (mp->b_cont == NULL) 5114 return (IOC_INVAL); 5115 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5116 5117 /* 5118 * Validate request parameters ... 5119 */ 5120 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5121 return (IOC_INVAL); 5122 5123 switch (cmd) { 5124 default: 5125 /* NOTREACHED */ 5126 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5127 return (IOC_INVAL); 5128 5129 case BGE_SEE_READ: 5130 case BGE_SEE_WRITE: 5131 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5132 seerwp->see_addr, &seerwp->see_data); 5133 return (IOC_REPLY); 5134 } 5135 5136 /* NOTREACHED */ 5137 } 5138 5139 #endif /* BGE_SEE_IO32 */ 5140 5141 #if BGE_FLASH_IO32 5142 5143 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5144 struct iocblk *iocp); 5145 #pragma no_inline(bge_flash_ioctl) 5146 5147 static enum ioc_reply 5148 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5149 { 5150 struct bge_flash_rw *flashrwp; 5151 5152 /* 5153 * Validate format of ioctl 5154 */ 5155 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5156 return (IOC_INVAL); 5157 if (mp->b_cont == NULL) 5158 return (IOC_INVAL); 5159 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5160 5161 /* 5162 * Validate request parameters ... 5163 */ 5164 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5165 return (IOC_INVAL); 5166 5167 switch (cmd) { 5168 default: 5169 /* NOTREACHED */ 5170 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5171 return (IOC_INVAL); 5172 5173 case BGE_FLASH_READ: 5174 case BGE_FLASH_WRITE: 5175 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5176 flashrwp->flash_addr, &flashrwp->flash_data); 5177 return (IOC_REPLY); 5178 } 5179 5180 /* NOTREACHED */ 5181 } 5182 5183 #endif /* BGE_FLASH_IO32 */ 5184 5185 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5186 struct iocblk *iocp); 5187 #pragma no_inline(bge_chip_ioctl) 5188 5189 enum ioc_reply 5190 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5191 { 5192 int cmd; 5193 5194 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5195 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5196 5197 ASSERT(mutex_owned(bgep->genlock)); 5198 5199 cmd = iocp->ioc_cmd; 5200 switch (cmd) { 5201 default: 5202 /* NOTREACHED */ 5203 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5204 return (IOC_INVAL); 5205 5206 case BGE_DIAG: 5207 case BGE_PEEK: 5208 case BGE_POKE: 5209 case BGE_PHY_RESET: 5210 case BGE_SOFT_RESET: 5211 case BGE_HARD_RESET: 5212 #if BGE_DEBUGGING || BGE_DO_PPIO 5213 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5214 #else 5215 return (IOC_INVAL); 5216 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5217 5218 case BGE_MII_READ: 5219 case BGE_MII_WRITE: 5220 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5221 5222 #if BGE_SEE_IO32 5223 case BGE_SEE_READ: 5224 case BGE_SEE_WRITE: 5225 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5226 #endif /* BGE_SEE_IO32 */ 5227 5228 #if BGE_FLASH_IO32 5229 case BGE_FLASH_READ: 5230 case BGE_FLASH_WRITE: 5231 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5232 #endif /* BGE_FLASH_IO32 */ 5233 } 5234 5235 /* NOTREACHED */ 5236 } 5237 5238 void 5239 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5240 { 5241 bge_t *bgep = arg; 5242 5243 mutex_enter(bgep->genlock); 5244 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5245 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5246 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5247 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5248 mutex_exit(bgep->genlock); 5249 } 5250 5251 #ifdef BGE_IPMI_ASF 5252 5253 uint32_t 5254 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5255 { 5256 uint32_t data; 5257 5258 if (!bgep->asf_wordswapped) { 5259 /* a workaround word swap error */ 5260 if (addr & 4) 5261 addr = addr - 4; 5262 else 5263 addr = addr + 4; 5264 } 5265 5266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5267 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5268 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5269 5270 return (data); 5271 } 5272 5273 5274 void 5275 bge_asf_update_status(bge_t *bgep) 5276 { 5277 uint32_t event; 5278 5279 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5280 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5281 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5282 5283 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5284 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5285 } 5286 5287 5288 /* 5289 * The driver is supposed to notify ASF that the OS is still running 5290 * every three seconds, otherwise the management server may attempt 5291 * to reboot the machine. If it hasn't actually failed, this is 5292 * not a desirable result. However, this isn't running as a real-time 5293 * thread, and even if it were, it might not be able to generate the 5294 * heartbeat in a timely manner due to system load. As it isn't a 5295 * significant strain on the machine, we will set the interval to half 5296 * of the required value. 5297 */ 5298 void 5299 bge_asf_heartbeat(void *arg) 5300 { 5301 bge_t *bgep = (bge_t *)arg; 5302 5303 mutex_enter(bgep->genlock); 5304 bge_asf_update_status((bge_t *)bgep); 5305 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5306 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5307 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5308 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5309 mutex_exit(bgep->genlock); 5310 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5311 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5312 } 5313 5314 5315 void 5316 bge_asf_stop_timer(bge_t *bgep) 5317 { 5318 timeout_id_t tmp_id = 0; 5319 5320 while ((bgep->asf_timeout_id != 0) && 5321 (tmp_id != bgep->asf_timeout_id)) { 5322 tmp_id = bgep->asf_timeout_id; 5323 (void) untimeout(tmp_id); 5324 } 5325 bgep->asf_timeout_id = 0; 5326 } 5327 5328 5329 5330 /* 5331 * This function should be placed at the earliest position of bge_attach(). 5332 */ 5333 void 5334 bge_asf_get_config(bge_t *bgep) 5335 { 5336 uint32_t nicsig; 5337 uint32_t niccfg; 5338 5339 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5340 if (nicsig == BGE_NIC_DATA_SIG) { 5341 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5342 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5343 /* 5344 * Here, we don't consider BAXTER, because BGE haven't 5345 * supported BAXTER (that is 5752). Also, as I know, 5346 * BAXTER doesn't support ASF feature. 5347 */ 5348 bgep->asf_enabled = B_TRUE; 5349 else 5350 bgep->asf_enabled = B_FALSE; 5351 } else 5352 bgep->asf_enabled = B_FALSE; 5353 } 5354 5355 5356 void 5357 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5358 { 5359 uint32_t tries; 5360 uint32_t event; 5361 5362 ASSERT(bgep->asf_enabled); 5363 5364 /* Issues "pause firmware" command and wait for ACK */ 5365 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5366 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5367 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5368 5369 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5370 tries = 0; 5371 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5372 drv_usecwait(1); 5373 tries ++; 5374 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5375 } 5376 5377 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5378 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5379 5380 if (bgep->asf_newhandshake) { 5381 switch (mode) { 5382 case BGE_INIT_RESET: 5383 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5384 BGE_DRV_STATE_START); 5385 break; 5386 case BGE_SHUTDOWN_RESET: 5387 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5388 BGE_DRV_STATE_UNLOAD); 5389 break; 5390 case BGE_SUSPEND_RESET: 5391 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5392 BGE_DRV_STATE_SUSPEND); 5393 break; 5394 default: 5395 break; 5396 } 5397 } 5398 } 5399 5400 5401 void 5402 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5403 { 5404 switch (mode) { 5405 case BGE_INIT_RESET: 5406 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5407 BGE_DRV_STATE_START); 5408 break; 5409 case BGE_SHUTDOWN_RESET: 5410 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5411 BGE_DRV_STATE_UNLOAD); 5412 break; 5413 case BGE_SUSPEND_RESET: 5414 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5415 BGE_DRV_STATE_SUSPEND); 5416 break; 5417 default: 5418 break; 5419 } 5420 } 5421 5422 5423 void 5424 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5425 { 5426 switch (mode) { 5427 case BGE_INIT_RESET: 5428 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5429 BGE_DRV_STATE_START_DONE); 5430 break; 5431 case BGE_SHUTDOWN_RESET: 5432 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5433 BGE_DRV_STATE_UNLOAD_DONE); 5434 break; 5435 default: 5436 break; 5437 } 5438 } 5439 5440 #endif /* BGE_IPMI_ASF */ 5441