1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transaction related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (e.g. tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 */ 542 command = bgep->chipid.command | PCI_COMM_MAE; 543 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 544 if (enable_dma) 545 command |= PCI_COMM_ME; 546 /* 547 * on BCM5714 revision A0, false parity error gets generated 548 * due to a logic bug. Provide a workaround by disabling parity 549 * error. 550 */ 551 if (((cidp->device == DEVICE_ID_5714C) || 552 (cidp->device == DEVICE_ID_5714S)) && 553 (cidp->revision == REVISION_ID_5714_A0)) { 554 command &= ~PCI_COMM_PARITY_DETECT; 555 } 556 pci_config_put16(handle, PCI_CONF_COMM, command); 557 558 /* 559 * On some PCI-E device, there were instances when 560 * the device was still link training. 561 */ 562 if (bgep->chipid.pci_type == BGE_PCI_E) { 563 i = 0; 564 value16 = pci_config_get16(handle, PCI_CONF_COMM); 565 while ((value16 != command) && (i < 100)) { 566 drv_usecwait(200); 567 value16 = pci_config_get16(handle, PCI_CONF_COMM); 568 ++i; 569 } 570 } 571 572 /* 573 * Clear any remaining error status bits 574 */ 575 pci_config_put16(handle, PCI_CONF_STAT, ~0); 576 577 /* 578 * Do following if and only if the device is NOT BCM5714C OR 579 * BCM5715C 580 */ 581 if (!((cidp->device == DEVICE_ID_5714C) || 582 (cidp->device == DEVICE_ID_5715C))) { 583 /* 584 * Make sure these indirect-access registers are sane 585 * rather than random after power-up or reset 586 */ 587 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 588 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 589 } 590 /* 591 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 592 */ 593 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 594 595 if (cidp->pci_type == BGE_PCI_E) 596 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 597 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 598 } 599 600 #ifdef __amd64 601 /* 602 * Distinguish CPU types 603 * 604 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 605 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 606 * for PCI-Express based network interface card. This is the work-around 607 * for those nics. 608 */ 609 static boolean_t bge_get_em64t_type(void); 610 #pragma inline(bge_get_em64t_type) 611 612 static boolean_t 613 bge_get_em64t_type(void) 614 { 615 616 return (x86_vendor == X86_VENDOR_Intel); 617 } 618 #endif 619 620 /* 621 * Operating register get/set access routines 622 */ 623 624 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 625 #pragma inline(bge_reg_get32) 626 627 uint32_t 628 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 629 { 630 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 631 (void *)bgep, regno)); 632 633 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 634 } 635 636 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 637 #pragma inline(bge_reg_put32) 638 639 void 640 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 641 { 642 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 643 (void *)bgep, regno, data)); 644 645 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 646 BGE_PCICHK(bgep); 647 } 648 649 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 650 #pragma inline(bge_reg_set32) 651 652 void 653 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 654 { 655 uint32_t regval; 656 657 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 658 (void *)bgep, regno, bits)); 659 660 regval = bge_reg_get32(bgep, regno); 661 regval |= bits; 662 bge_reg_put32(bgep, regno, regval); 663 } 664 665 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 666 #pragma inline(bge_reg_clr32) 667 668 void 669 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 670 { 671 uint32_t regval; 672 673 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 674 (void *)bgep, regno, bits)); 675 676 regval = bge_reg_get32(bgep, regno); 677 regval &= ~bits; 678 bge_reg_put32(bgep, regno, regval); 679 } 680 681 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 682 #pragma inline(bge_reg_get64) 683 684 static uint64_t 685 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 686 { 687 uint64_t regval; 688 689 #ifdef __amd64 690 if (bge_get_em64t_type()) { 691 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 692 regval <<= 32; 693 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 } else { 695 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 696 } 697 #else 698 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 699 #endif 700 701 #ifdef _LITTLE_ENDIAN 702 regval = (regval >> 32) | (regval << 32); 703 #endif /* _LITTLE_ENDIAN */ 704 705 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 706 (void *)bgep, regno, regval)); 707 708 return (regval); 709 } 710 711 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 712 #pragma inline(bge_reg_put64) 713 714 static void 715 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 716 { 717 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 718 (void *)bgep, regno, data)); 719 720 #ifdef _LITTLE_ENDIAN 721 data = ((data >> 32) | (data << 32)); 722 #endif /* _LITTLE_ENDIAN */ 723 724 #ifdef __amd64 725 if (bge_get_em64t_type()) { 726 ddi_put32(bgep->io_handle, 727 PIO_ADDR(bgep, regno), (uint32_t)data); 728 BGE_PCICHK(bgep); 729 ddi_put32(bgep->io_handle, 730 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 731 732 } else { 733 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 734 } 735 #else 736 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 737 #endif 738 739 BGE_PCICHK(bgep); 740 } 741 742 /* 743 * The DDI doesn't provide get/put functions for 128 bit data 744 * so we put RCBs out as two 64-bit chunks instead. 745 */ 746 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 747 #pragma inline(bge_reg_putrcb) 748 749 static void 750 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 751 { 752 uint64_t *p; 753 754 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 755 (void *)bgep, addr, rcbp->host_ring_addr, 756 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 757 758 ASSERT((addr % sizeof (*rcbp)) == 0); 759 760 p = (void *)rcbp; 761 bge_reg_put64(bgep, addr, *p++); 762 bge_reg_put64(bgep, addr+8, *p); 763 } 764 765 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 766 #pragma inline(bge_mbx_put) 767 768 void 769 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 770 { 771 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 772 (void *)bgep, regno, data)); 773 774 /* 775 * Mailbox registers are nominally 64 bits on the 5701, but 776 * the MSW isn't used. On the 5703, they're only 32 bits 777 * anyway. So here we just write the lower(!) 32 bits - 778 * remembering that the chip is big-endian, even though the 779 * PCI bus is little-endian ... 780 */ 781 #ifdef _BIG_ENDIAN 782 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 783 #else 784 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 785 #endif /* _BIG_ENDIAN */ 786 BGE_PCICHK(bgep); 787 } 788 789 #if BGE_DEBUGGING 790 791 void bge_led_mark(bge_t *bgep); 792 #pragma no_inline(bge_led_mark) 793 794 void 795 bge_led_mark(bge_t *bgep) 796 { 797 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 798 LED_CONTROL_1000MBPS_LED | 799 LED_CONTROL_100MBPS_LED | 800 LED_CONTROL_10MBPS_LED; 801 802 /* 803 * Blink all three LINK LEDs on simultaneously, then all off, 804 * then restore to automatic hardware control. This is used 805 * in laboratory testing to trigger a logic analyser or scope. 806 */ 807 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 808 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 809 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 810 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 811 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 812 } 813 814 #endif /* BGE_DEBUGGING */ 815 816 /* 817 * NIC on-chip memory access routines 818 * 819 * Only 32K of NIC memory is visible at a time, controlled by the 820 * Memory Window Base Address Register (in PCI config space). Once 821 * this is set, the 32K region of NIC-local memory that it refers 822 * to can be directly addressed in the upper 32K of the 64K of PCI 823 * memory space used for the device. 824 */ 825 826 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 827 #pragma inline(bge_nic_setwin) 828 829 static void 830 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 831 { 832 chip_id_t *cidp; 833 834 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 835 (void *)bgep, base)); 836 837 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 838 839 /* 840 * Don't do repeated zero data writes, 841 * if the device is BCM5714C/15C. 842 */ 843 cidp = &bgep->chipid; 844 if ((cidp->device == DEVICE_ID_5714C) || 845 (cidp->device == DEVICE_ID_5715C)) { 846 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 847 return; 848 /* Adjust lastWriteZeroData */ 849 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 850 B_TRUE : B_FALSE); 851 } 852 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 853 } 854 855 856 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 857 #pragma inline(bge_nic_get32) 858 859 static uint32_t 860 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 861 { 862 uint32_t data; 863 864 #ifdef BGE_IPMI_ASF 865 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 866 /* workaround for word swap error */ 867 if (addr & 4) 868 addr = addr - 4; 869 else 870 addr = addr + 4; 871 } 872 #endif 873 874 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 875 addr &= MWBAR_GRANULE_MASK; 876 addr += NIC_MEM_WINDOW_OFFSET; 877 878 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 879 880 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 881 (void *)bgep, addr, data)); 882 883 return (data); 884 } 885 886 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 887 #pragma inline(bge_nic_put32) 888 889 void 890 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 891 { 892 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 893 (void *)bgep, addr, data)); 894 895 #ifdef BGE_IPMI_ASF 896 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 897 /* workaround for word swap error */ 898 if (addr & 4) 899 addr = addr - 4; 900 else 901 addr = addr + 4; 902 } 903 #endif 904 905 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 906 addr &= MWBAR_GRANULE_MASK; 907 addr += NIC_MEM_WINDOW_OFFSET; 908 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 909 BGE_PCICHK(bgep); 910 } 911 912 913 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 914 #pragma inline(bge_nic_get64) 915 916 static uint64_t 917 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 918 { 919 uint64_t data; 920 921 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 922 addr &= MWBAR_GRANULE_MASK; 923 addr += NIC_MEM_WINDOW_OFFSET; 924 925 #ifdef __amd64 926 if (bge_get_em64t_type()) { 927 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 928 data <<= 32; 929 data |= ddi_get32(bgep->io_handle, 930 PIO_ADDR(bgep, addr + 4)); 931 } else { 932 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 933 } 934 #else 935 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 936 #endif 937 938 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 939 (void *)bgep, addr, data)); 940 941 return (data); 942 } 943 944 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 945 #pragma inline(bge_nic_put64) 946 947 static void 948 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 949 { 950 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 951 (void *)bgep, addr, data)); 952 953 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 954 addr &= MWBAR_GRANULE_MASK; 955 addr += NIC_MEM_WINDOW_OFFSET; 956 957 #ifdef __amd64 958 if (bge_get_em64t_type()) { 959 ddi_put32(bgep->io_handle, 960 PIO_ADDR(bgep, addr), (uint32_t)data); 961 BGE_PCICHK(bgep); 962 ddi_put32(bgep->io_handle, 963 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 966 } 967 #else 968 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 969 #endif 970 971 BGE_PCICHK(bgep); 972 } 973 974 /* 975 * The DDI doesn't provide get/put functions for 128 bit data 976 * so we put RCBs out as two 64-bit chunks instead. 977 */ 978 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 979 #pragma inline(bge_nic_putrcb) 980 981 static void 982 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 983 { 984 uint64_t *p; 985 986 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 987 (void *)bgep, addr, rcbp->host_ring_addr, 988 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 989 990 ASSERT((addr % sizeof (*rcbp)) == 0); 991 992 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 993 addr &= MWBAR_GRANULE_MASK; 994 addr += NIC_MEM_WINDOW_OFFSET; 995 996 p = (void *)rcbp; 997 #ifdef __amd64 998 if (bge_get_em64t_type()) { 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1000 (uint32_t)(*p)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1002 (uint32_t)(*p >> 32)); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1004 (uint32_t)(*(p + 1))); 1005 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1006 (uint32_t)(*p >> 32)); 1007 1008 } else { 1009 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1010 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1011 } 1012 #else 1013 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1014 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1015 #endif 1016 1017 BGE_PCICHK(bgep); 1018 } 1019 1020 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1021 #pragma inline(bge_nic_zero) 1022 1023 static void 1024 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1025 { 1026 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1027 (void *)bgep, addr, nbytes)); 1028 1029 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1030 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1031 1032 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1033 addr &= MWBAR_GRANULE_MASK; 1034 addr += NIC_MEM_WINDOW_OFFSET; 1035 1036 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1037 nbytes, 1, DDI_DATA_SZ08_ACC); 1038 BGE_PCICHK(bgep); 1039 } 1040 1041 /* 1042 * MII (PHY) register get/set access routines 1043 * 1044 * These use the chip's MII auto-access method, controlled by the 1045 * MII Communication register at 0x044c, so the CPU doesn't have 1046 * to fiddle with the individual bits. 1047 */ 1048 1049 #undef BGE_DBG 1050 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1051 1052 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1053 uint16_t data, uint32_t cmd); 1054 #pragma no_inline(bge_mii_access) 1055 1056 static uint16_t 1057 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1058 { 1059 uint32_t timeout; 1060 uint32_t regval1; 1061 uint32_t regval2; 1062 1063 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1064 (void *)bgep, regno, data, cmd)); 1065 1066 ASSERT(mutex_owned(bgep->genlock)); 1067 1068 /* 1069 * Assemble the command ... 1070 */ 1071 cmd |= data << MI_COMMS_DATA_SHIFT; 1072 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1073 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1074 cmd |= MI_COMMS_START; 1075 1076 /* 1077 * Wait for any command already in progress ... 1078 * 1079 * Note: this *shouldn't* ever find that there is a command 1080 * in progress, because we already hold the <genlock> mutex. 1081 * Nonetheless, we have sometimes seen the MI_COMMS_START 1082 * bit set here -- it seems that the chip can initiate MII 1083 * accesses internally, even with polling OFF. 1084 */ 1085 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1086 for (timeout = 100; ; ) { 1087 if ((regval2 & MI_COMMS_START) == 0) { 1088 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1089 break; 1090 } 1091 if (--timeout == 0) 1092 break; 1093 drv_usecwait(10); 1094 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1095 } 1096 1097 if (timeout == 0) 1098 return ((uint16_t)~0u); 1099 1100 if (timeout != 100) 1101 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1102 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1103 cmd, 10*(100-timeout), regval1, regval2)); 1104 1105 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1106 for (timeout = 1000; ; ) { 1107 if ((regval1 & MI_COMMS_START) == 0) 1108 break; 1109 if (--timeout == 0) 1110 break; 1111 drv_usecwait(10); 1112 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1113 } 1114 1115 /* 1116 * Drop out early if the READ FAILED bit is set -- this chip 1117 * could be a 5703/4S, with a SerDes instead of a PHY! 1118 */ 1119 if (regval2 & MI_COMMS_READ_FAILED) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout == 0) 1123 return ((uint16_t)~0u); 1124 1125 /* 1126 * The PRM says to wait 5us after seeing the START bit clear 1127 * and then re-read the register to get the final value of the 1128 * data field, in order to avoid a race condition where the 1129 * START bit is clear but the data field isn't yet valid. 1130 * 1131 * Note: we don't actually seem to be encounter this race; 1132 * except when the START bit is seen set again (see below), 1133 * the data field doesn't change during this 5us interval. 1134 */ 1135 drv_usecwait(5); 1136 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1137 1138 /* 1139 * Unfortunately, when following the PRMs instructions above, 1140 * we have occasionally seen the START bit set again(!) in the 1141 * value read after the 5us delay. This seems to be due to the 1142 * chip autonomously starting another MII access internally. 1143 * In such cases, the command/data/etc fields relate to the 1144 * internal command, rather than the one that we thought had 1145 * just finished. So in this case, we fall back to returning 1146 * the data from the original read that showed START clear. 1147 */ 1148 if (regval2 & MI_COMMS_START) { 1149 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1150 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1151 cmd, regval1, regval2)); 1152 regval2 = regval1; 1153 } 1154 1155 if (regval2 & MI_COMMS_START) 1156 return ((uint16_t)~0u); 1157 1158 if (regval2 & MI_COMMS_READ_FAILED) 1159 return ((uint16_t)~0u); 1160 1161 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1162 } 1163 1164 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1165 #pragma no_inline(bge_mii_get16) 1166 1167 uint16_t 1168 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1169 { 1170 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1171 (void *)bgep, regno)); 1172 1173 ASSERT(mutex_owned(bgep->genlock)); 1174 1175 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1176 } 1177 1178 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1179 #pragma no_inline(bge_mii_put16) 1180 1181 void 1182 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1183 { 1184 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1185 (void *)bgep, regno, data)); 1186 1187 ASSERT(mutex_owned(bgep->genlock)); 1188 1189 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1190 } 1191 1192 #undef BGE_DBG 1193 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1194 1195 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1196 1197 /* 1198 * Basic SEEPROM get/set access routine 1199 * 1200 * This uses the chip's SEEPROM auto-access method, controlled by the 1201 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1202 * doesn't have to fiddle with the individual bits. 1203 * 1204 * The caller should hold <genlock> and *also* have already acquired 1205 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1206 * 1207 * Return value: 1208 * 0 on success, 1209 * ENODATA on access timeout (maybe retryable: device may just be busy) 1210 * EPROTO on other h/w or s/w errors. 1211 * 1212 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1213 * from a (successful) SEEPROM_ACCESS_READ. 1214 */ 1215 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1216 uint32_t *dp); 1217 #pragma no_inline(bge_seeprom_access) 1218 1219 static int 1220 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1221 { 1222 uint32_t tries; 1223 uint32_t regval; 1224 1225 ASSERT(mutex_owned(bgep->genlock)); 1226 1227 /* 1228 * On the newer chips that support both SEEPROM & Flash, we need 1229 * to specifically enable SEEPROM access (Flash is the default). 1230 * On older chips, we don't; SEEPROM is the only NVtype supported, 1231 * and the NVM control registers don't exist ... 1232 */ 1233 switch (bgep->chipid.nvtype) { 1234 case BGE_NVTYPE_NONE: 1235 case BGE_NVTYPE_UNKNOWN: 1236 _NOTE(NOTREACHED) 1237 case BGE_NVTYPE_SEEPROM: 1238 break; 1239 1240 case BGE_NVTYPE_LEGACY_SEEPROM: 1241 case BGE_NVTYPE_UNBUFFERED_FLASH: 1242 case BGE_NVTYPE_BUFFERED_FLASH: 1243 default: 1244 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1245 NVM_CFG1_LEGACY_SEEPROM_MODE); 1246 break; 1247 } 1248 1249 /* 1250 * Check there's no command in progress. 1251 * 1252 * Note: this *shouldn't* ever find that there is a command 1253 * in progress, because we already hold the <genlock> mutex. 1254 * Also, to ensure we don't have a conflict with the chip's 1255 * internal firmware or a process accessing the same (shared) 1256 * SEEPROM through the other port of a 5704, we've already 1257 * been through the "software arbitration" protocol. 1258 * So this is just a final consistency check: we shouldn't 1259 * see EITHER the START bit (command started but not complete) 1260 * OR the COMPLETE bit (command completed but not cleared). 1261 */ 1262 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1263 if (regval & SEEPROM_ACCESS_START) 1264 return (EPROTO); 1265 if (regval & SEEPROM_ACCESS_COMPLETE) 1266 return (EPROTO); 1267 1268 /* 1269 * Assemble the command ... 1270 */ 1271 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1272 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1273 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1274 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1275 cmd |= SEEPROM_ACCESS_START; 1276 cmd |= SEEPROM_ACCESS_COMPLETE; 1277 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1278 1279 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1280 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1281 1282 /* 1283 * By observation, a successful access takes ~20us on a 5703/4, 1284 * but apparently much longer (up to 1000us) on the obsolescent 1285 * BCM5700/BCM5701. We want to be sure we don't get any false 1286 * timeouts here; but OTOH, we don't want a bogus access to lock 1287 * out interrupts for longer than necessary. So we'll allow up 1288 * to 1000us ... 1289 */ 1290 for (tries = 0; tries < 1000; ++tries) { 1291 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1292 if (regval & SEEPROM_ACCESS_COMPLETE) 1293 break; 1294 drv_usecwait(1); 1295 } 1296 1297 if (regval & SEEPROM_ACCESS_COMPLETE) { 1298 /* 1299 * All OK; read the SEEPROM data register, then write back 1300 * the value read from the address register in order to 1301 * clear the <complete> bit and leave the SEEPROM access 1302 * state machine idle, ready for the next access ... 1303 */ 1304 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1305 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1306 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1307 return (0); 1308 } 1309 1310 /* 1311 * Hmm ... what happened here? 1312 * 1313 * Most likely, the user addressed a non-existent SEEPROM. Or 1314 * maybe the SEEPROM was busy internally (e.g. processing a write) 1315 * and didn't respond to being addressed. Either way, it's left 1316 * the SEEPROM access state machine wedged. So we'll reset it 1317 * before we leave, so it's ready for next time ... 1318 */ 1319 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1320 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1321 return (ENODATA); 1322 } 1323 1324 /* 1325 * Basic Flash get/set access routine 1326 * 1327 * These use the chip's Flash auto-access method, controlled by the 1328 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1329 * fiddle with the individual bits. 1330 * 1331 * The caller should hold <genlock> and *also* have already acquired 1332 * the right to access the Flash, via bge_nvmem_acquire() above. 1333 * 1334 * Return value: 1335 * 0 on success, 1336 * ENODATA on access timeout (maybe retryable: device may just be busy) 1337 * ENODEV if the NVmem device is missing or otherwise unusable 1338 * 1339 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1340 * from a (successful) NVM_FLASH_CMD_RD. 1341 */ 1342 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1343 uint32_t *dp); 1344 #pragma no_inline(bge_flash_access) 1345 1346 static int 1347 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1348 { 1349 uint32_t tries; 1350 uint32_t regval; 1351 1352 ASSERT(mutex_owned(bgep->genlock)); 1353 1354 /* 1355 * On the newer chips that support both SEEPROM & Flash, we need 1356 * to specifically disable SEEPROM access while accessing Flash. 1357 * The older chips don't support Flash, and the NVM registers don't 1358 * exist, so we shouldn't be here at all! 1359 */ 1360 switch (bgep->chipid.nvtype) { 1361 case BGE_NVTYPE_NONE: 1362 case BGE_NVTYPE_UNKNOWN: 1363 _NOTE(NOTREACHED) 1364 case BGE_NVTYPE_SEEPROM: 1365 return (ENODEV); 1366 1367 case BGE_NVTYPE_LEGACY_SEEPROM: 1368 case BGE_NVTYPE_UNBUFFERED_FLASH: 1369 case BGE_NVTYPE_BUFFERED_FLASH: 1370 default: 1371 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1372 NVM_CFG1_LEGACY_SEEPROM_MODE); 1373 break; 1374 } 1375 1376 /* 1377 * Assemble the command ... 1378 */ 1379 addr &= NVM_FLASH_ADDR_MASK; 1380 cmd |= NVM_FLASH_CMD_DOIT; 1381 cmd |= NVM_FLASH_CMD_FIRST; 1382 cmd |= NVM_FLASH_CMD_LAST; 1383 cmd |= NVM_FLASH_CMD_DONE; 1384 1385 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1386 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1387 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1388 1389 /* 1390 * Allow up to 1000ms ... 1391 */ 1392 for (tries = 0; tries < 1000; ++tries) { 1393 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1394 if (regval & NVM_FLASH_CMD_DONE) 1395 break; 1396 drv_usecwait(1); 1397 } 1398 1399 if (regval & NVM_FLASH_CMD_DONE) { 1400 /* 1401 * All OK; read the data from the Flash read register 1402 */ 1403 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1404 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1405 return (0); 1406 } 1407 1408 /* 1409 * Hmm ... what happened here? 1410 * 1411 * Most likely, the user addressed a non-existent Flash. Or 1412 * maybe the Flash was busy internally (e.g. processing a write) 1413 * and didn't respond to being addressed. Either way, there's 1414 * nothing we can here ... 1415 */ 1416 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1417 return (ENODATA); 1418 } 1419 1420 /* 1421 * The next two functions regulate access to the NVram (if fitted). 1422 * 1423 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1424 * (SPI) interface, but they can be accessed through either port. These 1425 * are managed by different instance of this driver and have no software 1426 * state in common. 1427 * 1428 * In addition (and even on a single core chip) the chip's internal 1429 * firmware can access the SEEPROM/Flash, most notably after a RESET 1430 * when it may download code to run internally. 1431 * 1432 * So we need to arbitrate between these various software agents. For 1433 * this purpose, the chip provides the Software Arbitration Register, 1434 * which implements hardware(!) arbitration. 1435 * 1436 * This functionality didn't exist on older (5700/5701) chips, so there's 1437 * nothing we can do by way of arbitration on those; also, if there's no 1438 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1439 * nothing to do. 1440 * 1441 * The internal firmware appears to use Request 0, which is the highest 1442 * priority. So we'd like to use Request 2, leaving one higher and one 1443 * lower for any future developments ... but apparently this doesn't 1444 * always work. So for now, the code uses Request 1 ;-( 1445 */ 1446 1447 #define NVM_READ_REQ NVM_READ_REQ1 1448 #define NVM_RESET_REQ NVM_RESET_REQ1 1449 #define NVM_SET_REQ NVM_SET_REQ1 1450 1451 static void bge_nvmem_relinquish(bge_t *bgep); 1452 #pragma no_inline(bge_nvmem_relinquish) 1453 1454 static void 1455 bge_nvmem_relinquish(bge_t *bgep) 1456 { 1457 ASSERT(mutex_owned(bgep->genlock)); 1458 1459 switch (bgep->chipid.nvtype) { 1460 case BGE_NVTYPE_NONE: 1461 case BGE_NVTYPE_UNKNOWN: 1462 _NOTE(NOTREACHED) 1463 return; 1464 1465 case BGE_NVTYPE_SEEPROM: 1466 /* 1467 * No arbitration performed, no release needed 1468 */ 1469 return; 1470 1471 case BGE_NVTYPE_LEGACY_SEEPROM: 1472 case BGE_NVTYPE_UNBUFFERED_FLASH: 1473 case BGE_NVTYPE_BUFFERED_FLASH: 1474 default: 1475 break; 1476 } 1477 1478 /* 1479 * Our own request should be present (whether or not granted) ... 1480 */ 1481 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1482 1483 /* 1484 * ... this will make it go away. 1485 */ 1486 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1487 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1488 } 1489 1490 /* 1491 * Arbitrate for access to the NVmem, if necessary 1492 * 1493 * Return value: 1494 * 0 on success 1495 * EAGAIN if the device is in use (retryable) 1496 * ENODEV if the NVmem device is missing or otherwise unusable 1497 */ 1498 static int bge_nvmem_acquire(bge_t *bgep); 1499 #pragma no_inline(bge_nvmem_acquire) 1500 1501 static int 1502 bge_nvmem_acquire(bge_t *bgep) 1503 { 1504 uint32_t regval; 1505 uint32_t tries; 1506 1507 ASSERT(mutex_owned(bgep->genlock)); 1508 1509 switch (bgep->chipid.nvtype) { 1510 case BGE_NVTYPE_NONE: 1511 case BGE_NVTYPE_UNKNOWN: 1512 /* 1513 * Access denied: no (recognisable) device fitted 1514 */ 1515 return (ENODEV); 1516 1517 case BGE_NVTYPE_SEEPROM: 1518 /* 1519 * Access granted: no arbitration needed (or possible) 1520 */ 1521 return (0); 1522 1523 case BGE_NVTYPE_LEGACY_SEEPROM: 1524 case BGE_NVTYPE_UNBUFFERED_FLASH: 1525 case BGE_NVTYPE_BUFFERED_FLASH: 1526 default: 1527 /* 1528 * Access conditional: conduct arbitration protocol 1529 */ 1530 break; 1531 } 1532 1533 /* 1534 * We're holding the per-port mutex <genlock>, so no-one other 1535 * thread can be attempting to access the NVmem through *this* 1536 * port. But it could be in use by the *other* port (of a 5704), 1537 * or by the chip's internal firmware, so we have to go through 1538 * the full (hardware) arbitration protocol ... 1539 * 1540 * Note that *because* we're holding <genlock>, the interrupt handler 1541 * won't be able to progress. So we're only willing to spin for a 1542 * fairly short time. Specifically: 1543 * 1544 * We *must* wait long enough for the hardware to resolve all 1545 * requests and determine the winner. Fortunately, this is 1546 * "almost instantaneous", even as observed by GHz CPUs. 1547 * 1548 * A successful access by another Solaris thread (via either 1549 * port) typically takes ~20us. So waiting a bit longer than 1550 * that will give a good chance of success, if the other user 1551 * *is* another thread on the other port. 1552 * 1553 * However, the internal firmware can hold on to the NVmem 1554 * for *much* longer: at least 10 milliseconds just after a 1555 * RESET, and maybe even longer if the NVmem actually contains 1556 * code to download and run on the internal CPUs. 1557 * 1558 * So, we'll allow 50us; if that's not enough then it's up to the 1559 * caller to retry later (hence the choice of return code EAGAIN). 1560 */ 1561 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1562 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1563 1564 for (tries = 0; tries < 50; ++tries) { 1565 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1566 if (regval & NVM_WON_REQ1) 1567 break; 1568 drv_usecwait(1); 1569 } 1570 1571 if (regval & NVM_WON_REQ1) { 1572 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1573 return (0); 1574 } 1575 1576 /* 1577 * Somebody else must be accessing the NVmem, so abandon our 1578 * attempt take control of it. The caller can try again later ... 1579 */ 1580 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1581 bge_nvmem_relinquish(bgep); 1582 return (EAGAIN); 1583 } 1584 1585 /* 1586 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1587 * write protect line in such a way that the NVmem is protected when 1588 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1589 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1590 * 1591 * Note: there's only one set of GPIO pins on a 5704, even though they 1592 * can be accessed through either port. So the chip has to resolve what 1593 * happens if the two ports program a single pin differently ... the rule 1594 * it uses is that if the ports disagree about the *direction* of a pin, 1595 * "output" wins over "input", but if they disagree about its *value* as 1596 * an output, then the pin is TRISTATED instead! In such a case, no-one 1597 * wins, and the external signal does whatever the external circuitry 1598 * defines as the default -- which we've assumed is the PROTECTED state. 1599 * So, we always change GPIO1 back to being an *input* whenever we're not 1600 * specifically using it to unprotect the NVmem. This allows either port 1601 * to update the NVmem, although obviously only one at a time! 1602 * 1603 * The caller should hold <genlock> and *also* have already acquired the 1604 * right to access the NVmem, via bge_nvmem_acquire() above. 1605 */ 1606 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1607 #pragma inline(bge_nvmem_protect) 1608 1609 static void 1610 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1611 { 1612 uint32_t regval; 1613 1614 ASSERT(mutex_owned(bgep->genlock)); 1615 1616 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1617 if (protect) { 1618 regval |= MLCR_MISC_PINS_OUTPUT_1; 1619 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1620 } else { 1621 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1622 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1623 } 1624 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1625 } 1626 1627 /* 1628 * Now put it all together ... 1629 * 1630 * Try to acquire control of the NVmem; if successful, then: 1631 * unprotect it (if we want to write to it) 1632 * perform the requested access 1633 * reprotect it (after a write) 1634 * relinquish control 1635 * 1636 * Return value: 1637 * 0 on success, 1638 * EAGAIN if the device is in use (retryable) 1639 * ENODATA on access timeout (maybe retryable: device may just be busy) 1640 * ENODEV if the NVmem device is missing or otherwise unusable 1641 * EPROTO on other h/w or s/w errors. 1642 */ 1643 static int 1644 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1645 { 1646 int err; 1647 1648 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1649 switch (cmd) { 1650 case BGE_SEE_READ: 1651 err = bge_seeprom_access(bgep, 1652 SEEPROM_ACCESS_READ, addr, dp); 1653 break; 1654 1655 case BGE_SEE_WRITE: 1656 bge_nvmem_protect(bgep, B_FALSE); 1657 err = bge_seeprom_access(bgep, 1658 SEEPROM_ACCESS_WRITE, addr, dp); 1659 bge_nvmem_protect(bgep, B_TRUE); 1660 break; 1661 1662 case BGE_FLASH_READ: 1663 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1664 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1665 bge_reg_set32(bgep, NVM_ACCESS_REG, 1666 NVM_ACCESS_ENABLE); 1667 } 1668 err = bge_flash_access(bgep, 1669 NVM_FLASH_CMD_RD, addr, dp); 1670 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1671 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1672 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1673 NVM_ACCESS_ENABLE); 1674 } 1675 break; 1676 1677 case BGE_FLASH_WRITE: 1678 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1679 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1680 bge_reg_set32(bgep, NVM_ACCESS_REG, 1681 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1682 } 1683 bge_nvmem_protect(bgep, B_FALSE); 1684 err = bge_flash_access(bgep, 1685 NVM_FLASH_CMD_WR, addr, dp); 1686 bge_nvmem_protect(bgep, B_TRUE); 1687 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1688 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1689 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1690 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1691 } 1692 1693 break; 1694 1695 default: 1696 _NOTE(NOTREACHED) 1697 break; 1698 } 1699 bge_nvmem_relinquish(bgep); 1700 } 1701 1702 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1703 return (err); 1704 } 1705 1706 /* 1707 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1708 */ 1709 static uint64_t bge_get_nvmac(bge_t *bgep); 1710 #pragma no_inline(bge_get_nvmac) 1711 1712 static uint64_t 1713 bge_get_nvmac(bge_t *bgep) 1714 { 1715 uint32_t mac_high; 1716 uint32_t mac_low; 1717 uint32_t addr; 1718 uint32_t cmd; 1719 uint64_t mac; 1720 1721 BGE_TRACE(("bge_get_nvmac($%p)", 1722 (void *)bgep)); 1723 1724 switch (bgep->chipid.nvtype) { 1725 case BGE_NVTYPE_NONE: 1726 case BGE_NVTYPE_UNKNOWN: 1727 default: 1728 return (0ULL); 1729 1730 case BGE_NVTYPE_SEEPROM: 1731 case BGE_NVTYPE_LEGACY_SEEPROM: 1732 cmd = BGE_SEE_READ; 1733 break; 1734 1735 case BGE_NVTYPE_UNBUFFERED_FLASH: 1736 case BGE_NVTYPE_BUFFERED_FLASH: 1737 cmd = BGE_FLASH_READ; 1738 break; 1739 } 1740 1741 addr = NVMEM_DATA_MAC_ADDRESS; 1742 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1743 return (0ULL); 1744 addr += 4; 1745 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1746 return (0ULL); 1747 1748 /* 1749 * The Broadcom chip is natively BIG-endian, so that's how the 1750 * MAC address is represented in NVmem. We may need to swap it 1751 * around on a little-endian host ... 1752 */ 1753 #ifdef _BIG_ENDIAN 1754 mac = mac_high; 1755 mac = mac << 32; 1756 mac |= mac_low; 1757 #else 1758 mac = BGE_BSWAP_32(mac_high); 1759 mac = mac << 32; 1760 mac |= BGE_BSWAP_32(mac_low); 1761 #endif /* _BIG_ENDIAN */ 1762 1763 return (mac); 1764 } 1765 1766 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1767 1768 /* 1769 * Dummy version for when we're not supporting NVmem access 1770 */ 1771 static uint64_t bge_get_nvmac(bge_t *bgep); 1772 #pragma inline(bge_get_nvmac) 1773 1774 static uint64_t 1775 bge_get_nvmac(bge_t *bgep) 1776 { 1777 _NOTE(ARGUNUSED(bgep)) 1778 return (0ULL); 1779 } 1780 1781 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1782 1783 /* 1784 * Determine the type of NVmem that is (or may be) attached to this chip, 1785 */ 1786 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1787 #pragma no_inline(bge_nvmem_id) 1788 1789 static enum bge_nvmem_type 1790 bge_nvmem_id(bge_t *bgep) 1791 { 1792 enum bge_nvmem_type nvtype; 1793 uint32_t config1; 1794 1795 BGE_TRACE(("bge_nvmem_id($%p)", 1796 (void *)bgep)); 1797 1798 switch (bgep->chipid.device) { 1799 default: 1800 /* 1801 * We shouldn't get here; it means we don't recognise 1802 * the chip, which means we don't know how to determine 1803 * what sort of NVmem (if any) it has. So we'll say 1804 * NONE, to disable the NVmem access code ... 1805 */ 1806 nvtype = BGE_NVTYPE_NONE; 1807 break; 1808 1809 case DEVICE_ID_5700: 1810 case DEVICE_ID_5700x: 1811 case DEVICE_ID_5701: 1812 /* 1813 * These devices support *only* SEEPROMs 1814 */ 1815 nvtype = BGE_NVTYPE_SEEPROM; 1816 break; 1817 1818 case DEVICE_ID_5702: 1819 case DEVICE_ID_5702fe: 1820 case DEVICE_ID_5703C: 1821 case DEVICE_ID_5703S: 1822 case DEVICE_ID_5704C: 1823 case DEVICE_ID_5704S: 1824 case DEVICE_ID_5704: 1825 case DEVICE_ID_5705M: 1826 case DEVICE_ID_5705C: 1827 case DEVICE_ID_5705_2: 1828 case DEVICE_ID_5706: 1829 case DEVICE_ID_5782: 1830 case DEVICE_ID_5788: 1831 case DEVICE_ID_5789: 1832 case DEVICE_ID_5751: 1833 case DEVICE_ID_5751M: 1834 case DEVICE_ID_5752: 1835 case DEVICE_ID_5752M: 1836 case DEVICE_ID_5754: 1837 case DEVICE_ID_5721: 1838 case DEVICE_ID_5714C: 1839 case DEVICE_ID_5714S: 1840 case DEVICE_ID_5715C: 1841 case DEVICE_ID_5715S: 1842 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1843 if (config1 & NVM_CFG1_FLASH_MODE) 1844 if (config1 & NVM_CFG1_BUFFERED_MODE) 1845 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1846 else 1847 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1848 else 1849 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1850 break; 1851 } 1852 1853 return (nvtype); 1854 } 1855 1856 #undef BGE_DBG 1857 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1858 1859 static void 1860 bge_init_recv_rule(bge_t *bgep) 1861 { 1862 bge_recv_rule_t *rulep; 1863 uint32_t i; 1864 1865 /* 1866 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1867 * 1. to direct UDP traffic, set: 1868 * rulep->control = RULE_PROTO_CONTROL; 1869 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1870 * 2. to direct ICMP traffic, set: 1871 * rulep->control = RULE_PROTO_CONTROL; 1872 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1873 * 3. to direct traffic by source ip, set: 1874 * rulep->control = RULE_SIP_CONTROL; 1875 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1876 */ 1877 rulep = bgep->recv_rules; 1878 rulep->control = RULE_PROTO_CONTROL; 1879 rulep->mask_value = RULE_TCP_MASK_VALUE; 1880 1881 /* 1882 * set receive rule registers 1883 */ 1884 rulep = bgep->recv_rules; 1885 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1886 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1887 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1888 } 1889 } 1890 1891 /* 1892 * Using the values captured by bge_chip_cfg_init(), and additional probes 1893 * as required, characterise the chip fully: determine the label by which 1894 * to refer to this chip, the correct settings for various registers, and 1895 * of course whether the device and/or subsystem are supported! 1896 */ 1897 int bge_chip_id_init(bge_t *bgep); 1898 #pragma no_inline(bge_chip_id_init) 1899 1900 int 1901 bge_chip_id_init(bge_t *bgep) 1902 { 1903 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1904 boolean_t sys_ok; 1905 boolean_t dev_ok; 1906 chip_id_t *cidp; 1907 uint32_t subid; 1908 char *devname; 1909 char *sysname; 1910 int *ids; 1911 int err; 1912 uint_t i; 1913 1914 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1915 1916 sys_ok = dev_ok = B_FALSE; 1917 cidp = &bgep->chipid; 1918 1919 /* 1920 * Check the PCI device ID to determine the generic chip type and 1921 * select parameters that depend on this. 1922 * 1923 * Note: because the SPARC platforms in general don't fit the 1924 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1925 * as zero - which is why we use <asic_rev> rather than <revision> 1926 * below ... 1927 * 1928 * Note: in general we can't distinguish between the Copper/SerDes 1929 * versions by ID alone, as some Copper devices (e.g. some but not 1930 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1931 * treat them the same here, and the MII code works out the media 1932 * type later on ... 1933 */ 1934 cidp->mbuf_base = bge_mbuf_pool_base; 1935 cidp->mbuf_length = bge_mbuf_pool_len; 1936 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1937 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1938 cidp->pci_type = BGE_PCI_X; 1939 cidp->statistic_type = BGE_STAT_BLK; 1940 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1941 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1942 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1943 1944 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1945 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1946 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1947 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1948 1949 cidp->msi_enabled = B_FALSE; 1950 1951 switch (cidp->device) { 1952 case DEVICE_ID_5700: 1953 case DEVICE_ID_5700x: 1954 cidp->chip_label = 5700; 1955 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1956 break; 1957 1958 case DEVICE_ID_5701: 1959 cidp->chip_label = 5701; 1960 dev_ok = B_TRUE; 1961 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1962 break; 1963 1964 case DEVICE_ID_5702: 1965 case DEVICE_ID_5702fe: 1966 cidp->chip_label = 5702; 1967 dev_ok = B_TRUE; 1968 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1969 cidp->pci_type = BGE_PCI; 1970 break; 1971 1972 case DEVICE_ID_5703C: 1973 case DEVICE_ID_5703S: 1974 case DEVICE_ID_5703: 1975 /* 1976 * Revision A0 of the 5703/5793 had various errata 1977 * that we can't or don't work around, so it's not 1978 * supported, but all later versions are 1979 */ 1980 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1981 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1982 dev_ok = B_TRUE; 1983 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1984 break; 1985 1986 case DEVICE_ID_5704C: 1987 case DEVICE_ID_5704S: 1988 case DEVICE_ID_5704: 1989 /* 1990 * Revision A0 of the 5704/5794 had various errata 1991 * but we have workarounds, so it *is* supported. 1992 */ 1993 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1994 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1995 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1996 dev_ok = B_TRUE; 1997 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 1998 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1999 break; 2000 2001 case DEVICE_ID_5705C: 2002 case DEVICE_ID_5705M: 2003 case DEVICE_ID_5705MA3: 2004 case DEVICE_ID_5705F: 2005 case DEVICE_ID_5705_2: 2006 case DEVICE_ID_5754: 2007 if (cidp->device == DEVICE_ID_5754) { 2008 cidp->chip_label = 5754; 2009 cidp->pci_type = BGE_PCI_E; 2010 } else { 2011 cidp->chip_label = 5705; 2012 cidp->pci_type = BGE_PCI; 2013 } 2014 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2015 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2016 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2017 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2018 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2019 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2020 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2021 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2022 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2023 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2024 cidp->statistic_type = BGE_STAT_REG; 2025 dev_ok = B_TRUE; 2026 break; 2027 2028 case DEVICE_ID_5706: 2029 cidp->chip_label = 5706; 2030 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2031 break; 2032 2033 case DEVICE_ID_5782: 2034 /* 2035 * Apart from the label, we treat this as a 5705(?) 2036 */ 2037 cidp->chip_label = 5782; 2038 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2039 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2040 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2041 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2042 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2043 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2044 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2045 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2046 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2047 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2048 cidp->statistic_type = BGE_STAT_REG; 2049 dev_ok = B_TRUE; 2050 break; 2051 2052 case DEVICE_ID_5788: 2053 /* 2054 * Apart from the label, we treat this as a 5705(?) 2055 */ 2056 cidp->chip_label = 5788; 2057 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2058 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2059 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2060 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2061 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2062 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2063 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2064 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2065 cidp->statistic_type = BGE_STAT_REG; 2066 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2067 dev_ok = B_TRUE; 2068 break; 2069 2070 case DEVICE_ID_5714C: 2071 if (cidp->revision >= REVISION_ID_5714_A2) 2072 cidp->msi_enabled = bge_enable_msi; 2073 /* FALLTHRU */ 2074 case DEVICE_ID_5714S: 2075 cidp->chip_label = 5714; 2076 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2077 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2078 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2079 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2080 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2081 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2082 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2083 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2084 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2085 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2086 cidp->pci_type = BGE_PCI_E; 2087 cidp->statistic_type = BGE_STAT_REG; 2088 dev_ok = B_TRUE; 2089 break; 2090 2091 case DEVICE_ID_5715C: 2092 case DEVICE_ID_5715S: 2093 cidp->chip_label = 5715; 2094 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2095 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2096 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2097 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2098 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2099 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2100 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2101 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2102 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2103 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2104 cidp->pci_type = BGE_PCI_E; 2105 cidp->statistic_type = BGE_STAT_REG; 2106 if (cidp->revision >= REVISION_ID_5715_A2) 2107 cidp->msi_enabled = bge_enable_msi; 2108 dev_ok = B_TRUE; 2109 break; 2110 2111 case DEVICE_ID_5721: 2112 cidp->chip_label = 5721; 2113 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2114 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2115 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2116 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2117 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2118 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2119 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2120 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2121 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2122 cidp->pci_type = BGE_PCI_E; 2123 cidp->statistic_type = BGE_STAT_REG; 2124 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2125 dev_ok = B_TRUE; 2126 break; 2127 2128 case DEVICE_ID_5751: 2129 case DEVICE_ID_5751M: 2130 cidp->chip_label = 5751; 2131 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2132 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2133 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2134 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2135 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2136 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2137 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2138 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2139 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2140 cidp->pci_type = BGE_PCI_E; 2141 cidp->statistic_type = BGE_STAT_REG; 2142 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2143 dev_ok = B_TRUE; 2144 break; 2145 2146 case DEVICE_ID_5752: 2147 case DEVICE_ID_5752M: 2148 cidp->chip_label = 5752; 2149 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2150 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2151 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2152 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2153 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2154 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2155 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2156 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2157 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2158 cidp->pci_type = BGE_PCI_E; 2159 cidp->statistic_type = BGE_STAT_REG; 2160 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2161 dev_ok = B_TRUE; 2162 break; 2163 2164 case DEVICE_ID_5789: 2165 cidp->chip_label = 5789; 2166 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2167 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2168 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2169 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2170 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2171 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2172 cidp->pci_type = BGE_PCI_E; 2173 cidp->statistic_type = BGE_STAT_REG; 2174 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2175 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2176 cidp->msi_enabled = B_TRUE; 2177 dev_ok = B_TRUE; 2178 break; 2179 2180 } 2181 2182 /* 2183 * Setup the default jumbo parameter. 2184 */ 2185 cidp->ethmax_size = ETHERMAX; 2186 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2187 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2188 2189 /* 2190 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2191 * setup below jumbo specific parameters. 2192 * 2193 * For BCM5714/5715, there is only one standard receive ring. So the 2194 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2195 * feature is enabled. 2196 */ 2197 if (bge_jumbo_enable && 2198 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2199 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2200 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2201 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2202 cidp->mbuf_lo_water_rdma = 2203 RDMA_MBUF_LOWAT_5714_JUMBO; 2204 cidp->mbuf_lo_water_rmac = 2205 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2206 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2207 cidp->jumbo_slots = 0; 2208 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2209 } else { 2210 cidp->mbuf_lo_water_rdma = 2211 RDMA_MBUF_LOWAT_JUMBO; 2212 cidp->mbuf_lo_water_rmac = 2213 MAC_RX_MBUF_LOWAT_JUMBO; 2214 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2215 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2216 } 2217 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2218 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2219 cidp->ethmax_size = cidp->default_mtu + 2220 sizeof (struct ether_header); 2221 } 2222 2223 /* 2224 * Identify the NV memory type: SEEPROM or Flash? 2225 */ 2226 cidp->nvtype = bge_nvmem_id(bgep); 2227 2228 /* 2229 * Now, we want to check whether this device is part of a 2230 * supported subsystem (e.g., on the motherboard of a Sun 2231 * branded platform). 2232 * 2233 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2234 */ 2235 if (cidp->subven == VENDOR_ID_SUN) 2236 sys_ok = B_TRUE; 2237 2238 /* 2239 * Rule 2: If it's on the list on known subsystems, then it's OK. 2240 * Note: 0x14e41647 should *not* appear in the list, but the code 2241 * doesn't enforce that. 2242 */ 2243 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2244 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2245 if (err == DDI_PROP_SUCCESS) { 2246 /* 2247 * Got the list; scan for a matching subsystem vendor/device 2248 */ 2249 subid = (cidp->subven << 16) | cidp->subdev; 2250 while (i--) 2251 if (ids[i] == subid) 2252 sys_ok = B_TRUE; 2253 ddi_prop_free(ids); 2254 } 2255 2256 /* 2257 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2258 * 2259 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2260 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2261 * we have to check specially for the exact device paths to the 2262 * motherboard devices on those platforms ;-( 2263 * 2264 * Note: we can't just use the "supported-subsystems" mechanism 2265 * above, because the entry would have to be 0x14e41647 -- which 2266 * would then accept *any* plugin card that *didn't* contain a 2267 * (valid) SEEPROM ;-( 2268 */ 2269 sysname = ddi_node_name(ddi_root_node()); 2270 devname = ddi_pathname(bgep->devinfo, buf); 2271 ASSERT(strlen(devname) > 0); 2272 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2273 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2274 sys_ok = B_TRUE; 2275 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2276 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2277 sys_ok = B_TRUE; 2278 2279 /* 2280 * Now check what we've discovered: is this truly a supported 2281 * chip on (the motherboard of) a supported platform? 2282 * 2283 * Possible problems here: 2284 * 1) it's a completely unheard-of chip (e.g. 5761) 2285 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2286 * 3) it's a chip we would support if it were on the motherboard 2287 * of a Sun platform, but this one isn't ;-( 2288 */ 2289 if (cidp->chip_label == 0) 2290 bge_problem(bgep, 2291 "Device 'pci%04x,%04x' not recognized (%d?)", 2292 cidp->vendor, cidp->device, cidp->device); 2293 else if (!dev_ok) 2294 bge_problem(bgep, 2295 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2296 cidp->vendor, cidp->device, cidp->chip_label, 2297 cidp->revision); 2298 #if BGE_DEBUGGING 2299 else if (!sys_ok) 2300 bge_problem(bgep, 2301 "%d-based subsystem 'pci%04x,%04x' not validated", 2302 cidp->chip_label, cidp->subven, cidp->subdev); 2303 #endif 2304 else 2305 cidp->flags |= CHIP_FLAG_SUPPORTED; 2306 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2307 return (EIO); 2308 return (0); 2309 } 2310 2311 void 2312 bge_chip_msi_trig(bge_t *bgep) 2313 { 2314 uint32_t regval; 2315 2316 regval = bgep->param_msi_cnt<<4; 2317 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2318 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2319 } 2320 2321 /* 2322 * Various registers that control the chip's internal engines (state 2323 * machines) have a <reset> and <enable> bits (fortunately, in the 2324 * same place in each such register :-). 2325 * 2326 * To reset the state machine, the <reset> bit must be written with 1; 2327 * it will then read back as 1 while the reset is in progress, but 2328 * self-clear to 0 when the reset completes. 2329 * 2330 * To enable a state machine, one must set the <enable> bit, which 2331 * will continue to read back as 0 until the state machine is running. 2332 * 2333 * To disable a state machine, the <enable> bit must be cleared, but 2334 * it will continue to read back as 1 until the state machine actually 2335 * stops. 2336 * 2337 * This routine implements polling for completion of a reset, enable 2338 * or disable operation, returning B_TRUE on success (bit reached the 2339 * required state) or B_FALSE on timeout (200*100us == 20ms). 2340 */ 2341 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2342 uint32_t mask, uint32_t val); 2343 #pragma no_inline(bge_chip_poll_engine) 2344 2345 static boolean_t 2346 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2347 uint32_t mask, uint32_t val) 2348 { 2349 uint32_t regval; 2350 uint32_t n; 2351 2352 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2353 (void *)bgep, regno, mask, val)); 2354 2355 for (n = 200; n; --n) { 2356 regval = bge_reg_get32(bgep, regno); 2357 if ((regval & mask) == val) 2358 return (B_TRUE); 2359 drv_usecwait(100); 2360 } 2361 2362 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2363 return (B_FALSE); 2364 } 2365 2366 /* 2367 * Various registers that control the chip's internal engines (state 2368 * machines) have a <reset> bit (fortunately, in the same place in 2369 * each such register :-). To reset the state machine, this bit must 2370 * be written with 1; it will then read back as 1 while the reset is 2371 * in progress, but self-clear to 0 when the reset completes. 2372 * 2373 * This code sets the bit, then polls for it to read back as zero. 2374 * The return value is B_TRUE on success (reset bit cleared itself), 2375 * or B_FALSE if the state machine didn't recover :( 2376 * 2377 * NOTE: the Core reset is similar to other resets, except that we 2378 * can't poll for completion, since the Core reset disables memory 2379 * access! So we just have to assume that it will all complete in 2380 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2381 */ 2382 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2383 #pragma no_inline(bge_chip_reset_engine) 2384 2385 static boolean_t 2386 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2387 { 2388 uint32_t regval; 2389 uint32_t val32; 2390 2391 regval = bge_reg_get32(bgep, regno); 2392 2393 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2394 (void *)bgep, regno)); 2395 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2396 regno, regval)); 2397 2398 regval |= STATE_MACHINE_RESET_BIT; 2399 2400 switch (regno) { 2401 case MISC_CONFIG_REG: 2402 /* 2403 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2404 * resetting PCIE block and bringing PCIE link down, bit 29 2405 * in the register needs to be set first, and then set it again 2406 * while the reset bit is written. 2407 * See:P500 of 57xx-PG102-RDS.pdf. 2408 */ 2409 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2410 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2411 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2412 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2413 if (bgep->chipid.pci_type == BGE_PCI_E) { 2414 if (bgep->chipid.asic_rev == 2415 MHCR_CHIP_REV_5751_A0 || 2416 bgep->chipid.asic_rev == 2417 MHCR_CHIP_REV_5721_A0) { 2418 val32 = bge_reg_get32(bgep, 2419 PHY_TEST_CTRL_REG); 2420 if (val32 == (PHY_PCIE_SCRAM_MODE | 2421 PHY_PCIE_LTASS_MODE)) 2422 bge_reg_put32(bgep, 2423 PHY_TEST_CTRL_REG, 2424 PHY_PCIE_SCRAM_MODE); 2425 val32 = pci_config_get32 2426 (bgep->cfg_handle, 2427 PCI_CONF_BGE_CLKCTL); 2428 val32 |= CLKCTL_PCIE_A0_FIX; 2429 pci_config_put32(bgep->cfg_handle, 2430 PCI_CONF_BGE_CLKCTL, val32); 2431 } 2432 bge_reg_set32(bgep, regno, 2433 MISC_CONFIG_GRC_RESET_DISABLE); 2434 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2435 } 2436 } 2437 2438 /* 2439 * Special case - causes Core reset 2440 * 2441 * On SPARC v9 we want to ensure that we don't start 2442 * timing until the I/O access has actually reached 2443 * the chip, otherwise we might make the next access 2444 * too early. And we can't just force the write out 2445 * by following it with a read (even to config space) 2446 * because that would cause the fault we're trying 2447 * to avoid. Hence the need for membar_sync() here. 2448 */ 2449 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2450 #ifdef __sparcv9 2451 membar_sync(); 2452 #endif /* __sparcv9 */ 2453 /* 2454 * On some platforms,system need about 300us for 2455 * link setup. 2456 */ 2457 drv_usecwait(300); 2458 2459 if (bgep->chipid.pci_type == BGE_PCI_E) { 2460 /* PCI-E device need more reset time */ 2461 drv_usecwait(120000); 2462 2463 /* Set PCIE max payload size and clear error status. */ 2464 if ((bgep->chipid.chip_label == 5721) || 2465 (bgep->chipid.chip_label == 5751) || 2466 (bgep->chipid.chip_label == 5752) || 2467 (bgep->chipid.chip_label == 5789)) { 2468 pci_config_put16(bgep->cfg_handle, 2469 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2470 pci_config_put16(bgep->cfg_handle, 2471 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2472 } 2473 } 2474 2475 BGE_PCICHK(bgep); 2476 return (B_TRUE); 2477 2478 default: 2479 bge_reg_put32(bgep, regno, regval); 2480 return (bge_chip_poll_engine(bgep, regno, 2481 STATE_MACHINE_RESET_BIT, 0)); 2482 } 2483 } 2484 2485 /* 2486 * Various registers that control the chip's internal engines (state 2487 * machines) have an <enable> bit (fortunately, in the same place in 2488 * each such register :-). To stop the state machine, this bit must 2489 * be written with 0, then polled to see when the state machine has 2490 * actually stopped. 2491 * 2492 * The return value is B_TRUE on success (enable bit cleared), or 2493 * B_FALSE if the state machine didn't stop :( 2494 */ 2495 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2496 uint32_t morebits); 2497 #pragma no_inline(bge_chip_disable_engine) 2498 2499 static boolean_t 2500 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2501 { 2502 uint32_t regval; 2503 2504 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2505 (void *)bgep, regno, morebits)); 2506 2507 switch (regno) { 2508 case FTQ_RESET_REG: 2509 /* 2510 * Not quite like the others; it doesn't 2511 * have an <enable> bit, but instead we 2512 * have to set and then clear all the bits 2513 */ 2514 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2515 drv_usecwait(100); 2516 bge_reg_put32(bgep, regno, 0); 2517 return (B_TRUE); 2518 2519 default: 2520 regval = bge_reg_get32(bgep, regno); 2521 regval &= ~STATE_MACHINE_ENABLE_BIT; 2522 regval &= ~morebits; 2523 bge_reg_put32(bgep, regno, regval); 2524 return (bge_chip_poll_engine(bgep, regno, 2525 STATE_MACHINE_ENABLE_BIT, 0)); 2526 } 2527 } 2528 2529 /* 2530 * Various registers that control the chip's internal engines (state 2531 * machines) have an <enable> bit (fortunately, in the same place in 2532 * each such register :-). To start the state machine, this bit must 2533 * be written with 1, then polled to see when the state machine has 2534 * actually started. 2535 * 2536 * The return value is B_TRUE on success (enable bit set), or 2537 * B_FALSE if the state machine didn't start :( 2538 */ 2539 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2540 uint32_t morebits); 2541 #pragma no_inline(bge_chip_enable_engine) 2542 2543 static boolean_t 2544 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2545 { 2546 uint32_t regval; 2547 2548 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2549 (void *)bgep, regno, morebits)); 2550 2551 switch (regno) { 2552 case FTQ_RESET_REG: 2553 /* 2554 * Not quite like the others; it doesn't 2555 * have an <enable> bit, but instead we 2556 * have to set and then clear all the bits 2557 */ 2558 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2559 drv_usecwait(100); 2560 bge_reg_put32(bgep, regno, 0); 2561 return (B_TRUE); 2562 2563 default: 2564 regval = bge_reg_get32(bgep, regno); 2565 regval |= STATE_MACHINE_ENABLE_BIT; 2566 regval |= morebits; 2567 bge_reg_put32(bgep, regno, regval); 2568 return (bge_chip_poll_engine(bgep, regno, 2569 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2570 } 2571 } 2572 2573 /* 2574 * Reprogram the Ethernet, Transmit, and Receive MAC 2575 * modes to match the param_* variables 2576 */ 2577 static void bge_sync_mac_modes(bge_t *bgep); 2578 #pragma no_inline(bge_sync_mac_modes) 2579 2580 static void 2581 bge_sync_mac_modes(bge_t *bgep) 2582 { 2583 uint32_t macmode; 2584 uint32_t regval; 2585 2586 ASSERT(mutex_owned(bgep->genlock)); 2587 2588 /* 2589 * Reprogram the Ethernet MAC mode ... 2590 */ 2591 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2592 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2593 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2594 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2595 else 2596 macmode |= ETHERNET_MODE_LINK_POLARITY; 2597 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2598 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2599 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2600 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2601 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2602 macmode |= ETHERNET_MODE_PORTMODE_MII; 2603 else 2604 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2605 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2606 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2607 else 2608 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2609 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2610 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2611 else 2612 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2613 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2614 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2615 (void *)bgep, regval, macmode)); 2616 2617 /* 2618 * ... the Transmit MAC mode ... 2619 */ 2620 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2621 if (bgep->param_link_tx_pause) 2622 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2623 else 2624 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2625 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2626 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2627 (void *)bgep, regval, macmode)); 2628 2629 /* 2630 * ... and the Receive MAC mode 2631 */ 2632 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2633 if (bgep->param_link_rx_pause) 2634 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2635 else 2636 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2637 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2638 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2639 (void *)bgep, regval, macmode)); 2640 } 2641 2642 /* 2643 * bge_chip_sync() -- program the chip with the unicast MAC address, 2644 * the multicast hash table, the required level of promiscuity, and 2645 * the current loopback mode ... 2646 */ 2647 #ifdef BGE_IPMI_ASF 2648 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2649 #else 2650 int bge_chip_sync(bge_t *bgep); 2651 #endif 2652 #pragma no_inline(bge_chip_sync) 2653 2654 int 2655 #ifdef BGE_IPMI_ASF 2656 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2657 #else 2658 bge_chip_sync(bge_t *bgep) 2659 #endif 2660 { 2661 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2662 boolean_t promisc; 2663 uint64_t macaddr; 2664 uint32_t fill; 2665 int i, j; 2666 int retval = DDI_SUCCESS; 2667 2668 BGE_TRACE(("bge_chip_sync($%p)", 2669 (void *)bgep)); 2670 2671 ASSERT(mutex_owned(bgep->genlock)); 2672 2673 promisc = B_FALSE; 2674 fill = ~(uint32_t)0; 2675 2676 if (bgep->promisc) 2677 promisc = B_TRUE; 2678 else 2679 fill = (uint32_t)0; 2680 2681 /* 2682 * If the TX/RX MAC engines are already running, we should stop 2683 * them (and reset the RX engine) before changing the parameters. 2684 * If they're not running, this will have no effect ... 2685 * 2686 * NOTE: this is currently disabled by default because stopping 2687 * and restarting the Tx engine may cause an outgoing packet in 2688 * transit to be truncated. Also, stopping and restarting the 2689 * Rx engine seems to not work correctly on the 5705. Testing 2690 * has not (yet!) revealed any problems with NOT stopping and 2691 * restarting these engines (and Broadcom say their drivers don't 2692 * do this), but if it is found to cause problems, this variable 2693 * can be patched to re-enable the old behaviour ... 2694 */ 2695 if (bge_stop_start_on_sync) { 2696 #ifdef BGE_IPMI_ASF 2697 if (!bgep->asf_enabled) { 2698 if (!bge_chip_disable_engine(bgep, 2699 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2700 retval = DDI_FAILURE; 2701 } else { 2702 if (!bge_chip_disable_engine(bgep, 2703 RECEIVE_MAC_MODE_REG, 0)) 2704 retval = DDI_FAILURE; 2705 } 2706 #else 2707 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2708 RECEIVE_MODE_KEEP_VLAN_TAG)) 2709 retval = DDI_FAILURE; 2710 #endif 2711 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2712 retval = DDI_FAILURE; 2713 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2714 retval = DDI_FAILURE; 2715 } 2716 2717 /* 2718 * Reprogram the hashed multicast address table ... 2719 */ 2720 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2721 bge_reg_put32(bgep, MAC_HASH_REG(i), 2722 bgep->mcast_hash[i] | fill); 2723 2724 #ifdef BGE_IPMI_ASF 2725 if (!bgep->asf_enabled || !asf_keeplive) { 2726 #endif 2727 /* 2728 * Transform the MAC address(es) from host to chip format, then 2729 * reprogram the transmit random backoff seed and the unicast 2730 * MAC address(es) ... 2731 */ 2732 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2733 for (i = 0, fill = 0, macaddr = 0ull; 2734 i < ETHERADDRL; ++i) { 2735 macaddr <<= 8; 2736 macaddr |= bgep->curr_addr[j].addr[i]; 2737 fill += bgep->curr_addr[j].addr[i]; 2738 } 2739 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2740 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2741 } 2742 2743 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2744 (void *)bgep, macaddr)); 2745 #ifdef BGE_IPMI_ASF 2746 } 2747 #endif 2748 2749 /* 2750 * Set or clear the PROMISCUOUS mode bit 2751 */ 2752 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2753 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2754 2755 /* 2756 * Sync the rest of the MAC modes too ... 2757 */ 2758 bge_sync_mac_modes(bgep); 2759 2760 /* 2761 * Restart RX/TX MAC engines if required ... 2762 */ 2763 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2764 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2765 retval = DDI_FAILURE; 2766 #ifdef BGE_IPMI_ASF 2767 if (!bgep->asf_enabled) { 2768 if (!bge_chip_enable_engine(bgep, 2769 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2770 retval = DDI_FAILURE; 2771 } else { 2772 if (!bge_chip_enable_engine(bgep, 2773 RECEIVE_MAC_MODE_REG, 0)) 2774 retval = DDI_FAILURE; 2775 } 2776 #else 2777 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2778 RECEIVE_MODE_KEEP_VLAN_TAG)) 2779 retval = DDI_FAILURE; 2780 #endif 2781 } 2782 return (retval); 2783 } 2784 2785 /* 2786 * This array defines the sequence of state machine control registers 2787 * in which the <enable> bit must be cleared to bring the chip to a 2788 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2789 */ 2790 static bge_regno_t shutdown_engine_regs[] = { 2791 RECEIVE_MAC_MODE_REG, 2792 RCV_BD_INITIATOR_MODE_REG, 2793 RCV_LIST_PLACEMENT_MODE_REG, 2794 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2795 RCV_DATA_BD_INITIATOR_MODE_REG, 2796 RCV_DATA_COMPLETION_MODE_REG, 2797 RCV_BD_COMPLETION_MODE_REG, 2798 2799 SEND_BD_SELECTOR_MODE_REG, 2800 SEND_BD_INITIATOR_MODE_REG, 2801 SEND_DATA_INITIATOR_MODE_REG, 2802 READ_DMA_MODE_REG, 2803 SEND_DATA_COMPLETION_MODE_REG, 2804 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2805 SEND_BD_COMPLETION_MODE_REG, 2806 TRANSMIT_MAC_MODE_REG, 2807 2808 HOST_COALESCE_MODE_REG, 2809 WRITE_DMA_MODE_REG, 2810 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2811 FTQ_RESET_REG, /* special - see code */ 2812 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2813 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2814 BGE_REGNO_NONE /* terminator */ 2815 }; 2816 2817 /* 2818 * bge_chip_stop() -- stop all chip processing 2819 * 2820 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2821 * we've detected a problem internally; otherwise, this is a normal 2822 * (clean) stop (at user request i.e. the last STREAM has been closed). 2823 */ 2824 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2825 #pragma no_inline(bge_chip_stop) 2826 2827 void 2828 bge_chip_stop(bge_t *bgep, boolean_t fault) 2829 { 2830 bge_regno_t regno; 2831 bge_regno_t *rbp; 2832 boolean_t ok; 2833 2834 BGE_TRACE(("bge_chip_stop($%p)", 2835 (void *)bgep)); 2836 2837 ASSERT(mutex_owned(bgep->genlock)); 2838 2839 rbp = shutdown_engine_regs; 2840 /* 2841 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2842 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2843 * -ory arbiter should not be disabled. 2844 */ 2845 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2846 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2847 ok &= bge_chip_disable_engine(bgep, regno, 0); 2848 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2849 (regno != DMA_COMPLETION_MODE_REG) && 2850 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2851 (regno != BUFFER_MANAGER_MODE_REG) && 2852 (regno != MEMORY_ARBITER_MODE_REG)) 2853 ok &= bge_chip_disable_engine(bgep, 2854 regno, 0); 2855 } 2856 2857 if (!ok && !fault) 2858 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2859 2860 /* 2861 * Finally, disable (all) MAC events & clear the MAC status 2862 */ 2863 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2864 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2865 2866 /* 2867 * if we're stopping the chip because of a detected fault then do 2868 * appropriate actions 2869 */ 2870 if (fault) { 2871 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2872 bgep->bge_chip_state = BGE_CHIP_FAULT; 2873 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2874 if (bgep->bge_dma_error) { 2875 /* 2876 * need to free buffers in case the fault was 2877 * due to a memory error in a buffer - got to 2878 * do a fair bit of tidying first 2879 */ 2880 if (bgep->progress & PROGRESS_KSTATS) { 2881 bge_fini_kstats(bgep); 2882 bgep->progress &= ~PROGRESS_KSTATS; 2883 } 2884 if (bgep->progress & PROGRESS_INTR) { 2885 bge_intr_disable(bgep); 2886 rw_enter(bgep->errlock, RW_WRITER); 2887 bge_fini_rings(bgep); 2888 rw_exit(bgep->errlock); 2889 bgep->progress &= ~PROGRESS_INTR; 2890 } 2891 if (bgep->progress & PROGRESS_BUFS) { 2892 bge_free_bufs(bgep); 2893 bgep->progress &= ~PROGRESS_BUFS; 2894 } 2895 bgep->bge_dma_error = B_FALSE; 2896 } 2897 } 2898 } else 2899 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2900 } 2901 2902 /* 2903 * Poll for completion of chip's ROM firmware; also, at least on the 2904 * first time through, find and return the hardware MAC address, if any. 2905 */ 2906 static uint64_t bge_poll_firmware(bge_t *bgep); 2907 #pragma no_inline(bge_poll_firmware) 2908 2909 static uint64_t 2910 bge_poll_firmware(bge_t *bgep) 2911 { 2912 uint64_t magic; 2913 uint64_t mac; 2914 uint32_t gen; 2915 uint32_t i; 2916 2917 /* 2918 * Step 19: poll for firmware completion (GENCOMM port set 2919 * to the ones complement of T3_MAGIC_NUMBER). 2920 * 2921 * While we're at it, we also read the MAC address register; 2922 * at some stage the firmware will load this with the 2923 * factory-set value. 2924 * 2925 * When both the magic number and the MAC address are set, 2926 * we're done; but we impose a time limit of one second 2927 * (1000*1000us) in case the firmware fails in some fashion 2928 * or the SEEPROM that provides that MAC address isn't fitted. 2929 * 2930 * After the first time through (chip state != INITIAL), we 2931 * don't need the MAC address to be set (we've already got it 2932 * or not, from the first time), so we don't wait for it, but 2933 * we still have to wait for the T3_MAGIC_NUMBER. 2934 * 2935 * Note: the magic number is only a 32-bit quantity, but the NIC 2936 * memory is 64-bit (and big-endian) internally. Addressing the 2937 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2938 * it work correctly on both big- and little-endian hosts. 2939 */ 2940 for (i = 0; i < 1000; ++i) { 2941 drv_usecwait(1000); 2942 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2943 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2944 #ifdef BGE_IPMI_ASF 2945 if (!bgep->asf_enabled) { 2946 #endif 2947 if (gen != ~T3_MAGIC_NUMBER) 2948 continue; 2949 #ifdef BGE_IPMI_ASF 2950 } 2951 #endif 2952 if (mac != 0ULL) 2953 break; 2954 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2955 break; 2956 } 2957 2958 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2959 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2960 (void *)bgep, gen, i)); 2961 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2962 mac, magic)); 2963 2964 return (mac); 2965 } 2966 2967 /* 2968 * Maximum times of trying to get the NVRAM access lock 2969 * by calling bge_nvmem_acquire() 2970 */ 2971 #define MAX_TRY_NVMEM_ACQUIRE 10000 2972 2973 #ifdef BGE_IPMI_ASF 2974 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2975 #else 2976 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2977 #endif 2978 #pragma no_inline(bge_chip_reset) 2979 2980 int 2981 #ifdef BGE_IPMI_ASF 2982 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2983 #else 2984 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2985 #endif 2986 { 2987 chip_id_t chipid; 2988 uint64_t mac; 2989 uint64_t magic; 2990 uint32_t modeflags; 2991 uint32_t mhcr; 2992 uint32_t sx0; 2993 uint32_t i, tries; 2994 #ifdef BGE_IPMI_ASF 2995 uint32_t mailbox; 2996 #endif 2997 int retval = DDI_SUCCESS; 2998 2999 BGE_TRACE(("bge_chip_reset($%p, %d)", 3000 (void *)bgep, enable_dma)); 3001 3002 ASSERT(mutex_owned(bgep->genlock)); 3003 3004 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3005 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3006 3007 /* 3008 * Do we need to stop the chip cleanly before resetting? 3009 */ 3010 switch (bgep->bge_chip_state) { 3011 default: 3012 _NOTE(NOTREACHED) 3013 return (DDI_FAILURE); 3014 3015 case BGE_CHIP_INITIAL: 3016 case BGE_CHIP_STOPPED: 3017 case BGE_CHIP_RESET: 3018 break; 3019 3020 case BGE_CHIP_RUNNING: 3021 case BGE_CHIP_ERROR: 3022 case BGE_CHIP_FAULT: 3023 bge_chip_stop(bgep, B_FALSE); 3024 break; 3025 } 3026 3027 #ifdef BGE_IPMI_ASF 3028 if (bgep->asf_enabled) { 3029 if (asf_mode == ASF_MODE_INIT) { 3030 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3031 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3032 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3033 } 3034 } 3035 #endif 3036 /* 3037 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3038 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3039 * 3040 * Before reset Core clock,it is 3041 * also required to initialize the Memory Arbiter as specified in step9 3042 * and Misc Host Control Register as specified in step-13 3043 * Step 4-5: reset Core clock & wait for completion 3044 * Steps 6-8: are done by bge_chip_cfg_init() 3045 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3046 */ 3047 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3048 retval = DDI_FAILURE; 3049 3050 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3051 MHCR_ENABLE_TAGGED_STATUS_MODE | 3052 MHCR_MASK_INTERRUPT_MODE | 3053 MHCR_MASK_PCI_INT_OUTPUT | 3054 MHCR_CLEAR_INTERRUPT_INTA; 3055 #ifdef _BIG_ENDIAN 3056 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3057 #endif /* _BIG_ENDIAN */ 3058 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3059 #ifdef BGE_IPMI_ASF 3060 if (bgep->asf_enabled) 3061 bgep->asf_wordswapped = B_FALSE; 3062 #endif 3063 /* 3064 * NVRAM Corruption Workaround 3065 */ 3066 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3067 if (bge_nvmem_acquire(bgep) != EAGAIN) 3068 break; 3069 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3070 BGE_DEBUG(("%s: fail to acquire nvram lock", 3071 bgep->ifname)); 3072 3073 #ifdef BGE_IPMI_ASF 3074 if (!bgep->asf_enabled) { 3075 #endif 3076 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3077 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3078 #ifdef BGE_IPMI_ASF 3079 } 3080 #endif 3081 3082 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3083 retval = DDI_FAILURE; 3084 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3085 3086 /* 3087 * Step 8a: This may belong elsewhere, but BCM5721 needs 3088 * a bit set to avoid a fifo overflow/underflow bug. 3089 */ 3090 if ((bgep->chipid.chip_label == 5721) || 3091 (bgep->chipid.chip_label == 5751) || 3092 (bgep->chipid.chip_label == 5752) || 3093 (bgep->chipid.chip_label == 5789)) 3094 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3095 3096 3097 /* 3098 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3099 * not be changed. 3100 */ 3101 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3102 retval = DDI_FAILURE; 3103 3104 /* 3105 * Steps 10-11: configure PIO endianness options and 3106 * enable indirect register access -- already done 3107 * Steps 12-13: enable writing to the PCI state & clock 3108 * control registers -- not required; we aren't going to 3109 * use those features. 3110 * Steps 14-15: Configure DMA endianness options. See 3111 * the comments on the setting of the MHCR above. 3112 */ 3113 #ifdef _BIG_ENDIAN 3114 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3115 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3116 #else 3117 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3118 #endif /* _BIG_ENDIAN */ 3119 #ifdef BGE_IPMI_ASF 3120 if (bgep->asf_enabled) 3121 modeflags |= MODE_HOST_STACK_UP; 3122 #endif 3123 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3124 3125 #ifdef BGE_IPMI_ASF 3126 if (bgep->asf_enabled) { 3127 if (asf_mode != ASF_MODE_NONE) { 3128 /* Wait for NVRAM init */ 3129 i = 0; 3130 drv_usecwait(5000); 3131 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3132 while ((mailbox != (uint32_t) 3133 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3134 (i < 10000)) { 3135 drv_usecwait(100); 3136 mailbox = bge_nic_get32(bgep, 3137 BGE_FIRMWARE_MAILBOX); 3138 i++; 3139 } 3140 if (!bgep->asf_newhandshake) { 3141 if ((asf_mode == ASF_MODE_INIT) || 3142 (asf_mode == ASF_MODE_POST_INIT)) { 3143 3144 bge_asf_post_reset_old_mode(bgep, 3145 BGE_INIT_RESET); 3146 } else { 3147 bge_asf_post_reset_old_mode(bgep, 3148 BGE_SHUTDOWN_RESET); 3149 } 3150 } 3151 } 3152 } 3153 #endif 3154 /* 3155 * Steps 16-17: poll for firmware completion 3156 */ 3157 mac = bge_poll_firmware(bgep); 3158 3159 /* 3160 * Step 18: enable external memory -- doesn't apply. 3161 * 3162 * However we take the opportunity to set the MLCR anyway, as 3163 * this register also controls the SEEPROM auto-access method 3164 * which we may want to use later ... 3165 * 3166 * The proper value here depends on the way the chip is wired 3167 * into the circuit board, as this register *also* controls which 3168 * of the "Miscellaneous I/O" pins are driven as outputs and the 3169 * values driven onto those pins! 3170 * 3171 * See also step 74 in the PRM ... 3172 */ 3173 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3174 bgep->chipid.bge_mlcr_default); 3175 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3176 3177 /* 3178 * Step 20: clear the Ethernet MAC mode register 3179 */ 3180 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3181 3182 /* 3183 * Step 21: restore cache-line-size, latency timer, and 3184 * subsystem ID registers to their original values (not 3185 * those read into the local structure <chipid>, 'cos 3186 * that was after they were cleared by the RESET). 3187 * 3188 * Note: the Subsystem Vendor/Device ID registers are not 3189 * directly writable in config space, so we use the shadow 3190 * copy in "Page Zero" of register space to restore them 3191 * both in one go ... 3192 */ 3193 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3194 bgep->chipid.clsize); 3195 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3196 bgep->chipid.latency); 3197 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3198 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3199 3200 /* 3201 * The SEND INDEX registers should be reset to zero by the 3202 * global chip reset; if they're not, there'll be trouble 3203 * later on. 3204 */ 3205 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3206 if (sx0 != 0) { 3207 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3208 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3209 retval = DDI_FAILURE; 3210 } 3211 3212 /* Enable MSI code */ 3213 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3214 bge_reg_set32(bgep, MSI_MODE_REG, 3215 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3216 3217 /* 3218 * On the first time through, save the factory-set MAC address 3219 * (if any). If bge_poll_firmware() above didn't return one 3220 * (from a chip register) consider looking in the attached NV 3221 * memory device, if any. Once we have it, we save it in both 3222 * register-image (64-bit) and byte-array forms. All-zero and 3223 * all-one addresses are not valid, and we refuse to stash those. 3224 */ 3225 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3226 if (mac == 0ULL) 3227 mac = bge_get_nvmac(bgep); 3228 if (mac != 0ULL && mac != ~0ULL) { 3229 bgep->chipid.hw_mac_addr = mac; 3230 for (i = ETHERADDRL; i-- != 0; ) { 3231 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3232 mac >>= 8; 3233 } 3234 bgep->chipid.vendor_addr.set = B_TRUE; 3235 } 3236 } 3237 3238 #ifdef BGE_IPMI_ASF 3239 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3240 if (asf_mode != ASF_MODE_NONE) { 3241 if ((asf_mode == ASF_MODE_INIT) || 3242 (asf_mode == ASF_MODE_POST_INIT)) { 3243 3244 bge_asf_post_reset_new_mode(bgep, 3245 BGE_INIT_RESET); 3246 } else { 3247 bge_asf_post_reset_new_mode(bgep, 3248 BGE_SHUTDOWN_RESET); 3249 } 3250 } 3251 } 3252 #endif 3253 3254 /* 3255 * Record the new state 3256 */ 3257 bgep->chip_resets += 1; 3258 bgep->bge_chip_state = BGE_CHIP_RESET; 3259 return (retval); 3260 } 3261 3262 /* 3263 * bge_chip_start() -- start the chip transmitting and/or receiving, 3264 * including enabling interrupts 3265 */ 3266 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3267 #pragma no_inline(bge_chip_start) 3268 3269 int 3270 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3271 { 3272 uint32_t coalmode; 3273 uint32_t ledctl; 3274 uint32_t mtu; 3275 uint32_t maxring; 3276 uint32_t stats_mask; 3277 uint64_t ring; 3278 int retval = DDI_SUCCESS; 3279 3280 BGE_TRACE(("bge_chip_start($%p)", 3281 (void *)bgep)); 3282 3283 ASSERT(mutex_owned(bgep->genlock)); 3284 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3285 3286 /* 3287 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3288 * The document specifies 95 separate steps to fully 3289 * initialise the chip!!!! 3290 * 3291 * The reset code above has already got us as far as step 3292 * 21, so we continue with ... 3293 * 3294 * Step 22: clear the MAC statistics block 3295 * (0x0300-0x0aff in NIC-local memory) 3296 */ 3297 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3298 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3299 NIC_MEM_STATISTICS_SIZE); 3300 3301 /* 3302 * Step 23: clear the status block (in host memory) 3303 */ 3304 DMA_ZERO(bgep->status_block); 3305 3306 /* 3307 * Step 24: set DMA read/write control register 3308 */ 3309 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3310 bgep->chipid.bge_dma_rwctrl); 3311 3312 /* 3313 * Step 25: Configure DMA endianness -- already done (16/17) 3314 * Step 26: Configure Host-Based Send Rings 3315 * Step 27: Indicate Host Stack Up 3316 */ 3317 bge_reg_set32(bgep, MODE_CONTROL_REG, 3318 MODE_HOST_SEND_BDS | 3319 MODE_HOST_STACK_UP); 3320 3321 /* 3322 * Step 28: Configure checksum options: 3323 * Solaris supports the hardware default checksum options. 3324 * 3325 * Workaround for Incorrect pseudo-header checksum calculation. 3326 */ 3327 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3328 bge_reg_set32(bgep, MODE_CONTROL_REG, 3329 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3330 3331 /* 3332 * Step 29: configure Timer Prescaler. The value is always the 3333 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3334 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3335 * for the whole chip! 3336 */ 3337 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3338 3339 /* 3340 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3341 * 3342 * If the mbuf_length is specified as 0, we just leave these at 3343 * their hardware defaults, rather than explicitly setting them. 3344 * As the Broadcom HRM,driver better not change the parameters 3345 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3346 */ 3347 if ((bgep->chipid.mbuf_length != 0) && 3348 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3349 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3350 bgep->chipid.mbuf_base); 3351 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3352 bgep->chipid.mbuf_length); 3353 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3354 DMAD_POOL_BASE_DEFAULT); 3355 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3356 DMAD_POOL_LENGTH_DEFAULT); 3357 } 3358 3359 /* 3360 * Step 32: configure MAC memory pool watermarks 3361 */ 3362 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3363 bgep->chipid.mbuf_lo_water_rdma); 3364 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3365 bgep->chipid.mbuf_lo_water_rmac); 3366 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3367 bgep->chipid.mbuf_hi_water); 3368 3369 /* 3370 * Step 33: configure DMA resource watermarks 3371 */ 3372 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3373 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3374 bge_dmad_lo_water); 3375 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3376 bge_dmad_hi_water); 3377 } 3378 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3379 3380 /* 3381 * Steps 34-36: enable buffer manager & internal h/w queues 3382 */ 3383 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3384 STATE_MACHINE_ATTN_ENABLE_BIT)) 3385 retval = DDI_FAILURE; 3386 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3387 retval = DDI_FAILURE; 3388 3389 /* 3390 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3391 */ 3392 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3393 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3394 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3395 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3396 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3397 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3398 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3399 } 3400 3401 /* 3402 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3403 */ 3404 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3405 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3406 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3407 bge_replenish_jumbo); 3408 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3409 bge_replenish_mini); 3410 } 3411 3412 /* 3413 * Steps 41-43: clear Send Ring Producer Indices and initialise 3414 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3415 */ 3416 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3417 maxring = BGE_SEND_RINGS_MAX; 3418 else 3419 maxring = BGE_SEND_RINGS_MAX_5705; 3420 for (ring = 0; ring < maxring; ++ring) { 3421 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3422 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3423 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3424 &bgep->send[ring].hw_rcb); 3425 } 3426 3427 /* 3428 * Steps 44-45: initialise Receive Return Rings 3429 * (0x0200-0x02ff in NIC-local memory) 3430 */ 3431 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3432 maxring = BGE_RECV_RINGS_MAX; 3433 else 3434 maxring = BGE_RECV_RINGS_MAX_5705; 3435 for (ring = 0; ring < maxring; ++ring) 3436 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3437 &bgep->recv[ring].hw_rcb); 3438 3439 /* 3440 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3441 */ 3442 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3443 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3444 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3445 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3446 } 3447 /* 3448 * Step 47: configure the MAC unicast address 3449 * Step 48: configure the random backoff seed 3450 * Step 96: set up multicast filters 3451 */ 3452 #ifdef BGE_IPMI_ASF 3453 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3454 #else 3455 if (bge_chip_sync(bgep) == DDI_FAILURE) 3456 #endif 3457 retval = DDI_FAILURE; 3458 3459 /* 3460 * Step 49: configure the MTU 3461 */ 3462 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3463 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3464 3465 /* 3466 * Step 50: configure the IPG et al 3467 */ 3468 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3469 3470 /* 3471 * Step 51: configure the default Rx Return Ring 3472 */ 3473 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3474 3475 /* 3476 * Steps 52-54: configure Receive List Placement, 3477 * and enable Receive List Placement Statistics 3478 */ 3479 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3480 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3481 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3482 case MHCR_CHIP_ASIC_REV_5700: 3483 case MHCR_CHIP_ASIC_REV_5701: 3484 case MHCR_CHIP_ASIC_REV_5703: 3485 case MHCR_CHIP_ASIC_REV_5704: 3486 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3487 break; 3488 case MHCR_CHIP_ASIC_REV_5705: 3489 break; 3490 default: 3491 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3492 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3493 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3494 break; 3495 } 3496 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3497 3498 if (bgep->chipid.rx_rings > 1) 3499 bge_init_recv_rule(bgep); 3500 3501 /* 3502 * Steps 55-56: enable Send Data Initiator Statistics 3503 */ 3504 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3505 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3506 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3507 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3508 } else { 3509 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3510 SEND_INIT_STATS_ENABLE); 3511 } 3512 /* 3513 * Steps 57-58: stop (?) the Host Coalescing Engine 3514 */ 3515 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3516 retval = DDI_FAILURE; 3517 3518 /* 3519 * Steps 59-62: initialise Host Coalescing parameters 3520 */ 3521 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3522 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3523 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3524 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3525 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3526 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3527 bge_tx_count_intr); 3528 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3529 bge_tx_ticks_intr); 3530 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3531 bge_rx_count_intr); 3532 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3533 bge_rx_ticks_intr); 3534 } 3535 3536 /* 3537 * Steps 63-64: initialise status block & statistics 3538 * host memory addresses 3539 * The statistic block does not exist in some chipsets 3540 * Step 65: initialise Statistics Coalescing Tick Counter 3541 */ 3542 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3543 bgep->status_block.cookie.dmac_laddress); 3544 3545 /* 3546 * Steps 66-67: initialise status block & statistics 3547 * NIC-local memory addresses 3548 */ 3549 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3550 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3551 bgep->statistics.cookie.dmac_laddress); 3552 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3553 STATISTICS_TICKS_DEFAULT); 3554 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3555 NIC_MEM_STATUS_BLOCK); 3556 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3557 NIC_MEM_STATISTICS); 3558 } 3559 3560 /* 3561 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3562 * Completion Engine, the Receive List Placement Engine, and the 3563 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3564 * and BCM5715. 3565 */ 3566 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3567 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3568 coalmode = COALESCE_64_BYTE_STATUS; 3569 else 3570 coalmode = 0; 3571 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3572 retval = DDI_FAILURE; 3573 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3574 STATE_MACHINE_ATTN_ENABLE_BIT)) 3575 retval = DDI_FAILURE; 3576 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3577 retval = DDI_FAILURE; 3578 3579 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3580 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3581 STATE_MACHINE_ATTN_ENABLE_BIT)) 3582 retval = DDI_FAILURE; 3583 3584 /* 3585 * Step 72: Enable MAC DMA engines 3586 * Step 73: Clear & enable MAC statistics 3587 */ 3588 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3589 ETHERNET_MODE_ENABLE_FHDE | 3590 ETHERNET_MODE_ENABLE_RDE | 3591 ETHERNET_MODE_ENABLE_TDE); 3592 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3593 ETHERNET_MODE_ENABLE_TX_STATS | 3594 ETHERNET_MODE_ENABLE_RX_STATS | 3595 ETHERNET_MODE_CLEAR_TX_STATS | 3596 ETHERNET_MODE_CLEAR_RX_STATS); 3597 3598 /* 3599 * Step 74: configure the MLCR (Miscellaneous Local Control 3600 * Register); not required, as we set up the MLCR in step 10 3601 * (part of the reset code) above. 3602 * 3603 * Step 75: clear Interrupt Mailbox 0 3604 */ 3605 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3606 3607 /* 3608 * Steps 76-87: Gentlemen, start your engines ... 3609 * 3610 * Enable the DMA Completion Engine, the Write DMA Engine, 3611 * the Read DMA Engine, Receive Data Completion Engine, 3612 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3613 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3614 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3615 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3616 * 3617 * Beware exhaust fumes? 3618 */ 3619 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3620 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3621 retval = DDI_FAILURE; 3622 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3623 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3624 retval = DDI_FAILURE; 3625 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3626 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3627 retval = DDI_FAILURE; 3628 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3629 STATE_MACHINE_ATTN_ENABLE_BIT)) 3630 retval = DDI_FAILURE; 3631 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3632 if (!bge_chip_enable_engine(bgep, 3633 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3634 retval = DDI_FAILURE; 3635 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3636 retval = DDI_FAILURE; 3637 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3638 STATE_MACHINE_ATTN_ENABLE_BIT)) 3639 retval = DDI_FAILURE; 3640 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3641 RCV_BD_DISABLED_RING_ATTN)) 3642 retval = DDI_FAILURE; 3643 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3644 RCV_DATA_BD_ILL_RING_ATTN)) 3645 retval = DDI_FAILURE; 3646 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3647 retval = DDI_FAILURE; 3648 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3649 STATE_MACHINE_ATTN_ENABLE_BIT)) 3650 retval = DDI_FAILURE; 3651 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3652 STATE_MACHINE_ATTN_ENABLE_BIT)) 3653 retval = DDI_FAILURE; 3654 3655 /* 3656 * Step 88: download firmware -- doesn't apply 3657 * Steps 89-90: enable Transmit & Receive MAC Engines 3658 */ 3659 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3660 retval = DDI_FAILURE; 3661 #ifdef BGE_IPMI_ASF 3662 if (!bgep->asf_enabled) { 3663 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3664 RECEIVE_MODE_KEEP_VLAN_TAG)) 3665 retval = DDI_FAILURE; 3666 } else { 3667 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3668 retval = DDI_FAILURE; 3669 } 3670 #else 3671 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3672 RECEIVE_MODE_KEEP_VLAN_TAG)) 3673 retval = DDI_FAILURE; 3674 #endif 3675 3676 /* 3677 * Step 91: disable auto-polling of PHY status 3678 */ 3679 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3680 3681 /* 3682 * Step 92: configure D0 power state (not required) 3683 * Step 93: initialise LED control register () 3684 */ 3685 ledctl = LED_CONTROL_DEFAULT; 3686 switch (bgep->chipid.device) { 3687 case DEVICE_ID_5700: 3688 case DEVICE_ID_5700x: 3689 case DEVICE_ID_5701: 3690 /* 3691 * Switch to 5700 (MAC) mode on these older chips 3692 */ 3693 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3694 ledctl |= LED_CONTROL_LED_MODE_5700; 3695 break; 3696 3697 default: 3698 break; 3699 } 3700 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3701 3702 /* 3703 * Step 94: activate link 3704 */ 3705 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3706 3707 /* 3708 * Step 95: set up physical layer (PHY/SerDes) 3709 * restart autoneg (if required) 3710 */ 3711 if (reset_phys) 3712 if (bge_phys_update(bgep) == DDI_FAILURE) 3713 retval = DDI_FAILURE; 3714 3715 /* 3716 * Extra step (DSG): hand over all the Receive Buffers to the chip 3717 */ 3718 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3719 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3720 bgep->buff[ring].rf_next); 3721 3722 /* 3723 * MSI bits:The least significant MSI 16-bit word. 3724 * ISR will be triggered different. 3725 */ 3726 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3727 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3728 3729 /* 3730 * Extra step (DSG): select which interrupts are enabled 3731 * 3732 * Program the Ethernet MAC engine to signal attention on 3733 * Link Change events, then enable interrupts on MAC, DMA, 3734 * and FLOW attention signals. 3735 */ 3736 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3737 ETHERNET_EVENT_LINK_INT | 3738 ETHERNET_STATUS_PCS_ERROR_INT); 3739 #ifdef BGE_IPMI_ASF 3740 if (bgep->asf_enabled) { 3741 bge_reg_set32(bgep, MODE_CONTROL_REG, 3742 MODE_INT_ON_FLOW_ATTN | 3743 MODE_INT_ON_DMA_ATTN | 3744 MODE_HOST_STACK_UP| 3745 MODE_INT_ON_MAC_ATTN); 3746 } else { 3747 #endif 3748 bge_reg_set32(bgep, MODE_CONTROL_REG, 3749 MODE_INT_ON_FLOW_ATTN | 3750 MODE_INT_ON_DMA_ATTN | 3751 MODE_INT_ON_MAC_ATTN); 3752 #ifdef BGE_IPMI_ASF 3753 } 3754 #endif 3755 3756 /* 3757 * Step 97: enable PCI interrupts!!! 3758 */ 3759 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3760 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3761 MHCR_MASK_PCI_INT_OUTPUT); 3762 3763 /* 3764 * All done! 3765 */ 3766 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3767 return (retval); 3768 } 3769 3770 3771 /* 3772 * ========== Hardware interrupt handler ========== 3773 */ 3774 3775 #undef BGE_DBG 3776 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3777 3778 /* 3779 * Sync the status block, then atomically clear the specified bits in 3780 * the <flags-and-tag> field of the status block. 3781 * the <flags> word of the status block, returning the value of the 3782 * <tag> and the <flags> before the bits were cleared. 3783 */ 3784 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3785 #pragma inline(bge_status_sync) 3786 3787 static int 3788 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3789 { 3790 bge_status_t *bsp; 3791 int retval; 3792 3793 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3794 (void *)bgep, bits)); 3795 3796 ASSERT(bgep->bge_guard == BGE_GUARD); 3797 3798 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3799 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3800 if (retval != DDI_FM_OK) 3801 return (retval); 3802 3803 bsp = DMA_VPTR(bgep->status_block); 3804 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3805 3806 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3807 (void *)bgep, bits, *flags)); 3808 3809 return (retval); 3810 } 3811 3812 static void bge_wake_factotum(bge_t *bgep); 3813 #pragma inline(bge_wake_factotum) 3814 3815 static void 3816 bge_wake_factotum(bge_t *bgep) 3817 { 3818 mutex_enter(bgep->softintrlock); 3819 if (bgep->factotum_flag == 0) { 3820 bgep->factotum_flag = 1; 3821 ddi_trigger_softintr(bgep->factotum_id); 3822 } 3823 mutex_exit(bgep->softintrlock); 3824 } 3825 3826 /* 3827 * bge_intr() -- handle chip interrupts 3828 */ 3829 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3830 #pragma no_inline(bge_intr) 3831 3832 uint_t 3833 bge_intr(caddr_t arg1, caddr_t arg2) 3834 { 3835 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3836 bge_status_t *bsp; 3837 uint64_t flags; 3838 uint32_t mlcr = 0; 3839 uint_t result; 3840 int retval; 3841 3842 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3843 3844 /* 3845 * GLD v2 checks that s/w setup is complete before passing 3846 * interrupts to this routine, thus eliminating the old 3847 * (and well-known) race condition around ddi_add_intr() 3848 */ 3849 ASSERT(bgep->progress & PROGRESS_HWINT); 3850 3851 /* 3852 * Check whether chip's says it's asserting #INTA; 3853 * if not, don't process or claim the interrupt. 3854 * 3855 * Note that the PCI signal is active low, so the 3856 * bit is *zero* when the interrupt is asserted. 3857 */ 3858 result = DDI_INTR_UNCLAIMED; 3859 mutex_enter(bgep->genlock); 3860 3861 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3862 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3863 3864 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3865 3866 if ((mlcr & MLCR_INTA_STATE) == 0) { 3867 /* 3868 * Block further PCI interrupts ... 3869 */ 3870 result = DDI_INTR_CLAIMED; 3871 3872 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3873 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3874 MHCR_MASK_PCI_INT_OUTPUT); 3875 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 3876 DDI_FM_OK) 3877 goto chip_stop; 3878 } 3879 3880 /* 3881 * Sync the status block and grab the flags-n-tag from it. 3882 * We count the number of interrupts where there doesn't 3883 * seem to have been a DMA update of the status block; if 3884 * it *has* been updated, the counter will be cleared in 3885 * the while() loop below ... 3886 */ 3887 bgep->missed_dmas += 1; 3888 bsp = DMA_VPTR(bgep->status_block); 3889 for (;;) { 3890 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3891 /* 3892 * bge_chip_stop() may have freed dma area etc 3893 * while we were in this interrupt handler - 3894 * better not call bge_status_sync() 3895 */ 3896 (void) bge_check_acc_handle(bgep, 3897 bgep->io_handle); 3898 mutex_exit(bgep->genlock); 3899 return (DDI_INTR_CLAIMED); 3900 } 3901 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3902 &flags); 3903 if (retval != DDI_FM_OK) { 3904 bgep->bge_dma_error = B_TRUE; 3905 goto chip_stop; 3906 } 3907 3908 if (!(flags & STATUS_FLAG_UPDATED)) 3909 break; 3910 3911 /* 3912 * Tell the chip that we're processing the interrupt 3913 */ 3914 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3915 INTERRUPT_MBOX_DISABLE(flags)); 3916 if (bge_check_acc_handle(bgep, bgep->io_handle) != 3917 DDI_FM_OK) 3918 goto chip_stop; 3919 3920 /* 3921 * Drop the mutex while we: 3922 * Receive any newly-arrived packets 3923 * Recycle any newly-finished send buffers 3924 */ 3925 bgep->bge_intr_running = B_TRUE; 3926 mutex_exit(bgep->genlock); 3927 bge_receive(bgep, bsp); 3928 bge_recycle(bgep, bsp); 3929 mutex_enter(bgep->genlock); 3930 bgep->bge_intr_running = B_FALSE; 3931 3932 /* 3933 * Tell the chip we've finished processing, and 3934 * give it the tag that we got from the status 3935 * block earlier, so that it knows just how far 3936 * we've gone. If it's got more for us to do, 3937 * it will now update the status block and try 3938 * to assert an interrupt (but we've got the 3939 * #INTA blocked at present). If we see the 3940 * update, we'll loop around to do some more. 3941 * Eventually we'll get out of here ... 3942 */ 3943 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3944 INTERRUPT_MBOX_ENABLE(flags)); 3945 bgep->missed_dmas = 0; 3946 } 3947 3948 /* 3949 * Check for exceptional conditions that we need to handle 3950 * 3951 * Link status changed 3952 * Status block not updated 3953 */ 3954 if (flags & STATUS_FLAG_LINK_CHANGED) 3955 bge_wake_factotum(bgep); 3956 3957 if (bgep->missed_dmas) { 3958 /* 3959 * Probably due to the internal status tag not 3960 * being reset. Force a status block update now; 3961 * this should ensure that we get an update and 3962 * a new interrupt. After that, we should be in 3963 * sync again ... 3964 */ 3965 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3966 "not updated?", flags)); 3967 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3968 COALESCE_NOW); 3969 3970 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3971 /* 3972 * If this happens multiple times in a row, 3973 * it means DMA is just not working. Maybe 3974 * the chip's failed, or maybe there's a 3975 * problem on the PCI bus or in the host-PCI 3976 * bridge (Tomatillo). 3977 * 3978 * At all events, we want to stop further 3979 * interrupts and let the recovery code take 3980 * over to see whether anything can be done 3981 * about it ... 3982 */ 3983 bge_fm_ereport(bgep, 3984 DDI_FM_DEVICE_BADINT_LIMIT); 3985 goto chip_stop; 3986 } 3987 } 3988 3989 /* 3990 * Reenable assertion of #INTA, unless there's a DMA fault 3991 */ 3992 if (result == DDI_INTR_CLAIMED) { 3993 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3994 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 3995 MHCR_MASK_PCI_INT_OUTPUT); 3996 if (bge_check_acc_handle(bgep, 3997 bgep->cfg_handle) != DDI_FM_OK) 3998 goto chip_stop; 3999 } 4000 } 4001 } 4002 4003 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4004 goto chip_stop; 4005 4006 mutex_exit(bgep->genlock); 4007 return (result); 4008 4009 chip_stop: 4010 #ifdef BGE_IPMI_ASF 4011 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4012 /* 4013 * We must stop ASF heart beat before 4014 * bge_chip_stop(), otherwise some 4015 * computers (ex. IBM HS20 blade 4016 * server) may crash. 4017 */ 4018 bge_asf_update_status(bgep); 4019 bge_asf_stop_timer(bgep); 4020 bgep->asf_status = ASF_STAT_STOP; 4021 4022 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4023 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4024 } 4025 #endif 4026 bge_chip_stop(bgep, B_TRUE); 4027 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4028 mutex_exit(bgep->genlock); 4029 return (result); 4030 } 4031 4032 /* 4033 * ========== Factotum, implemented as a softint handler ========== 4034 */ 4035 4036 #undef BGE_DBG 4037 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4038 4039 static void bge_factotum_error_handler(bge_t *bgep); 4040 #pragma no_inline(bge_factotum_error_handler) 4041 4042 static void 4043 bge_factotum_error_handler(bge_t *bgep) 4044 { 4045 uint32_t flow; 4046 uint32_t rdma; 4047 uint32_t wdma; 4048 uint32_t tmac; 4049 uint32_t rmac; 4050 uint32_t rxrs; 4051 uint32_t txrs = 0; 4052 4053 ASSERT(mutex_owned(bgep->genlock)); 4054 4055 /* 4056 * Read all the registers that show the possible 4057 * reasons for the ERROR bit to be asserted 4058 */ 4059 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4060 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4061 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4062 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4063 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4064 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4065 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4066 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4067 4068 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4069 (void *)bgep, flow, rdma, wdma)); 4070 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4071 (void *)bgep, tmac, rmac, rxrs, txrs)); 4072 4073 /* 4074 * For now, just clear all the errors ... 4075 */ 4076 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4077 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4078 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4079 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4080 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4081 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4082 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4083 } 4084 4085 /* 4086 * Handler for hardware link state change. 4087 * 4088 * When this routine is called, the hardware link state has changed 4089 * and the new state is reflected in the param_* variables. Here 4090 * we must update the softstate, reprogram the MAC to match, and 4091 * record the change in the log and/or on the console. 4092 */ 4093 static void bge_factotum_link_handler(bge_t *bgep); 4094 #pragma no_inline(bge_factotum_link_handler) 4095 4096 static void 4097 bge_factotum_link_handler(bge_t *bgep) 4098 { 4099 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4100 const char *msg; 4101 hrtime_t deltat; 4102 4103 ASSERT(mutex_owned(bgep->genlock)); 4104 4105 /* 4106 * Update the s/w link_state 4107 */ 4108 if (bgep->param_link_up) 4109 bgep->link_state = LINK_STATE_UP; 4110 else 4111 bgep->link_state = LINK_STATE_DOWN; 4112 4113 /* 4114 * Reprogram the MAC modes to match 4115 */ 4116 bge_sync_mac_modes(bgep); 4117 4118 /* 4119 * Finally, we have to decide whether to write a message 4120 * on the console or only in the log. If the PHY has 4121 * been reprogrammed (at user request) "recently", then 4122 * the message only goes in the log. Otherwise it's an 4123 * "unexpected" event, and it goes on the console as well. 4124 */ 4125 deltat = bgep->phys_event_time - bgep->phys_write_time; 4126 if (deltat > BGE_LINK_SETTLE_TIME) 4127 msg = ""; 4128 else if (bgep->param_link_up) 4129 msg = bgep->link_up_msg; 4130 else 4131 msg = bgep->link_down_msg; 4132 4133 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4134 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4135 } 4136 4137 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4138 #pragma no_inline(bge_factotum_link_check) 4139 4140 static boolean_t 4141 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4142 { 4143 boolean_t check; 4144 uint64_t flags; 4145 uint32_t tmac_status; 4146 4147 ASSERT(mutex_owned(bgep->genlock)); 4148 4149 /* 4150 * Get & clear the writable status bits in the Tx status register 4151 * (some bits are write-1-to-clear, others are just readonly). 4152 */ 4153 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4154 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4155 4156 /* 4157 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4158 */ 4159 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4160 STATUS_FLAG_LINK_CHANGED, &flags); 4161 if (*dma_state != DDI_FM_OK) 4162 return (B_FALSE); 4163 4164 /* 4165 * Clear any errors flagged in the status block ... 4166 */ 4167 if (flags & STATUS_FLAG_ERROR) 4168 bge_factotum_error_handler(bgep); 4169 4170 /* 4171 * We need to check the link status if: 4172 * the status block says there's been a link change 4173 * or there's any discrepancy between the various 4174 * flags indicating the link state (link_state, 4175 * param_link_up, and the LINK STATE bit in the 4176 * Transmit MAC status register). 4177 */ 4178 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4179 switch (bgep->link_state) { 4180 case LINK_STATE_UP: 4181 check |= (bgep->param_link_up == B_FALSE); 4182 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4183 break; 4184 4185 case LINK_STATE_DOWN: 4186 check |= (bgep->param_link_up != B_FALSE); 4187 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4188 break; 4189 4190 default: 4191 check = B_TRUE; 4192 break; 4193 } 4194 4195 /* 4196 * If <check> is false, we're sure the link hasn't changed. 4197 * If true, however, it's not yet definitive; we have to call 4198 * bge_phys_check() to determine whether the link has settled 4199 * into a new state yet ... and if it has, then call the link 4200 * state change handler.But when the chip is 5700 in Dell 6650 4201 * ,even if check is false, the link may have changed.So we 4202 * have to call bge_phys_check() to determine the link state. 4203 */ 4204 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4205 check = bge_phys_check(bgep); 4206 if (check) 4207 bge_factotum_link_handler(bgep); 4208 } 4209 4210 return (check); 4211 } 4212 4213 /* 4214 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4215 */ 4216 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4217 #pragma no_inline(bge_factotum_stall_check) 4218 4219 static boolean_t 4220 bge_factotum_stall_check(bge_t *bgep) 4221 { 4222 uint32_t dogval; 4223 4224 ASSERT(mutex_owned(bgep->genlock)); 4225 4226 /* 4227 * Specific check for Tx stall ... 4228 * 4229 * The 'watchdog' counter is incremented whenever a packet 4230 * is queued, reset to 1 when some (but not all) buffers 4231 * are reclaimed, reset to 0 (disabled) when all buffers 4232 * are reclaimed, and shifted left here. If it exceeds the 4233 * threshold value, the chip is assumed to have stalled and 4234 * is put into the ERROR state. The factotum will then reset 4235 * it on the next pass. 4236 * 4237 * All of which should ensure that we don't get into a state 4238 * where packets are left pending indefinitely! 4239 */ 4240 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4241 if (dogval < bge_watchdog_count) 4242 return (B_FALSE); 4243 4244 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4245 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4246 return (B_TRUE); 4247 } 4248 4249 /* 4250 * The factotum is woken up when there's something to do that we'd rather 4251 * not do from inside a hardware interrupt handler or high-level cyclic. 4252 * Its two main tasks are: 4253 * reset & restart the chip after an error 4254 * check the link status whenever necessary 4255 */ 4256 uint_t bge_chip_factotum(caddr_t arg); 4257 #pragma no_inline(bge_chip_factotum) 4258 4259 uint_t 4260 bge_chip_factotum(caddr_t arg) 4261 { 4262 bge_t *bgep; 4263 uint_t result; 4264 boolean_t error; 4265 boolean_t linkchg; 4266 int dma_state; 4267 4268 bgep = (bge_t *)arg; 4269 4270 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4271 4272 mutex_enter(bgep->softintrlock); 4273 if (bgep->factotum_flag == 0) { 4274 mutex_exit(bgep->softintrlock); 4275 return (DDI_INTR_UNCLAIMED); 4276 } 4277 bgep->factotum_flag = 0; 4278 mutex_exit(bgep->softintrlock); 4279 4280 result = DDI_INTR_CLAIMED; 4281 error = B_FALSE; 4282 linkchg = B_FALSE; 4283 4284 mutex_enter(bgep->genlock); 4285 switch (bgep->bge_chip_state) { 4286 default: 4287 break; 4288 4289 case BGE_CHIP_RUNNING: 4290 linkchg = bge_factotum_link_check(bgep, &dma_state); 4291 error = bge_factotum_stall_check(bgep); 4292 if (dma_state != DDI_FM_OK) { 4293 bgep->bge_dma_error = B_TRUE; 4294 error = B_TRUE; 4295 } 4296 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4297 error = B_TRUE; 4298 if (error) 4299 bgep->bge_chip_state = BGE_CHIP_ERROR; 4300 break; 4301 4302 case BGE_CHIP_ERROR: 4303 error = B_TRUE; 4304 break; 4305 4306 case BGE_CHIP_FAULT: 4307 /* 4308 * Fault detected, time to reset ... 4309 */ 4310 if (bge_autorecover) { 4311 if (!(bgep->progress & PROGRESS_BUFS)) { 4312 /* 4313 * if we can't allocate the ring buffers, 4314 * try later 4315 */ 4316 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4317 mutex_exit(bgep->genlock); 4318 return (result); 4319 } 4320 bgep->progress |= PROGRESS_BUFS; 4321 } 4322 if (!(bgep->progress & PROGRESS_INTR)) { 4323 bge_init_rings(bgep); 4324 bge_intr_enable(bgep); 4325 bgep->progress |= PROGRESS_INTR; 4326 } 4327 if (!(bgep->progress & PROGRESS_KSTATS)) { 4328 bge_init_kstats(bgep, 4329 ddi_get_instance(bgep->devinfo)); 4330 bgep->progress |= PROGRESS_KSTATS; 4331 } 4332 4333 BGE_REPORT((bgep, "automatic recovery activated")); 4334 4335 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4336 bgep->bge_chip_state = BGE_CHIP_ERROR; 4337 error = B_TRUE; 4338 } 4339 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4340 DDI_FM_OK) { 4341 bgep->bge_chip_state = BGE_CHIP_ERROR; 4342 error = B_TRUE; 4343 } 4344 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4345 DDI_FM_OK) { 4346 bgep->bge_chip_state = BGE_CHIP_ERROR; 4347 error = B_TRUE; 4348 } 4349 if (error == B_FALSE) { 4350 #ifdef BGE_IPMI_ASF 4351 if (bgep->asf_enabled && 4352 bgep->asf_status != ASF_STAT_RUN) { 4353 bgep->asf_timeout_id = timeout( 4354 bge_asf_heartbeat, (void *)bgep, 4355 drv_usectohz( 4356 BGE_ASF_HEARTBEAT_INTERVAL)); 4357 bgep->asf_status = ASF_STAT_RUN; 4358 } 4359 #endif 4360 ddi_fm_service_impact(bgep->devinfo, 4361 DDI_SERVICE_RESTORED); 4362 } 4363 } 4364 break; 4365 } 4366 4367 4368 /* 4369 * If an error is detected, stop the chip now, marking it as 4370 * faulty, so that it will be reset next time through ... 4371 * 4372 * Note that if intr_running is set, then bge_intr() has dropped 4373 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4374 * this point so have to wait until the next time the factotum runs. 4375 */ 4376 if (error && !bgep->bge_intr_running) { 4377 #ifdef BGE_IPMI_ASF 4378 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4379 /* 4380 * We must stop ASF heart beat before bge_chip_stop(), 4381 * otherwise some computers (ex. IBM HS20 blade server) 4382 * may crash. 4383 */ 4384 bge_asf_update_status(bgep); 4385 bge_asf_stop_timer(bgep); 4386 bgep->asf_status = ASF_STAT_STOP; 4387 4388 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4389 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4390 } 4391 #endif 4392 bge_chip_stop(bgep, B_TRUE); 4393 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4394 } 4395 mutex_exit(bgep->genlock); 4396 4397 /* 4398 * If the link state changed, tell the world about it. 4399 * Note: can't do this while still holding the mutex. 4400 */ 4401 if (linkchg) 4402 mac_link_update(bgep->mh, bgep->link_state); 4403 4404 return (result); 4405 } 4406 4407 /* 4408 * High-level cyclic handler 4409 * 4410 * This routine schedules a (low-level) softint callback to the 4411 * factotum, and prods the chip to update the status block (which 4412 * will cause a hardware interrupt when complete). 4413 */ 4414 void bge_chip_cyclic(void *arg); 4415 #pragma no_inline(bge_chip_cyclic) 4416 4417 void 4418 bge_chip_cyclic(void *arg) 4419 { 4420 bge_t *bgep; 4421 4422 bgep = arg; 4423 4424 switch (bgep->bge_chip_state) { 4425 default: 4426 return; 4427 4428 case BGE_CHIP_RUNNING: 4429 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4430 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4431 ddi_fm_service_impact(bgep->devinfo, 4432 DDI_SERVICE_UNAFFECTED); 4433 break; 4434 4435 case BGE_CHIP_FAULT: 4436 case BGE_CHIP_ERROR: 4437 break; 4438 } 4439 4440 bge_wake_factotum(bgep); 4441 } 4442 4443 4444 /* 4445 * ========== Ioctl subfunctions ========== 4446 */ 4447 4448 #undef BGE_DBG 4449 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4450 4451 #if BGE_DEBUGGING || BGE_DO_PPIO 4452 4453 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4454 #pragma no_inline(bge_chip_peek_cfg) 4455 4456 static void 4457 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4458 { 4459 uint64_t regval; 4460 uint64_t regno; 4461 4462 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4463 (void *)bgep, (void *)ppd)); 4464 4465 regno = ppd->pp_acc_offset; 4466 4467 switch (ppd->pp_acc_size) { 4468 case 1: 4469 regval = pci_config_get8(bgep->cfg_handle, regno); 4470 break; 4471 4472 case 2: 4473 regval = pci_config_get16(bgep->cfg_handle, regno); 4474 break; 4475 4476 case 4: 4477 regval = pci_config_get32(bgep->cfg_handle, regno); 4478 break; 4479 4480 case 8: 4481 regval = pci_config_get64(bgep->cfg_handle, regno); 4482 break; 4483 } 4484 4485 ppd->pp_acc_data = regval; 4486 } 4487 4488 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4489 #pragma no_inline(bge_chip_poke_cfg) 4490 4491 static void 4492 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4493 { 4494 uint64_t regval; 4495 uint64_t regno; 4496 4497 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4498 (void *)bgep, (void *)ppd)); 4499 4500 regno = ppd->pp_acc_offset; 4501 regval = ppd->pp_acc_data; 4502 4503 switch (ppd->pp_acc_size) { 4504 case 1: 4505 pci_config_put8(bgep->cfg_handle, regno, regval); 4506 break; 4507 4508 case 2: 4509 pci_config_put16(bgep->cfg_handle, regno, regval); 4510 break; 4511 4512 case 4: 4513 pci_config_put32(bgep->cfg_handle, regno, regval); 4514 break; 4515 4516 case 8: 4517 pci_config_put64(bgep->cfg_handle, regno, regval); 4518 break; 4519 } 4520 } 4521 4522 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4523 #pragma no_inline(bge_chip_peek_reg) 4524 4525 static void 4526 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4527 { 4528 uint64_t regval; 4529 void *regaddr; 4530 4531 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4532 (void *)bgep, (void *)ppd)); 4533 4534 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4535 4536 switch (ppd->pp_acc_size) { 4537 case 1: 4538 regval = ddi_get8(bgep->io_handle, regaddr); 4539 break; 4540 4541 case 2: 4542 regval = ddi_get16(bgep->io_handle, regaddr); 4543 break; 4544 4545 case 4: 4546 regval = ddi_get32(bgep->io_handle, regaddr); 4547 break; 4548 4549 case 8: 4550 regval = ddi_get64(bgep->io_handle, regaddr); 4551 break; 4552 } 4553 4554 ppd->pp_acc_data = regval; 4555 } 4556 4557 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4558 #pragma no_inline(bge_chip_peek_reg) 4559 4560 static void 4561 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4562 { 4563 uint64_t regval; 4564 void *regaddr; 4565 4566 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4567 (void *)bgep, (void *)ppd)); 4568 4569 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4570 regval = ppd->pp_acc_data; 4571 4572 switch (ppd->pp_acc_size) { 4573 case 1: 4574 ddi_put8(bgep->io_handle, regaddr, regval); 4575 break; 4576 4577 case 2: 4578 ddi_put16(bgep->io_handle, regaddr, regval); 4579 break; 4580 4581 case 4: 4582 ddi_put32(bgep->io_handle, regaddr, regval); 4583 break; 4584 4585 case 8: 4586 ddi_put64(bgep->io_handle, regaddr, regval); 4587 break; 4588 } 4589 BGE_PCICHK(bgep); 4590 } 4591 4592 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4593 #pragma no_inline(bge_chip_peek_nic) 4594 4595 static void 4596 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4597 { 4598 uint64_t regoff; 4599 uint64_t regval; 4600 void *regaddr; 4601 4602 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4603 (void *)bgep, (void *)ppd)); 4604 4605 regoff = ppd->pp_acc_offset; 4606 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4607 regoff &= MWBAR_GRANULE_MASK; 4608 regoff += NIC_MEM_WINDOW_OFFSET; 4609 regaddr = PIO_ADDR(bgep, regoff); 4610 4611 switch (ppd->pp_acc_size) { 4612 case 1: 4613 regval = ddi_get8(bgep->io_handle, regaddr); 4614 break; 4615 4616 case 2: 4617 regval = ddi_get16(bgep->io_handle, regaddr); 4618 break; 4619 4620 case 4: 4621 regval = ddi_get32(bgep->io_handle, regaddr); 4622 break; 4623 4624 case 8: 4625 regval = ddi_get64(bgep->io_handle, regaddr); 4626 break; 4627 } 4628 4629 ppd->pp_acc_data = regval; 4630 } 4631 4632 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4633 #pragma no_inline(bge_chip_poke_nic) 4634 4635 static void 4636 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4637 { 4638 uint64_t regoff; 4639 uint64_t regval; 4640 void *regaddr; 4641 4642 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4643 (void *)bgep, (void *)ppd)); 4644 4645 regoff = ppd->pp_acc_offset; 4646 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4647 regoff &= MWBAR_GRANULE_MASK; 4648 regoff += NIC_MEM_WINDOW_OFFSET; 4649 regaddr = PIO_ADDR(bgep, regoff); 4650 regval = ppd->pp_acc_data; 4651 4652 switch (ppd->pp_acc_size) { 4653 case 1: 4654 ddi_put8(bgep->io_handle, regaddr, regval); 4655 break; 4656 4657 case 2: 4658 ddi_put16(bgep->io_handle, regaddr, regval); 4659 break; 4660 4661 case 4: 4662 ddi_put32(bgep->io_handle, regaddr, regval); 4663 break; 4664 4665 case 8: 4666 ddi_put64(bgep->io_handle, regaddr, regval); 4667 break; 4668 } 4669 BGE_PCICHK(bgep); 4670 } 4671 4672 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4673 #pragma no_inline(bge_chip_peek_mii) 4674 4675 static void 4676 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4677 { 4678 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4679 (void *)bgep, (void *)ppd)); 4680 4681 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4682 } 4683 4684 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4685 #pragma no_inline(bge_chip_poke_mii) 4686 4687 static void 4688 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4689 { 4690 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4691 (void *)bgep, (void *)ppd)); 4692 4693 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4694 } 4695 4696 #if BGE_SEE_IO32 4697 4698 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4699 #pragma no_inline(bge_chip_peek_seeprom) 4700 4701 static void 4702 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4703 { 4704 uint32_t data; 4705 int err; 4706 4707 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4708 (void *)bgep, (void *)ppd)); 4709 4710 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4711 ppd->pp_acc_data = err ? ~0ull : data; 4712 } 4713 4714 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4715 #pragma no_inline(bge_chip_poke_seeprom) 4716 4717 static void 4718 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4719 { 4720 uint32_t data; 4721 4722 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4723 (void *)bgep, (void *)ppd)); 4724 4725 data = ppd->pp_acc_data; 4726 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4727 } 4728 #endif /* BGE_SEE_IO32 */ 4729 4730 #if BGE_FLASH_IO32 4731 4732 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4733 #pragma no_inline(bge_chip_peek_flash) 4734 4735 static void 4736 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4737 { 4738 uint32_t data; 4739 int err; 4740 4741 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4742 (void *)bgep, (void *)ppd)); 4743 4744 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4745 ppd->pp_acc_data = err ? ~0ull : data; 4746 } 4747 4748 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4749 #pragma no_inline(bge_chip_poke_flash) 4750 4751 static void 4752 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4753 { 4754 uint32_t data; 4755 4756 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4757 (void *)bgep, (void *)ppd)); 4758 4759 data = ppd->pp_acc_data; 4760 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4761 ppd->pp_acc_offset, &data); 4762 } 4763 #endif /* BGE_FLASH_IO32 */ 4764 4765 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4766 #pragma no_inline(bge_chip_peek_mem) 4767 4768 static void 4769 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4770 { 4771 uint64_t regval; 4772 void *vaddr; 4773 4774 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4775 (void *)bgep, (void *)ppd)); 4776 4777 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4778 4779 switch (ppd->pp_acc_size) { 4780 case 1: 4781 regval = *(uint8_t *)vaddr; 4782 break; 4783 4784 case 2: 4785 regval = *(uint16_t *)vaddr; 4786 break; 4787 4788 case 4: 4789 regval = *(uint32_t *)vaddr; 4790 break; 4791 4792 case 8: 4793 regval = *(uint64_t *)vaddr; 4794 break; 4795 } 4796 4797 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4798 (void *)bgep, (void *)ppd, regval, vaddr)); 4799 4800 ppd->pp_acc_data = regval; 4801 } 4802 4803 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4804 #pragma no_inline(bge_chip_poke_mem) 4805 4806 static void 4807 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4808 { 4809 uint64_t regval; 4810 void *vaddr; 4811 4812 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4813 (void *)bgep, (void *)ppd)); 4814 4815 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4816 regval = ppd->pp_acc_data; 4817 4818 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4819 (void *)bgep, (void *)ppd, regval, vaddr)); 4820 4821 switch (ppd->pp_acc_size) { 4822 case 1: 4823 *(uint8_t *)vaddr = (uint8_t)regval; 4824 break; 4825 4826 case 2: 4827 *(uint16_t *)vaddr = (uint16_t)regval; 4828 break; 4829 4830 case 4: 4831 *(uint32_t *)vaddr = (uint32_t)regval; 4832 break; 4833 4834 case 8: 4835 *(uint64_t *)vaddr = (uint64_t)regval; 4836 break; 4837 } 4838 } 4839 4840 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4841 struct iocblk *iocp); 4842 #pragma no_inline(bge_pp_ioctl) 4843 4844 static enum ioc_reply 4845 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4846 { 4847 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4848 bge_peekpoke_t *ppd; 4849 dma_area_t *areap; 4850 uint64_t sizemask; 4851 uint64_t mem_va; 4852 uint64_t maxoff; 4853 boolean_t peek; 4854 4855 switch (cmd) { 4856 default: 4857 /* NOTREACHED */ 4858 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4859 return (IOC_INVAL); 4860 4861 case BGE_PEEK: 4862 peek = B_TRUE; 4863 break; 4864 4865 case BGE_POKE: 4866 peek = B_FALSE; 4867 break; 4868 } 4869 4870 /* 4871 * Validate format of ioctl 4872 */ 4873 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4874 return (IOC_INVAL); 4875 if (mp->b_cont == NULL) 4876 return (IOC_INVAL); 4877 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4878 4879 /* 4880 * Validate request parameters 4881 */ 4882 switch (ppd->pp_acc_space) { 4883 default: 4884 return (IOC_INVAL); 4885 4886 case BGE_PP_SPACE_CFG: 4887 /* 4888 * Config space 4889 */ 4890 sizemask = 8|4|2|1; 4891 mem_va = 0; 4892 maxoff = PCI_CONF_HDR_SIZE; 4893 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4894 break; 4895 4896 case BGE_PP_SPACE_REG: 4897 /* 4898 * Memory-mapped I/O space 4899 */ 4900 sizemask = 8|4|2|1; 4901 mem_va = 0; 4902 maxoff = RIAAR_REGISTER_MAX; 4903 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4904 break; 4905 4906 case BGE_PP_SPACE_NIC: 4907 /* 4908 * NIC on-chip memory 4909 */ 4910 sizemask = 8|4|2|1; 4911 mem_va = 0; 4912 maxoff = MWBAR_ONCHIP_MAX; 4913 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4914 break; 4915 4916 case BGE_PP_SPACE_MII: 4917 /* 4918 * PHY's MII registers 4919 * NB: all PHY registers are two bytes, but the 4920 * addresses increment in ones (word addressing). 4921 * So we scale the address here, then undo the 4922 * transformation inside the peek/poke functions. 4923 */ 4924 ppd->pp_acc_offset *= 2; 4925 sizemask = 2; 4926 mem_va = 0; 4927 maxoff = (MII_MAXREG+1)*2; 4928 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4929 break; 4930 4931 #if BGE_SEE_IO32 4932 case BGE_PP_SPACE_SEEPROM: 4933 /* 4934 * Attached SEEPROM(s), if any. 4935 * NB: we use the high-order bits of the 'address' as 4936 * a device select to accommodate multiple SEEPROMS, 4937 * If each one is the maximum size (64kbytes), this 4938 * makes them appear contiguous. Otherwise, there may 4939 * be holes in the mapping. ENxS doesn't have any 4940 * SEEPROMs anyway ... 4941 */ 4942 sizemask = 4; 4943 mem_va = 0; 4944 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4945 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4946 break; 4947 #endif /* BGE_SEE_IO32 */ 4948 4949 #if BGE_FLASH_IO32 4950 case BGE_PP_SPACE_FLASH: 4951 /* 4952 * Attached Flash device (if any); a maximum of one device 4953 * is currently supported. But it can be up to 1MB (unlike 4954 * the 64k limit on SEEPROMs) so why would you need more ;-) 4955 */ 4956 sizemask = 4; 4957 mem_va = 0; 4958 maxoff = NVM_FLASH_ADDR_MASK; 4959 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4960 break; 4961 #endif /* BGE_FLASH_IO32 */ 4962 4963 case BGE_PP_SPACE_BGE: 4964 /* 4965 * BGE data structure! 4966 */ 4967 sizemask = 8|4|2|1; 4968 mem_va = (uintptr_t)bgep; 4969 maxoff = sizeof (*bgep); 4970 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4971 break; 4972 4973 case BGE_PP_SPACE_STATUS: 4974 case BGE_PP_SPACE_STATISTICS: 4975 case BGE_PP_SPACE_TXDESC: 4976 case BGE_PP_SPACE_TXBUFF: 4977 case BGE_PP_SPACE_RXDESC: 4978 case BGE_PP_SPACE_RXBUFF: 4979 /* 4980 * Various DMA_AREAs 4981 */ 4982 switch (ppd->pp_acc_space) { 4983 case BGE_PP_SPACE_TXDESC: 4984 areap = &bgep->tx_desc; 4985 break; 4986 case BGE_PP_SPACE_TXBUFF: 4987 areap = &bgep->tx_buff[0]; 4988 break; 4989 case BGE_PP_SPACE_RXDESC: 4990 areap = &bgep->rx_desc[0]; 4991 break; 4992 case BGE_PP_SPACE_RXBUFF: 4993 areap = &bgep->rx_buff[0]; 4994 break; 4995 case BGE_PP_SPACE_STATUS: 4996 areap = &bgep->status_block; 4997 break; 4998 case BGE_PP_SPACE_STATISTICS: 4999 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5000 areap = &bgep->statistics; 5001 break; 5002 } 5003 5004 sizemask = 8|4|2|1; 5005 mem_va = (uintptr_t)areap->mem_va; 5006 maxoff = areap->alength; 5007 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5008 break; 5009 } 5010 5011 switch (ppd->pp_acc_size) { 5012 default: 5013 return (IOC_INVAL); 5014 5015 case 8: 5016 case 4: 5017 case 2: 5018 case 1: 5019 if ((ppd->pp_acc_size & sizemask) == 0) 5020 return (IOC_INVAL); 5021 break; 5022 } 5023 5024 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5025 return (IOC_INVAL); 5026 5027 if (ppd->pp_acc_offset >= maxoff) 5028 return (IOC_INVAL); 5029 5030 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5031 return (IOC_INVAL); 5032 5033 /* 5034 * All OK - go do it! 5035 */ 5036 ppd->pp_acc_offset += mem_va; 5037 (*ppfn)(bgep, ppd); 5038 return (peek ? IOC_REPLY : IOC_ACK); 5039 } 5040 5041 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5042 struct iocblk *iocp); 5043 #pragma no_inline(bge_diag_ioctl) 5044 5045 static enum ioc_reply 5046 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5047 { 5048 ASSERT(mutex_owned(bgep->genlock)); 5049 5050 switch (cmd) { 5051 default: 5052 /* NOTREACHED */ 5053 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5054 return (IOC_INVAL); 5055 5056 case BGE_DIAG: 5057 /* 5058 * Currently a no-op 5059 */ 5060 return (IOC_ACK); 5061 5062 case BGE_PEEK: 5063 case BGE_POKE: 5064 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5065 5066 case BGE_PHY_RESET: 5067 return (IOC_RESTART_ACK); 5068 5069 case BGE_SOFT_RESET: 5070 case BGE_HARD_RESET: 5071 /* 5072 * Reset and reinitialise the 570x hardware 5073 */ 5074 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5075 return (IOC_ACK); 5076 } 5077 5078 /* NOTREACHED */ 5079 } 5080 5081 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5082 5083 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5084 struct iocblk *iocp); 5085 #pragma no_inline(bge_mii_ioctl) 5086 5087 static enum ioc_reply 5088 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5089 { 5090 struct bge_mii_rw *miirwp; 5091 5092 /* 5093 * Validate format of ioctl 5094 */ 5095 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5096 return (IOC_INVAL); 5097 if (mp->b_cont == NULL) 5098 return (IOC_INVAL); 5099 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5100 5101 /* 5102 * Validate request parameters ... 5103 */ 5104 if (miirwp->mii_reg > MII_MAXREG) 5105 return (IOC_INVAL); 5106 5107 switch (cmd) { 5108 default: 5109 /* NOTREACHED */ 5110 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5111 return (IOC_INVAL); 5112 5113 case BGE_MII_READ: 5114 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5115 return (IOC_REPLY); 5116 5117 case BGE_MII_WRITE: 5118 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5119 return (IOC_ACK); 5120 } 5121 5122 /* NOTREACHED */ 5123 } 5124 5125 #if BGE_SEE_IO32 5126 5127 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5128 struct iocblk *iocp); 5129 #pragma no_inline(bge_see_ioctl) 5130 5131 static enum ioc_reply 5132 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5133 { 5134 struct bge_see_rw *seerwp; 5135 5136 /* 5137 * Validate format of ioctl 5138 */ 5139 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5140 return (IOC_INVAL); 5141 if (mp->b_cont == NULL) 5142 return (IOC_INVAL); 5143 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5144 5145 /* 5146 * Validate request parameters ... 5147 */ 5148 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5149 return (IOC_INVAL); 5150 5151 switch (cmd) { 5152 default: 5153 /* NOTREACHED */ 5154 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5155 return (IOC_INVAL); 5156 5157 case BGE_SEE_READ: 5158 case BGE_SEE_WRITE: 5159 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5160 seerwp->see_addr, &seerwp->see_data); 5161 return (IOC_REPLY); 5162 } 5163 5164 /* NOTREACHED */ 5165 } 5166 5167 #endif /* BGE_SEE_IO32 */ 5168 5169 #if BGE_FLASH_IO32 5170 5171 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5172 struct iocblk *iocp); 5173 #pragma no_inline(bge_flash_ioctl) 5174 5175 static enum ioc_reply 5176 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5177 { 5178 struct bge_flash_rw *flashrwp; 5179 5180 /* 5181 * Validate format of ioctl 5182 */ 5183 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5184 return (IOC_INVAL); 5185 if (mp->b_cont == NULL) 5186 return (IOC_INVAL); 5187 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5188 5189 /* 5190 * Validate request parameters ... 5191 */ 5192 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5193 return (IOC_INVAL); 5194 5195 switch (cmd) { 5196 default: 5197 /* NOTREACHED */ 5198 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5199 return (IOC_INVAL); 5200 5201 case BGE_FLASH_READ: 5202 case BGE_FLASH_WRITE: 5203 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5204 flashrwp->flash_addr, &flashrwp->flash_data); 5205 return (IOC_REPLY); 5206 } 5207 5208 /* NOTREACHED */ 5209 } 5210 5211 #endif /* BGE_FLASH_IO32 */ 5212 5213 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5214 struct iocblk *iocp); 5215 #pragma no_inline(bge_chip_ioctl) 5216 5217 enum ioc_reply 5218 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5219 { 5220 int cmd; 5221 5222 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5223 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5224 5225 ASSERT(mutex_owned(bgep->genlock)); 5226 5227 cmd = iocp->ioc_cmd; 5228 switch (cmd) { 5229 default: 5230 /* NOTREACHED */ 5231 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5232 return (IOC_INVAL); 5233 5234 case BGE_DIAG: 5235 case BGE_PEEK: 5236 case BGE_POKE: 5237 case BGE_PHY_RESET: 5238 case BGE_SOFT_RESET: 5239 case BGE_HARD_RESET: 5240 #if BGE_DEBUGGING || BGE_DO_PPIO 5241 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5242 #else 5243 return (IOC_INVAL); 5244 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5245 5246 case BGE_MII_READ: 5247 case BGE_MII_WRITE: 5248 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5249 5250 #if BGE_SEE_IO32 5251 case BGE_SEE_READ: 5252 case BGE_SEE_WRITE: 5253 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5254 #endif /* BGE_SEE_IO32 */ 5255 5256 #if BGE_FLASH_IO32 5257 case BGE_FLASH_READ: 5258 case BGE_FLASH_WRITE: 5259 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5260 #endif /* BGE_FLASH_IO32 */ 5261 } 5262 5263 /* NOTREACHED */ 5264 } 5265 5266 void 5267 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5268 { 5269 bge_t *bgep = arg; 5270 5271 mutex_enter(bgep->genlock); 5272 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5273 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5274 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5275 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5276 mutex_exit(bgep->genlock); 5277 } 5278 5279 #ifdef BGE_IPMI_ASF 5280 5281 uint32_t 5282 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5283 { 5284 uint32_t data; 5285 5286 if (!bgep->asf_wordswapped) { 5287 /* a workaround word swap error */ 5288 if (addr & 4) 5289 addr = addr - 4; 5290 else 5291 addr = addr + 4; 5292 } 5293 5294 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5295 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5296 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5297 5298 return (data); 5299 } 5300 5301 5302 void 5303 bge_asf_update_status(bge_t *bgep) 5304 { 5305 uint32_t event; 5306 5307 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5308 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5309 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5310 5311 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5312 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5313 } 5314 5315 5316 /* 5317 * The driver is supposed to notify ASF that the OS is still running 5318 * every three seconds, otherwise the management server may attempt 5319 * to reboot the machine. If it hasn't actually failed, this is 5320 * not a desirable result. However, this isn't running as a real-time 5321 * thread, and even if it were, it might not be able to generate the 5322 * heartbeat in a timely manner due to system load. As it isn't a 5323 * significant strain on the machine, we will set the interval to half 5324 * of the required value. 5325 */ 5326 void 5327 bge_asf_heartbeat(void *arg) 5328 { 5329 bge_t *bgep = (bge_t *)arg; 5330 5331 mutex_enter(bgep->genlock); 5332 bge_asf_update_status((bge_t *)bgep); 5333 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5334 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5335 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5336 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5337 mutex_exit(bgep->genlock); 5338 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5339 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5340 } 5341 5342 5343 void 5344 bge_asf_stop_timer(bge_t *bgep) 5345 { 5346 timeout_id_t tmp_id = 0; 5347 5348 while ((bgep->asf_timeout_id != 0) && 5349 (tmp_id != bgep->asf_timeout_id)) { 5350 tmp_id = bgep->asf_timeout_id; 5351 (void) untimeout(tmp_id); 5352 } 5353 bgep->asf_timeout_id = 0; 5354 } 5355 5356 5357 5358 /* 5359 * This function should be placed at the earliest position of bge_attach(). 5360 */ 5361 void 5362 bge_asf_get_config(bge_t *bgep) 5363 { 5364 uint32_t nicsig; 5365 uint32_t niccfg; 5366 5367 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5368 if (nicsig == BGE_NIC_DATA_SIG) { 5369 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5370 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5371 /* 5372 * Here, we don't consider BAXTER, because BGE haven't 5373 * supported BAXTER (that is 5752). Also, as I know, 5374 * BAXTER doesn't support ASF feature. 5375 */ 5376 bgep->asf_enabled = B_TRUE; 5377 else 5378 bgep->asf_enabled = B_FALSE; 5379 } else 5380 bgep->asf_enabled = B_FALSE; 5381 } 5382 5383 5384 void 5385 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5386 { 5387 uint32_t tries; 5388 uint32_t event; 5389 5390 ASSERT(bgep->asf_enabled); 5391 5392 /* Issues "pause firmware" command and wait for ACK */ 5393 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5394 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5395 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5396 5397 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5398 tries = 0; 5399 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5400 drv_usecwait(1); 5401 tries ++; 5402 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5403 } 5404 5405 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5406 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5407 5408 if (bgep->asf_newhandshake) { 5409 switch (mode) { 5410 case BGE_INIT_RESET: 5411 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5412 BGE_DRV_STATE_START); 5413 break; 5414 case BGE_SHUTDOWN_RESET: 5415 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5416 BGE_DRV_STATE_UNLOAD); 5417 break; 5418 case BGE_SUSPEND_RESET: 5419 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5420 BGE_DRV_STATE_SUSPEND); 5421 break; 5422 default: 5423 break; 5424 } 5425 } 5426 } 5427 5428 5429 void 5430 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5431 { 5432 switch (mode) { 5433 case BGE_INIT_RESET: 5434 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5435 BGE_DRV_STATE_START); 5436 break; 5437 case BGE_SHUTDOWN_RESET: 5438 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5439 BGE_DRV_STATE_UNLOAD); 5440 break; 5441 case BGE_SUSPEND_RESET: 5442 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5443 BGE_DRV_STATE_SUSPEND); 5444 break; 5445 default: 5446 break; 5447 } 5448 } 5449 5450 5451 void 5452 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5453 { 5454 switch (mode) { 5455 case BGE_INIT_RESET: 5456 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5457 BGE_DRV_STATE_START_DONE); 5458 break; 5459 case BGE_SHUTDOWN_RESET: 5460 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5461 BGE_DRV_STATE_UNLOAD_DONE); 5462 break; 5463 default: 5464 break; 5465 } 5466 } 5467 5468 #endif /* BGE_IPMI_ASF */ 5469