1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_BGE_H 28 #define _SYS_BGE_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 /* 39 * Name of the driver 40 */ 41 #define BGE_DRIVER_NAME "bge" 42 43 /* 44 * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback 45 * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE 46 * 47 * These are the values to use with LD_SET_MODE. 48 * Note: they may not all be supported on any given chip/driver. 49 */ 50 #define BGE_LOOP_NONE 0 51 #define BGE_LOOP_EXTERNAL_1000 1 /* with Gbit loopback cable */ 52 #define BGE_LOOP_EXTERNAL_100 2 /* with loopback cable */ 53 #define BGE_LOOP_EXTERNAL_10 3 /* with loopback cable */ 54 #define BGE_LOOP_INTERNAL_PHY 4 55 #define BGE_LOOP_INTERNAL_MAC 5 56 57 /* 58 * BGE-specific ioctls ... 59 */ 60 #define BGE_IOC ((((('B' << 8) + 'G') << 8) + 'E') << 8) 61 62 /* 63 * PHY register read/write ioctls, used by cable test software 64 */ 65 #define BGE_MII_READ (BGE_IOC|1) 66 #define BGE_MII_WRITE (BGE_IOC|2) 67 68 struct bge_mii_rw { 69 uint32_t mii_reg; /* PHY register number [0..31] */ 70 uint32_t mii_data; /* data to write/data read */ 71 }; 72 73 /* 74 * SEEPROM read/write ioctls, for use by SEEPROM upgrade utility 75 * 76 * Note: SEEPROMs can only be accessed as 32-bit words, so <see_addr> 77 * must be a multiple of 4. Not all systems have a SEEPROM fitted! 78 */ 79 #define BGE_SEE_READ (BGE_IOC|3) 80 #define BGE_SEE_WRITE (BGE_IOC|4) 81 82 struct bge_see_rw { 83 uint32_t see_addr; /* Byte offset within SEEPROM */ 84 uint32_t see_data; /* Data read/data to write */ 85 }; 86 87 /* 88 * Flash read/write ioctls, for flash upgrade utility 89 * 90 * Note: flash can only be accessed as 32-bit words, so <flash_addr> 91 * must be a multiple of 4. Not all systems have flash fitted! 92 */ 93 #define BGE_FLASH_READ (BGE_IOC|5) 94 #define BGE_FLASH_WRITE (BGE_IOC|6) 95 96 struct bge_flash_rw { 97 uint32_t flash_addr; /* Byte offset within flash */ 98 uint32_t flash_data; /* Data read/data to write */ 99 }; 100 101 /* 102 * These diagnostic IOCTLS are enabled only in DEBUG drivers 103 */ 104 #define BGE_DIAG (BGE_IOC|10) /* currently a no-op */ 105 #define BGE_PEEK (BGE_IOC|11) 106 #define BGE_POKE (BGE_IOC|12) 107 #define BGE_PHY_RESET (BGE_IOC|13) 108 #define BGE_SOFT_RESET (BGE_IOC|14) 109 #define BGE_HARD_RESET (BGE_IOC|15) 110 111 typedef struct { 112 uint64_t pp_acc_size; /* in bytes: 1,2,4,8 */ 113 uint64_t pp_acc_space; /* See #defines below */ 114 uint64_t pp_acc_offset; 115 uint64_t pp_acc_data; /* output for peek */ 116 /* input for poke */ 117 } bge_peekpoke_t; 118 119 #define BGE_PP_SPACE_CFG 0 /* PCI config space */ 120 #define BGE_PP_SPACE_REG 1 /* PCI memory space */ 121 #define BGE_PP_SPACE_NIC 2 /* on-chip memory */ 122 #define BGE_PP_SPACE_MII 3 /* PHY's MII registers */ 123 #define BGE_PP_SPACE_BGE 4 /* driver's soft state */ 124 #define BGE_PP_SPACE_TXDESC 5 /* TX descriptors */ 125 #define BGE_PP_SPACE_TXBUFF 6 /* TX buffers */ 126 #define BGE_PP_SPACE_RXDESC 7 /* RX descriptors */ 127 #define BGE_PP_SPACE_RXBUFF 8 /* RX buffers */ 128 #define BGE_PP_SPACE_STATUS 9 /* status block */ 129 #define BGE_PP_SPACE_STATISTICS 10 /* statistics block */ 130 #define BGE_PP_SPACE_SEEPROM 11 /* SEEPROM (if fitted) */ 131 #define BGE_PP_SPACE_FLASH 12 /* FLASH (if fitted) */ 132 133 #define BGE_IPMI_ASF 134 135 /* 136 * Enable BGE_NETCONSOLE only with SPARC 137 */ 138 #ifdef __sparc 139 #define BGE_NETCONSOLE 140 #endif 141 142 /* 143 * BGE_MAXPKT_RCVED is defined to make sure bge does not stick 144 * in a receiving loop too long. This value is the tuning result 145 * of performance testing on sparc/x86 platforms, with regarding 146 * to throughput/latency/CPU utilization, TCP/UDP 147 */ 148 #define BGE_MAXPKT_RCVED 32 149 150 #ifdef __cplusplus 151 } 152 #endif 153 154 #endif /* _SYS_BGE_H */ 155