xref: /titanic_50/usr/src/uts/common/io/bfe/bfe_hw.h (revision 1a5e258f5471356ca102c7176637cdce45bac147)
1 /*
2  * Copyright (c) 2003 Stuart Walsh
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 /*
26  * $FreeBSD: src/sys/dev/bfe/if_bfereg.h,v 1.10.2.4.2.1 2008/11/25 02:59:29
27  * kensmith Exp $
28  */
29 
30 #ifndef _BFE_HW_H
31 #define	_BFE_HW_H
32 
33 /* PCI registers */
34 #define	BFE_PCI_MEMLO		0x10
35 #define	BFE_PCI_MEMHIGH		0x14
36 #define	BFE_PCI_INTLINE		0x3C
37 
38 /* Register layout. */
39 #define	BFE_DEVCTRL		0x00000000  /* Device Control */
40 #define	BFE_PFE			0x00000080  /* Pattern Filtering Enable */
41 #define	BFE_IPP			0x00000400  /* Internal EPHY Present */
42 #define	BFE_EPR			0x00008000  /* EPHY Reset */
43 #define	BFE_PME			0x00001000  /* PHY Mode Enable */
44 #define	BFE_PMCE		0x00002000  /* PHY Mode Clocks Enable */
45 #define	BFE_PADDR		0x0007c000  /* PHY Address */
46 #define	BFE_PADDR_SHIFT		18
47 
48 #define	BFE_BIST_STAT		0x0000000C  /* Built-In Self-Test Status */
49 #define	BFE_WKUP_LEN		0x00000010  /* Wakeup Length */
50 
51 #define	BFE_INTR_STAT		0x00000020  /* Interrupt Status */
52 #define	BFE_ISTAT_PME		0x00000040 /* Power Management Event */
53 #define	BFE_ISTAT_TO		0x00000080 /* General Purpose Timeout */
54 #define	BFE_ISTAT_DSCE		0x00000400 /* Descriptor Error */
55 #define	BFE_ISTAT_DATAE		0x00000800 /* Data Error */
56 #define	BFE_ISTAT_DPE		0x00001000 /* Descr. Protocol Error */
57 #define	BFE_ISTAT_RDU		0x00002000 /* Receive Descr. Underflow */
58 #define	BFE_ISTAT_RFO		0x00004000 /* Receive FIFO Overflow */
59 #define	BFE_ISTAT_TFU		0x00008000 /* Transmit FIFO Underflow */
60 #define	BFE_ISTAT_RX		0x00010000 /* RX Interrupt */
61 #define	BFE_ISTAT_TX		0x01000000 /* TX Interrupt */
62 #define	BFE_ISTAT_EMAC		0x04000000 /* EMAC Interrupt */
63 #define	BFE_ISTAT_MII_WRITE	0x08000000 /* MII Write Interrupt */
64 #define	BFE_ISTAT_MII_READ	0x10000000 /* MII Read Interrupt */
65 #define	BFE_ISTAT_ERRORS	(BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | \
66     BFE_ISTAT_DPE | BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
67 
68 #define	BFE_INTR_MASK		0x00000024 /* Interrupt Mask */
69 #define	BFE_IMASK_DEF		(BFE_ISTAT_ERRORS | BFE_ISTAT_TO | \
70     BFE_ISTAT_RX | BFE_ISTAT_TX)
71 
72 #define	BFE_MAC_CTRL		0x000000A8 /* MAC Control */
73 #define	BFE_CTRL_CRC32_ENAB	0x00000001 /* CRC32 Generation Enable */
74 #define	BFE_CTRL_PDOWN		0x00000004 /* Onchip EPHY Powerdown */
75 #define	BFE_CTRL_EDET		0x00000008 /* Onchip EPHY Energy Detected */
76 #define	BFE_CTRL_LED		0x000000e0 /* Onchip EPHY LED Control */
77 #define	BFE_CTRL_LED_SHIFT	5
78 
79 #define	BFE_MAC_FLOW		0x000000AC /* MAC Flow Control */
80 #define	BFE_FLOW_RX_HIWAT	0x000000ff /* Onchip FIFO HI Water Mark */
81 #define	BFE_FLOW_PAUSE_ENAB	0x00008000 /* Enable Pause Frame Generation */
82 
83 #define	BFE_RCV_LAZY		0x00000100 /* Lazy Interrupt Control */
84 #define	BFE_LAZY_TO_MASK	0x00ffffff /* Timeout */
85 #define	BFE_LAZY_FC_MASK	0xff000000 /* Frame Count */
86 #define	BFE_LAZY_FC_SHIFT	24
87 
88 #define	BFE_DMATX_CTRL		0x00000200 /* DMA TX Control */
89 #define	BFE_TX_CTRL_ENABLE	0x00000001 /* Enable */
90 #define	BFE_TX_CTRL_SUSPEND	0x00000002 /* Suepend Request */
91 #define	BFE_TX_CTRL_LPBACK	0x00000004 /* Loopback Enable */
92 #define	BFE_TX_CTRL_FAIRPRI	0x00000008 /* Fair Priority */
93 #define	BFE_TX_CTRL_FLUSH	0x00000010 /* Flush Request */
94 
95 #define	BFE_DMATX_ADDR		0x00000204 /* TX Descriptor Ring Address */
96 #define	BFE_DMATX_PTR		0x00000208 /* TX Last Posted Descriptor */
97 #define	BFE_DMATX_STAT		0x0000020C /* TX Curr Active Desc + Status */
98 #define	BFE_STAT_CDMASK		0x00000fff /* Current Descriptor Mask */
99 #define	BFE_STAT_SMASK		0x0000f000 /* State Mask */
100 #define	BFE_STAT_DISABLE	0x00000000 /* State Disabled */
101 #define	BFE_STAT_SACTIVE	0x00001000 /* State Active */
102 #define	BFE_STAT_SIDLE		0x00002000 /* State Idle Wait */
103 #define	BFE_STAT_STOPPED	0x00003000 /* State Stopped */
104 #define	BFE_STAT_SSUSP		0x00004000 /* State Suspend Pending */
105 #define	BFE_STAT_EMASK		0x000f0000 /* Error Mask */
106 #define	BFE_STAT_ENONE		0x00000000 /* Error None */
107 #define	BFE_STAT_EDPE		0x00010000 /* Error Desc. Protocol Error */
108 #define	BFE_STAT_EDFU		0x00020000 /* Error Data FIFO Underrun */
109 #define	BFE_STAT_EBEBR		0x00030000 /* Error Bus Error on Buffer Read */
110 #define	BFE_STAT_EBEDA		0x00040000 /* Error Bus Error on Desc. Access */
111 #define	BFE_STAT_FLUSHED	0x00100000 /* Flushed */
112 
113 #define	BFE_DMARX_CTRL		0x00000210 /* DMA RX Control */
114 #define	BFE_RX_CTRL_ENABLE	0x00000001 /* Enable */
115 #define	BFE_RX_CTRL_ROMASK	0x000000fe /* Receive Offset Mask */
116 #define	BFE_RX_CTRL_ROSHIFT	1	/* Receive Offset Shift */
117 
118 #define	BFE_DMARX_ADDR	0x00000214 /* DMA RX Descriptor Ring Address */
119 #define	BFE_DMARX_PTR	0x00000218 /* DMA RX Last Posted Descriptor */
120 #define	BFE_DMARX_STAT	0x0000021C /* DMA RX Current Active Desc. + Status */
121 
122 #define	BFE_RXCONF	0x00000400 /* EMAC RX Config */
123 #define	BFE_RXCONF_DBCAST	0x00000001 /* Disable Broadcast */
124 #define	BFE_RXCONF_ALLMULTI	0x00000002 /* Accept All Multicast */
125 #define	BFE_RXCONF_NORXTX	0x00000004 /* rev. Disable While Transmitting */
126 #define	BFE_RXCONF_PROMISC	0x00000008 /* Promiscuous Enable */
127 #define	BFE_RXCONF_LPBACK	0x00000010 /* Loopback Enable */
128 #define	BFE_RXCONF_FLOW		0x00000020 /* Flow Control Enable */
129 #define	BFE_RXCONF_ACCEPT	0x00000040 /* Accept Unicst Flow Ctrl Frame */
130 #define	BFE_RXCONF_RFILT	0x00000080 /* Reject Filter */
131 
132 #define	BFE_RXMAXLEN	0x00000404 /* EMAC RX Max Packet Length */
133 #define	BFE_TXMAXLEN	0x00000408 /* EMAC TX Max Packet Length */
134 
135 #define	BFE_MDIO_CTRL		0x00000410 /* EMAC MDIO Control */
136 #define	BFE_MDIO_MAXF_MASK	0x0000007f /* MDC Frequency */
137 #define	BFE_MDIO_PREAMBLE	0x00000080 /* MII Preamble Enable */
138 
139 #define	BFE_MDIO_DATA		0x00000414 /* EMAC MDIO Data */
140 #define	BFE_MDIO_DATA_DATA	0x0000ffff /* R/W Data */
141 #define	BFE_MDIO_TA_MASK	0x00030000 /* Turnaround Value */
142 #define	BFE_MDIO_TA_SHIFT	16
143 #define	BFE_MDIO_TA_VALID	2
144 
145 #define	BFE_MDIO_RA_MASK	0x007c0000 /* Register Address */
146 #define	BFE_MDIO_PMD_MASK	0x0f800000 /* Physical Media Device */
147 #define	BFE_MDIO_OP_MASK	0x30000000 /* Opcode */
148 #define	BFE_MDIO_SB_MASK	0xc0000000 /* Start Bits */
149 #define	BFE_MDIO_SB_START	0x40000000 /* Start Of Frame */
150 #define	BFE_MDIO_RA_SHIFT	18
151 #define	BFE_MDIO_PMD_SHIFT	23
152 #define	BFE_MDIO_OP_SHIFT	28
153 #define	BFE_MDIO_OP_WRITE	1
154 #define	BFE_MDIO_OP_READ	2
155 #define	BFE_MDIO_SB_SHIFT	30
156 
157 #define	BFE_EMAC_IMASK		0x00000418 /* EMAC Interrupt Mask */
158 #define	BFE_EMAC_ISTAT		0x0000041C /* EMAC Interrupt Status */
159 #define	BFE_EMAC_INT_MII	0x00000001 /* MII MDIO Interrupt */
160 #define	BFE_EMAC_INT_MIB	0x00000002 /* MIB Interrupt */
161 #define	BFE_EMAC_INT_FLOW	0x00000003 /* Flow Control Interrupt */
162 
163 #define	BFE_CAM_DATA_LO		0x00000420 /* EMAC CAM Data Low */
164 #define	BFE_CAM_DATA_HI		0x00000424 /* EMAC CAM Data High */
165 #define	BFE_CAM_HI_VALID	0x00010000 /* Valid Bit */
166 
167 #define	BFE_CAM_CTRL		0x00000428 /* EMAC CAM Control */
168 #define	BFE_CAM_ENABLE		0x00000001 /* CAM Enable */
169 #define	BFE_CAM_MSEL		0x00000002 /* Mask Select */
170 #define	BFE_CAM_READ		0x00000004 /* Read */
171 #define	BFE_CAM_WRITE		0x00000008 /* Read */
172 #define	BFE_CAM_INDEX_MASK	0x003f0000 /* Index Mask */
173 #define	BFE_CAM_BUSY		0x80000000 /* CAM Busy */
174 #define	BFE_CAM_INDEX_SHIFT	16
175 
176 #define	BFE_ENET_CTRL		0x0000042C /* EMAC ENET Control */
177 #define	BFE_ENET_ENABLE		0x00000001 /* EMAC Enable */
178 #define	BFE_ENET_DISABLE	0x00000002 /* EMAC Disable */
179 #define	BFE_ENET_SRST		0x00000004 /* EMAC Soft Reset */
180 #define	BFE_ENET_EPSEL		0x00000008 /* External PHY Select */
181 
182 #define	BFE_TX_CTRL		0x00000430 /* EMAC TX Control */
183 #define	BFE_TX_DUPLEX		0x00000001 /* Full Duplex */
184 #define	BFE_TX_FMODE		0x00000002 /* Flow Mode */
185 #define	BFE_TX_SBENAB		0x00000004 /* Single Backoff Enable */
186 #define	BFE_TX_SMALL_SLOT	0x00000008 /* Small Slottime */
187 
188 #define	BFE_TX_WMARK		0x00000434 /* EMAC TX Watermark */
189 
190 #define	BFE_MIB_CTRL		0x00000438 /* EMAC MIB Control */
191 #define	BFE_MIB_CLR_ON_READ	0x00000001 /* Autoclear on Read */
192 
193 /* Status registers */
194 #define	BFE_TX_GOOD_O	0x00000500 /* MIB TX Good Octets */
195 #define	BFE_TX_GOOD_P	0x00000504 /* MIB TX Good Packets */
196 #define	BFE_TX_O	0x00000508 /* MIB TX Octets */
197 #define	BFE_TX_P	0x0000050C /* MIB TX Packets */
198 #define	BFE_TX_BCAST	0x00000510 /* MIB TX Broadcast Packets */
199 #define	BFE_TX_MCAST	0x00000514 /* MIB TX Multicast Packets */
200 #define	BFE_TX_64	0x00000518 /* MIB TX <= 64 byte Packets */
201 #define	BFE_TX_65_127	0x0000051C /* MIB TX 65 to 127 byte Packets */
202 #define	BFE_TX_128_255	0x00000520 /* MIB TX 128 to 255 byte Packets */
203 #define	BFE_TX_256_511	0x00000524 /* MIB TX 256 to 511 byte Packets */
204 #define	BFE_TX_512_1023	0x00000528 /* MIB TX 512 to 1023 byte Packets */
205 #define	BFE_TX_1024_MAX	0x0000052C /* MIB TX 1024 to max byte Packets */
206 #define	BFE_TX_JABBER	0x00000530 /* MIB TX Jabber Packets */
207 #define	BFE_TX_OSIZE	0x00000534 /* MIB TX Oversize Packets */
208 #define	BFE_TX_FRAG	0x00000538 /* MIB TX Fragment Packets */
209 #define	BFE_TX_URUNS	0x0000053C /* MIB TX Underruns */
210 #define	BFE_TX_TCOLS	0x00000540 /* MIB TX Total Collisions */
211 #define	BFE_TX_SCOLS	0x00000544 /* MIB TX Single Collisions */
212 #define	BFE_TX_MCOLS	0x00000548 /* MIB TX Multiple Collisions */
213 #define	BFE_TX_ECOLS	0x0000054C /* MIB TX Excessive Collisions */
214 #define	BFE_TX_LCOLS	0x00000550 /* MIB TX Late Collisions */
215 #define	BFE_TX_DEFERED	0x00000554 /* MIB TX Defered Packets */
216 #define	BFE_TX_CLOST	0x00000558 /* MIB TX Carrier Lost */
217 #define	BFE_TX_PAUSE	0x0000055C /* MIB TX Pause Packets */
218 #define	BFE_RX_GOOD_O	0x00000580 /* MIB RX Good Octets */
219 #define	BFE_RX_GOOD_P	0x00000584 /* MIB RX Good Packets */
220 #define	BFE_RX_O	0x00000588 /* MIB RX Octets */
221 #define	BFE_RX_P	0x0000058C /* MIB RX Packets */
222 #define	BFE_RX_BCAST	0x00000590 /* MIB RX Broadcast Packets */
223 #define	BFE_RX_MCAST	0x00000594 /* MIB RX Multicast Packets */
224 #define	BFE_RX_64	0x00000598 /* MIB RX <= 64 byte Packets */
225 #define	BFE_RX_65_127	0x0000059C /* MIB RX 65 to 127 byte Packets */
226 #define	BFE_RX_128_255	0x000005A0 /* MIB RX 128 to 255 byte Packets */
227 #define	BFE_RX_256_511	0x000005A4 /* MIB RX 256 to 511 byte Packets */
228 #define	BFE_RX_512_1023	0x000005A8 /* MIB RX 512 to 1023 byte Packets */
229 #define	BFE_RX_1024_MAX	0x000005AC /* MIB RX 1024 to max byte Packets */
230 #define	BFE_RX_JABBER	0x000005B0 /* MIB RX Jabber Packets */
231 #define	BFE_RX_OSIZE	0x000005B4 /* MIB RX Oversize Packets */
232 #define	BFE_RX_FRAG	0x000005B8 /* MIB RX Fragment Packets */
233 #define	BFE_RX_MISS	0x000005BC /* MIB RX Missed Packets */
234 #define	BFE_RX_CRCA	0x000005C0 /* MIB RX CRC Align Errors */
235 #define	BFE_RX_USIZE	0x000005C4 /* MIB RX Undersize Packets */
236 #define	BFE_RX_CRC	0x000005C8 /* MIB RX CRC Errors */
237 #define	BFE_RX_ALIGN	0x000005CC /* MIB RX Align Errors */
238 #define	BFE_RX_SYM	0x000005D0 /* MIB RX Symbol Errors */
239 #define	BFE_RX_PAUSE	0x000005D4 /* MIB RX Pause Packets */
240 #define	BFE_RX_NPAUSE	0x000005D8 /* MIB RX Non-Pause Packets */
241 
242 #define	BFE_SBIMSTATE	0x00000F90 /* BFE_SB Initiator Agent State */
243 #define	BFE_PC		0x0000000f /* Pipe Count */
244 #define	BFE_AP_MASK	0x00000030 /* Arbitration Priority */
245 #define	BFE_AP_BOTH	0x00000000 /* Use both timeslices and token */
246 #define	BFE_AP_TS	0x00000010 /* Use timeslices only */
247 #define	BFE_AP_TK	0x00000020 /* Use token only */
248 #define	BFE_AP_RSV	0x00000030 /* Reserved */
249 #define	BFE_IBE		0x00020000 /* In Band Error */
250 #define	BFE_TO		0x00040000 /* Timeout */
251 
252 
253 /*
254  * Seems the bcm440x has a fairly generic core, we only need be concerned with
255  * a couple of these
256  */
257 #define	BFE_SBINTVEC		0x00000F94 /* BFE_SB Interrupt Mask */
258 #define	BFE_INTVEC_PCI		0x00000001 /* Enable interrupts for PCI */
259 #define	BFE_INTVEC_ENET0	0x00000002 /* Enable interrupts for enet 0 */
260 #define	BFE_INTVEC_ILINE20	0x00000004 /* Enable interrupts for iline20 */
261 #define	BFE_INTVEC_CODEC	0x00000008 /* Enable interrupts for v90 codec */
262 #define	BFE_INTVEC_USB		0x00000010 /* Enable interrupts for usb */
263 #define	BFE_INTVEC_EXTIF	0x00000020 /* Enable intrs for external i/f */
264 #define	BFE_INTVEC_ENET1	0x00000040 /* Enable interrupts for enet 1 */
265 
266 #define	BFE_SBTMSLOW		0x00000F98 /* BFE_SB Target State Low */
267 #define	BFE_RESET		0x00000001 /* Reset */
268 #define	BFE_REJECT		0x00000002 /* Reject */
269 #define	BFE_CLOCK		0x00010000 /* Clock Enable */
270 #define	BFE_FGC			0x00020000 /* Force Gated Clocks On */
271 #define	BFE_PE			0x40000000 /* Power Management Enable */
272 #define	BFE_BE			0x80000000 /* BIST Enable */
273 
274 #define	BFE_SBTMSHIGH	0x00000F9C /* BFE_SB Target State High */
275 #define	BFE_SERR	0x00000001 /* S-error */
276 #define	BFE_INT		0x00000002 /* Interrupt */
277 #define	BFE_BUSY	0x00000004 /* Busy */
278 #define	BFE_GCR		0x20000000 /* Gated Clock Request */
279 #define	BFE_BISTF	0x40000000 /* BIST Failed */
280 #define	BFE_BISTD	0x80000000 /* BIST Done */
281 
282 #define	BFE_SBBWA0	0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */
283 #define	BFE_TAB0_MASK	0x0000ffff /* Lookup Table 0 */
284 #define	BFE_TAB1_MASK	0xffff0000 /* Lookup Table 0 */
285 #define	BFE_TAB0_SHIFT	0
286 #define	BFE_TAB1_SHIFT	16
287 
288 #define	BFE_SBIMCFGLOW	0x00000FA8 /* BFE_SB Initiator Configuration Low */
289 #define	BFE_STO_MASK	0x00000003 /* Service Timeout */
290 #define	BFE_RTO_MASK	0x00000030 /* Request Timeout */
291 #define	BFE_CID_MASK	0x00ff0000 /* Connection ID */
292 #define	BFE_RTO_SHIFT	4
293 #define	BFE_CID_SHIFT	16
294 
295 #define	BFE_SBIMCFGHIGH	0x00000FAC /* BFE_SB Initiator Configuration High */
296 #define	BFE_IEM_MASK	0x0000000c /* Inband Error Mode */
297 #define	BFE_TEM_MASK	0x00000030 /* Timeout Error Mode */
298 #define	BFE_BEM_MASK	0x000000c0 /* Bus Error Mode */
299 #define	BFE_TEM_SHIFT	4
300 #define	BFE_BEM_SHIFT	6
301 
302 #define	BFE_SBTMCFGLOW	0x00000FB8 /* BFE_SB Target Configuration Low */
303 #define	BFE_LOW_CD_MASK	0x000000ff /* Clock Divide Mask */
304 #define	BFE_LOW_CO_MASK	0x0000f800 /* Clock Offset Mask */
305 #define	BFE_LOW_IF_MASK	0x00fc0000 /* Interrupt Flags Mask */
306 #define	BFE_LOW_IM_MASK	0x03000000 /* Interrupt Mode Mask */
307 #define	BFE_LOW_CO_SHIFT	11
308 #define	BFE_LOW_IF_SHIFT	18
309 #define	BFE_LOW_IM_SHIFT	24
310 
311 #define	BFE_SBTMCFGHIGH	0x00000FBC /* BFE_SB Target Configuration High */
312 #define	BFE_HIGH_BM_MASK	0x00000003 /* Busy Mode */
313 #define	BFE_HIGH_RM_MASK	0x0000000C /* Retry Mode */
314 #define	BFE_HIGH_SM_MASK	0x00000030 /* Stop Mode */
315 #define	BFE_HIGH_EM_MASK	0x00000300 /* Error Mode */
316 #define	BFE_HIGH_IM_MASK	0x00000c00 /* Interrupt Mode */
317 #define	BFE_HIGH_RM_SHIFT	2
318 #define	BFE_HIGH_SM_SHIFT	4
319 #define	BFE_HIGH_EM_SHIFT	8
320 #define	BFE_HIGH_IM_SHIFT	10
321 
322 #define	BFE_SBBCFG	0x00000FC0 /* BFE_SB Broadcast Configuration */
323 #define	BFE_LAT_MASK	0x00000003 /* BFE_SB Latency */
324 #define	BFE_MAX0_MASK	0x000f0000 /* MAX Counter 0 */
325 #define	BFE_MAX1_MASK	0x00f00000 /* MAX Counter 1 */
326 #define	BFE_MAX0_SHIFT	16
327 #define	BFE_MAX1_SHIFT	20
328 
329 #define	BFE_SBBSTATE		0x00000FC8 /* BFE_SB Broadcast State */
330 #define	BFE_SBBSTATE_SRD	0x00000001 /* ST Reg Disable */
331 #define	BFE_SBBSTATE_HRD	0x00000002 /* Hold Reg Disable */
332 
333 #define	BFE_SBACTCNFG		0x00000FD8 /* BFE_SB Activate Configuration */
334 #define	BFE_SBFLAGST		0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */
335 
336 #define	BFE_SBIDLOW		0x00000FF8 /* BFE_SB Identification Low */
337 #define	BFE_CS_MASK		0x00000003 /* Config Space Mask */
338 #define	BFE_AR_MASK		0x00000038 /* Num Address Ranges Supported */
339 #define	BFE_SYNCH		0x00000040 /* Sync */
340 #define	BFE_INIT		0x00000080 /* Initiator */
341 #define	BFE_MINLAT_MASK		0x00000f00 /* Minimum Backplane Latency */
342 #define	BFE_MAXLAT_MASK		0x0000f000 /* Maximum Backplane Latency */
343 #define	BFE_FIRST		0x00010000 /* This Initiator is First */
344 #define	BFE_CW_MASK		0x000c0000 /* Cycle Counter Width */
345 #define	BFE_TP_MASK		0x00f00000 /* Target Ports */
346 #define	BFE_IP_MASK		0x0f000000 /* Initiator Ports */
347 #define	BFE_AR_SHIFT		3
348 #define	BFE_MINLAT_SHIFT	8
349 #define	BFE_MAXLAT_SHIFT	12
350 #define	BFE_CW_SHIFT		18
351 #define	BFE_TP_SHIFT		20
352 #define	BFE_IP_SHIFT		24
353 
354 #define	BFE_SBIDHIGH		0x00000FFC /* BFE_SB Identification High */
355 #define	BFE_RC_MASK		0x0000000f /* Revision Code */
356 #define	BFE_CC_MASK		0x0000fff0 /* Core Code */
357 #define	BFE_VC_MASK		0xffff0000 /* Vendor Code */
358 #define	BFE_CC_SHIFT		4
359 #define	BFE_VC_SHIFT		16
360 
361 #define	BFE_CORE_ILINE20	0x801
362 #define	BFE_CORE_SDRAM		0x803
363 #define	BFE_CORE_PCI		0x804
364 #define	BFE_CORE_MIPS		0x805
365 #define	BFE_CORE_ENET		0x806
366 #define	BFE_CORE_CODEC		0x807
367 #define	BFE_CORE_USB		0x808
368 #define	BFE_CORE_ILINE100	0x80a
369 #define	BFE_CORE_EXTIF		0x811
370 #define	BFE_CORE_PCI_SHIFT	4
371 #define	BFE_IDH_CORE		0x0000FFF0
372 
373 
374 /* SSB PCI config space registers.  */
375 #define	BFE_BAR0_WIN		0x80
376 #define	BFE_BAR1_WIN		0x84
377 #define	BFE_SPROM_CONTROL	0x88
378 #define	BFE_BAR1_CONTROL	0x8c
379 
380 /* SSB core and hsot control registers.  */
381 #define	BFE_SSB_CONTROL		0x00000000
382 #define	BFE_SSB_ARBCONTROL	0x00000010
383 #define	BFE_SSB_ISTAT		0x00000020
384 #define	BFE_SSB_IMASK		0x00000024
385 #define	BFE_SSB_MBOX		0x00000028
386 #define	BFE_SSB_BCAST_ADDR	0x00000050
387 #define	BFE_SSB_BCAST_DATA	0x00000054
388 #define	BFE_SSB_PCI_TRANS_0	0x00000100
389 #define	BFE_SSB_PCI_TRANS_1	0x00000104
390 #define	BFE_SSB_PCI_TRANS_2	0x00000108
391 #define	BFE_SSB_SPROM		0x00000800
392 
393 #define	BFE_SSB_PCI_MEM		0x00000000
394 #define	BFE_SSB_PCI_IO		0x00000001
395 #define	BFE_SSB_PCI_CFG0	0x00000002
396 #define	BFE_SSB_PCI_CFG1	0x00000003
397 #define	BFE_SSB_PCI_PREF	0x00000004
398 #define	BFE_SSB_PCI_BURST	0x00000008
399 #define	BFE_SSB_PCI_MASK0	0xfc000000
400 #define	BFE_SSB_PCI_MASK1	0xfc000000
401 #define	BFE_SSB_PCI_MASK2	0xc0000000
402 
403 #define	BFE_DESC_LEN		0x00001fff
404 #define	BFE_DESC_CMASK		0x0ff00000 /* Core specific bits */
405 #define	BFE_DESC_EOT		0x10000000 /* End of Table */
406 #define	BFE_DESC_IOC		0x20000000 /* Interrupt On Completion */
407 #define	BFE_DESC_EOF		0x40000000 /* End of Frame */
408 #define	BFE_DESC_SOF		0x80000000 /* Start of Frame */
409 
410 #define	BFE_RX_CP_THRESHOLD	256
411 #define	BFE_RX_HEADER_LEN	28
412 #define	RX_HEAD_ROOM		(BFE_RX_HEADER_LEN + 2)
413 
414 #define	BFE_RX_FLAG_OFIFO	0x00000001 /* FIFO Overflow */
415 #define	BFE_RX_FLAG_CRCERR	0x00000002 /* CRC Error */
416 #define	BFE_RX_FLAG_SERR	0x00000004 /* Receive Symbol Error */
417 #define	BFE_RX_FLAG_ODD		0x00000008 /* Frame has odd number of nibbles */
418 #define	BFE_RX_FLAG_LARGE	0x00000010 /* Frame is > RX MAX Length */
419 #define	BFE_RX_FLAG_MCAST	0x00000020 /* Dest is Multicast Address */
420 #define	BFE_RX_FLAG_BCAST	0x00000040 /* Dest is Broadcast Address */
421 #define	BFE_RX_FLAG_MISS	0x00000080 /* Received due to promisc mode */
422 #define	BFE_RX_FLAG_LAST	0x00000800 /* Last buffer in frame */
423 #define	BFE_RX_FLAG_ERRORS	(BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \
424     BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
425 
426 #define	BFE_MCAST_TBL_SIZE	32
427 #define	BFE_PCI_DMA		0x40000000
428 #define	BFE_REG_PCI		0x18002000
429 
430 #define	BCOM_VENDORID		0x14E4
431 #define	BCOM_DEVICEID_BCM4401	0x4401
432 #define	BCOM_DEVICEID_BCM4401B0	0x170c
433 
434 #define	BFE_TX_LIST_CNT		128
435 #define	BFE_RX_LIST_CNT		128
436 #define	BFE_TX_LIST_SIZE	BFE_TX_LIST_CNT * sizeof (struct bfe_desc)
437 #define	BFE_RX_OFFSET		30
438 #define	BFE_TX_QLEN		256
439 
440 #define	BFE_DESC_ALIGN		0x1000
441 #define	BFE_RX_RING_ALIGN	4096
442 #define	BFE_TX_RING_ALIGN	4096
443 #define	BFE_MAXTXSEGS		16
444 #define	BFE_DMA_MAXADDR		0x3FFFFFFF	/* 1GB DMA address limit. */
445 #define	BFE_ADDR_LO(x)		((uint64_t)(x) & 0xFFFFFFFF)
446 
447 /* Card's EEPROM */
448 #define	BFE_EEPROM_BASE		0x1000
449 #define	BFE_EEPROM_SIZE		32
450 #define	BFE_EEPROM_NODEADDR	78
451 #define	BFE_EEPROM_PHYADDR	90
452 #define	BFE_EEPROM_MAGIC	126
453 
454 typedef	struct	bfe_hw_stats {
455 	/* TX Side */
456 	uint32_t	tx_good_octets;
457 	uint32_t	tx_good_pkts;
458 	uint32_t	tx_octets;
459 	uint32_t	tx_pkts;
460 	uint32_t	tx_broadcast_pkts;
461 	uint32_t	tx_multicast_pkts;
462 	uint32_t	tx_len_64;
463 	uint32_t	tx_len_65_to_127;
464 	uint32_t	tx_len_128_to_255;
465 	uint32_t	tx_len_256_to_511;
466 	uint32_t	tx_len_512_to_1023;
467 	uint32_t	tx_len_1024_to_max;
468 	uint32_t	tx_jabber_pkts;
469 	uint32_t	tx_oversize_pkts;
470 	uint32_t	tx_fragment_pkts;
471 	uint32_t	tx_underruns;
472 	uint32_t	tx_total_cols;
473 	uint32_t	tx_single_cols;
474 	uint32_t	tx_multiple_cols;
475 	uint32_t	tx_excessive_cols;
476 	uint32_t	tx_late_cols;
477 	uint32_t	tx_defered;
478 	uint32_t	tx_carrier_lost;
479 	uint32_t	tx_pause_pkts;
480 	uint32_t	pad1[8];
481 
482 	/* RX Side */
483 	uint32_t	rx_good_octets;
484 	uint32_t	rx_good_pkts;
485 	uint32_t	rx_octets;
486 	uint32_t	rx_pkts;
487 	uint32_t	rx_broadcast_pkts;
488 	uint32_t	rx_multicast_pkts;
489 	uint32_t	rx_len_64;
490 	uint32_t	rx_len_65_to_127;
491 	uint32_t	rx_len_128_to_255;
492 	uint32_t	rx_len_256_to_511;
493 	uint32_t	rx_len_512_to_1023;
494 	uint32_t	rx_len_1024_to_max;
495 	uint32_t	rx_jabber_pkts;
496 	uint32_t	rx_oversize_pkts;
497 	uint32_t	rx_fragment_pkts;
498 	uint32_t	rx_missed_pkts;
499 	uint32_t	rx_crc_align_errs;
500 	uint32_t	rx_undersize;
501 	uint32_t	rx_crc_errs;
502 	uint32_t	rx_align_errs;
503 	uint32_t	rx_symbol_errs;
504 	uint32_t	rx_pause_pkts;
505 	uint32_t	rx_nonpause_pkts;
506 } bfe_hw_stats_t;
507 
508 #endif /* _BFE_HW_H */
509