1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008 Atheros Communications Inc. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #include <sys/param.h> 23 #include <sys/types.h> 24 #include <sys/cmn_err.h> 25 #include <sys/kmem.h> 26 #include <sys/ddi.h> 27 #include <sys/sunddi.h> 28 #include <sys/varargs.h> 29 30 #include "arn_ath9k.h" 31 #include "arn_core.h" 32 #include "arn_hw.h" 33 #include "arn_reg.h" 34 #include "arn_phy.h" 35 #include "arn_initvals.h" 36 37 static const uint8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 }; 38 39 extern struct hal_percal_data iq_cal_multi_sample; 40 extern struct hal_percal_data iq_cal_single_sample; 41 extern struct hal_percal_data adc_gain_cal_multi_sample; 42 extern struct hal_percal_data adc_gain_cal_single_sample; 43 extern struct hal_percal_data adc_dc_cal_multi_sample; 44 extern struct hal_percal_data adc_dc_cal_single_sample; 45 extern struct hal_percal_data adc_init_dc_cal; 46 47 static boolean_t ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type); 48 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 49 enum ath9k_ht_macmode macmode); 50 static uint32_t ath9k_hw_ini_fixup(struct ath_hal *ah, 51 struct ar5416_eeprom_def *pEepData, 52 uint32_t reg, uint32_t value); 53 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, 54 struct ath9k_channel *chan); 55 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, 56 struct ath9k_channel *chan); 57 58 /* Helper Functions */ 59 60 static uint32_t 61 ath9k_hw_mac_usec(struct ath_hal *ah, uint32_t clks) 62 { 63 if (ah->ah_curchan != NULL) 64 return (clks / 65 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]); 66 else 67 return (clks / CLOCK_RATE[ATH9K_MODE_11B]); 68 } 69 70 static uint32_t 71 ath9k_hw_mac_to_usec(struct ath_hal *ah, uint32_t clks) 72 { 73 struct ath9k_channel *chan = ah->ah_curchan; 74 75 if (chan && IS_CHAN_HT40(chan)) 76 return (ath9k_hw_mac_usec(ah, clks) / 2); 77 else 78 return (ath9k_hw_mac_usec(ah, clks)); 79 } 80 81 static uint32_t 82 ath9k_hw_mac_clks(struct ath_hal *ah, uint32_t usecs) 83 { 84 if (ah->ah_curchan != NULL) 85 return (usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, 86 ah->ah_curchan)]); 87 else 88 return (usecs * CLOCK_RATE[ATH9K_MODE_11B]); 89 } 90 91 static uint32_t 92 ath9k_hw_mac_to_clks(struct ath_hal *ah, uint32_t usecs) 93 { 94 struct ath9k_channel *chan = ah->ah_curchan; 95 96 if (chan && IS_CHAN_HT40(chan)) 97 return (ath9k_hw_mac_clks(ah, usecs) * 2); 98 else 99 return (ath9k_hw_mac_clks(ah, usecs)); 100 } 101 102 /* ARGSUSED */ 103 enum wireless_mode 104 ath9k_hw_chan2wmode(struct ath_hal *ah, const struct ath9k_channel *chan) 105 { 106 if (IS_CHAN_B(chan)) 107 return (ATH9K_MODE_11B); 108 if (IS_CHAN_G(chan)) 109 return (ATH9K_MODE_11G); 110 111 return (ATH9K_MODE_11A); 112 } 113 114 boolean_t 115 ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask, uint32_t val) 116 { 117 int i; 118 119 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) { 120 if ((REG_READ(ah, reg) & mask) == val) 121 return (B_TRUE); 122 123 drv_usecwait(AH_TIME_QUANTUM); 124 } 125 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_wait(): " 126 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 127 reg, REG_READ(ah, reg), mask, val)); 128 129 return (B_FALSE); 130 } 131 132 uint32_t 133 ath9k_hw_reverse_bits(uint32_t val, uint32_t n) 134 { 135 uint32_t retval; 136 int i; 137 138 for (i = 0, retval = 0; i < n; i++) { 139 retval = (retval << 1) | (val & 1); 140 val >>= 1; 141 } 142 return (retval); 143 } 144 145 boolean_t 146 ath9k_get_channel_edges(struct ath_hal *ah, 147 uint16_t flags, uint16_t *low, uint16_t *high) 148 { 149 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 150 151 if (flags & CHANNEL_5GHZ) { 152 *low = pCap->low_5ghz_chan; 153 *high = pCap->high_5ghz_chan; 154 return (B_TRUE); 155 } 156 if ((flags & CHANNEL_2GHZ)) { 157 *low = pCap->low_2ghz_chan; 158 *high = pCap->high_2ghz_chan; 159 return (B_TRUE); 160 } 161 return (B_FALSE); 162 } 163 164 uint16_t 165 ath9k_hw_computetxtime(struct ath_hal *ah, 166 struct ath_rate_table *rates, 167 uint32_t frameLen, uint16_t rateix, 168 boolean_t shortPreamble) 169 { 170 uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 171 uint32_t kbps; 172 173 kbps = rates->info[rateix].ratekbps; 174 175 if (kbps == 0) 176 return (0); 177 178 switch (rates->info[rateix].phy) { 179 case WLAN_RC_PHY_CCK: 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 181 if (shortPreamble && rates->info[rateix].short_preamble) 182 phyTime >>= 1; 183 numBits = frameLen << 3; 184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 185 break; 186 case WLAN_RC_PHY_OFDM: 187 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { 188 bitsPerSymbol = 189 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 190 numBits = OFDM_PLCP_BITS + (frameLen << 3); 191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 192 txTime = OFDM_SIFS_TIME_QUARTER + 193 OFDM_PREAMBLE_TIME_QUARTER + 194 (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 195 } else if (ah->ah_curchan && 196 IS_CHAN_HALF_RATE(ah->ah_curchan)) { 197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 198 numBits = OFDM_PLCP_BITS + (frameLen << 3); 199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 200 txTime = OFDM_SIFS_TIME_HALF + 201 OFDM_PREAMBLE_TIME_HALF + 202 (numSymbols * OFDM_SYMBOL_TIME_HALF); 203 } else { 204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 205 numBits = OFDM_PLCP_BITS + (frameLen << 3); 206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME + 208 (numSymbols * OFDM_SYMBOL_TIME); 209 } 210 break; 211 default: 212 arn_problem("arn: " 213 "%s: unknown phy %u (rate ix %u)\n", __func__, 214 rates->info[rateix].phy, rateix); 215 txTime = 0; 216 break; 217 } 218 219 return ((uint16_t)txTime); 220 } 221 222 uint32_t 223 ath9k_hw_mhz2ieee(struct ath_hal *ah, uint32_t freq, uint32_t flags) 224 { 225 if (flags & CHANNEL_2GHZ) { 226 if (freq == 2484) 227 return (14); 228 if (freq < 2484) 229 return ((freq - 2407) / 5); 230 else 231 return (15 + ((freq - 2512) / 20)); 232 } else if (flags & CHANNEL_5GHZ) { 233 if (ath9k_regd_is_public_safety_sku(ah) && 234 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) { 235 return (((freq * 10) + 236 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5); 237 } else if ((flags & CHANNEL_A) && (freq <= 5000)) { 238 return ((freq - 4000) / 5); 239 } else { 240 return ((freq - 5000) / 5); 241 } 242 } else { 243 if (freq == 2484) 244 return (14); 245 if (freq < 2484) 246 return ((freq - 2407) / 5); 247 if (freq < 5000) { 248 if (ath9k_regd_is_public_safety_sku(ah) && 249 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) { 250 return (((freq * 10) + 251 (((freq % 5) == 252 2) ? 5 : 0) - 49400) / 5); 253 } else if (freq > 4900) { 254 return ((freq - 4000) / 5); 255 } else { 256 return (15 + ((freq - 2512) / 20)); 257 } 258 } 259 return ((freq - 5000) / 5); 260 } 261 } 262 263 void 264 ath9k_hw_get_channel_centers(struct ath_hal *ah, 265 struct ath9k_channel *chan, 266 struct chan_centers *centers) 267 { 268 int8_t extoff; 269 struct ath_hal_5416 *ahp = AH5416(ah); 270 271 if (!IS_CHAN_HT40(chan)) { 272 centers->ctl_center = centers->ext_center = 273 centers->synth_center = chan->channel; 274 return; 275 } 276 277 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 278 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 279 centers->synth_center = 280 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 281 extoff = 1; 282 } else { 283 centers->synth_center = 284 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 285 extoff = -1; 286 } 287 288 centers->ctl_center = 289 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 290 centers->ext_center = 291 centers->synth_center + (extoff * 292 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? 293 HT40_CHANNEL_CENTER_SHIFT : 15)); 294 295 } 296 297 /* Chip Revisions */ 298 299 static void 300 ath9k_hw_read_revisions(struct ath_hal *ah) 301 { 302 uint32_t val; 303 304 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 305 306 if (val == 0xFF) { 307 val = REG_READ(ah, AR_SREV); 308 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 309 ah->ah_macRev = MS(val, AR_SREV_REVISION2); 310 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 311 } else { 312 if (!AR_SREV_9100(ah)) 313 ah->ah_macVersion = MS(val, AR_SREV_VERSION); 314 315 ah->ah_macRev = val & AR_SREV_REVISION; 316 317 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) 318 ah->ah_isPciExpress = B_TRUE; 319 } 320 } 321 322 static int 323 ath9k_hw_get_radiorev(struct ath_hal *ah) 324 { 325 uint32_t val; 326 int i; 327 328 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 329 330 for (i = 0; i < 8; i++) 331 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 332 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 333 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 334 335 return (ath9k_hw_reverse_bits(val, 8)); 336 } 337 338 /* HW Attach, Detach, Init Routines */ 339 340 static void 341 ath9k_hw_disablepcie(struct ath_hal *ah) 342 { 343 if (!AR_SREV_9100(ah)) 344 return; 345 346 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 347 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 348 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 349 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 350 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 351 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 352 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 353 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 354 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 355 356 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 357 } 358 359 static boolean_t 360 ath9k_hw_chip_test(struct ath_hal *ah) 361 { 362 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 363 uint32_t regHold[2]; 364 uint32_t patternData[4] = { 0x55555555, 0xaaaaaaaa, 365 0x66666666, 0x99999999 }; 366 int i, j; 367 368 for (i = 0; i < 2; i++) { 369 uint32_t addr = regAddr[i]; 370 uint32_t wrData, rdData; 371 372 regHold[i] = REG_READ(ah, addr); 373 for (j = 0; j < 0x100; j++) { 374 wrData = (j << 16) | j; 375 REG_WRITE(ah, addr, wrData); 376 rdData = REG_READ(ah, addr); 377 if (rdData != wrData) { 378 ARN_DBG((ARN_DBG_REG_IO, 379 "arn: ath9k_hw_chip_test(): " 380 "address test failed " 381 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 382 addr, wrData, rdData)); 383 384 return (B_FALSE); 385 } 386 } 387 for (j = 0; j < 4; j++) { 388 wrData = patternData[j]; 389 REG_WRITE(ah, addr, wrData); 390 rdData = REG_READ(ah, addr); 391 if (wrData != rdData) { 392 ARN_DBG((ARN_DBG_REG_IO, 393 "arn: ath9k_hw_chip_test(): " 394 "address test failed " 395 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 396 addr, wrData, rdData)); 397 398 return (B_FALSE); 399 } 400 } 401 REG_WRITE(ah, regAddr[i], regHold[i]); 402 } 403 drv_usecwait(100); 404 405 return (B_TRUE); 406 } 407 408 static const char * 409 ath9k_hw_devname(uint16_t devid) 410 { 411 switch (devid) { 412 case AR5416_DEVID_PCI: 413 return ("Atheros 5416"); 414 case AR5416_DEVID_PCIE: 415 return ("Atheros 5418"); 416 case AR9160_DEVID_PCI: 417 return ("Atheros 9160"); 418 case AR9280_DEVID_PCI: 419 case AR9280_DEVID_PCIE: 420 return ("Atheros 9280"); 421 case AR9285_DEVID_PCIE: 422 return ("Atheros 9285"); 423 } 424 425 return (NULL); 426 } 427 428 static void 429 ath9k_hw_set_defaults(struct ath_hal *ah) 430 { 431 int i; 432 433 ah->ah_config.dma_beacon_response_time = 2; 434 ah->ah_config.sw_beacon_response_time = 10; 435 ah->ah_config.additional_swba_backoff = 0; 436 ah->ah_config.ack_6mb = 0x0; 437 ah->ah_config.cwm_ignore_extcca = 0; 438 ah->ah_config.pcie_powersave_enable = 0; 439 ah->ah_config.pcie_l1skp_enable = 0; 440 ah->ah_config.pcie_clock_req = 0; 441 ah->ah_config.pcie_power_reset = 0x100; 442 ah->ah_config.pcie_restore = 0; 443 ah->ah_config.pcie_waen = 0; 444 ah->ah_config.analog_shiftreg = 1; 445 ah->ah_config.ht_enable = 1; 446 ah->ah_config.ofdm_trig_low = 200; 447 ah->ah_config.ofdm_trig_high = 500; 448 ah->ah_config.cck_trig_high = 200; 449 ah->ah_config.cck_trig_low = 100; 450 ah->ah_config.enable_ani = 1; 451 ah->ah_config.noise_immunity_level = 4; 452 ah->ah_config.ofdm_weaksignal_det = 1; 453 ah->ah_config.cck_weaksignal_thr = 0; 454 ah->ah_config.spur_immunity_level = 2; 455 ah->ah_config.firstep_level = 0; 456 ah->ah_config.rssi_thr_high = 40; 457 ah->ah_config.rssi_thr_low = 7; 458 ah->ah_config.diversity_control = 0; 459 ah->ah_config.antenna_switch_swap = 0; 460 461 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 462 ah->ah_config.spurchans[i][0] = AR_NO_SPUR; 463 ah->ah_config.spurchans[i][1] = AR_NO_SPUR; 464 } 465 466 ah->ah_config.intr_mitigation = 1; 467 468 /* 469 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 470 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 471 * This means we use it for all AR5416 devices, and the few 472 * minor PCI AR9280 devices out there. 473 * 474 * Serialization is required because these devices do not handle 475 * well the case of two concurrent reads/writes due to the latency 476 * involved. During one read/write another read/write can be issued 477 * on another CPU while the previous read/write may still be working 478 * on our hardware, if we hit this case the hardware poops in a loop. 479 * We prevent this by serializing reads and writes. 480 * 481 * This issue is not present on PCI-Express devices or pre-AR5416 482 * devices (legacy, 802.11abg). 483 */ 484 485 /* num_of_cpus */ 486 } 487 488 static struct ath_hal_5416 * 489 ath9k_hw_newstate(uint16_t device_id, struct arn_softc *sc, caddr_t mem, 490 int *status) 491 { 492 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 493 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 494 struct ath_hal_5416 *ahp; 495 struct ath_hal *ah; 496 497 ahp = (struct ath_hal_5416 *) 498 kmem_zalloc(sizeof (struct ath_hal_5416), KM_SLEEP); 499 if (ahp == NULL) { 500 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_newstate(): " 501 "failed to alloc mem for ahp\n")); 502 *status = ENOMEM; 503 return (NULL); 504 } 505 506 ah = &ahp->ah; 507 ah->ah_sc = sc; 508 ah->ah_sh = mem; 509 ah->ah_magic = AR5416_MAGIC; 510 ah->ah_countryCode = CTRY_DEFAULT; 511 ah->ah_devid = device_id; 512 ah->ah_subvendorid = 0; 513 514 ah->ah_flags = 0; 515 if ((device_id == AR5416_AR9100_DEVID)) 516 ah->ah_macVersion = AR_SREV_VERSION_9100; 517 if (!AR_SREV_9100(ah)) 518 ah->ah_flags = AH_USE_EEPROM; 519 520 ah->ah_powerLimit = MAX_RATE_POWER; 521 ah->ah_tpScale = ATH9K_TP_SCALE_MAX; 522 ahp->ah_atimWindow = 0; 523 ahp->ah_diversityControl = ah->ah_config.diversity_control; 524 ahp->ah_antennaSwitchSwap = 525 ah->ah_config.antenna_switch_swap; 526 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 527 ahp->ah_beaconInterval = 100; 528 ahp->ah_enable32kHzClock = DONT_USE_32KHZ; 529 ahp->ah_slottime = (uint32_t)-1; 530 ahp->ah_acktimeout = (uint32_t)-1; 531 ahp->ah_ctstimeout = (uint32_t)-1; 532 ahp->ah_globaltxtimeout = (uint32_t)-1; 533 (void) memcpy(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 534 535 ahp->ah_gBeaconRate = 0; 536 537 return (ahp); 538 } 539 540 static int 541 ath9k_hw_rfattach(struct ath_hal *ah) 542 { 543 boolean_t rfStatus = B_FALSE; 544 int ecode = 0; 545 546 rfStatus = ath9k_hw_init_rf(ah, &ecode); 547 if (!rfStatus) { 548 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_rfattach(): " 549 "RF setup failed, status %u\n", ecode)); 550 551 return (ecode); 552 } 553 554 return (0); 555 } 556 557 static int 558 ath9k_hw_rf_claim(struct ath_hal *ah) 559 { 560 uint32_t val; 561 562 REG_WRITE(ah, AR_PHY(0), 0x00000007); 563 564 val = ath9k_hw_get_radiorev(ah); 565 switch (val & AR_RADIO_SREV_MAJOR) { 566 case 0: 567 val = AR_RAD5133_SREV_MAJOR; 568 break; 569 case AR_RAD5133_SREV_MAJOR: 570 case AR_RAD5122_SREV_MAJOR: 571 case AR_RAD2133_SREV_MAJOR: 572 case AR_RAD2122_SREV_MAJOR: 573 break; 574 default: 575 ARN_DBG((ARN_DBG_CHANNEL, 576 "arn: ath9k_hw_rf_claim(): " 577 "5G Radio Chip Rev 0x%02X " 578 "is not supported by this driver\n", 579 ah->ah_analog5GhzRev)); 580 581 return (ENOTSUP); 582 } 583 584 ah->ah_analog5GhzRev = (uint16_t)val; 585 586 return (0); 587 } 588 589 static int 590 ath9k_hw_init_macaddr(struct ath_hal *ah) 591 { 592 uint32_t sum; 593 int i; 594 uint16_t eeval; 595 struct ath_hal_5416 *ahp = AH5416(ah); 596 597 sum = 0; 598 for (i = 0; i < 3; i++) { 599 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); 600 sum += eeval; 601 ahp->ah_macaddr[2 * i] = eeval >> 8; 602 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff; 603 } 604 if (sum == 0 || sum == 0xffff * 3) { 605 ARN_DBG((ARN_DBG_EEPROM, "arn: ath9k_hw_init_macaddr(): " 606 "mac address read failed: %pM\n", 607 ahp->ah_macaddr)); 608 609 return (EADDRNOTAVAIL); 610 } 611 612 return (0); 613 } 614 615 static void 616 ath9k_hw_init_rxgain_ini(struct ath_hal *ah) 617 { 618 uint32_t rxgain_type; 619 struct ath_hal_5416 *ahp = AH5416(ah); 620 621 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 622 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); 623 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) { 624 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 625 ar9280Modes_backoff_13db_rxgain_9280_2, 626 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 627 6); 628 } else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) { 629 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 630 ar9280Modes_backoff_23db_rxgain_9280_2, 631 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 632 6); 633 } else { 634 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 635 ar9280Modes_original_rxgain_9280_2, 636 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 637 } 638 } else { 639 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 640 ar9280Modes_original_rxgain_9280_2, 641 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 642 } 643 } 644 645 static void 646 ath9k_hw_init_txgain_ini(struct ath_hal *ah) 647 { 648 uint32_t txgain_type; 649 struct ath_hal_5416 *ahp = AH5416(ah); 650 651 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 652 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); 653 654 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 655 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 656 ar9280Modes_high_power_tx_gain_9280_2, 657 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 658 6); 659 } else { 660 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 661 ar9280Modes_original_tx_gain_9280_2, 662 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 663 } 664 } else { 665 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 666 ar9280Modes_original_tx_gain_9280_2, 667 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 668 } 669 } 670 671 static int 672 ath9k_hw_post_attach(struct ath_hal *ah) 673 { 674 int ecode; 675 676 if (!ath9k_hw_chip_test(ah)) { 677 ARN_DBG((ARN_DBG_REG_IO, "arn: ath9k_hw_post_attach(): " 678 "hardware self-test failed\n")); 679 680 } 681 682 ecode = ath9k_hw_rf_claim(ah); 683 if (ecode != 0) 684 return (ecode); 685 686 ecode = ath9k_hw_eeprom_attach(ah); 687 if (ecode != 0) 688 return (ecode); 689 ecode = ath9k_hw_rfattach(ah); 690 if (ecode != 0) 691 return (ecode); 692 693 if (!AR_SREV_9100(ah)) { 694 ath9k_hw_ani_setup(ah); 695 ath9k_hw_ani_attach(ah); 696 } 697 698 return (0); 699 } 700 701 static struct ath_hal * 702 ath9k_hw_do_attach(uint16_t device_id, struct arn_softc *sc, 703 caddr_t mem, int *status) 704 { 705 struct ath_hal_5416 *ahp; 706 struct ath_hal *ah; 707 int ecode; 708 uint32_t i; 709 uint32_t j; 710 711 ahp = ath9k_hw_newstate(device_id, sc, mem, status); 712 if (ahp == NULL) 713 return (NULL); 714 715 ah = &ahp->ah; 716 717 ath9k_hw_set_defaults(ah); 718 719 if (ah->ah_config.intr_mitigation != 0) 720 ahp->ah_intrMitigation = B_TRUE; 721 722 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 723 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_reset_reg(): " 724 "couldn't reset chip \n")); 725 ecode = EIO; 726 goto bad; 727 } 728 729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 730 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_setpower(): " 731 "couldn't wakeup chip \n")); 732 ecode = EIO; 733 goto bad; 734 } 735 736 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { 737 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI || 738 (AR_SREV_9280(ah) && !ah->ah_isPciExpress)) { 739 ah->ah_config.serialize_regmode = 740 SER_REG_MODE_ON; 741 } else { 742 ah->ah_config.serialize_regmode = 743 SER_REG_MODE_OFF; 744 } 745 } 746 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): " 747 "serialize_regmode is %d\n", 748 ah->ah_config.serialize_regmode)); 749 750 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && 751 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && 752 (ah->ah_macVersion != AR_SREV_VERSION_9160) && 753 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && 754 (!AR_SREV_9285(ah))) { 755 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): " 756 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 757 ah->ah_macVersion, ah->ah_macRev)); 758 ecode = ENOTSUP; 759 goto bad; 760 } 761 762 if (AR_SREV_9100(ah)) { 763 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 764 ahp->ah_suppCals = IQ_MISMATCH_CAL; 765 ah->ah_isPciExpress = B_FALSE; 766 } 767 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 768 769 if (AR_SREV_9160_10_OR_LATER(ah)) { 770 if (AR_SREV_9280_10_OR_LATER(ah)) { 771 ahp->ah_iqCalData.calData = &iq_cal_single_sample; 772 ahp->ah_adcGainCalData.calData = 773 &adc_gain_cal_single_sample; 774 ahp->ah_adcDcCalData.calData = 775 &adc_dc_cal_single_sample; 776 ahp->ah_adcDcCalInitData.calData = 777 &adc_init_dc_cal; 778 } else { 779 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 780 ahp->ah_adcGainCalData.calData = 781 &adc_gain_cal_multi_sample; 782 ahp->ah_adcDcCalData.calData = 783 &adc_dc_cal_multi_sample; 784 ahp->ah_adcDcCalInitData.calData = 785 &adc_init_dc_cal; 786 } 787 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 788 } 789 790 if (AR_SREV_9160(ah)) { 791 ah->ah_config.enable_ani = 1; 792 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 793 ATH9K_ANI_FIRSTEP_LEVEL); 794 } else { 795 ahp->ah_ani_function = ATH9K_ANI_ALL; 796 if (AR_SREV_9280_10_OR_LATER(ah)) { 797 ahp->ah_ani_function &= 798 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 799 } 800 } 801 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): " 802 "This Mac Chip Rev 0x%02x.%x is \n", 803 ah->ah_macVersion, ah->ah_macRev)); 804 805 if (AR_SREV_9285_12_OR_LATER(ah)) { 806 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, 807 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 808 809 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2, 810 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 811 812 if (ah->ah_config.pcie_clock_req) { 813 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 814 ar9285PciePhy_clkreq_off_L1_9285_1_2, 815 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 816 2); 817 } else { 818 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 819 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 820 ARRAY_SIZE 821 (ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 2); 822 } 823 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 824 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285, 825 ARRAY_SIZE(ar9285Modes_9285), 6); 826 827 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285, 828 ARRAY_SIZE(ar9285Common_9285), 2); 829 830 if (ah->ah_config.pcie_clock_req) { 831 832 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 833 ar9285PciePhy_clkreq_off_L1_9285, 834 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 835 } else { 836 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 837 ar9285PciePhy_clkreq_always_on_L1_9285, 838 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 839 2); 840 } 841 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 842 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 843 ARRAY_SIZE(ar9280Modes_9280_2), 6); 844 845 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 846 ARRAY_SIZE(ar9280Common_9280_2), 2); 847 848 if (ah->ah_config.pcie_clock_req) { 849 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 850 ar9280PciePhy_clkreq_off_L1_9280, 851 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); 852 } else { 853 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 854 ar9280PciePhy_clkreq_always_on_L1_9280, 855 ARRAY_SIZE 856 (ar9280PciePhy_clkreq_always_on_L1_9280), 2); 857 } 858 859 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, 860 ar9280Modes_fast_clock_9280_2, 861 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 862 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 863 864 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, 865 ARRAY_SIZE(ar9280Modes_9280), 6); 866 867 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, 868 ARRAY_SIZE(ar9280Common_9280), 2); 869 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 870 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, 871 ARRAY_SIZE(ar5416Modes_9160), 6); 872 873 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, 874 ARRAY_SIZE(ar5416Common_9160), 2); 875 876 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, 877 ARRAY_SIZE(ar5416Bank0_9160), 2); 878 879 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, 880 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 881 882 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, 883 ARRAY_SIZE(ar5416Bank1_9160), 2); 884 885 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, 886 ARRAY_SIZE(ar5416Bank2_9160), 2); 887 888 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, 889 ARRAY_SIZE(ar5416Bank3_9160), 3); 890 891 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, 892 ARRAY_SIZE(ar5416Bank6_9160), 3); 893 894 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, 895 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 896 897 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, 898 ARRAY_SIZE(ar5416Bank7_9160), 2); 899 if (AR_SREV_9160_11(ah)) { 900 INIT_INI_ARRAY(&ahp->ah_iniAddac, 901 ar5416Addac_91601_1, 902 ARRAY_SIZE(ar5416Addac_91601_1), 2); 903 } else { 904 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, 905 ARRAY_SIZE(ar5416Addac_9160), 2); 906 } 907 } else if (AR_SREV_9100_OR_LATER(ah)) { 908 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, 909 ARRAY_SIZE(ar5416Modes_9100), 6); 910 911 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, 912 ARRAY_SIZE(ar5416Common_9100), 2); 913 914 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, 915 ARRAY_SIZE(ar5416Bank0_9100), 2); 916 917 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, 918 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 919 920 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, 921 ARRAY_SIZE(ar5416Bank1_9100), 2); 922 923 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, 924 ARRAY_SIZE(ar5416Bank2_9100), 2); 925 926 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, 927 ARRAY_SIZE(ar5416Bank3_9100), 3); 928 929 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, 930 ARRAY_SIZE(ar5416Bank6_9100), 3); 931 932 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, 933 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 934 935 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, 936 ARRAY_SIZE(ar5416Bank7_9100), 2); 937 938 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, 939 ARRAY_SIZE(ar5416Addac_9100), 2); 940 } else { 941 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, 942 ARRAY_SIZE(ar5416Modes), 6); 943 944 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, 945 ARRAY_SIZE(ar5416Common), 2); 946 947 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, 948 ARRAY_SIZE(ar5416Bank0), 2); 949 950 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, 951 ARRAY_SIZE(ar5416BB_RfGain), 3); 952 953 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, 954 ARRAY_SIZE(ar5416Bank1), 2); 955 956 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, 957 ARRAY_SIZE(ar5416Bank2), 2); 958 959 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, 960 ARRAY_SIZE(ar5416Bank3), 3); 961 962 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, 963 ARRAY_SIZE(ar5416Bank6), 3); 964 965 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, 966 ARRAY_SIZE(ar5416Bank6TPC), 3); 967 968 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, 969 ARRAY_SIZE(ar5416Bank7), 2); 970 971 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, 972 ARRAY_SIZE(ar5416Addac), 2); 973 } 974 975 if (ah->ah_isPciExpress) 976 ath9k_hw_configpcipowersave(ah, 0); 977 else 978 ath9k_hw_disablepcie(ah); 979 980 ecode = ath9k_hw_post_attach(ah); 981 if (ecode != 0) 982 goto bad; 983 984 /* rxgain table */ 985 if (AR_SREV_9280_20(ah)) 986 ath9k_hw_init_rxgain_ini(ah); 987 988 /* txgain table */ 989 if (AR_SREV_9280_20(ah)) 990 ath9k_hw_init_txgain_ini(ah); 991 992 if (ah->ah_devid == AR9280_DEVID_PCI) { 993 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 994 uint32_t reg = 995 INI_RA(&ahp->ah_iniModes, i, 0); 996 997 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { 998 uint32_t val 999 = INI_RA(&ahp->ah_iniModes, i, j); 1000 1001 INI_RA(&ahp->ah_iniModes, i, j) = 1002 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom.def, 1003 reg, val); 1004 } 1005 } 1006 } 1007 1008 if (!ath9k_hw_fill_cap_info(ah)) { 1009 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): " 1010 "failed ath9k_hw_fill_cap_info\n")); 1011 goto bad; 1012 } 1013 1014 ecode = ath9k_hw_init_macaddr(ah); 1015 if (ecode != 0) { 1016 ARN_DBG((ARN_DBG_HW, "arn: " 1017 "%s: failed initializing mac address\n", 1018 __func__)); 1019 goto bad; 1020 } 1021 1022 if (AR_SREV_9285(ah)) 1023 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); 1024 else 1025 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); 1026 1027 ath9k_init_nfcal_hist_buffer(ah); 1028 1029 return (ah); 1030 bad: 1031 if (ahp) 1032 ath9k_hw_detach((struct ath_hal *)ahp); 1033 if (status) 1034 *status = ecode; 1035 1036 return (NULL); 1037 } 1038 1039 static void 1040 ath9k_hw_init_bb(struct ath_hal *ah, struct ath9k_channel *chan) 1041 { 1042 uint32_t synthDelay; 1043 1044 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1045 if (IS_CHAN_B(chan)) 1046 synthDelay = (4 * synthDelay) / 22; 1047 else 1048 synthDelay /= 10; 1049 1050 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1051 1052 drv_usecwait(synthDelay + BASE_ACTIVATE_DELAY); 1053 } 1054 1055 static void 1056 ath9k_hw_init_qos(struct ath_hal *ah) 1057 { 1058 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 1059 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 1060 1061 REG_WRITE(ah, AR_QOS_NO_ACK, 1062 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 1063 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 1064 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 1065 1066 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 1067 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 1068 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 1069 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 1070 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 1071 } 1072 1073 static void 1074 ath9k_hw_init_pll(struct ath_hal *ah, struct ath9k_channel *chan) 1075 { 1076 uint32_t pll; 1077 1078 if (AR_SREV_9100(ah)) { 1079 if (chan && IS_CHAN_5GHZ(chan)) 1080 pll = 0x1450; 1081 else 1082 pll = 0x1458; 1083 } else { 1084 if (AR_SREV_9280_10_OR_LATER(ah)) { 1085 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1086 1087 if (chan && IS_CHAN_HALF_RATE(chan)) 1088 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1089 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1090 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1091 1092 if (chan && IS_CHAN_5GHZ(chan)) { 1093 pll |= SM(0x28, AR_RTC_9160_PLL_DIV); 1094 1095 1096 if (AR_SREV_9280_20(ah)) { 1097 if (((chan->channel % 20) == 0) || 1098 ((chan->channel % 10) == 0)) 1099 pll = 0x2850; 1100 else 1101 pll = 0x142c; 1102 } 1103 } else { 1104 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); 1105 } 1106 1107 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1108 1109 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1110 1111 if (chan && IS_CHAN_HALF_RATE(chan)) 1112 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1113 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1114 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1115 1116 if (chan && IS_CHAN_5GHZ(chan)) 1117 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 1118 else 1119 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 1120 } else { 1121 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1122 1123 if (chan && IS_CHAN_HALF_RATE(chan)) 1124 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1125 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1126 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1127 1128 if (chan && IS_CHAN_5GHZ(chan)) 1129 pll |= SM(0xa, AR_RTC_PLL_DIV); 1130 else 1131 pll |= SM(0xb, AR_RTC_PLL_DIV); 1132 } 1133 } 1134 REG_WRITE(ah, (uint16_t)(AR_RTC_PLL_CONTROL), pll); 1135 1136 drv_usecwait(RTC_PLL_SETTLE_DELAY); 1137 1138 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1139 } 1140 1141 static void 1142 ath9k_hw_init_chain_masks(struct ath_hal *ah) 1143 { 1144 struct ath_hal_5416 *ahp = AH5416(ah); 1145 int rx_chainmask, tx_chainmask; 1146 1147 rx_chainmask = ahp->ah_rxchainmask; 1148 tx_chainmask = ahp->ah_txchainmask; 1149 1150 switch (rx_chainmask) { 1151 case 0x5: 1152 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1153 AR_PHY_SWAP_ALT_CHAIN); 1154 /*FALLTHRU*/ 1155 case 0x3: 1156 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) { 1157 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1158 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1159 break; 1160 } 1161 /*FALLTHRU*/ 1162 case 0x1: 1163 case 0x2: 1164 case 0x7: 1165 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1166 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1167 break; 1168 default: 1169 break; 1170 } 1171 1172 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 1173 if (tx_chainmask == 0x5) { 1174 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1175 AR_PHY_SWAP_ALT_CHAIN); 1176 } 1177 if (AR_SREV_9100(ah)) 1178 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1179 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1180 } 1181 1182 static void 1183 ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode) 1184 { 1185 struct ath_hal_5416 *ahp = AH5416(ah); 1186 1187 ahp->ah_maskReg = AR_IMR_TXERR | 1188 AR_IMR_TXURN | 1189 AR_IMR_RXERR | 1190 AR_IMR_RXORN | 1191 AR_IMR_BCNMISC; 1192 1193 if (ahp->ah_intrMitigation) 1194 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1195 else 1196 ahp->ah_maskReg |= AR_IMR_RXOK; 1197 1198 ahp->ah_maskReg |= AR_IMR_TXOK; 1199 1200 if (opmode == ATH9K_M_HOSTAP) 1201 ahp->ah_maskReg |= AR_IMR_MIB; 1202 1203 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 1204 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 1205 1206 if (!AR_SREV_9100(ah)) { 1207 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 1208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 1209 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 1210 } 1211 } 1212 1213 static boolean_t 1214 ath9k_hw_set_ack_timeout(struct ath_hal *ah, uint32_t us) 1215 { 1216 struct ath_hal_5416 *ahp = AH5416(ah); 1217 1218 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1219 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_ack_timeout(): " 1220 "bad ack timeout %u\n", us)); 1221 1222 ahp->ah_acktimeout = (uint32_t)-1; 1223 return (B_FALSE); 1224 } else { 1225 REG_RMW_FIELD(ah, AR_TIME_OUT, 1226 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); 1227 ahp->ah_acktimeout = us; 1228 return (B_TRUE); 1229 } 1230 } 1231 1232 static boolean_t 1233 ath9k_hw_set_cts_timeout(struct ath_hal *ah, uint32_t us) 1234 { 1235 struct ath_hal_5416 *ahp = AH5416(ah); 1236 1237 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1238 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_cts_timeout(): " 1239 "bad cts timeout %u\n", us)); 1240 1241 ahp->ah_ctstimeout = (uint32_t)-1; 1242 return (B_FALSE); 1243 } else { 1244 REG_RMW_FIELD(ah, AR_TIME_OUT, 1245 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1246 ahp->ah_ctstimeout = us; 1247 return (B_TRUE); 1248 } 1249 } 1250 1251 static boolean_t 1252 ath9k_hw_set_global_txtimeout(struct ath_hal *ah, uint32_t tu) 1253 { 1254 struct ath_hal_5416 *ahp = AH5416(ah); 1255 1256 if (tu > 0xFFFF) { 1257 ARN_DBG((ARN_DBG_XMIT, 1258 "arn: ath9k_hw_set_global_txtimeout(): " 1259 "ath9k_hw_set_global_txtimeout\n", tu)); 1260 1261 ahp->ah_globaltxtimeout = (uint32_t)-1; 1262 return (B_FALSE); 1263 } else { 1264 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1265 ahp->ah_globaltxtimeout = tu; 1266 return (B_TRUE); 1267 } 1268 } 1269 1270 static void 1271 ath9k_hw_init_user_settings(struct ath_hal *ah) 1272 { 1273 struct ath_hal_5416 *ahp = AH5416(ah); 1274 1275 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_init_user_settings(): " 1276 "--AP ahp->ah_miscMode 0x%x\n", ahp->ah_miscMode)); 1277 1278 if (ahp->ah_miscMode != 0) 1279 REG_WRITE(ah, AR_PCU_MISC, 1280 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); 1281 if (ahp->ah_slottime != (uint32_t)-1) 1282 (void) ath9k_hw_setslottime(ah, ahp->ah_slottime); 1283 if (ahp->ah_acktimeout != (uint32_t)-1) 1284 (void) ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); 1285 if (ahp->ah_ctstimeout != (uint32_t)-1) 1286 (void) ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); 1287 if (ahp->ah_globaltxtimeout != (uint32_t)-1) 1288 (void) ath9k_hw_set_global_txtimeout 1289 (ah, ahp->ah_globaltxtimeout); 1290 } 1291 1292 const char * 1293 ath9k_hw_probe(uint16_t vendorid, uint16_t devid) 1294 { 1295 return (vendorid == ATHEROS_VENDOR_ID ? 1296 ath9k_hw_devname(devid) : NULL); 1297 } 1298 1299 void 1300 ath9k_hw_detach(struct ath_hal *ah) 1301 { 1302 if (!AR_SREV_9100(ah)) 1303 ath9k_hw_ani_detach(ah); 1304 1305 ath9k_hw_rfdetach(ah); 1306 (void) ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1307 kmem_free(ah, sizeof (struct ath_hal_5416)); /* ???? */ 1308 } 1309 1310 struct ath_hal * 1311 ath9k_hw_attach(uint16_t device_id, struct arn_softc *sc, 1312 caddr_t mem, int *error) 1313 { 1314 struct ath_hal *ah = NULL; 1315 1316 switch (device_id) { 1317 case AR5416_DEVID_PCI: 1318 case AR5416_DEVID_PCIE: 1319 case AR9160_DEVID_PCI: 1320 case AR9280_DEVID_PCI: 1321 case AR9280_DEVID_PCIE: 1322 case AR9285_DEVID_PCIE: 1323 ah = ath9k_hw_do_attach(device_id, sc, mem, error); 1324 break; 1325 default: 1326 *error = ENXIO; 1327 break; 1328 } 1329 1330 return (ah); 1331 } 1332 1333 /* INI */ 1334 1335 /* ARGSUSED */ 1336 static void 1337 ath9k_hw_override_ini(struct ath_hal *ah, struct ath9k_channel *chan) 1338 { 1339 /* 1340 * Set the RX_ABORT and RX_DIS and clear if off only after 1341 * RXE is set for MAC. This prevents frames with corrupted 1342 * descriptor status. 1343 */ 1344 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 1345 1346 if (!AR_SREV_5416_V20_OR_LATER(ah) || 1347 AR_SREV_9280_10_OR_LATER(ah)) 1348 return; 1349 1350 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1351 } 1352 1353 static uint32_t 1354 ath9k_hw_def_ini_fixup(struct ath_hal *ah, 1355 struct ar5416_eeprom_def *pEepData, 1356 uint32_t reg, uint32_t value) 1357 { 1358 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1359 1360 switch (ah->ah_devid) { 1361 case AR9280_DEVID_PCI: 1362 if (reg == 0x7894) { 1363 ARN_DBG((ARN_DBG_ANY, 1364 "arn: ath9k_hw_ini_fixup(): " 1365 "ini VAL: %x EEPROM: %x\n", 1366 value, (pBase->version & 0xff))); 1367 1368 if ((pBase->version & 0xff) > 0x0a) { 1369 ARN_DBG((ARN_DBG_ANY, 1370 "arn: ath9k_hw_ini_fixup(): " 1371 "PWDCLKIND: %d\n", 1372 pBase->pwdclkind)); 1373 1374 value &= ~AR_AN_TOP2_PWDCLKIND; 1375 value |= AR_AN_TOP2_PWDCLKIND & 1376 (pBase->pwdclkind << 1377 AR_AN_TOP2_PWDCLKIND_S); 1378 } else { 1379 ARN_DBG((ARN_DBG_ANY, 1380 "arn: ath9k_hw_ini_fixup(): " 1381 "PWDCLKIND Earlier Rev\n")); 1382 } 1383 1384 ARN_DBG((ARN_DBG_ANY, 1385 "arn: ath9k_hw_ini_fixup(): " 1386 "final ini VAL: %x\n\n", value)); 1387 } 1388 break; 1389 } 1390 1391 return (value); 1392 } 1393 1394 static uint32_t 1395 ath9k_hw_ini_fixup(struct ath_hal *ah, struct ar5416_eeprom_def *pEepData, 1396 uint32_t reg, uint32_t value) 1397 { 1398 struct ath_hal_5416 *ahp = AH5416(ah); 1399 1400 if (ahp->ah_eep_map == EEP_MAP_4KBITS) 1401 return (value); 1402 else 1403 return (ath9k_hw_def_ini_fixup(ah, pEepData, reg, value)); 1404 } 1405 1406 static int 1407 ath9k_hw_process_ini(struct ath_hal *ah, 1408 struct ath9k_channel *chan, 1409 enum ath9k_ht_macmode macmode) 1410 { 1411 int i, regWrites = 0; 1412 struct ath_hal_5416 *ahp = AH5416(ah); 1413 uint32_t modesIndex, freqIndex; 1414 int status; 1415 1416 switch (chan->chanmode) { 1417 case CHANNEL_A: 1418 case CHANNEL_A_HT20: 1419 modesIndex = 1; 1420 freqIndex = 1; 1421 break; 1422 case CHANNEL_A_HT40PLUS: 1423 case CHANNEL_A_HT40MINUS: 1424 modesIndex = 2; 1425 freqIndex = 1; 1426 break; 1427 case CHANNEL_G: 1428 case CHANNEL_G_HT20: 1429 case CHANNEL_B: 1430 modesIndex = 4; 1431 freqIndex = 2; 1432 break; 1433 case CHANNEL_G_HT40PLUS: 1434 case CHANNEL_G_HT40MINUS: 1435 modesIndex = 3; 1436 freqIndex = 2; 1437 break; 1438 1439 default: 1440 ARN_DBG((ARN_DBG_CHANNEL, "arn: " 1441 "%s: err: unknow chan->chanmode\n", __func__)); 1442 return (EINVAL); 1443 } 1444 1445 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1446 1447 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1448 1449 ath9k_hw_set_addac(ah, chan); 1450 1451 if (AR_SREV_5416_V22_OR_LATER(ah)) { 1452 /* LINTED: E_CONSTANT_CONDITION */ 1453 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); 1454 } else { 1455 struct ar5416IniArray temp; 1456 uint32_t addacSize = 1457 sizeof (uint32_t) * ahp->ah_iniAddac.ia_rows * 1458 ahp->ah_iniAddac.ia_columns; 1459 1460 (void) memcpy(ahp->ah_addac5416_21, 1461 ahp->ah_iniAddac.ia_array, addacSize); 1462 1463 (ahp->ah_addac5416_21) 1464 [31 * ahp->ah_iniAddac.ia_columns + 1] = 0; 1465 1466 temp.ia_array = ahp->ah_addac5416_21; 1467 temp.ia_columns = ahp->ah_iniAddac.ia_columns; 1468 temp.ia_rows = ahp->ah_iniAddac.ia_rows; 1469 /* LINTED: E_CONSTANT_CONDITION */ 1470 REG_WRITE_ARRAY(&temp, 1, regWrites); 1471 } 1472 1473 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1474 1475 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 1476 uint32_t reg = INI_RA(&ahp->ah_iniModes, i, 0); 1477 uint32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex); 1478 1479 REG_WRITE(ah, reg, val); 1480 1481 if (reg >= 0x7800 && reg < 0x78a0 && 1482 ah->ah_config.analog_shiftreg) { 1483 drv_usecwait(100); 1484 } 1485 1486 /* LINTED: E_CONSTANT_CONDITION */ 1487 DO_DELAY(regWrites); 1488 } 1489 1490 if (AR_SREV_9280(ah)) { 1491 /* LINTED: E_CONSTANT_CONDITION */ 1492 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, 1493 regWrites); 1494 } 1495 1496 if (AR_SREV_9280(ah)) { 1497 /* LINTED: E_CONSTANT_CONDITION */ 1498 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, 1499 regWrites); 1500 } 1501 1502 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { 1503 uint32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0); 1504 uint32_t val = INI_RA(&ahp->ah_iniCommon, i, 1); 1505 1506 REG_WRITE(ah, reg, val); 1507 1508 if (reg >= 0x7800 && reg < 0x78a0 && 1509 ah->ah_config.analog_shiftreg) { 1510 drv_usecwait(100); 1511 } 1512 1513 /* LINTED: E_CONSTANT_CONDITION */ 1514 DO_DELAY(regWrites); 1515 } 1516 1517 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1518 1519 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1520 /* LINTED: E_CONSTANT_CONDITION */ 1521 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, 1522 regWrites); 1523 } 1524 1525 ath9k_hw_override_ini(ah, chan); 1526 ath9k_hw_set_regs(ah, chan, macmode); 1527 ath9k_hw_init_chain_masks(ah); 1528 1529 status = ath9k_hw_set_txpower(ah, chan, 1530 ath9k_regd_get_ctl(ah, chan), 1531 ath9k_regd_get_antenna_allowed(ah, chan), 1532 chan->maxRegTxPower * 2, 1533 min((uint32_t)MAX_RATE_POWER, 1534 (uint32_t)ah->ah_powerLimit)); 1535 if (status != 0) { 1536 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_process_ini(): " 1537 "%s: error init'ing transmit power\n", __func__)); 1538 1539 return (EIO); 1540 } 1541 1542 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1543 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_process_ini(): " 1544 "%s: ar5416SetRfRegs failed\n", __func__)); 1545 1546 return (EIO); 1547 } 1548 1549 return (0); 1550 } 1551 1552 /* Reset and Channel Switching Routines */ 1553 1554 static void 1555 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) 1556 { 1557 uint32_t rfMode = 0; 1558 1559 if (chan == NULL) 1560 return; 1561 1562 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 1563 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1564 1565 if (!AR_SREV_9280_10_OR_LATER(ah)) 1566 rfMode |= (IS_CHAN_5GHZ(chan)) ? 1567 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 1568 1569 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) 1570 rfMode |= (AR_PHY_MODE_DYNAMIC | 1571 AR_PHY_MODE_DYN_CCK_DISABLE); 1572 1573 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1574 } 1575 1576 static void 1577 ath9k_hw_mark_phy_inactive(struct ath_hal *ah) 1578 { 1579 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1580 } 1581 1582 static inline void 1583 ath9k_hw_set_dma(struct ath_hal *ah) 1584 { 1585 uint32_t regval; 1586 1587 regval = REG_READ(ah, AR_AHB_MODE); 1588 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 1589 1590 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 1591 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 1592 1593 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); 1594 1595 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 1596 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 1597 1598 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1599 1600 if (AR_SREV_9285(ah)) { 1601 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1602 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1603 } else { 1604 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1605 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1606 } 1607 } 1608 1609 static void 1610 ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) 1611 { 1612 uint32_t val; 1613 1614 val = REG_READ(ah, AR_STA_ID1); 1615 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 1616 switch (opmode) { 1617 case ATH9K_M_HOSTAP: 1618 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP | 1619 AR_STA_ID1_KSRCH_MODE); 1620 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1621 break; 1622 case ATH9K_M_IBSS: 1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC | 1624 AR_STA_ID1_KSRCH_MODE); 1625 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1626 break; 1627 case ATH9K_M_STA: 1628 case ATH9K_M_MONITOR: 1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 1630 break; 1631 } 1632 } 1633 1634 /* ARGSUSED */ 1635 static inline void 1636 ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, 1637 uint32_t coef_scaled, 1638 uint32_t *coef_mantissa, 1639 uint32_t *coef_exponent) 1640 { 1641 uint32_t coef_exp, coef_man; 1642 1643 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1644 if ((coef_scaled >> coef_exp) & 0x1) 1645 break; 1646 1647 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1648 1649 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1650 1651 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1652 *coef_exponent = coef_exp - 16; 1653 } 1654 1655 static void 1656 ath9k_hw_set_delta_slope(struct ath_hal *ah, 1657 struct ath9k_channel *chan) 1658 { 1659 uint32_t coef_scaled, ds_coef_exp, ds_coef_man; 1660 uint32_t clockMhzScaled = 0x64000000; 1661 struct chan_centers centers; 1662 1663 if (IS_CHAN_HALF_RATE(chan)) 1664 clockMhzScaled = clockMhzScaled >> 1; 1665 else if (IS_CHAN_QUARTER_RATE(chan)) 1666 clockMhzScaled = clockMhzScaled >> 2; 1667 1668 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1669 coef_scaled = clockMhzScaled / centers.synth_center; 1670 1671 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1672 &ds_coef_exp); 1673 1674 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1675 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1676 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1677 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1678 1679 coef_scaled = (9 * coef_scaled) / 10; 1680 1681 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1682 &ds_coef_exp); 1683 1684 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1685 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 1686 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1687 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1688 } 1689 1690 static boolean_t 1691 ath9k_hw_set_reset(struct ath_hal *ah, int type) 1692 { 1693 uint32_t rst_flags; 1694 uint32_t tmpReg; 1695 1696 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1697 AR_RTC_FORCE_WAKE_ON_INT); 1698 1699 if (AR_SREV_9100(ah)) { 1700 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1701 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1702 } else { 1703 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1704 if (tmpReg & 1705 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1706 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1707 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1708 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1709 } else { 1710 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1711 } 1712 1713 rst_flags = AR_RTC_RC_MAC_WARM; 1714 if (type == ATH9K_RESET_COLD) 1715 rst_flags |= AR_RTC_RC_MAC_COLD; 1716 } 1717 1718 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), rst_flags); 1719 drv_usecwait(50); 1720 1721 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), 0); 1722 if (!ath9k_hw_wait(ah, (uint16_t)(AR_RTC_RC), AR_RTC_RC_M, 0)) { 1723 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_reset(): " 1724 "RTC stuck in MAC reset\n")); 1725 1726 return (B_FALSE); 1727 } 1728 1729 if (!AR_SREV_9100(ah)) 1730 REG_WRITE(ah, AR_RC, 0); 1731 1732 ath9k_hw_init_pll(ah, NULL); 1733 1734 if (AR_SREV_9100(ah)) 1735 drv_usecwait(50); 1736 1737 return (B_TRUE); 1738 } 1739 1740 static boolean_t 1741 ath9k_hw_set_reset_power_on(struct ath_hal *ah) 1742 { 1743 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1744 AR_RTC_FORCE_WAKE_ON_INT); 1745 1746 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 0); 1747 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 1); 1748 1749 if (!ath9k_hw_wait(ah, 1750 AR_RTC_STATUS, 1751 AR_RTC_STATUS_M, 1752 AR_RTC_STATUS_ON)) { 1753 ARN_DBG((ARN_DBG_HW, 1754 "arn: ath9k_hw_set_reset_power_on(): " 1755 "RTC not waking up \n")); 1756 1757 return (B_FALSE); 1758 } 1759 1760 ath9k_hw_read_revisions(ah); 1761 1762 return (ath9k_hw_set_reset(ah, ATH9K_RESET_WARM)); 1763 } 1764 1765 static boolean_t 1766 ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type) 1767 { 1768 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1769 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1770 1771 switch (type) { 1772 case ATH9K_RESET_POWER_ON: 1773 return (ath9k_hw_set_reset_power_on(ah)); 1774 case ATH9K_RESET_WARM: 1775 case ATH9K_RESET_COLD: 1776 return (ath9k_hw_set_reset(ah, type)); 1777 default: 1778 return (B_FALSE); 1779 } 1780 } 1781 1782 static void 1783 ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 1784 enum ath9k_ht_macmode macmode) 1785 { 1786 uint32_t phymode; 1787 uint32_t enableDacFifo = 0; 1788 struct ath_hal_5416 *ahp = AH5416(ah); 1789 1790 if (AR_SREV_9285_10_OR_LATER(ah)) 1791 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1792 AR_PHY_FC_ENABLE_DAC_FIFO); 1793 1794 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 | 1795 AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 1796 1797 if (IS_CHAN_HT40(chan)) { 1798 phymode |= AR_PHY_FC_DYN2040_EN; 1799 1800 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 1801 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1802 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1803 1804 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) 1805 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 1806 } 1807 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1808 1809 ath9k_hw_set11nmac2040(ah, macmode); 1810 1811 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 1812 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1813 } 1814 1815 static boolean_t 1816 ath9k_hw_chip_reset(struct ath_hal *ah, 1817 struct ath9k_channel *chan) 1818 { 1819 struct ath_hal_5416 *ahp = AH5416(ah); 1820 1821 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1822 return (B_FALSE); 1823 1824 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1825 return (B_FALSE); 1826 1827 ahp->ah_chipFullSleep = B_FALSE; 1828 1829 ath9k_hw_init_pll(ah, chan); 1830 1831 ath9k_hw_set_rfmode(ah, chan); 1832 1833 return (B_TRUE); 1834 } 1835 1836 static struct ath9k_channel * 1837 ath9k_hw_check_chan(struct ath_hal *ah, struct ath9k_channel *chan) 1838 { 1839 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) { 1840 ARN_DBG((ARN_DBG_CHANNEL, "arn: " 1841 "%s: invalid channel %u/0x%x; not marked as " 1842 "2GHz or 5GHz\n", 1843 __func__, chan->channel, chan->channelFlags)); 1844 return (NULL); 1845 } 1846 1847 if (!IS_CHAN_OFDM(chan) && 1848 !IS_CHAN_B(chan) && 1849 !IS_CHAN_HT20(chan) && 1850 !IS_CHAN_HT40(chan)) { 1851 ARN_DBG((ARN_DBG_CHANNEL, "arn: " 1852 "%s: invalid channel %u/0x%x; not marked as " 1853 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", 1854 __func__, chan->channel, chan->channelFlags)); 1855 1856 return (NULL); 1857 } 1858 1859 return (ath9k_regd_check_channel(ah, chan)); 1860 } 1861 1862 static boolean_t 1863 ath9k_hw_channel_change(struct ath_hal *ah, 1864 struct ath9k_channel *chan, 1865 enum ath9k_ht_macmode macmode) 1866 { 1867 uint32_t synthDelay, qnum; 1868 1869 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1870 if (ath9k_hw_numtxpending(ah, qnum)) { 1871 ARN_DBG((ARN_DBG_QUEUE, "arn: " 1872 "%s: Transmit frames pending on queue %d\n", 1873 __func__, qnum)); 1874 1875 return (B_FALSE); 1876 } 1877 } 1878 1879 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1880 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1881 AR_PHY_RFBUS_GRANT_EN)) { 1882 ARN_DBG((ARN_DBG_HW, "arn: " 1883 "%s: Could not kill baseband RX\n", __func__)); 1884 1885 return (B_FALSE); 1886 } 1887 1888 ath9k_hw_set_regs(ah, chan, macmode); 1889 1890 if (AR_SREV_9280_10_OR_LATER(ah)) { 1891 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 1892 ARN_DBG((ARN_DBG_CHANNEL, "arn: " 1893 "%s: failed to set channel\n", __func__)); 1894 return (B_FALSE); 1895 } 1896 } else { 1897 if (!(ath9k_hw_set_channel(ah, chan))) { 1898 ARN_DBG((ARN_DBG_CHANNEL, "arn: " 1899 "%s: failed to set channel\n", __func__)); 1900 1901 return (B_FALSE); 1902 } 1903 } 1904 1905 if (ath9k_hw_set_txpower(ah, chan, 1906 ath9k_regd_get_ctl(ah, chan), 1907 ath9k_regd_get_antenna_allowed(ah, chan), 1908 chan->maxRegTxPower * 2, 1909 min((uint32_t)MAX_RATE_POWER, 1910 (uint32_t)ah->ah_powerLimit)) != 0) { 1911 ARN_DBG((ARN_DBG_EEPROM, "arn: " 1912 "%s: error init'ing transmit power\n", __func__)); 1913 1914 return (B_FALSE); 1915 } 1916 1917 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1918 if (IS_CHAN_B(chan)) 1919 synthDelay = (4 * synthDelay) / 22; 1920 else 1921 synthDelay /= 10; 1922 1923 drv_usecwait(synthDelay + BASE_ACTIVATE_DELAY); 1924 1925 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 1926 1927 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1928 ath9k_hw_set_delta_slope(ah, chan); 1929 1930 if (AR_SREV_9280_10_OR_LATER(ah)) 1931 ath9k_hw_9280_spur_mitigate(ah, chan); 1932 else 1933 ath9k_hw_spur_mitigate(ah, chan); 1934 1935 if (!chan->oneTimeCalsDone) 1936 chan->oneTimeCalsDone = B_TRUE; 1937 1938 return (B_TRUE); 1939 } 1940 1941 static void 1942 ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1943 { 1944 int bb_spur = AR_NO_SPUR; 1945 int freq; 1946 int bin, cur_bin; 1947 int bb_spur_off, spur_subchannel_sd; 1948 int spur_freq_sd; 1949 int spur_delta_phase; 1950 int denominator; 1951 int upper, lower, cur_vit_mask; 1952 int tmp, newVal; 1953 int i; 1954 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 1955 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 1956 }; 1957 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 1958 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 1959 }; 1960 int inc[4] = { 0, 100, 0, 0 }; 1961 struct chan_centers centers; 1962 1963 int8_t mask_m[123]; 1964 int8_t mask_p[123]; 1965 int8_t mask_amt; 1966 int tmp_mask; 1967 int cur_bb_spur; 1968 boolean_t is2GHz = IS_CHAN_2GHZ(chan); 1969 1970 (void) memset(&mask_m, 0, sizeof (int8_t) * 123); 1971 (void) memset(&mask_p, 0, sizeof (int8_t) * 123); 1972 1973 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1974 freq = centers.synth_center; 1975 1976 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; 1977 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1978 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); 1979 1980 if (is2GHz) 1981 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 1982 else 1983 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 1984 1985 if (AR_NO_SPUR == cur_bb_spur) 1986 break; 1987 cur_bb_spur = cur_bb_spur - freq; 1988 1989 if (IS_CHAN_HT40(chan)) { 1990 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 1991 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 1992 bb_spur = cur_bb_spur; 1993 break; 1994 } 1995 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 1996 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 1997 bb_spur = cur_bb_spur; 1998 break; 1999 } 2000 } 2001 2002 if (AR_NO_SPUR == bb_spur) { 2003 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, 2004 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 2005 return; 2006 } else { 2007 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, 2008 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 2009 } 2010 2011 bin = bb_spur * 320; 2012 2013 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 2014 2015 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 2016 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 2017 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 2018 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 2019 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); 2020 2021 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 2022 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 2023 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 2024 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 2025 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 2026 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 2027 2028 if (IS_CHAN_HT40(chan)) { 2029 if (bb_spur < 0) { 2030 spur_subchannel_sd = 1; 2031 bb_spur_off = bb_spur + 10; 2032 } else { 2033 spur_subchannel_sd = 0; 2034 bb_spur_off = bb_spur - 10; 2035 } 2036 } else { 2037 spur_subchannel_sd = 0; 2038 bb_spur_off = bb_spur; 2039 } 2040 2041 if (IS_CHAN_HT40(chan)) 2042 spur_delta_phase = 2043 ((bb_spur * 262144) / 10) & 2044 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 2045 else 2046 spur_delta_phase = 2047 ((bb_spur * 524288) / 10) & 2048 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 2049 2050 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; 2051 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 2052 2053 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 2054 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 2055 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 2056 REG_WRITE(ah, AR_PHY_TIMING11, newVal); 2057 2058 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 2059 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 2060 2061 cur_bin = -6000; 2062 upper = bin + 100; 2063 lower = bin - 100; 2064 2065 for (i = 0; i < 4; i++) { 2066 int pilot_mask = 0; 2067 int chan_mask = 0; 2068 int bp = 0; 2069 for (bp = 0; bp < 30; bp++) { 2070 if ((cur_bin > lower) && (cur_bin < upper)) { 2071 pilot_mask = pilot_mask | 0x1 << bp; 2072 chan_mask = chan_mask | 0x1 << bp; 2073 } 2074 cur_bin += 100; 2075 } 2076 cur_bin += inc[i]; 2077 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 2078 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 2079 } 2080 2081 cur_vit_mask = 6100; 2082 upper = bin + 120; 2083 lower = bin - 120; 2084 2085 for (i = 0; i < 123; i++) { 2086 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 2087 2088 /* workaround for gcc bug #37014 */ 2089 volatile int tmp = abs(cur_vit_mask - bin); 2090 2091 if (tmp < 75) 2092 mask_amt = 1; 2093 else 2094 mask_amt = 0; 2095 if (cur_vit_mask < 0) 2096 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 2097 else 2098 mask_p[cur_vit_mask / 100] = mask_amt; 2099 } 2100 cur_vit_mask -= 100; 2101 } 2102 2103 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | 2104 (mask_m[48] << 26) | (mask_m[49] << 24) | 2105 (mask_m[50] << 22) | (mask_m[51] << 20) | 2106 (mask_m[52] << 18) | (mask_m[53] << 16) | 2107 (mask_m[54] << 14) | (mask_m[55] << 12) | 2108 (mask_m[56] << 10) | (mask_m[57] << 8) | 2109 (mask_m[58] << 6) | (mask_m[59] << 4) | 2110 (mask_m[60] << 2) | (mask_m[61] << 0); 2111 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 2112 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 2113 2114 tmp_mask = (mask_m[31] << 28) | 2115 (mask_m[32] << 26) | (mask_m[33] << 24) | 2116 (mask_m[34] << 22) | (mask_m[35] << 20) | 2117 (mask_m[36] << 18) | (mask_m[37] << 16) | 2118 (mask_m[48] << 14) | (mask_m[39] << 12) | 2119 (mask_m[40] << 10) | (mask_m[41] << 8) | 2120 (mask_m[42] << 6) | (mask_m[43] << 4) | 2121 (mask_m[44] << 2) | (mask_m[45] << 0); 2122 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 2123 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 2124 2125 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | 2126 (mask_m[18] << 26) | (mask_m[18] << 24) | 2127 (mask_m[20] << 22) | (mask_m[20] << 20) | 2128 (mask_m[22] << 18) | (mask_m[22] << 16) | 2129 (mask_m[24] << 14) | (mask_m[24] << 12) | 2130 (mask_m[25] << 10) | (mask_m[26] << 8) | 2131 (mask_m[27] << 6) | (mask_m[28] << 4) | 2132 (mask_m[29] << 2) | (mask_m[30] << 0); 2133 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 2134 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 2135 2136 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | 2137 (mask_m[2] << 26) | (mask_m[3] << 24) | 2138 (mask_m[4] << 22) | (mask_m[5] << 20) | 2139 (mask_m[6] << 18) | (mask_m[7] << 16) | 2140 (mask_m[8] << 14) | (mask_m[9] << 12) | 2141 (mask_m[10] << 10) | (mask_m[11] << 8) | 2142 (mask_m[12] << 6) | (mask_m[13] << 4) | 2143 (mask_m[14] << 2) | (mask_m[15] << 0); 2144 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 2145 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 2146 2147 tmp_mask = (mask_p[15] << 28) | 2148 (mask_p[14] << 26) | (mask_p[13] << 24) | 2149 (mask_p[12] << 22) | (mask_p[11] << 20) | 2150 (mask_p[10] << 18) | (mask_p[9] << 16) | 2151 (mask_p[8] << 14) | (mask_p[7] << 12) | 2152 (mask_p[6] << 10) | (mask_p[5] << 8) | 2153 (mask_p[4] << 6) | (mask_p[3] << 4) | 2154 (mask_p[2] << 2) | (mask_p[1] << 0); 2155 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 2156 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 2157 2158 tmp_mask = (mask_p[30] << 28) | 2159 (mask_p[29] << 26) | (mask_p[28] << 24) | 2160 (mask_p[27] << 22) | (mask_p[26] << 20) | 2161 (mask_p[25] << 18) | (mask_p[24] << 16) | 2162 (mask_p[23] << 14) | (mask_p[22] << 12) | 2163 (mask_p[21] << 10) | (mask_p[20] << 8) | 2164 (mask_p[19] << 6) | (mask_p[18] << 4) | 2165 (mask_p[17] << 2) | (mask_p[16] << 0); 2166 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 2167 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 2168 2169 tmp_mask = (mask_p[45] << 28) | 2170 (mask_p[44] << 26) | (mask_p[43] << 24) | 2171 (mask_p[42] << 22) | (mask_p[41] << 20) | 2172 (mask_p[40] << 18) | (mask_p[39] << 16) | 2173 (mask_p[38] << 14) | (mask_p[37] << 12) | 2174 (mask_p[36] << 10) | (mask_p[35] << 8) | 2175 (mask_p[34] << 6) | (mask_p[33] << 4) | 2176 (mask_p[32] << 2) | (mask_p[31] << 0); 2177 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 2178 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 2179 2180 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) | 2181 (mask_p[59] << 26) | (mask_p[58] << 24) | 2182 (mask_p[57] << 22) | (mask_p[56] << 20) | 2183 (mask_p[55] << 18) | (mask_p[54] << 16) | 2184 (mask_p[53] << 14) | (mask_p[52] << 12) | 2185 (mask_p[51] << 10) | (mask_p[50] << 8) | 2186 (mask_p[49] << 6) | (mask_p[48] << 4) | 2187 (mask_p[47] << 2) | (mask_p[46] << 0); 2188 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 2189 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2190 } 2191 2192 static void 2193 ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 2194 { 2195 int bb_spur = AR_NO_SPUR; 2196 int bin, cur_bin; 2197 int spur_freq_sd; 2198 int spur_delta_phase; 2199 int denominator; 2200 int upper, lower, cur_vit_mask; 2201 int tmp, new; 2202 int i; 2203 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 2204 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 2205 }; 2206 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 2207 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 2208 }; 2209 int inc[4] = { 0, 100, 0, 0 }; 2210 2211 int8_t mask_m[123]; 2212 int8_t mask_p[123]; 2213 int8_t mask_amt; 2214 int tmp_mask; 2215 int cur_bb_spur; 2216 boolean_t is2GHz = IS_CHAN_2GHZ(chan); 2217 2218 (void) memset(&mask_m, 0, sizeof (int8_t) * 123); 2219 (void) memset(&mask_p, 0, sizeof (int8_t) * 123); 2220 2221 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 2222 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); 2223 if (AR_NO_SPUR == cur_bb_spur) 2224 break; 2225 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 2226 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 2227 bb_spur = cur_bb_spur; 2228 break; 2229 } 2230 } 2231 2232 if (AR_NO_SPUR == bb_spur) 2233 return; 2234 2235 bin = bb_spur * 32; 2236 2237 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 2238 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 2239 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 2240 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 2241 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 2242 2243 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 2244 2245 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 2246 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 2247 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 2248 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 2249 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 2250 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 2251 2252 spur_delta_phase = ((bb_spur * 524288) / 100) & 2253 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 2254 2255 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 2256 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 2257 2258 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 2259 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 2260 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 2261 REG_WRITE(ah, AR_PHY_TIMING11, new); 2262 2263 cur_bin = -6000; 2264 upper = bin + 100; 2265 lower = bin - 100; 2266 2267 for (i = 0; i < 4; i++) { 2268 int pilot_mask = 0; 2269 int chan_mask = 0; 2270 int bp = 0; 2271 for (bp = 0; bp < 30; bp++) { 2272 if ((cur_bin > lower) && (cur_bin < upper)) { 2273 pilot_mask = pilot_mask | 0x1 << bp; 2274 chan_mask = chan_mask | 0x1 << bp; 2275 } 2276 cur_bin += 100; 2277 } 2278 cur_bin += inc[i]; 2279 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 2280 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 2281 } 2282 2283 cur_vit_mask = 6100; 2284 upper = bin + 120; 2285 lower = bin - 120; 2286 2287 for (i = 0; i < 123; i++) { 2288 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 2289 2290 /* workaround for gcc bug #37014 */ 2291 volatile int tmp = abs(cur_vit_mask - bin); 2292 2293 if (tmp < 75) 2294 mask_amt = 1; 2295 else 2296 mask_amt = 0; 2297 if (cur_vit_mask < 0) 2298 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 2299 else 2300 mask_p[cur_vit_mask / 100] = mask_amt; 2301 } 2302 cur_vit_mask -= 100; 2303 } 2304 2305 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) | 2306 (mask_m[48] << 26) | (mask_m[49] << 24) | 2307 (mask_m[50] << 22) | (mask_m[51] << 20) | 2308 (mask_m[52] << 18) | (mask_m[53] << 16) | 2309 (mask_m[54] << 14) | (mask_m[55] << 12) | 2310 (mask_m[56] << 10) | (mask_m[57] << 8) | 2311 (mask_m[58] << 6) | (mask_m[59] << 4) | 2312 (mask_m[60] << 2) | (mask_m[61] << 0); 2313 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 2314 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 2315 2316 tmp_mask = (mask_m[31] << 28) | 2317 (mask_m[32] << 26) | (mask_m[33] << 24) | 2318 (mask_m[34] << 22) | (mask_m[35] << 20) | 2319 (mask_m[36] << 18) | (mask_m[37] << 16) | 2320 (mask_m[48] << 14) | (mask_m[39] << 12) | 2321 (mask_m[40] << 10) | (mask_m[41] << 8) | 2322 (mask_m[42] << 6) | (mask_m[43] << 4) | 2323 (mask_m[44] << 2) | (mask_m[45] << 0); 2324 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 2325 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 2326 2327 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) | 2328 (mask_m[18] << 26) | (mask_m[18] << 24) | 2329 (mask_m[20] << 22) | (mask_m[20] << 20) | 2330 (mask_m[22] << 18) | (mask_m[22] << 16) | 2331 (mask_m[24] << 14) | (mask_m[24] << 12) | 2332 (mask_m[25] << 10) | (mask_m[26] << 8) | 2333 (mask_m[27] << 6) | (mask_m[28] << 4) | 2334 (mask_m[29] << 2) | (mask_m[30] << 0); 2335 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 2336 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 2337 2338 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) | 2339 (mask_m[2] << 26) | (mask_m[3] << 24) | 2340 (mask_m[4] << 22) | (mask_m[5] << 20) | 2341 (mask_m[6] << 18) | (mask_m[7] << 16) | 2342 (mask_m[8] << 14) | (mask_m[9] << 12) | 2343 (mask_m[10] << 10) | (mask_m[11] << 8) | 2344 (mask_m[12] << 6) | (mask_m[13] << 4) | 2345 (mask_m[14] << 2) | (mask_m[15] << 0); 2346 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 2347 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 2348 2349 tmp_mask = (mask_p[15] << 28) | 2350 (mask_p[14] << 26) | (mask_p[13] << 24) | 2351 (mask_p[12] << 22) | (mask_p[11] << 20) | 2352 (mask_p[10] << 18) | (mask_p[9] << 16) | 2353 (mask_p[8] << 14) | (mask_p[7] << 12) | 2354 (mask_p[6] << 10) | (mask_p[5] << 8) | 2355 (mask_p[4] << 6) | (mask_p[3] << 4) | 2356 (mask_p[2] << 2) | (mask_p[1] << 0); 2357 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 2358 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 2359 2360 tmp_mask = (mask_p[30] << 28) | 2361 (mask_p[29] << 26) | (mask_p[28] << 24) | 2362 (mask_p[27] << 22) | (mask_p[26] << 20) | 2363 (mask_p[25] << 18) | (mask_p[24] << 16) | 2364 (mask_p[23] << 14) | (mask_p[22] << 12) | 2365 (mask_p[21] << 10) | (mask_p[20] << 8) | 2366 (mask_p[19] << 6) | (mask_p[18] << 4) | 2367 (mask_p[17] << 2) | (mask_p[16] << 0); 2368 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 2369 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 2370 2371 tmp_mask = (mask_p[45] << 28) | 2372 (mask_p[44] << 26) | (mask_p[43] << 24) | 2373 (mask_p[42] << 22) | (mask_p[41] << 20) | 2374 (mask_p[40] << 18) | (mask_p[39] << 16) | 2375 (mask_p[38] << 14) | (mask_p[37] << 12) | 2376 (mask_p[36] << 10) | (mask_p[35] << 8) | 2377 (mask_p[34] << 6) | (mask_p[33] << 4) | 2378 (mask_p[32] << 2) | (mask_p[31] << 0); 2379 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 2380 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 2381 2382 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) | 2383 (mask_p[59] << 26) | (mask_p[58] << 24) | 2384 (mask_p[57] << 22) | (mask_p[56] << 20) | 2385 (mask_p[55] << 18) | (mask_p[54] << 16) | 2386 (mask_p[53] << 14) | (mask_p[52] << 12) | 2387 (mask_p[51] << 10) | (mask_p[50] << 8) | 2388 (mask_p[49] << 6) | (mask_p[48] << 4) | 2389 (mask_p[47] << 2) | (mask_p[46] << 0); 2390 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 2391 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2392 } 2393 2394 boolean_t 2395 ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 2396 enum ath9k_ht_macmode macmode, 2397 uint8_t txchainmask, uint8_t rxchainmask, 2398 enum ath9k_ht_extprotspacing extprotspacing, 2399 boolean_t bChannelChange, int *status) 2400 { 2401 uint32_t saveLedState; 2402 struct ath_hal_5416 *ahp = AH5416(ah); 2403 struct ath9k_channel *curchan = ah->ah_curchan; 2404 uint32_t saveDefAntenna; 2405 uint32_t macStaId1; 2406 int ecode; 2407 int i, rx_chainmask; 2408 2409 ahp->ah_extprotspacing = extprotspacing; 2410 ahp->ah_txchainmask = txchainmask; 2411 ahp->ah_rxchainmask = rxchainmask; 2412 2413 if (AR_SREV_9280(ah)) { 2414 ahp->ah_txchainmask &= 0x3; 2415 ahp->ah_rxchainmask &= 0x3; 2416 } 2417 2418 if (ath9k_hw_check_chan(ah, chan) == NULL) { 2419 ARN_DBG((ARN_DBG_ANY, "arn: " 2420 "%s: invalid channel %u/0x%x; no mapping\n", 2421 __func__, chan->channel, chan->channelFlags)); 2422 ecode = EINVAL; 2423 goto bad; 2424 } 2425 2426 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 2427 ARN_DBG((ARN_DBG_ANY, "arn: " 2428 "%s: ath9k_hw_setpower failed!!!\n", __func__)); 2429 ecode = EIO; 2430 goto bad; 2431 } 2432 2433 if (curchan) 2434 (void) ath9k_hw_getnf(ah, curchan); 2435 2436 if (bChannelChange && 2437 (ahp->ah_chipFullSleep != B_TRUE) && 2438 (ah->ah_curchan != NULL) && 2439 (chan->channel != ah->ah_curchan->channel) && 2440 ((chan->channelFlags & CHANNEL_ALL) == 2441 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && 2442 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && 2443 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { 2444 2445 if (ath9k_hw_channel_change(ah, chan, macmode)) { 2446 ath9k_hw_loadnf(ah, ah->ah_curchan); 2447 ath9k_hw_start_nfcal(ah); 2448 return (B_TRUE); 2449 } 2450 } 2451 2452 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 2453 if (saveDefAntenna == 0) 2454 saveDefAntenna = 1; 2455 2456 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2457 2458 saveLedState = REG_READ(ah, AR_CFG_LED) & 2459 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 2460 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 2461 2462 ath9k_hw_mark_phy_inactive(ah); 2463 2464 if (!ath9k_hw_chip_reset(ah, chan)) { 2465 ARN_DBG((ARN_DBG_RESET, "arn: " 2466 "%s: chip reset failed\n", __func__)); 2467 ecode = EINVAL; 2468 goto bad; 2469 } 2470 2471 if (AR_SREV_9280(ah)) { 2472 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 2473 AR_GPIO_JTAG_DISABLE); 2474 if (is_set(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) { 2475 if (IS_CHAN_5GHZ(chan)) 2476 ath9k_hw_set_gpio(ah, 9, 0); 2477 else 2478 ath9k_hw_set_gpio(ah, 9, 1); 2479 } 2480 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 2481 } 2482 2483 ecode = ath9k_hw_process_ini(ah, chan, macmode); 2484 if (ecode != 0) { 2485 ecode = EINVAL; 2486 goto bad; 2487 } 2488 2489 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2490 ath9k_hw_set_delta_slope(ah, chan); 2491 2492 if (AR_SREV_9280_10_OR_LATER(ah)) 2493 ath9k_hw_9280_spur_mitigate(ah, chan); 2494 else 2495 ath9k_hw_spur_mitigate(ah, chan); 2496 2497 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { 2498 ARN_DBG((ARN_DBG_EEPROM, "arn: " 2499 "%s: error setting board options\n", __func__)); 2500 ecode = EIO; 2501 goto bad; 2502 } 2503 2504 ath9k_hw_decrease_chain_power(ah, chan); 2505 2506 REG_WRITE(ah, AR_STA_ID0, ARN_LE_READ_32(ahp->ah_macaddr)); 2507 REG_WRITE(ah, AR_STA_ID1, ARN_LE_READ_16(ahp->ah_macaddr + 4) | 2508 macStaId1 | 2509 AR_STA_ID1_RTS_USE_DEF | 2510 (ah->ah_config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) | 2511 ahp->ah_staId1Defaults); 2512 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 2513 2514 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask)); 2515 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4)); 2516 2517 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2518 2519 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid)); 2520 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) | 2521 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S)); 2522 2523 REG_WRITE(ah, AR_ISR, ~0); 2524 2525 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2526 2527 if (AR_SREV_9280_10_OR_LATER(ah)) { 2528 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 2529 ARN_DBG((ARN_DBG_FATAL, "arn: " 2530 "%s: ath9k_hw_ar9280_set_channel failed!!!\n", 2531 __func__)); 2532 ecode = EIO; 2533 goto bad; 2534 } 2535 } else { 2536 if (!(ath9k_hw_set_channel(ah, chan))) { 2537 ARN_DBG((ARN_DBG_FATAL, "arn: " 2538 "%s: ath9k_hw_set_channel failed!!!\n", __func__)); 2539 ecode = EIO; 2540 goto bad; 2541 } 2542 } 2543 2544 for (i = 0; i < AR_NUM_DCU; i++) 2545 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2546 2547 ahp->ah_intrTxqs = 0; 2548 for (i = 0; i < ah->ah_caps.total_queues; i++) 2549 (void) ath9k_hw_resettxqueue(ah, i); 2550 2551 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); 2552 ath9k_hw_init_qos(ah); 2553 2554 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2555 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2556 ath9k_enable_rfkill(ah); 2557 #endif 2558 ath9k_hw_init_user_settings(ah); 2559 2560 REG_WRITE(ah, AR_STA_ID1, 2561 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 2562 2563 ath9k_hw_set_dma(ah); 2564 2565 REG_WRITE(ah, AR_OBS, 8); 2566 2567 if (ahp->ah_intrMitigation) { 2568 2569 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2570 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2571 } 2572 2573 ath9k_hw_init_bb(ah, chan); 2574 2575 if (!ath9k_hw_init_cal(ah, chan)) { 2576 ecode = EIO; 2577 goto bad; 2578 } 2579 2580 rx_chainmask = ahp->ah_rxchainmask; 2581 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2582 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2583 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2584 } 2585 2586 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2587 2588 if (AR_SREV_9100(ah)) { 2589 uint32_t mask; 2590 mask = REG_READ(ah, AR_CFG); 2591 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2592 ARN_DBG((ARN_DBG_RESET, "arn: " 2593 "%s CFG Byte Swap Set 0x%x\n", 2594 __func__, mask)); 2595 } else { 2596 mask = INIT_CONFIG_STATUS | 2597 AR_CFG_SWRB | AR_CFG_SWTB; 2598 REG_WRITE(ah, AR_CFG, mask); 2599 ARN_DBG((ARN_DBG_RESET, "arn: " 2600 "%s Setting CFG 0x%x\n", 2601 __func__, REG_READ(ah, AR_CFG))); 2602 } 2603 } else { 2604 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_keyreset(): " 2605 "#ifdef __BIG_ENDIAN \n")); 2606 #ifdef __BIG_ENDIAN 2607 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2608 #endif 2609 } 2610 2611 return (B_TRUE); 2612 bad: 2613 if (status) 2614 *status = ecode; 2615 return (B_FALSE); 2616 } 2617 2618 /* Key Cache Management */ 2619 2620 boolean_t 2621 ath9k_hw_keyreset(struct ath_hal *ah, uint16_t entry) 2622 { 2623 uint32_t keyType; 2624 2625 if (entry >= ah->ah_caps.keycache_size) { 2626 ARN_DBG((ARN_DBG_KEYCACHE, "arn: ath9k_hw_keyreset(): " 2627 "entry %u out of range\n", entry)); 2628 2629 return (B_FALSE); 2630 } 2631 2632 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 2633 2634 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 2635 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 2636 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 2637 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 2638 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 2639 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 2640 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 2641 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 2642 2643 if (keyType == AR_KEYTABLE_TYPE_TKIP && 2644 ATH9K_IS_MIC_ENABLED(ah)) { 2645 uint16_t micentry = entry + 64; 2646 2647 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 2648 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2649 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 2650 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2651 2652 } 2653 2654 if (ah->ah_curchan == NULL) 2655 return (B_TRUE); 2656 2657 return (B_TRUE); 2658 } 2659 2660 boolean_t 2661 ath9k_hw_keysetmac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac) 2662 { 2663 uint32_t macHi, macLo; 2664 2665 if (entry >= ah->ah_caps.keycache_size) { 2666 ARN_DBG((ARN_DBG_KEYCACHE, "arn: " 2667 "%s: entry %u out of range\n", __func__, entry)); 2668 return (B_FALSE); 2669 } 2670 2671 if (mac != NULL) { 2672 macHi = (mac[5] << 8) | mac[4]; 2673 macLo = (mac[3] << 24) | 2674 (mac[2] << 16) | 2675 (mac[1] << 8) | 2676 mac[0]; 2677 macLo >>= 1; 2678 macLo |= (macHi & 1) << 31; 2679 macHi >>= 1; 2680 } else { 2681 macLo = macHi = 0; 2682 } 2683 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 2684 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 2685 2686 return (B_TRUE); 2687 } 2688 2689 boolean_t 2690 ath9k_hw_set_keycache_entry(struct ath_hal *ah, uint16_t entry, 2691 const struct ath9k_keyval *k, const uint8_t *mac, int xorKey) 2692 { 2693 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2694 uint32_t key0, key1, key2, key3, key4; 2695 uint32_t keyType; 2696 uint32_t xorMask = xorKey ? 2697 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | 2698 ATH9K_KEY_XOR << 8 | ATH9K_KEY_XOR) : 0; 2699 struct ath_hal_5416 *ahp = AH5416(ah); 2700 2701 if (entry >= pCap->keycache_size) { 2702 ARN_DBG((ARN_DBG_KEYCACHE, "arn: " 2703 "%s: entry %u out of range\n", __func__, entry)); 2704 return (B_FALSE); 2705 } 2706 2707 switch (k->kv_type) { 2708 case ATH9K_CIPHER_AES_OCB: 2709 keyType = AR_KEYTABLE_TYPE_AES; 2710 break; 2711 case ATH9K_CIPHER_AES_CCM: 2712 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2713 ARN_DBG((ARN_DBG_KEYCACHE, "arn: " 2714 "%s: AES-CCM not supported by " 2715 "mac rev 0x%x\n", __func__, 2716 ah->ah_macRev)); 2717 return (B_FALSE); 2718 } 2719 keyType = AR_KEYTABLE_TYPE_CCM; 2720 break; 2721 case ATH9K_CIPHER_TKIP: 2722 keyType = AR_KEYTABLE_TYPE_TKIP; 2723 if (ATH9K_IS_MIC_ENABLED(ah) && 2724 entry + 64 >= pCap->keycache_size) { 2725 ARN_DBG((ARN_DBG_KEYCACHE, "arn: " 2726 "%s: entry %u inappropriate for TKIP\n", 2727 __func__, entry)); 2728 return (B_FALSE); 2729 } 2730 break; 2731 case ATH9K_CIPHER_WEP: 2732 if (k->kv_len < ATH9K_LEN_WEP40) { 2733 ARN_DBG((ARN_DBG_KEYCACHE, "arn: " 2734 "%s: WEP key length %u too small\n", 2735 __func__, k->kv_len)); 2736 return (B_FALSE); 2737 } 2738 if (k->kv_len <= ATH9K_LEN_WEP40) 2739 keyType = AR_KEYTABLE_TYPE_40; 2740 else if (k->kv_len <= ATH9K_LEN_WEP104) 2741 keyType = AR_KEYTABLE_TYPE_104; 2742 else 2743 keyType = AR_KEYTABLE_TYPE_128; 2744 break; 2745 case ATH9K_CIPHER_CLR: 2746 keyType = AR_KEYTABLE_TYPE_CLR; 2747 break; 2748 default: 2749 ARN_DBG((ARN_DBG_KEYCACHE, "arn: " 2750 "%s: cipher %u not supported\n", __func__, 2751 k->kv_type)); 2752 return (B_FALSE); 2753 } 2754 2755 key0 = ARN_LE_READ_32(k->kv_val + 0) ^ xorMask; 2756 key1 = (ARN_LE_READ_16(k->kv_val + 4) ^ xorMask) & 0xffff; 2757 key2 = ARN_LE_READ_32(k->kv_val + 6) ^ xorMask; 2758 key3 = (ARN_LE_READ_16(k->kv_val + 10) ^ xorMask) & 0xffff; 2759 key4 = ARN_LE_READ_32(k->kv_val + 12) ^ xorMask; 2760 2761 if (k->kv_len <= ATH9K_LEN_WEP104) 2762 key4 &= 0xff; 2763 2764 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2765 uint16_t micentry = entry + 64; 2766 2767 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 2768 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 2769 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2770 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2771 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2772 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2773 (void) ath9k_hw_keysetmac(ah, entry, mac); 2774 2775 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { 2776 uint32_t mic0, mic1, mic2, mic3, mic4; 2777 mic0 = ARN_LE_READ_32(k->kv_mic + 0); 2778 mic2 = ARN_LE_READ_32(k->kv_mic + 4); 2779 mic1 = ARN_LE_READ_16(k->kv_txmic + 2) & 0xffff; 2780 mic3 = ARN_LE_READ_16(k->kv_txmic + 0) & 0xffff; 2781 mic4 = ARN_LE_READ_32(k->kv_txmic + 4); 2782 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2783 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 2784 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2785 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 2786 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 2787 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2788 AR_KEYTABLE_TYPE_CLR); 2789 2790 } else { 2791 uint32_t mic0, mic2; 2792 mic0 = ARN_LE_READ_32(k->kv_mic + 0); 2793 mic2 = ARN_LE_READ_32(k->kv_mic + 4); 2794 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2795 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2796 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2797 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2798 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 2799 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2800 AR_KEYTABLE_TYPE_CLR); 2801 } 2802 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 2803 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 2804 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2805 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2806 } else { 2807 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2808 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2809 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2810 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2811 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2812 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2813 2814 (void) ath9k_hw_keysetmac(ah, entry, mac); 2815 } 2816 2817 if (ah->ah_curchan == NULL) 2818 return (B_TRUE); 2819 2820 return (B_TRUE); 2821 } 2822 2823 boolean_t 2824 ath9k_hw_keyisvalid(struct ath_hal *ah, uint16_t entry) 2825 { 2826 if (entry < ah->ah_caps.keycache_size) { 2827 uint32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2828 if (val & AR_KEYTABLE_VALID) 2829 return (B_TRUE); 2830 } 2831 return (B_FALSE); 2832 } 2833 2834 /* Power Management (Chipset) */ 2835 2836 static void 2837 ath9k_set_power_sleep(struct ath_hal *ah, int setChip) 2838 { 2839 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2840 if (setChip) { 2841 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2842 AR_RTC_FORCE_WAKE_EN); 2843 if (!AR_SREV_9100(ah)) 2844 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2845 2846 REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET), 2847 AR_RTC_RESET_EN); 2848 } 2849 } 2850 2851 static void 2852 ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) 2853 { 2854 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2855 if (setChip) { 2856 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2857 2858 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2859 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2860 AR_RTC_FORCE_WAKE_ON_INT); 2861 } else { 2862 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2863 AR_RTC_FORCE_WAKE_EN); 2864 } 2865 } 2866 } 2867 2868 static boolean_t 2869 ath9k_hw_set_power_awake(struct ath_hal *ah, int setChip) 2870 { 2871 uint32_t val; 2872 int i; 2873 2874 if (setChip) { 2875 if ((REG_READ(ah, AR_RTC_STATUS) & 2876 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2877 if (ath9k_hw_set_reset_reg(ah, 2878 ATH9K_RESET_POWER_ON) != B_TRUE) { 2879 return (B_FALSE); 2880 } 2881 } 2882 if (AR_SREV_9100(ah)) 2883 REG_SET_BIT(ah, AR_RTC_RESET, 2884 AR_RTC_RESET_EN); 2885 2886 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2887 AR_RTC_FORCE_WAKE_EN); 2888 drv_usecwait(50); 2889 2890 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2891 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2892 if (val == AR_RTC_STATUS_ON) 2893 break; 2894 drv_usecwait(50); 2895 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2896 AR_RTC_FORCE_WAKE_EN); 2897 } 2898 if (i == 0) { 2899 ARN_DBG((ARN_DBG_POWER_MGMT, 2900 "arn: ath9k_hw_set_power_awake(): " 2901 "Failed to wakeup in %uus\n", 2902 POWER_UP_TIME / 20)); 2903 2904 return (B_FALSE); 2905 } 2906 } 2907 2908 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2909 2910 return (B_TRUE); 2911 } 2912 2913 boolean_t 2914 ath9k_hw_setpower(struct ath_hal *ah, enum ath9k_power_mode mode) 2915 { 2916 struct ath_hal_5416 *ahp = AH5416(ah); 2917 static const char *modes[] = { 2918 "AWAKE", 2919 "FULL-SLEEP", 2920 "NETWORK SLEEP", 2921 "UNDEFINED" 2922 }; 2923 int status = B_TRUE, setChip = B_TRUE; 2924 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_setpower(): " 2925 "%s -> %s (%s)\n", 2926 modes[ahp->ah_powerMode], 2927 modes[mode], 2928 setChip ? "set chip " : "")); 2929 2930 switch (mode) { 2931 case ATH9K_PM_AWAKE: 2932 status = ath9k_hw_set_power_awake(ah, setChip); 2933 break; 2934 case ATH9K_PM_FULL_SLEEP: 2935 ath9k_set_power_sleep(ah, setChip); 2936 ahp->ah_chipFullSleep = B_TRUE; 2937 break; 2938 case ATH9K_PM_NETWORK_SLEEP: 2939 ath9k_set_power_network_sleep(ah, setChip); 2940 break; 2941 default: 2942 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_setpower(): " 2943 "unknown power mode %u\n", mode)); 2944 return (B_FALSE); 2945 } 2946 ahp->ah_powerMode = mode; 2947 2948 return (status); 2949 } 2950 2951 void 2952 ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 2953 { 2954 struct ath_hal_5416 *ahp = AH5416(ah); 2955 uint8_t i; 2956 2957 if (ah->ah_isPciExpress != B_TRUE) 2958 return; 2959 2960 if (ah->ah_config.pcie_powersave_enable == 2) 2961 return; 2962 2963 if (restore) 2964 return; 2965 2966 if (AR_SREV_9280_20_OR_LATER(ah)) { 2967 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { 2968 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), 2969 INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); 2970 } 2971 drv_usecwait(1000); 2972 } else if (AR_SREV_9280(ah) && 2973 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) { 2974 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); 2975 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2976 2977 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 2978 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 2979 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 2980 2981 if (ah->ah_config.pcie_clock_req) 2982 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 2983 else 2984 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 2985 2986 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2987 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2988 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); 2989 2990 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2991 2992 drv_usecwait(1000); 2993 } else { 2994 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2996 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 2997 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 2998 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 3000 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 3001 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 3002 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 3003 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 3004 } 3005 3006 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 3007 3008 if (ah->ah_config.pcie_waen) { 3009 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); 3010 } else { 3011 if (AR_SREV_9285(ah)) 3012 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 3013 else if (AR_SREV_9280(ah)) 3014 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 3015 else 3016 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 3017 } 3018 } 3019 3020 /* Interrupt Handling */ 3021 3022 boolean_t 3023 ath9k_hw_intrpend(struct ath_hal *ah) 3024 { 3025 uint32_t host_isr; 3026 3027 if (AR_SREV_9100(ah)) 3028 return (B_TRUE); 3029 3030 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 3031 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) 3032 return (B_TRUE); 3033 3034 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); 3035 3036 if ((host_isr & AR_INTR_SYNC_DEFAULT) && 3037 (host_isr != AR_INTR_SPURIOUS)) 3038 return (B_TRUE); 3039 3040 return (B_FALSE); 3041 } 3042 3043 boolean_t 3044 ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) 3045 { 3046 uint32_t isr = 0; 3047 uint32_t mask2 = 0; 3048 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3049 uint32_t sync_cause = 0; 3050 boolean_t fatal_int = B_FALSE; 3051 struct ath_hal_5416 *ahp = AH5416(ah); 3052 3053 if (!AR_SREV_9100(ah)) { 3054 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 3055 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 3056 == AR_RTC_STATUS_ON) { 3057 isr = REG_READ(ah, AR_ISR); 3058 } 3059 } 3060 3061 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & 3062 AR_INTR_SYNC_DEFAULT; 3063 3064 *masked = 0; 3065 3066 if (!isr && !sync_cause) 3067 return (B_FALSE); 3068 } else { 3069 *masked = 0; 3070 isr = REG_READ(ah, AR_ISR); 3071 } 3072 3073 if (isr) { 3074 if (isr & AR_ISR_BCNMISC) { 3075 uint32_t isr2; 3076 isr2 = REG_READ(ah, AR_ISR_S2); 3077 if (isr2 & AR_ISR_S2_TIM) 3078 mask2 |= ATH9K_INT_TIM; 3079 if (isr2 & AR_ISR_S2_DTIM) 3080 mask2 |= ATH9K_INT_DTIM; 3081 if (isr2 & AR_ISR_S2_DTIMSYNC) 3082 mask2 |= ATH9K_INT_DTIMSYNC; 3083 if (isr2 & (AR_ISR_S2_CABEND)) 3084 mask2 |= ATH9K_INT_CABEND; 3085 if (isr2 & AR_ISR_S2_GTT) 3086 mask2 |= ATH9K_INT_GTT; 3087 if (isr2 & AR_ISR_S2_CST) 3088 mask2 |= ATH9K_INT_CST; 3089 } 3090 3091 isr = REG_READ(ah, AR_ISR_RAC); 3092 if (isr == 0xffffffff) { 3093 *masked = 0; 3094 return (B_FALSE); 3095 } 3096 3097 *masked = isr & ATH9K_INT_COMMON; 3098 3099 if (ahp->ah_intrMitigation) { 3100 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 3101 *masked |= ATH9K_INT_RX; 3102 } 3103 3104 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 3105 *masked |= ATH9K_INT_RX; 3106 if (isr & 3107 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 3108 AR_ISR_TXEOL)) { 3109 uint32_t s0_s, s1_s; 3110 3111 *masked |= ATH9K_INT_TX; 3112 3113 s0_s = REG_READ(ah, AR_ISR_S0_S); 3114 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 3115 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 3116 3117 s1_s = REG_READ(ah, AR_ISR_S1_S); 3118 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 3119 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 3120 } 3121 3122 if (isr & AR_ISR_RXORN) { 3123 ARN_DBG((ARN_DBG_INTERRUPT, "arn: " 3124 "%s: receive FIFO overrun interrupt\n", __func__)); 3125 } 3126 3127 if (!AR_SREV_9100(ah)) { 3128 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 3129 uint32_t isr5 = REG_READ(ah, AR_ISR_S5_S); 3130 if (isr5 & AR_ISR_S5_TIM_TIMER) 3131 *masked |= ATH9K_INT_TIM_TIMER; 3132 } 3133 } 3134 3135 *masked |= mask2; 3136 } 3137 3138 if (AR_SREV_9100(ah)) 3139 return (B_TRUE); 3140 3141 if (sync_cause) { 3142 fatal_int = (sync_cause & 3143 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) ? 3144 B_TRUE : B_FALSE; 3145 3146 if (fatal_int) { 3147 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 3148 ARN_DBG((ARN_DBG_INTERRUPT, "arn: " 3149 "%s: received PCI FATAL interrupt\n", 3150 __func__)); 3151 } 3152 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 3153 ARN_DBG((ARN_DBG_INTERRUPT, "arn: " 3154 "%s: received PCI PERR interrupt\n", 3155 __func__)); 3156 } 3157 } 3158 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 3159 ARN_DBG((ARN_DBG_INTERRUPT, "arn: " 3160 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", 3161 __func__)); 3162 3163 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 3164 REG_WRITE(ah, AR_RC, 0); 3165 *masked |= ATH9K_INT_FATAL; 3166 } 3167 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 3168 ARN_DBG((ARN_DBG_ANY, "arn: " 3169 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", 3170 __func__)); 3171 } 3172 3173 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 3174 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 3175 } 3176 3177 return (B_TRUE); 3178 } 3179 3180 enum ath9k_int 3181 ath9k_hw_intrget(struct ath_hal *ah) 3182 { 3183 return (AH5416(ah)->ah_maskReg); 3184 } 3185 3186 enum ath9k_int 3187 ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) 3188 { 3189 struct ath_hal_5416 *ahp = AH5416(ah); 3190 uint32_t omask = ahp->ah_maskReg; 3191 uint32_t mask, mask2; 3192 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3193 3194 ARN_DBG((ARN_DBG_INTERRUPT, 3195 "arn: ath9k_hw_set_interrupts(): " 3196 "0x%x => 0x%x\n", omask, ints)); 3197 3198 if (omask & ATH9K_INT_GLOBAL) { 3199 ARN_DBG((ARN_DBG_INTERRUPT, 3200 "arn: ath9k_hw_set_interrupts(): " 3201 "disable IER\n")); 3202 3203 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 3204 (void) REG_READ(ah, AR_IER); 3205 if (!AR_SREV_9100(ah)) { 3206 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 3207 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); 3208 3209 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 3210 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); 3211 } 3212 } 3213 3214 mask = ints & ATH9K_INT_COMMON; 3215 mask2 = 0; 3216 3217 if (ints & ATH9K_INT_TX) { 3218 if (ahp->ah_txOkInterruptMask) 3219 mask |= AR_IMR_TXOK; 3220 if (ahp->ah_txDescInterruptMask) 3221 mask |= AR_IMR_TXDESC; 3222 if (ahp->ah_txErrInterruptMask) 3223 mask |= AR_IMR_TXERR; 3224 if (ahp->ah_txEolInterruptMask) 3225 mask |= AR_IMR_TXEOL; 3226 } 3227 if (ints & ATH9K_INT_RX) { 3228 mask |= AR_IMR_RXERR; 3229 if (ahp->ah_intrMitigation) 3230 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 3231 else 3232 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 3233 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 3234 mask |= AR_IMR_GENTMR; 3235 } 3236 3237 if (ints & (ATH9K_INT_BMISC)) { 3238 mask |= AR_IMR_BCNMISC; 3239 if (ints & ATH9K_INT_TIM) 3240 mask2 |= AR_IMR_S2_TIM; 3241 if (ints & ATH9K_INT_DTIM) 3242 mask2 |= AR_IMR_S2_DTIM; 3243 if (ints & ATH9K_INT_DTIMSYNC) 3244 mask2 |= AR_IMR_S2_DTIMSYNC; 3245 if (ints & ATH9K_INT_CABEND) 3246 mask2 |= (AR_IMR_S2_CABEND); 3247 } 3248 3249 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { 3250 mask |= AR_IMR_BCNMISC; 3251 if (ints & ATH9K_INT_GTT) 3252 mask2 |= AR_IMR_S2_GTT; 3253 if (ints & ATH9K_INT_CST) 3254 mask2 |= AR_IMR_S2_CST; 3255 } 3256 3257 REG_WRITE(ah, AR_IMR, mask); 3258 mask = REG_READ(ah, AR_IMR_S2) & 3259 ~(AR_IMR_S2_TIM | 3260 AR_IMR_S2_DTIM | 3261 AR_IMR_S2_DTIMSYNC | 3262 AR_IMR_S2_CABEND | 3263 AR_IMR_S2_CABTO | 3264 AR_IMR_S2_TSFOOR | 3265 AR_IMR_S2_GTT | 3266 AR_IMR_S2_CST); 3267 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 3268 ahp->ah_maskReg = ints; 3269 3270 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 3271 if (ints & ATH9K_INT_TIM_TIMER) 3272 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 3273 else 3274 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 3275 } 3276 3277 if (ints & ATH9K_INT_GLOBAL) { 3278 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 3279 if (!AR_SREV_9100(ah)) { 3280 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 3281 AR_INTR_MAC_IRQ); 3282 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 3283 3284 3285 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 3286 AR_INTR_SYNC_DEFAULT); 3287 REG_WRITE(ah, AR_INTR_SYNC_MASK, 3288 AR_INTR_SYNC_DEFAULT); 3289 } 3290 3291 } 3292 3293 return (omask); 3294 } 3295 3296 /* Beacon Handling */ 3297 3298 void 3299 ath9k_hw_beaconinit(struct ath_hal *ah, uint32_t next_beacon, 3300 uint32_t beacon_period) 3301 { 3302 struct ath_hal_5416 *ahp = AH5416(ah); 3303 int flags = 0; 3304 3305 ahp->ah_beaconInterval = beacon_period; 3306 3307 switch (ah->ah_opmode) { 3308 case ATH9K_M_STA: 3309 case ATH9K_M_MONITOR: 3310 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3311 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 3312 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 3313 flags |= AR_TBTT_TIMER_EN; 3314 break; 3315 case ATH9K_M_IBSS: 3316 REG_SET_BIT(ah, AR_TXCFG, 3317 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 3318 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 3319 TU_TO_USEC(next_beacon + 3320 (ahp->ah_atimWindow ? ahp-> 3321 ah_atimWindow : 1))); 3322 flags |= AR_NDP_TIMER_EN; 3323 /*FALLTHRU*/ 3324 case ATH9K_M_HOSTAP: 3325 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3326 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 3327 TU_TO_USEC(next_beacon - 3328 ah->ah_config. 3329 dma_beacon_response_time)); 3330 REG_WRITE(ah, AR_NEXT_SWBA, 3331 TU_TO_USEC(next_beacon - 3332 ah->ah_config. 3333 sw_beacon_response_time)); 3334 flags |= 3335 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3336 break; 3337 default: 3338 ARN_DBG((ARN_DBG_BEACON, 3339 "%s: unsupported opmode: %d\n", 3340 __func__, ah->ah_opmode)); 3341 return; 3342 } 3343 3344 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3345 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3346 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 3347 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 3348 3349 beacon_period &= ~ATH9K_BEACON_ENA; 3350 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 3351 beacon_period &= ~ATH9K_BEACON_RESET_TSF; 3352 ath9k_hw_reset_tsf(ah); 3353 } 3354 3355 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3356 } 3357 3358 void 3359 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 3360 const struct ath9k_beacon_state *bs) 3361 { 3362 uint32_t nextTbtt, beaconintval, dtimperiod, beacontimeout; 3363 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3364 3365 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3366 3367 REG_WRITE(ah, AR_BEACON_PERIOD, 3368 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3369 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 3370 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3371 3372 REG_RMW_FIELD(ah, AR_RSSI_THR, 3373 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 3374 3375 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 3376 3377 if (bs->bs_sleepduration > beaconintval) 3378 beaconintval = bs->bs_sleepduration; 3379 3380 dtimperiod = bs->bs_dtimperiod; 3381 if (bs->bs_sleepduration > dtimperiod) 3382 dtimperiod = bs->bs_sleepduration; 3383 3384 if (beaconintval == dtimperiod) 3385 nextTbtt = bs->bs_nextdtim; 3386 else 3387 nextTbtt = bs->bs_nexttbtt; 3388 3389 ARN_DBG((ARN_DBG_BEACON, "arn: " 3390 "%s: next DTIM %d\n", __func__, bs->bs_nextdtim)); 3391 ARN_DBG((ARN_DBG_BEACON, "arn: " 3392 "%s: next beacon %d\n", __func__, nextTbtt)); 3393 ARN_DBG((ARN_DBG_BEACON, "arn: " 3394 "%s: beacon period %d\n", __func__, beaconintval)); 3395 ARN_DBG((ARN_DBG_BEACON, "arn: " 3396 "%s: DTIM period %d\n", __func__, dtimperiod)); 3397 3398 REG_WRITE(ah, AR_NEXT_DTIM, 3399 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3400 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 3401 3402 REG_WRITE(ah, AR_SLEEP1, 3403 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | 3404 AR_SLEEP1_ASSUME_DTIM); 3405 3406 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 3407 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 3408 else 3409 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 3410 3411 REG_WRITE(ah, AR_SLEEP2, 3412 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 3413 3414 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 3415 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 3416 3417 REG_SET_BIT(ah, AR_TIMER_MODE, 3418 AR_TBTT_TIMER_EN | 3419 AR_TIM_TIMER_EN | 3420 AR_DTIM_TIMER_EN); 3421 3422 /* TSF Out of Range Threshold */ 3423 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 3424 } 3425 3426 /* HW Capabilities */ 3427 3428 boolean_t 3429 ath9k_hw_fill_cap_info(struct ath_hal *ah) 3430 { 3431 struct ath_hal_5416 *ahp = AH5416(ah); 3432 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3433 uint16_t capField = 0, eeval; 3434 3435 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); 3436 3437 ah->ah_currentRD = eeval; 3438 3439 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); 3440 ah->ah_currentRDExt = eeval; 3441 3442 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); 3443 3444 if (ah->ah_opmode != ATH9K_M_HOSTAP && 3445 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 3446 if (ah->ah_currentRD == 0x64 || 3447 ah->ah_currentRD == 0x65) 3448 ah->ah_currentRD += 5; 3449 else if (ah->ah_currentRD == 0x41) 3450 ah->ah_currentRD = 0x43; 3451 3452 ARN_DBG((ARN_DBG_REGULATORY, 3453 "%s: regdomain mapped to 0x%x\n", __func__, 3454 ah->ah_currentRD)); 3455 } 3456 3457 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); 3458 3459 bzero(pCap->wireless_modes, sizeof (uint8_t)*4); 3460 3461 if (eeval & AR5416_OPFLAGS_11A) { 3462 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 3463 if (ah->ah_config.ht_enable) { 3464 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 3465 set_bit(ATH9K_MODE_11NA_HT20, 3466 pCap->wireless_modes); 3467 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 3468 set_bit(ATH9K_MODE_11NA_HT40PLUS, 3469 pCap->wireless_modes); 3470 set_bit(ATH9K_MODE_11NA_HT40MINUS, 3471 pCap->wireless_modes); 3472 } 3473 } 3474 } 3475 3476 if (eeval & AR5416_OPFLAGS_11G) { 3477 set_bit(ATH9K_MODE_11B, pCap->wireless_modes); 3478 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 3479 if (ah->ah_config.ht_enable) { 3480 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 3481 set_bit(ATH9K_MODE_11NG_HT20, 3482 pCap->wireless_modes); 3483 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 3484 set_bit(ATH9K_MODE_11NG_HT40PLUS, 3485 pCap->wireless_modes); 3486 set_bit(ATH9K_MODE_11NG_HT40MINUS, 3487 pCap->wireless_modes); 3488 } 3489 } 3490 } 3491 3492 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK); 3493 if ((ah->ah_isPciExpress) || 3494 (eeval & AR5416_OPFLAGS_11A)) { 3495 pCap->rx_chainmask = 3496 ath9k_hw_get_eeprom(ah, EEP_RX_MASK); 3497 } else { 3498 pCap->rx_chainmask = 3499 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; 3500 } 3501 3502 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) 3503 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; 3504 3505 pCap->low_2ghz_chan = 2312; 3506 pCap->high_2ghz_chan = 2732; 3507 3508 pCap->low_5ghz_chan = 4920; 3509 pCap->high_5ghz_chan = 6100; 3510 3511 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 3512 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 3513 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 3514 3515 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 3516 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 3517 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 3518 3519 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; 3520 #ifdef ARN_11N_SUPPORT 3521 if (ah->ah_config.ht_enable) 3522 pCap->hw_caps |= ATH9K_HW_CAP_HT; 3523 else 3524 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3525 #else 3526 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3527 #endif 3528 3529 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 3530 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 3531 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 3532 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 3533 3534 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 3535 pCap->total_queues = 3536 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 3537 else 3538 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 3539 3540 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 3541 pCap->keycache_size = 3542 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 3543 else 3544 pCap->keycache_size = AR_KEYTABLE_SIZE; 3545 3546 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 3547 pCap->num_mr_retries = 4; 3548 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 3549 3550 if (AR_SREV_9280_10_OR_LATER(ah)) 3551 pCap->num_gpio_pins = AR928X_NUM_GPIO; 3552 else 3553 pCap->num_gpio_pins = AR_NUM_GPIO; 3554 3555 if (AR_SREV_9280_10_OR_LATER(ah)) { 3556 pCap->hw_caps |= ATH9K_HW_CAP_WOW; 3557 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; 3558 } else { 3559 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW; 3560 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; 3561 } 3562 3563 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 3564 pCap->hw_caps |= ATH9K_HW_CAP_CST; 3565 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 3566 } else { 3567 pCap->rts_aggr_limit = (8 * 1024); 3568 } 3569 3570 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 3571 3572 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3573 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT); 3574 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { 3575 ah->ah_rfkill_gpio = 3576 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 3577 ah->ah_rfkill_polarity = 3578 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); 3579 3580 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 3581 } 3582 #endif 3583 3584 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || 3585 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || 3586 (ah->ah_macVersion == AR_SREV_VERSION_9160) || 3587 (ah->ah_macVersion == AR_SREV_VERSION_9100) || 3588 (ah->ah_macVersion == AR_SREV_VERSION_9280)) 3589 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 3590 else 3591 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 3592 3593 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 3594 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 3595 else 3596 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 3597 3598 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { 3599 pCap->reg_cap = 3600 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3601 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 3602 AR_EEPROM_EEREGCAP_EN_KK_U2 | 3603 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 3604 } else { 3605 pCap->reg_cap = 3606 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3607 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3608 } 3609 3610 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3611 3612 /* ATH9K_HAL_FREQ_BAND_5GHZ == 0 */ 3613 pCap->num_antcfg_5ghz = 3614 ath9k_hw_get_num_ant_config(ah, 0); 3615 /* ATH9K_HAL_FREQ_BAND_2GHZ == 1 */ 3616 pCap->num_antcfg_2ghz = 3617 ath9k_hw_get_num_ant_config(ah, 1); 3618 3619 return (B_TRUE); 3620 } 3621 3622 boolean_t 3623 ath9k_hw_getcapability(struct ath_hal *ah, 3624 enum ath9k_capability_type type, 3625 uint32_t capability, uint32_t *result) 3626 { 3627 struct ath_hal_5416 *ahp = AH5416(ah); 3628 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3629 3630 switch (type) { 3631 case ATH9K_CAP_CIPHER: 3632 switch (capability) { 3633 case ATH9K_CIPHER_AES_CCM: 3634 case ATH9K_CIPHER_AES_OCB: 3635 case ATH9K_CIPHER_TKIP: 3636 case ATH9K_CIPHER_WEP: 3637 case ATH9K_CIPHER_MIC: 3638 case ATH9K_CIPHER_CLR: 3639 return (B_TRUE); 3640 default: 3641 return (B_FALSE); 3642 } 3643 case ATH9K_CAP_TKIP_MIC: 3644 switch (capability) { 3645 case 0: 3646 return (B_TRUE); 3647 case 1: 3648 return ((ahp->ah_staId1Defaults & 3649 AR_STA_ID1_CRPT_MIC_ENABLE) ? B_TRUE : 3650 B_FALSE); 3651 } 3652 /*FALLTHRU*/ 3653 case ATH9K_CAP_TKIP_SPLIT: 3654 return ((ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? 3655 B_FALSE : B_TRUE); 3656 case ATH9K_CAP_WME_TKIPMIC: 3657 return (0); 3658 case ATH9K_CAP_PHYCOUNTERS: 3659 return (ahp->ah_hasHwPhyCounters ? 0 : -ENXIO); 3660 case ATH9K_CAP_DIVERSITY: 3661 return ((REG_READ(ah, AR_PHY_CCK_DETECT) & 3662 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3663 B_TRUE : B_FALSE); 3664 case ATH9K_CAP_PHYDIAG: 3665 return (B_TRUE); 3666 case ATH9K_CAP_MCAST_KEYSRCH: 3667 switch (capability) { 3668 case 0: 3669 return (B_TRUE); 3670 case 1: 3671 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3672 return (B_FALSE); 3673 } else { 3674 return ((ahp->ah_staId1Defaults & 3675 AR_STA_ID1_MCAST_KSRCH) ? B_TRUE : 3676 B_FALSE); 3677 } 3678 } 3679 return (B_FALSE); 3680 case ATH9K_CAP_TSF_ADJUST: 3681 return ((ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? 3682 B_TRUE : B_FALSE); 3683 case ATH9K_CAP_RFSILENT: 3684 if (capability == 3) 3685 return (B_FALSE); 3686 /*FALLTHRU*/ 3687 case ATH9K_CAP_ANT_CFG_2GHZ: 3688 *result = pCap->num_antcfg_2ghz; 3689 return (B_TRUE); 3690 case ATH9K_CAP_ANT_CFG_5GHZ: 3691 *result = pCap->num_antcfg_5ghz; 3692 return (B_TRUE); 3693 case ATH9K_CAP_TXPOW: 3694 switch (capability) { 3695 case 0: 3696 return (0); 3697 case 1: 3698 *result = ah->ah_powerLimit; 3699 return (0); 3700 case 2: 3701 *result = ah->ah_maxPowerLevel; 3702 return (0); 3703 case 3: 3704 *result = ah->ah_tpScale; 3705 return (0); 3706 } 3707 return (B_FALSE); 3708 default: 3709 return (B_FALSE); 3710 } 3711 } 3712 3713 /* ARGSUSED */ 3714 boolean_t 3715 ath9k_hw_setcapability(struct ath_hal *ah, 3716 enum ath9k_capability_type type, 3717 uint32_t capability, uint32_t setting, 3718 int *status) 3719 { 3720 struct ath_hal_5416 *ahp = AH5416(ah); 3721 uint32_t v; 3722 3723 switch (type) { 3724 case ATH9K_CAP_TKIP_MIC: 3725 if (setting) 3726 ahp->ah_staId1Defaults |= 3727 AR_STA_ID1_CRPT_MIC_ENABLE; 3728 else 3729 ahp->ah_staId1Defaults &= 3730 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3731 return (B_TRUE); 3732 case ATH9K_CAP_DIVERSITY: 3733 v = REG_READ(ah, AR_PHY_CCK_DETECT); 3734 if (setting) 3735 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3736 else 3737 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3738 REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 3739 return (B_TRUE); 3740 case ATH9K_CAP_MCAST_KEYSRCH: 3741 if (setting) 3742 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 3743 else 3744 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3745 return (B_TRUE); 3746 case ATH9K_CAP_TSF_ADJUST: 3747 if (setting) 3748 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3749 else 3750 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3751 return (B_TRUE); 3752 default: 3753 return (B_FALSE); 3754 } 3755 } 3756 3757 /* GPIO / RFKILL / Antennae */ 3758 3759 static void 3760 ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, 3761 uint32_t gpio, uint32_t type) 3762 { 3763 int addr; 3764 uint32_t gpio_shift, tmp; 3765 3766 if (gpio > 11) 3767 addr = AR_GPIO_OUTPUT_MUX3; 3768 else if (gpio > 5) 3769 addr = AR_GPIO_OUTPUT_MUX2; 3770 else 3771 addr = AR_GPIO_OUTPUT_MUX1; 3772 3773 gpio_shift = (gpio % 6) * 5; 3774 3775 if (AR_SREV_9280_20_OR_LATER(ah) || 3776 (addr != AR_GPIO_OUTPUT_MUX1)) { 3777 REG_RMW(ah, addr, (type << gpio_shift), 3778 (0x1f << gpio_shift)); 3779 } else { 3780 tmp = REG_READ(ah, addr); 3781 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 3782 tmp &= ~(0x1f << gpio_shift); 3783 tmp |= (type << gpio_shift); 3784 REG_WRITE(ah, addr, tmp); 3785 } 3786 } 3787 3788 void 3789 ath9k_hw_cfg_gpio_input(struct ath_hal *ah, uint32_t gpio) 3790 { 3791 uint32_t gpio_shift; 3792 3793 ASSERT(gpio < ah->ah_caps.num_gpio_pins); 3794 3795 gpio_shift = gpio << 1; 3796 3797 REG_RMW(ah, 3798 AR_GPIO_OE_OUT, 3799 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 3800 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3801 } 3802 3803 uint32_t 3804 ath9k_hw_gpio_get(struct ath_hal *ah, uint32_t gpio) 3805 { 3806 if (gpio >= ah->ah_caps.num_gpio_pins) 3807 return (0xffffffff); 3808 3809 if (AR_SREV_9280_10_OR_LATER(ah)) { 3810 return ((MS(REG_READ(ah, AR_GPIO_IN_OUT), 3811 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0); 3812 } else { 3813 return ((MS(REG_READ(ah, 3814 AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) & 3815 AR_GPIO_BIT(gpio)) != 0); 3816 } 3817 } 3818 3819 void 3820 ath9k_hw_cfg_output(struct ath_hal *ah, uint32_t gpio, 3821 uint32_t ah_signal_type) 3822 { 3823 uint32_t gpio_shift; 3824 3825 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 3826 3827 gpio_shift = 2 * gpio; 3828 3829 REG_RMW(ah, 3830 AR_GPIO_OE_OUT, 3831 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 3832 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3833 } 3834 3835 void 3836 ath9k_hw_set_gpio(struct ath_hal *ah, uint32_t gpio, uint32_t val) 3837 { 3838 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3839 AR_GPIO_BIT(gpio)); 3840 } 3841 3842 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3843 void 3844 ath9k_enable_rfkill(struct ath_hal *ah) 3845 { 3846 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3847 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 3848 3849 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 3850 AR_GPIO_INPUT_MUX2_RFSILENT); 3851 3852 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); 3853 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 3854 } 3855 #endif 3856 3857 int 3858 ath9k_hw_select_antconfig(struct ath_hal *ah, uint32_t cfg) 3859 { 3860 struct ath9k_channel *chan = ah->ah_curchan; 3861 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3862 uint16_t ant_config; 3863 uint32_t halNumAntConfig; 3864 3865 halNumAntConfig = IS_CHAN_2GHZ(chan) ? 3866 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz; 3867 3868 if (cfg < halNumAntConfig) { 3869 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 3870 cfg, &ant_config)) { 3871 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 3872 return (0); 3873 } 3874 } 3875 3876 return (-EINVAL); 3877 } 3878 3879 uint32_t 3880 ath9k_hw_getdefantenna(struct ath_hal *ah) 3881 { 3882 return (REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 3883 } 3884 3885 void 3886 ath9k_hw_setantenna(struct ath_hal *ah, uint32_t antenna) 3887 { 3888 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3889 } 3890 3891 /* ARGSUSED */ 3892 boolean_t 3893 ath9k_hw_setantennaswitch(struct ath_hal *ah, 3894 enum ath9k_ant_setting settings, 3895 struct ath9k_channel *chan, 3896 uint8_t *tx_chainmask, 3897 uint8_t *rx_chainmask, 3898 uint8_t *antenna_cfgd) 3899 { 3900 struct ath_hal_5416 *ahp = AH5416(ah); 3901 static uint8_t tx_chainmask_cfg, rx_chainmask_cfg; 3902 3903 if (AR_SREV_9280(ah)) { 3904 if (!tx_chainmask_cfg) { 3905 3906 tx_chainmask_cfg = *tx_chainmask; 3907 rx_chainmask_cfg = *rx_chainmask; 3908 } 3909 3910 switch (settings) { 3911 case ATH9K_ANT_FIXED_A: 3912 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK; 3913 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK; 3914 *antenna_cfgd = B_TRUE; 3915 break; 3916 case ATH9K_ANT_FIXED_B: 3917 if (ah->ah_caps.tx_chainmask > 3918 ATH9K_ANTENNA1_CHAINMASK) { 3919 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 3920 } 3921 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 3922 *antenna_cfgd = B_TRUE; 3923 break; 3924 case ATH9K_ANT_VARIABLE: 3925 *tx_chainmask = tx_chainmask_cfg; 3926 *rx_chainmask = rx_chainmask_cfg; 3927 *antenna_cfgd = B_TRUE; 3928 break; 3929 default: 3930 break; 3931 } 3932 } else { 3933 ahp->ah_diversityControl = settings; 3934 } 3935 3936 return (B_TRUE); 3937 } 3938 3939 /* General Operation */ 3940 3941 uint32_t 3942 ath9k_hw_getrxfilter(struct ath_hal *ah) 3943 { 3944 uint32_t bits = REG_READ(ah, AR_RX_FILTER); 3945 uint32_t phybits = REG_READ(ah, AR_PHY_ERR); 3946 3947 if (phybits & AR_PHY_ERR_RADAR) 3948 bits |= ATH9K_RX_FILTER_PHYRADAR; 3949 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 3950 bits |= ATH9K_RX_FILTER_PHYERR; 3951 3952 return (bits); 3953 } 3954 3955 void 3956 ath9k_hw_setrxfilter(struct ath_hal *ah, uint32_t bits) 3957 { 3958 uint32_t phybits; 3959 3960 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR); 3961 phybits = 0; 3962 if (bits & ATH9K_RX_FILTER_PHYRADAR) 3963 phybits |= AR_PHY_ERR_RADAR; 3964 if (bits & ATH9K_RX_FILTER_PHYERR) 3965 phybits |= AR_PHY_ERR_OFDM_TIMING | 3966 AR_PHY_ERR_CCK_TIMING; 3967 REG_WRITE(ah, AR_PHY_ERR, phybits); 3968 3969 if (phybits) 3970 REG_WRITE(ah, AR_RXCFG, 3971 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 3972 else 3973 REG_WRITE(ah, AR_RXCFG, 3974 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3975 } 3976 3977 boolean_t 3978 ath9k_hw_phy_disable(struct ath_hal *ah) 3979 { 3980 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)); 3981 } 3982 3983 boolean_t 3984 ath9k_hw_disable(struct ath_hal *ah) 3985 { 3986 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3987 return (B_FALSE); 3988 3989 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)); 3990 } 3991 3992 boolean_t 3993 ath9k_hw_set_txpowerlimit(struct ath_hal *ah, uint32_t limit) 3994 { 3995 struct ath9k_channel *chan = ah->ah_curchan; 3996 3997 /* LINT */ 3998 ah->ah_powerLimit = (uint16_t)min(limit, (uint32_t)MAX_RATE_POWER); 3999 4000 if (ath9k_hw_set_txpower(ah, chan, 4001 ath9k_regd_get_ctl(ah, chan), 4002 ath9k_regd_get_antenna_allowed(ah, chan), 4003 chan->maxRegTxPower * 2, 4004 ARN_MIN((uint32_t)MAX_RATE_POWER, 4005 (uint32_t)ah->ah_powerLimit)) != 0) 4006 return (B_FALSE); 4007 4008 return (B_TRUE); 4009 } 4010 4011 void 4012 ath9k_hw_getmac(struct ath_hal *ah, uint8_t *mac) 4013 { 4014 struct ath_hal_5416 *ahp = AH5416(ah); 4015 4016 (void) memcpy(mac, ahp->ah_macaddr, 6); 4017 } 4018 4019 boolean_t 4020 ath9k_hw_setmac(struct ath_hal *ah, const uint8_t *mac) 4021 { 4022 struct ath_hal_5416 *ahp = AH5416(ah); 4023 4024 (void) memcpy(ahp->ah_macaddr, mac, 6); 4025 4026 return (B_TRUE); 4027 } 4028 4029 void 4030 ath9k_hw_setopmode(struct ath_hal *ah) 4031 { 4032 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 4033 } 4034 4035 void 4036 ath9k_hw_setmcastfilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 4037 { 4038 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 4039 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 4040 } 4041 4042 void 4043 ath9k_hw_getbssidmask(struct ath_hal *ah, uint8_t *mask) 4044 { 4045 struct ath_hal_5416 *ahp = AH5416(ah); 4046 4047 (void) memcpy(mask, ahp->ah_bssidmask, 6); 4048 } 4049 4050 boolean_t 4051 ath9k_hw_setbssidmask(struct ath_hal *ah, const uint8_t *mask) 4052 { 4053 struct ath_hal_5416 *ahp = AH5416(ah); 4054 4055 (void) memcpy(ahp->ah_bssidmask, mask, 6); 4056 4057 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask)); 4058 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4)); 4059 4060 return (B_TRUE); 4061 } 4062 4063 void 4064 ath9k_hw_write_associd(struct ath_hal *ah, 4065 const uint8_t *bssid, uint16_t assocId) 4066 { 4067 struct ath_hal_5416 *ahp = AH5416(ah); 4068 4069 (void) memcpy(ahp->ah_bssid, bssid, 6); 4070 ahp->ah_assocId = assocId; 4071 4072 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid)); 4073 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) | 4074 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S)); 4075 } 4076 4077 uint64_t 4078 ath9k_hw_gettsf64(struct ath_hal *ah) 4079 { 4080 uint64_t tsf; 4081 4082 tsf = REG_READ(ah, AR_TSF_U32); 4083 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); 4084 4085 return (tsf); 4086 } 4087 4088 void 4089 ath9k_hw_reset_tsf(struct ath_hal *ah) 4090 { 4091 int count; 4092 4093 count = 0; 4094 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 4095 count++; 4096 if (count > 10) { 4097 ARN_DBG((ARN_DBG_HW, "arn: " 4098 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", 4099 __func__)); 4100 4101 break; 4102 } 4103 drv_usecwait(10); 4104 } 4105 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 4106 } 4107 4108 boolean_t 4109 ath9k_hw_set_tsfadjust(struct ath_hal *ah, uint32_t setting) 4110 { 4111 struct ath_hal_5416 *ahp = AH5416(ah); 4112 4113 if (setting) 4114 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 4115 else 4116 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 4117 4118 return (B_TRUE); 4119 } 4120 4121 boolean_t 4122 ath9k_hw_setslottime(struct ath_hal *ah, uint32_t us) 4123 { 4124 struct ath_hal_5416 *ahp = AH5416(ah); 4125 4126 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 4127 ARN_DBG((ARN_DBG_HW, "arn: " 4128 "%s: bad slot time %u\n", __func__, us)); 4129 4130 ahp->ah_slottime = (uint32_t)-1; 4131 return (B_FALSE); 4132 } else { 4133 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 4134 ahp->ah_slottime = us; 4135 return (B_TRUE); 4136 } 4137 } 4138 4139 void 4140 ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) 4141 { 4142 uint32_t macmode; 4143 4144 if (mode == ATH9K_HT_MACMODE_2040 && 4145 !ah->ah_config.cwm_ignore_extcca) 4146 macmode = AR_2040_JOINED_RX_CLEAR; 4147 else 4148 macmode = 0; 4149 4150 REG_WRITE(ah, AR_2040_MODE, macmode); 4151 } 4152