xref: /titanic_50/usr/src/lib/libcpc/common/libcpc_impl.h (revision 84ab085a13f931bc78e7415e7ce921dbaa14fcb3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_LIBCPC_IMPL_H
28 #define	_LIBCPC_IMPL_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #include <libcpc.h>
33 #include <inttypes.h>
34 #include <thread.h>
35 #include <synch.h>
36 #include <sys/types.h>
37 #include <sys/cpc_impl.h>
38 
39 #ifdef	__cplusplus
40 extern "C" {
41 #endif
42 
43 #define	CPC_VER_1 1
44 #define	CPC1_BUFSIZE (2 * sizeof (uint64_t))
45 
46 struct _cpc_attr {
47 	char			ca_name[CPC_MAX_ATTR_LEN];
48 	uint64_t		ca_val;
49 };
50 
51 typedef struct __cpc_request cpc_request_t;
52 
53 struct __cpc_request {
54 	char			cr_event[CPC_MAX_EVENT_LEN];
55 	uint64_t		cr_preset;	/* Initial value */
56 	uint16_t		cr_index;	/* Index of request in data */
57 	uint_t			cr_flags;
58 	uint_t			cr_nattrs;	/* # CPU-specific attrs */
59 	kcpc_attr_t		*cr_attr;
60 	cpc_request_t		*cr_next;	/* next request in set */
61 };
62 
63 struct __cpc_buf {
64 	uint64_t		*cb_data;	/* Pointer to data store */
65 	hrtime_t		cb_hrtime;	/* hrtime at last sample */
66 	uint64_t		cb_tick;	/* virtualized tsc/tick */
67 	size_t			cb_size;	/* Size of data store, bytes */
68 	cpc_buf_t		*cb_next;	/* List of all bufs */
69 };
70 
71 /*
72  * Possible cpc_set_t states:
73  */
74 typedef enum {
75 	CS_UNBOUND,		/* Set is not currently bound */
76 	CS_BOUND_CURLWP,	/* Set has been bound to curlwp */
77 	CS_BOUND_PCTX,		/* Set has been bound via libpctx */
78 	CS_BOUND_CPU		/* Set has been bound to a CPU */
79 } __cpc_state_t;
80 
81 struct __cpc_set {
82 	cpc_request_t		*cs_request;	/* linked list of requests */
83 	__cpc_state_t		cs_state;	/* State of this set */
84 	int			cs_nreqs;	/* Number of requests in set */
85 	int			cs_fd;		/* file descriptor of cpc dev */
86 	processorid_t		cs_obind;	/* previous proc binding */
87 	pctx_t			*cs_pctx;	/* pctx of process bound to */
88 	id_t			cs_id;		/* lwp ID of pctx binding */
89 	thread_t		cs_thr;		/* thread ID which bound set */
90 	cpc_set_t		*cs_next;	/* Linked list of all sets */
91 };
92 
93 struct __cpc {
94 	cpc_set_t		*cpc_sets;	/* List of existing sets */
95 	cpc_buf_t		*cpc_bufs;	/* List of existing bufs */
96 	cpc_errhndlr_t		*cpc_errfn;	/* Handles library errors */
97 	mutex_t			cpc_lock;	/* Protect various ops */
98 	char			*cpc_attrlist;	/* List of supported attrs */
99 	char			**cpc_evlist;	/* List of events per pic */
100 	char			cpc_cpuref[CPC_MAX_CPUREF];
101 	char			cpc_cciname[CPC_MAX_IMPL_NAME];
102 	uint_t			cpc_caps;
103 	uint_t			cpc_npic;
104 };
105 
106 /*
107  * cpc_t handle for CPCv1 clients.
108  */
109 extern cpc_t *__cpc;
110 
111 /*PRINTFLIKE2*/
112 extern void __cpc_error(const char *fn, const char *fmt, ...);
113 
114 extern const char *__cpc_reg_to_name(int cpuver, int regno, uint8_t bits);
115 extern int __cpc_name_to_reg(int cpuver, int regno,
116     const char *name, uint8_t *bits);
117 
118 extern uint_t __cpc_workver;
119 extern int __cpc_v1_cpuver;
120 #ifdef __sparc
121 extern uint64_t __cpc_v1_pcr;
122 #else
123 extern uint32_t __cpc_v1_pes[2];
124 #endif /* __sparc */
125 
126 extern char *__cpc_pack_set(cpc_set_t *set, uint_t flags, size_t *buflen);
127 
128 typedef struct __cpc_strhash cpc_strhash_t;
129 
130 struct __cpc_strhash {
131 	char *str;
132 	struct __cpc_strhash *cur;
133 	struct __cpc_strhash *next;
134 };
135 
136 extern cpc_strhash_t *__cpc_strhash_alloc(void);
137 extern void __cpc_strhash_free(cpc_strhash_t *hash);
138 extern int __cpc_strhash_add(cpc_strhash_t *hash, char *key);
139 extern char *__cpc_strhash_next(cpc_strhash_t *hash);
140 
141 /*
142  * Implementation-private system call used by libcpc
143  */
144 struct __cpc;
145 extern int __pctx_cpc(pctx_t *pctx, struct __cpc *cpc, int cmd, id_t lwpid,
146     void *data1, void *data2, void *data3, int bufsize);
147 
148 #define	CPUDRV				"/devices/pseudo/cpc@0"
149 #define	CPUDRV_SHARED			CPUDRV":shared"
150 
151 #if defined(__sparc) || defined(__i386)
152 /*
153  * These two are only used for backwards compatibility to the Obsolete CPCv1.
154  */
155 extern int __cpc_init(void);
156 extern cpc_set_t *__cpc_eventtoset(cpc_t *cpc, cpc_event_t *event, int flags);
157 
158 /*
159  * ce_cpuver values
160  */
161 #define	CPC_ULTRA1		1000
162 #define	CPC_ULTRA2		1001	/* same as ultra1 for these purposes */
163 #define	CPC_ULTRA3		1002
164 #define	CPC_ULTRA3_PLUS		1003
165 #define	CPC_ULTRA3_I		1004
166 
167 #define	CPC_PENTIUM		2000
168 #define	CPC_PENTIUM_MMX		2001
169 #define	CPC_PENTIUM_PRO		2002
170 #define	CPC_PENTIUM_PRO_MMX	2003
171 
172 #define	CPC_SPARC64_III		3000
173 #define	CPC_SPARC64_V		3002
174 
175 #endif /* __sparc || __i386 */
176 
177 #if defined(__i386) || defined(__amd64)
178 /*
179  * This is common between i386 and amd64, because amd64 implements %tick.
180  * Currently only used by the cpc tools to print the label atop the CPU ticks
181  * column on amd64.
182  */
183 #define	CPC_TICKREG_NAME	"tsc"
184 #endif /* __i386 || __amd64 */
185 
186 #if defined(__sparc)
187 
188 /*
189  * UltraSPARC I, II and III processors
190  *
191  * The performance counters on these processors allow up to two 32-bit
192  * performance events to be captured simultaneously from a selection
193  * of metrics.   The metrics are selected by writing to the performance
194  * control register, and subsequent values collected by reading from the
195  * performance instrumentation counter registers.  Both registers are
196  * priviliged by default, and implemented as ASRs.
197  */
198 
199 struct _cpc_event {
200 	int ce_cpuver;
201 	hrtime_t ce_hrt;	/* gethrtime() */
202 	uint64_t ce_tick;	/* virtualized %tick */
203 	uint64_t ce_pic[2];	/* virtualized %pic */
204 	uint64_t ce_pcr;	/* %pcr */
205 };
206 
207 #define	CPC_TICKREG(ev)		((ev)->ce_tick)
208 #define	CPC_TICKREG_NAME	"%tick"
209 
210 /*
211  * "Well known" bitfields in the UltraSPARC %pcr register
212  * The interfaces in libcpc should make these #defines uninteresting.
213  */
214 #define	CPC_ULTRA_PCR_USR		2
215 #define	CPC_ULTRA_PCR_SYS		1
216 #define	CPC_ULTRA_PCR_PRIVPIC		0
217 
218 #define	CPC_ULTRA_PCR_PIC0_SHIFT	4
219 #define	CPC_ULTRA2_PCR_PIC0_MASK	UINT64_C(0xf)
220 #define	CPC_ULTRA3_PCR_PIC0_MASK	UINT64_C(0x3f)
221 #define	CPC_ULTRA_PCR_PIC1_SHIFT	11
222 #define	CPC_ULTRA2_PCR_PIC1_MASK	UINT64_C(0xf)
223 #define	CPC_ULTRA3_PCR_PIC1_MASK	UINT64_C(0x3f)
224 
225 #elif defined(__i386)
226 
227 /*
228  * Pentium I, II and III processors
229  *
230  * These CPUs allow pairs of events to captured.
231  * The hardware counters count up to 40-bits of significance, but
232  * only allow 32 (signed) bits to be programmed into them.
233  * Pentium I and Pentium II processors are programmed differently, but
234  * the resulting counters and timestamps can be handled portably.
235  */
236 
237 struct _cpc_event {
238 	int ce_cpuver;
239 	hrtime_t ce_hrt;	/* gethrtime() */
240 	uint64_t ce_tsc;	/* virtualized rdtsc value */
241 	uint64_t ce_pic[2];	/* virtualized PerfCtr[01] */
242 	uint32_t ce_pes[2];	/* Pentium II */
243 #define	ce_cesr	ce_pes[0]	/* Pentium I */
244 };
245 
246 #define	CPC_TICKREG(ev)		((ev)->ce_tsc)
247 
248 /*
249  * "Well known" bit fields in the Pentium CES register
250  * The interfaces in libcpc should make these #defines uninteresting.
251  */
252 #define	CPC_P5_CESR_ES0_SHIFT	0
253 #define	CPC_P5_CESR_ES0_MASK	0x3f
254 #define	CPC_P5_CESR_ES1_SHIFT	16
255 #define	CPC_P5_CESR_ES1_MASK	0x3f
256 
257 #define	CPC_P5_CESR_OS0		6
258 #define	CPC_P5_CESR_USR0	7
259 #define	CPC_P5_CESR_CLK0	8
260 #define	CPC_P5_CESR_PC0		9
261 #define	CPC_P5_CESR_OS1		(CPC_P5_CESR_OS0 + 16)
262 #define	CPC_P5_CESR_USR1	(CPC_P5_CESR_USR0 + 16)
263 #define	CPC_P5_CESR_CLK1	(CPC_P5_CESR_CLK0 + 16)
264 #define	CPC_P5_CESR_PC1		(CPC_P5_CESR_PC0 + 16)
265 
266 /*
267  * "Well known" bit fields in the Pentium Pro PerfEvtSel registers
268  * The interfaces in libcpc should make these #defines uninteresting.
269  */
270 #define	CPC_P6_PES_INV		23
271 #define	CPC_P6_PES_EN		22
272 #define	CPC_P6_PES_INT		20
273 #define	CPC_P6_PES_PC		19
274 #define	CPC_P6_PES_E		18
275 #define	CPC_P6_PES_OS		17
276 #define	CPC_P6_PES_USR		16
277 
278 #define	CPC_P6_PES_UMASK_SHIFT	8
279 #define	CPC_P6_PES_UMASK_MASK	(0xffu)
280 
281 #define	CPC_P6_PES_CMASK_SHIFT	24
282 #define	CPC_P6_PES_CMASK_MASK	(0xffu)
283 
284 #define	CPC_P6_PES_PIC0_MASK	(0xffu)
285 #define	CPC_P6_PES_PIC1_MASK	(0xffu)
286 
287 #endif /* __i386 */
288 
289 #ifdef	__cplusplus
290 }
291 #endif
292 
293 #endif	/* _LIBCPC_IMPL_H */
294