1 /* $Id: tg3.h,v 1.3 2003/02/25 06:02:58 ebiederm Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@mandrakesoft.com) 6 */ 7 8 #ifndef _T3_H 9 #define _T3_H 10 11 #include "stdint.h" 12 13 typedef unsigned long dma_addr_t; 14 15 /* From mii.h */ 16 17 /* Indicates what features are advertised by the interface. */ 18 #define ADVERTISED_10baseT_Half (1 << 0) 19 #define ADVERTISED_10baseT_Full (1 << 1) 20 #define ADVERTISED_100baseT_Half (1 << 2) 21 #define ADVERTISED_100baseT_Full (1 << 3) 22 #define ADVERTISED_1000baseT_Half (1 << 4) 23 #define ADVERTISED_1000baseT_Full (1 << 5) 24 #define ADVERTISED_Autoneg (1 << 6) 25 #define ADVERTISED_TP (1 << 7) 26 #define ADVERTISED_AUI (1 << 8) 27 #define ADVERTISED_MII (1 << 9) 28 #define ADVERTISED_FIBRE (1 << 10) 29 #define ADVERTISED_BNC (1 << 11) 30 31 /* The following are all involved in forcing a particular link 32 * mode for the device for setting things. When getting the 33 * devices settings, these indicate the current mode and whether 34 * it was foced up into this mode or autonegotiated. 35 */ 36 37 /* The forced speed, 10Mb, 100Mb, gigabit. */ 38 #define SPEED_10 0 39 #define SPEED_100 1 40 #define SPEED_1000 2 41 #define SPEED_INVALID 3 42 43 44 /* Duplex, half or full. */ 45 #define DUPLEX_HALF 0x00 46 #define DUPLEX_FULL 0x01 47 #define DUPLEX_INVALID 0x02 48 49 /* Which connector port. */ 50 #define PORT_TP 0x00 51 #define PORT_AUI 0x01 52 #define PORT_MII 0x02 53 #define PORT_FIBRE 0x03 54 #define PORT_BNC 0x04 55 56 /* Which tranceiver to use. */ 57 #define XCVR_INTERNAL 0x00 58 #define XCVR_EXTERNAL 0x01 59 #define XCVR_DUMMY1 0x02 60 #define XCVR_DUMMY2 0x03 61 #define XCVR_DUMMY3 0x04 62 63 /* Enable or disable autonegotiation. If this is set to enable, 64 * the forced link modes above are completely ignored. 65 */ 66 #define AUTONEG_DISABLE 0x00 67 #define AUTONEG_ENABLE 0x01 68 69 /* Wake-On-Lan options. */ 70 #define WAKE_PHY (1 << 0) 71 #define WAKE_UCAST (1 << 1) 72 #define WAKE_MCAST (1 << 2) 73 #define WAKE_BCAST (1 << 3) 74 #define WAKE_ARP (1 << 4) 75 #define WAKE_MAGIC (1 << 5) 76 #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ 77 78 /* Generic MII registers. */ 79 80 #define MII_BMCR 0x00 /* Basic mode control register */ 81 #define MII_BMSR 0x01 /* Basic mode status register */ 82 #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 83 #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 84 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 85 #define MII_LPA 0x05 /* Link partner ability reg */ 86 #define MII_EXPANSION 0x06 /* Expansion register */ 87 #define MII_DCOUNTER 0x12 /* Disconnect counter */ 88 #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 89 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 90 #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 91 #define MII_SREVISION 0x16 /* Silicon revision */ 92 #define MII_RESV1 0x17 /* Reserved... */ 93 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 94 #define MII_PHYADDR 0x19 /* PHY address */ 95 #define MII_RESV2 0x1a /* Reserved... */ 96 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 97 #define MII_NCONFIG 0x1c /* Network interface config */ 98 99 /* Basic mode control register. */ 100 #define BMCR_RESV 0x007f /* Unused... */ 101 #define BMCR_CTST 0x0080 /* Collision test */ 102 #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 103 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 104 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ 105 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ 106 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 107 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 108 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 109 #define BMCR_RESET 0x8000 /* Reset the DP83840 */ 110 111 /* Basic mode status register. */ 112 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 113 #define BMSR_JCD 0x0002 /* Jabber detected */ 114 #define BMSR_LSTATUS 0x0004 /* Link status */ 115 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 116 #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 117 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 118 #define BMSR_RESV 0x07c0 /* Unused... */ 119 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 120 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 121 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 122 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 123 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 124 125 /* Advertisement control register. */ 126 #define ADVERTISE_SLCT 0x001f /* Selector bits */ 127 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 128 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 129 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 130 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 131 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 132 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 133 #define ADVERTISE_RESV 0x1c00 /* Unused... */ 134 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 135 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 136 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 137 138 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 139 ADVERTISE_CSMA) 140 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 141 ADVERTISE_100HALF | ADVERTISE_100FULL) 142 143 /* Link partner ability register. */ 144 #define LPA_SLCT 0x001f /* Same as advertise selector */ 145 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 146 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 147 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 148 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 149 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 150 #define LPA_RESV 0x1c00 /* Unused... */ 151 #define LPA_RFAULT 0x2000 /* Link partner faulted */ 152 #define LPA_LPACK 0x4000 /* Link partner acked us */ 153 #define LPA_NPAGE 0x8000 /* Next page bit */ 154 155 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 156 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 157 158 /* Expansion register for auto-negotiation. */ 159 #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 160 #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 161 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 162 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 163 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 164 #define EXPANSION_RESV 0xffe0 /* Unused... */ 165 166 /* N-way test register. */ 167 #define NWAYTEST_RESV1 0x00ff /* Unused... */ 168 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ 169 #define NWAYTEST_RESV2 0xfe00 /* Unused... */ 170 171 172 /* From tg3.h */ 173 174 #define TG3_64BIT_REG_HIGH 0x00UL 175 #define TG3_64BIT_REG_LOW 0x04UL 176 177 /* Descriptor block info. */ 178 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 179 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 180 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 181 #define BDINFO_FLAGS_DISABLED 0x00000002 182 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 183 #define BDINFO_FLAGS_MAXLEN_SHIFT 16 184 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 185 #define TG3_BDINFO_SIZE 0x10UL 186 187 #define RX_COPY_THRESHOLD 256 188 189 #define RX_STD_MAX_SIZE 1536 190 #define RX_STD_MAX_SIZE_5705 512 191 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ 192 193 /* First 256 bytes are a mirror of PCI config space. */ 194 #define TG3PCI_VENDOR 0x00000000 195 #define TG3PCI_VENDOR_BROADCOM 0x14e4 196 #define TG3PCI_DEVICE 0x00000002 197 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 198 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 199 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 200 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 201 #define TG3PCI_COMMAND 0x00000004 202 #define TG3PCI_STATUS 0x00000006 203 #define TG3PCI_CCREVID 0x00000008 204 #define TG3PCI_CACHELINESZ 0x0000000c 205 #define TG3PCI_LATTIMER 0x0000000d 206 #define TG3PCI_HEADERTYPE 0x0000000e 207 #define TG3PCI_BIST 0x0000000f 208 #define TG3PCI_BASE0_LOW 0x00000010 209 #define TG3PCI_BASE0_HIGH 0x00000014 210 /* 0x18 --> 0x2c unused */ 211 #define TG3PCI_SUBSYSVENID 0x0000002c 212 #define TG3PCI_SUBSYSID 0x0000002e 213 #define TG3PCI_ROMADDR 0x00000030 214 #define TG3PCI_CAPLIST 0x00000034 215 /* 0x35 --> 0x3c unused */ 216 #define TG3PCI_IRQ_LINE 0x0000003c 217 #define TG3PCI_IRQ_PIN 0x0000003d 218 #define TG3PCI_MIN_GNT 0x0000003e 219 #define TG3PCI_MAX_LAT 0x0000003f 220 #define TG3PCI_X_CAPS 0x00000040 221 #define PCIX_CAPS_RELAXED_ORDERING 0x00020000 222 #define PCIX_CAPS_SPLIT_MASK 0x00700000 223 #define PCIX_CAPS_SPLIT_SHIFT 20 224 #define PCIX_CAPS_BURST_MASK 0x000c0000 225 #define PCIX_CAPS_BURST_SHIFT 18 226 #define PCIX_CAPS_MAX_BURST_CPIOB 2 227 #define TG3PCI_PM_CAP_PTR 0x00000041 228 #define TG3PCI_X_COMMAND 0x00000042 229 #define TG3PCI_X_STATUS 0x00000044 230 #define TG3PCI_PM_CAP_ID 0x00000048 231 #define TG3PCI_VPD_CAP_PTR 0x00000049 232 #define TG3PCI_PM_CAPS 0x0000004a 233 #define TG3PCI_PM_CTRL_STAT 0x0000004c 234 #define TG3PCI_BR_SUPP_EXT 0x0000004e 235 #define TG3PCI_PM_DATA 0x0000004f 236 #define TG3PCI_VPD_CAP_ID 0x00000050 237 #define TG3PCI_MSI_CAP_PTR 0x00000051 238 #define TG3PCI_VPD_ADDR_FLAG 0x00000052 239 #define VPD_ADDR_FLAG_WRITE 0x00008000 240 #define TG3PCI_VPD_DATA 0x00000054 241 #define TG3PCI_MSI_CAP_ID 0x00000058 242 #define TG3PCI_NXT_CAP_PTR 0x00000059 243 #define TG3PCI_MSI_CTRL 0x0000005a 244 #define TG3PCI_MSI_ADDR_LOW 0x0000005c 245 #define TG3PCI_MSI_ADDR_HIGH 0x00000060 246 #define TG3PCI_MSI_DATA 0x00000064 247 /* 0x66 --> 0x68 unused */ 248 #define TG3PCI_MISC_HOST_CTRL 0x00000068 249 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 250 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 251 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 252 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 253 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 254 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 255 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 256 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 257 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 258 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 259 #define MISC_HOST_CTRL_CHIPREV 0xffff0000 260 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 261 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ 262 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ 263 MISC_HOST_CTRL_CHIPREV_SHIFT) 264 #define CHIPREV_ID_5700_A0 0x7000 265 #define CHIPREV_ID_5700_A1 0x7001 266 #define CHIPREV_ID_5700_B0 0x7100 267 #define CHIPREV_ID_5700_B1 0x7101 268 #define CHIPREV_ID_5700_B3 0x7102 269 #define CHIPREV_ID_5700_ALTIMA 0x7104 270 #define CHIPREV_ID_5700_C0 0x7200 271 #define CHIPREV_ID_5701_A0 0x0000 272 #define CHIPREV_ID_5701_B0 0x0100 273 #define CHIPREV_ID_5701_B2 0x0102 274 #define CHIPREV_ID_5701_B5 0x0105 275 #define CHIPREV_ID_5703_A0 0x1000 276 #define CHIPREV_ID_5703_A1 0x1001 277 #define CHIPREV_ID_5703_A2 0x1002 278 #define CHIPREV_ID_5703_A3 0x1003 279 #define CHIPREV_ID_5704_A0 0x2000 280 #define CHIPREV_ID_5704_A1 0x2001 281 #define CHIPREV_ID_5704_A2 0x2002 282 #define CHIPREV_ID_5705_A0 0x3000 283 #define CHIPREV_ID_5705_A1 0x3001 284 #define CHIPREV_ID_5705_A2 0x3002 285 #define CHIPREV_ID_5705_A3 0x3003 286 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 287 #define ASIC_REV_5700 0x07 288 #define ASIC_REV_5701 0x00 289 #define ASIC_REV_5703 0x01 290 #define ASIC_REV_5704 0x02 291 #define ASIC_REV_5705 0x03 292 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 293 #define CHIPREV_5700_AX 0x70 294 #define CHIPREV_5700_BX 0x71 295 #define CHIPREV_5700_CX 0x72 296 #define CHIPREV_5701_AX 0x00 297 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) 298 #define METAL_REV_A0 0x00 299 #define METAL_REV_A1 0x01 300 #define METAL_REV_B0 0x00 301 #define METAL_REV_B1 0x01 302 #define METAL_REV_B2 0x02 303 #define TG3PCI_DMA_RW_CTRL 0x0000006c 304 #define DMA_RWCTRL_MIN_DMA 0x000000ff 305 #define DMA_RWCTRL_MIN_DMA_SHIFT 0 306 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 307 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 308 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 309 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 310 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 311 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 312 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 313 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 314 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 315 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 316 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 317 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 318 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 319 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 320 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 321 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 322 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 323 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 324 #define DMA_RWCTRL_ONE_DMA 0x00004000 325 #define DMA_RWCTRL_READ_WATER 0x00070000 326 #define DMA_RWCTRL_READ_WATER_SHIFT 16 327 #define DMA_RWCTRL_WRITE_WATER 0x00380000 328 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 329 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 330 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 331 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 332 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 333 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 334 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 335 #define TG3PCI_PCISTATE 0x00000070 336 #define PCISTATE_FORCE_RESET 0x00000001 337 #define PCISTATE_INT_NOT_ACTIVE 0x00000002 338 #define PCISTATE_CONV_PCI_MODE 0x00000004 339 #define PCISTATE_BUS_SPEED_HIGH 0x00000008 340 #define PCISTATE_BUS_32BIT 0x00000010 341 #define PCISTATE_ROM_ENABLE 0x00000020 342 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 343 #define PCISTATE_FLAT_VIEW 0x00000100 344 #define PCISTATE_RETRY_SAME_DMA 0x00002000 345 #define TG3PCI_CLOCK_CTRL 0x00000074 346 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 347 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 348 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 349 #define CLOCK_CTRL_ALTCLK 0x00001000 350 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 351 #define CLOCK_CTRL_44MHZ_CORE 0x00040000 352 #define CLOCK_CTRL_625_CORE 0x00100000 353 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 354 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 355 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 356 #define TG3PCI_REG_BASE_ADDR 0x00000078 357 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 358 #define TG3PCI_REG_DATA 0x00000080 359 #define TG3PCI_MEM_WIN_DATA 0x00000084 360 #define TG3PCI_MODE_CTRL 0x00000088 361 #define TG3PCI_MISC_CFG 0x0000008c 362 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 363 /* 0x94 --> 0x98 unused */ 364 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 365 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 366 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */ 367 /* 0xb0 --> 0x100 unused */ 368 369 /* 0x100 --> 0x200 unused */ 370 371 /* Mailbox registers */ 372 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 373 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 374 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 375 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 376 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 377 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 378 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 379 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 380 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 381 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 382 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 383 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 384 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 385 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 386 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 387 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 388 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 389 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 390 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 391 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 392 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 393 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 394 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 395 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 396 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 397 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 398 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 399 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 400 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 401 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 402 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 403 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 404 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 405 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 406 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 407 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 408 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 409 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 410 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 411 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 412 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 413 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 414 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 415 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 416 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 417 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 418 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 419 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 420 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 421 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 422 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 423 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 424 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 425 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 426 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 427 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 428 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 429 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 430 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 431 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 432 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 433 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 434 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 435 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 436 437 /* MAC control registers */ 438 #define MAC_MODE 0x00000400 439 #define MAC_MODE_RESET 0x00000001 440 #define MAC_MODE_HALF_DUPLEX 0x00000002 441 #define MAC_MODE_PORT_MODE_MASK 0x0000000c 442 #define MAC_MODE_PORT_MODE_TBI 0x0000000c 443 #define MAC_MODE_PORT_MODE_GMII 0x00000008 444 #define MAC_MODE_PORT_MODE_MII 0x00000004 445 #define MAC_MODE_PORT_MODE_NONE 0x00000000 446 #define MAC_MODE_PORT_INT_LPBACK 0x00000010 447 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 448 #define MAC_MODE_TX_BURSTING 0x00000100 449 #define MAC_MODE_MAX_DEFER 0x00000200 450 #define MAC_MODE_LINK_POLARITY 0x00000400 451 #define MAC_MODE_RXSTAT_ENABLE 0x00000800 452 #define MAC_MODE_RXSTAT_CLEAR 0x00001000 453 #define MAC_MODE_RXSTAT_FLUSH 0x00002000 454 #define MAC_MODE_TXSTAT_ENABLE 0x00004000 455 #define MAC_MODE_TXSTAT_CLEAR 0x00008000 456 #define MAC_MODE_TXSTAT_FLUSH 0x00010000 457 #define MAC_MODE_SEND_CONFIGS 0x00020000 458 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 459 #define MAC_MODE_ACPI_ENABLE 0x00080000 460 #define MAC_MODE_MIP_ENABLE 0x00100000 461 #define MAC_MODE_TDE_ENABLE 0x00200000 462 #define MAC_MODE_RDE_ENABLE 0x00400000 463 #define MAC_MODE_FHDE_ENABLE 0x00800000 464 #define MAC_STATUS 0x00000404 465 #define MAC_STATUS_PCS_SYNCED 0x00000001 466 #define MAC_STATUS_SIGNAL_DET 0x00000002 467 #define MAC_STATUS_RCVD_CFG 0x00000004 468 #define MAC_STATUS_CFG_CHANGED 0x00000008 469 #define MAC_STATUS_SYNC_CHANGED 0x00000010 470 #define MAC_STATUS_PORT_DEC_ERR 0x00000400 471 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 472 #define MAC_STATUS_MI_COMPLETION 0x00400000 473 #define MAC_STATUS_MI_INTERRUPT 0x00800000 474 #define MAC_STATUS_AP_ERROR 0x01000000 475 #define MAC_STATUS_ODI_ERROR 0x02000000 476 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 477 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 478 #define MAC_EVENT 0x00000408 479 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 480 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 481 #define MAC_EVENT_MI_COMPLETION 0x00400000 482 #define MAC_EVENT_MI_INTERRUPT 0x00800000 483 #define MAC_EVENT_AP_ERROR 0x01000000 484 #define MAC_EVENT_ODI_ERROR 0x02000000 485 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 486 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 487 #define MAC_LED_CTRL 0x0000040c 488 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 489 #define LED_CTRL_1000MBPS_ON 0x00000002 490 #define LED_CTRL_100MBPS_ON 0x00000004 491 #define LED_CTRL_10MBPS_ON 0x00000008 492 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 493 #define LED_CTRL_TRAFFIC_BLINK 0x00000020 494 #define LED_CTRL_TRAFFIC_LED 0x00000040 495 #define LED_CTRL_1000MBPS_STATUS 0x00000080 496 #define LED_CTRL_100MBPS_STATUS 0x00000100 497 #define LED_CTRL_10MBPS_STATUS 0x00000200 498 #define LED_CTRL_TRAFFIC_STATUS 0x00000400 499 #define LED_CTRL_MAC_MODE 0x00000000 500 #define LED_CTRL_PHY_MODE_1 0x00000800 501 #define LED_CTRL_PHY_MODE_2 0x00001000 502 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 503 #define LED_CTRL_BLINK_RATE_SHIFT 19 504 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 505 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 506 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 507 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 508 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 509 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 510 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 511 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 512 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 513 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 514 #define MAC_ACPI_MBUF_PTR 0x00000430 515 #define MAC_ACPI_LEN_OFFSET 0x00000434 516 #define ACPI_LENOFF_LEN_MASK 0x0000ffff 517 #define ACPI_LENOFF_LEN_SHIFT 0 518 #define ACPI_LENOFF_OFF_MASK 0x0fff0000 519 #define ACPI_LENOFF_OFF_SHIFT 16 520 #define MAC_TX_BACKOFF_SEED 0x00000438 521 #define TX_BACKOFF_SEED_MASK 0x000003ff 522 #define MAC_RX_MTU_SIZE 0x0000043c 523 #define RX_MTU_SIZE_MASK 0x0000ffff 524 #define MAC_PCS_TEST 0x00000440 525 #define PCS_TEST_PATTERN_MASK 0x000fffff 526 #define PCS_TEST_PATTERN_SHIFT 0 527 #define PCS_TEST_ENABLE 0x00100000 528 #define MAC_TX_AUTO_NEG 0x00000444 529 #define TX_AUTO_NEG_MASK 0x0000ffff 530 #define TX_AUTO_NEG_SHIFT 0 531 #define MAC_RX_AUTO_NEG 0x00000448 532 #define RX_AUTO_NEG_MASK 0x0000ffff 533 #define RX_AUTO_NEG_SHIFT 0 534 #define MAC_MI_COM 0x0000044c 535 #define MI_COM_CMD_MASK 0x0c000000 536 #define MI_COM_CMD_WRITE 0x04000000 537 #define MI_COM_CMD_READ 0x08000000 538 #define MI_COM_READ_FAILED 0x10000000 539 #define MI_COM_START 0x20000000 540 #define MI_COM_BUSY 0x20000000 541 #define MI_COM_PHY_ADDR_MASK 0x03e00000 542 #define MI_COM_PHY_ADDR_SHIFT 21 543 #define MI_COM_REG_ADDR_MASK 0x001f0000 544 #define MI_COM_REG_ADDR_SHIFT 16 545 #define MI_COM_DATA_MASK 0x0000ffff 546 #define MAC_MI_STAT 0x00000450 547 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 548 #define MAC_MI_MODE 0x00000454 549 #define MAC_MI_MODE_CLK_10MHZ 0x00000001 550 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 551 #define MAC_MI_MODE_AUTO_POLL 0x00000010 552 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000 553 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 554 #define MAC_AUTO_POLL_STATUS 0x00000458 555 #define MAC_AUTO_POLL_ERROR 0x00000001 556 #define MAC_TX_MODE 0x0000045c 557 #define TX_MODE_RESET 0x00000001 558 #define TX_MODE_ENABLE 0x00000002 559 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 560 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 561 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 562 #define MAC_TX_STATUS 0x00000460 563 #define TX_STATUS_XOFFED 0x00000001 564 #define TX_STATUS_SENT_XOFF 0x00000002 565 #define TX_STATUS_SENT_XON 0x00000004 566 #define TX_STATUS_LINK_UP 0x00000008 567 #define TX_STATUS_ODI_UNDERRUN 0x00000010 568 #define TX_STATUS_ODI_OVERRUN 0x00000020 569 #define MAC_TX_LENGTHS 0x00000464 570 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 571 #define TX_LENGTHS_SLOT_TIME_SHIFT 0 572 #define TX_LENGTHS_IPG_MASK 0x00000f00 573 #define TX_LENGTHS_IPG_SHIFT 8 574 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 575 #define TX_LENGTHS_IPG_CRS_SHIFT 12 576 #define MAC_RX_MODE 0x00000468 577 #define RX_MODE_RESET 0x00000001 578 #define RX_MODE_ENABLE 0x00000002 579 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 580 #define RX_MODE_KEEP_MAC_CTRL 0x00000008 581 #define RX_MODE_KEEP_PAUSE 0x00000010 582 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 583 #define RX_MODE_ACCEPT_RUNTS 0x00000040 584 #define RX_MODE_LEN_CHECK 0x00000080 585 #define RX_MODE_PROMISC 0x00000100 586 #define RX_MODE_NO_CRC_CHECK 0x00000200 587 #define RX_MODE_KEEP_VLAN_TAG 0x00000400 588 #define MAC_RX_STATUS 0x0000046c 589 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 590 #define RX_STATUS_XOFF_RCVD 0x00000002 591 #define RX_STATUS_XON_RCVD 0x00000004 592 #define MAC_HASH_REG_0 0x00000470 593 #define MAC_HASH_REG_1 0x00000474 594 #define MAC_HASH_REG_2 0x00000478 595 #define MAC_HASH_REG_3 0x0000047c 596 #define MAC_RCV_RULE_0 0x00000480 597 #define MAC_RCV_VALUE_0 0x00000484 598 #define MAC_RCV_RULE_1 0x00000488 599 #define MAC_RCV_VALUE_1 0x0000048c 600 #define MAC_RCV_RULE_2 0x00000490 601 #define MAC_RCV_VALUE_2 0x00000494 602 #define MAC_RCV_RULE_3 0x00000498 603 #define MAC_RCV_VALUE_3 0x0000049c 604 #define MAC_RCV_RULE_4 0x000004a0 605 #define MAC_RCV_VALUE_4 0x000004a4 606 #define MAC_RCV_RULE_5 0x000004a8 607 #define MAC_RCV_VALUE_5 0x000004ac 608 #define MAC_RCV_RULE_6 0x000004b0 609 #define MAC_RCV_VALUE_6 0x000004b4 610 #define MAC_RCV_RULE_7 0x000004b8 611 #define MAC_RCV_VALUE_7 0x000004bc 612 #define MAC_RCV_RULE_8 0x000004c0 613 #define MAC_RCV_VALUE_8 0x000004c4 614 #define MAC_RCV_RULE_9 0x000004c8 615 #define MAC_RCV_VALUE_9 0x000004cc 616 #define MAC_RCV_RULE_10 0x000004d0 617 #define MAC_RCV_VALUE_10 0x000004d4 618 #define MAC_RCV_RULE_11 0x000004d8 619 #define MAC_RCV_VALUE_11 0x000004dc 620 #define MAC_RCV_RULE_12 0x000004e0 621 #define MAC_RCV_VALUE_12 0x000004e4 622 #define MAC_RCV_RULE_13 0x000004e8 623 #define MAC_RCV_VALUE_13 0x000004ec 624 #define MAC_RCV_RULE_14 0x000004f0 625 #define MAC_RCV_VALUE_14 0x000004f4 626 #define MAC_RCV_RULE_15 0x000004f8 627 #define MAC_RCV_VALUE_15 0x000004fc 628 #define RCV_RULE_DISABLE_MASK 0x7fffffff 629 #define MAC_RCV_RULE_CFG 0x00000500 630 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 631 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 632 /* 0x508 --> 0x520 unused */ 633 #define MAC_HASHREGU_0 0x00000520 634 #define MAC_HASHREGU_1 0x00000524 635 #define MAC_HASHREGU_2 0x00000528 636 #define MAC_HASHREGU_3 0x0000052c 637 #define MAC_EXTADDR_0_HIGH 0x00000530 638 #define MAC_EXTADDR_0_LOW 0x00000534 639 #define MAC_EXTADDR_1_HIGH 0x00000538 640 #define MAC_EXTADDR_1_LOW 0x0000053c 641 #define MAC_EXTADDR_2_HIGH 0x00000540 642 #define MAC_EXTADDR_2_LOW 0x00000544 643 #define MAC_EXTADDR_3_HIGH 0x00000548 644 #define MAC_EXTADDR_3_LOW 0x0000054c 645 #define MAC_EXTADDR_4_HIGH 0x00000550 646 #define MAC_EXTADDR_4_LOW 0x00000554 647 #define MAC_EXTADDR_5_HIGH 0x00000558 648 #define MAC_EXTADDR_5_LOW 0x0000055c 649 #define MAC_EXTADDR_6_HIGH 0x00000560 650 #define MAC_EXTADDR_6_LOW 0x00000564 651 #define MAC_EXTADDR_7_HIGH 0x00000568 652 #define MAC_EXTADDR_7_LOW 0x0000056c 653 #define MAC_EXTADDR_8_HIGH 0x00000570 654 #define MAC_EXTADDR_8_LOW 0x00000574 655 #define MAC_EXTADDR_9_HIGH 0x00000578 656 #define MAC_EXTADDR_9_LOW 0x0000057c 657 #define MAC_EXTADDR_10_HIGH 0x00000580 658 #define MAC_EXTADDR_10_LOW 0x00000584 659 #define MAC_EXTADDR_11_HIGH 0x00000588 660 #define MAC_EXTADDR_11_LOW 0x0000058c 661 #define MAC_SERDES_CFG 0x00000590 662 #define MAC_SERDES_STAT 0x00000594 663 /* 0x598 --> 0x600 unused */ 664 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 665 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 666 /* 0x624 --> 0x800 unused */ 667 #define MAC_TX_STATS_OCTETS 0x00000800 668 #define MAC_TX_STATS_RESV1 0x00000804 669 #define MAC_TX_STATS_COLLISIONS 0x00000808 670 #define MAC_TX_STATS_XON_SENT 0x0000080c 671 #define MAC_TX_STATS_XOFF_SENT 0x00000810 672 #define MAC_TX_STATS_RESV2 0x00000814 673 #define MAC_TX_STATS_MAC_ERRORS 0x00000818 674 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 675 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 676 #define MAC_TX_STATS_DEFERRED 0x00000824 677 #define MAC_TX_STATS_RESV3 0x00000828 678 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 679 #define MAC_TX_STATS_LATE_COL 0x00000830 680 #define MAC_TX_STATS_RESV4_1 0x00000834 681 #define MAC_TX_STATS_RESV4_2 0x00000838 682 #define MAC_TX_STATS_RESV4_3 0x0000083c 683 #define MAC_TX_STATS_RESV4_4 0x00000840 684 #define MAC_TX_STATS_RESV4_5 0x00000844 685 #define MAC_TX_STATS_RESV4_6 0x00000848 686 #define MAC_TX_STATS_RESV4_7 0x0000084c 687 #define MAC_TX_STATS_RESV4_8 0x00000850 688 #define MAC_TX_STATS_RESV4_9 0x00000854 689 #define MAC_TX_STATS_RESV4_10 0x00000858 690 #define MAC_TX_STATS_RESV4_11 0x0000085c 691 #define MAC_TX_STATS_RESV4_12 0x00000860 692 #define MAC_TX_STATS_RESV4_13 0x00000864 693 #define MAC_TX_STATS_RESV4_14 0x00000868 694 #define MAC_TX_STATS_UCAST 0x0000086c 695 #define MAC_TX_STATS_MCAST 0x00000870 696 #define MAC_TX_STATS_BCAST 0x00000874 697 #define MAC_TX_STATS_RESV5_1 0x00000878 698 #define MAC_TX_STATS_RESV5_2 0x0000087c 699 #define MAC_RX_STATS_OCTETS 0x00000880 700 #define MAC_RX_STATS_RESV1 0x00000884 701 #define MAC_RX_STATS_FRAGMENTS 0x00000888 702 #define MAC_RX_STATS_UCAST 0x0000088c 703 #define MAC_RX_STATS_MCAST 0x00000890 704 #define MAC_RX_STATS_BCAST 0x00000894 705 #define MAC_RX_STATS_FCS_ERRORS 0x00000898 706 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 707 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 708 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 709 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 710 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 711 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 712 #define MAC_RX_STATS_JABBERS 0x000008b4 713 #define MAC_RX_STATS_UNDERSIZE 0x000008b8 714 /* 0x8bc --> 0xc00 unused */ 715 716 /* Send data initiator control registers */ 717 #define SNDDATAI_MODE 0x00000c00 718 #define SNDDATAI_MODE_RESET 0x00000001 719 #define SNDDATAI_MODE_ENABLE 0x00000002 720 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 721 #define SNDDATAI_STATUS 0x00000c04 722 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 723 #define SNDDATAI_STATSCTRL 0x00000c08 724 #define SNDDATAI_SCTRL_ENABLE 0x00000001 725 #define SNDDATAI_SCTRL_FASTUPD 0x00000002 726 #define SNDDATAI_SCTRL_CLEAR 0x00000004 727 #define SNDDATAI_SCTRL_FLUSH 0x00000008 728 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 729 #define SNDDATAI_STATSENAB 0x00000c0c 730 #define SNDDATAI_STATSINCMASK 0x00000c10 731 /* 0xc14 --> 0xc80 unused */ 732 #define SNDDATAI_COS_CNT_0 0x00000c80 733 #define SNDDATAI_COS_CNT_1 0x00000c84 734 #define SNDDATAI_COS_CNT_2 0x00000c88 735 #define SNDDATAI_COS_CNT_3 0x00000c8c 736 #define SNDDATAI_COS_CNT_4 0x00000c90 737 #define SNDDATAI_COS_CNT_5 0x00000c94 738 #define SNDDATAI_COS_CNT_6 0x00000c98 739 #define SNDDATAI_COS_CNT_7 0x00000c9c 740 #define SNDDATAI_COS_CNT_8 0x00000ca0 741 #define SNDDATAI_COS_CNT_9 0x00000ca4 742 #define SNDDATAI_COS_CNT_10 0x00000ca8 743 #define SNDDATAI_COS_CNT_11 0x00000cac 744 #define SNDDATAI_COS_CNT_12 0x00000cb0 745 #define SNDDATAI_COS_CNT_13 0x00000cb4 746 #define SNDDATAI_COS_CNT_14 0x00000cb8 747 #define SNDDATAI_COS_CNT_15 0x00000cbc 748 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 749 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 750 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 751 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 752 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 753 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 754 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 755 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 756 /* 0xce0 --> 0x1000 unused */ 757 758 /* Send data completion control registers */ 759 #define SNDDATAC_MODE 0x00001000 760 #define SNDDATAC_MODE_RESET 0x00000001 761 #define SNDDATAC_MODE_ENABLE 0x00000002 762 /* 0x1004 --> 0x1400 unused */ 763 764 /* Send BD ring selector */ 765 #define SNDBDS_MODE 0x00001400 766 #define SNDBDS_MODE_RESET 0x00000001 767 #define SNDBDS_MODE_ENABLE 0x00000002 768 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 769 #define SNDBDS_STATUS 0x00001404 770 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 771 #define SNDBDS_HWDIAG 0x00001408 772 /* 0x140c --> 0x1440 */ 773 #define SNDBDS_SEL_CON_IDX_0 0x00001440 774 #define SNDBDS_SEL_CON_IDX_1 0x00001444 775 #define SNDBDS_SEL_CON_IDX_2 0x00001448 776 #define SNDBDS_SEL_CON_IDX_3 0x0000144c 777 #define SNDBDS_SEL_CON_IDX_4 0x00001450 778 #define SNDBDS_SEL_CON_IDX_5 0x00001454 779 #define SNDBDS_SEL_CON_IDX_6 0x00001458 780 #define SNDBDS_SEL_CON_IDX_7 0x0000145c 781 #define SNDBDS_SEL_CON_IDX_8 0x00001460 782 #define SNDBDS_SEL_CON_IDX_9 0x00001464 783 #define SNDBDS_SEL_CON_IDX_10 0x00001468 784 #define SNDBDS_SEL_CON_IDX_11 0x0000146c 785 #define SNDBDS_SEL_CON_IDX_12 0x00001470 786 #define SNDBDS_SEL_CON_IDX_13 0x00001474 787 #define SNDBDS_SEL_CON_IDX_14 0x00001478 788 #define SNDBDS_SEL_CON_IDX_15 0x0000147c 789 /* 0x1480 --> 0x1800 unused */ 790 791 /* Send BD initiator control registers */ 792 #define SNDBDI_MODE 0x00001800 793 #define SNDBDI_MODE_RESET 0x00000001 794 #define SNDBDI_MODE_ENABLE 0x00000002 795 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 796 #define SNDBDI_STATUS 0x00001804 797 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 798 #define SNDBDI_IN_PROD_IDX_0 0x00001808 799 #define SNDBDI_IN_PROD_IDX_1 0x0000180c 800 #define SNDBDI_IN_PROD_IDX_2 0x00001810 801 #define SNDBDI_IN_PROD_IDX_3 0x00001814 802 #define SNDBDI_IN_PROD_IDX_4 0x00001818 803 #define SNDBDI_IN_PROD_IDX_5 0x0000181c 804 #define SNDBDI_IN_PROD_IDX_6 0x00001820 805 #define SNDBDI_IN_PROD_IDX_7 0x00001824 806 #define SNDBDI_IN_PROD_IDX_8 0x00001828 807 #define SNDBDI_IN_PROD_IDX_9 0x0000182c 808 #define SNDBDI_IN_PROD_IDX_10 0x00001830 809 #define SNDBDI_IN_PROD_IDX_11 0x00001834 810 #define SNDBDI_IN_PROD_IDX_12 0x00001838 811 #define SNDBDI_IN_PROD_IDX_13 0x0000183c 812 #define SNDBDI_IN_PROD_IDX_14 0x00001840 813 #define SNDBDI_IN_PROD_IDX_15 0x00001844 814 /* 0x1848 --> 0x1c00 unused */ 815 816 /* Send BD completion control registers */ 817 #define SNDBDC_MODE 0x00001c00 818 #define SNDBDC_MODE_RESET 0x00000001 819 #define SNDBDC_MODE_ENABLE 0x00000002 820 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 821 /* 0x1c04 --> 0x2000 unused */ 822 823 /* Receive list placement control registers */ 824 #define RCVLPC_MODE 0x00002000 825 #define RCVLPC_MODE_RESET 0x00000001 826 #define RCVLPC_MODE_ENABLE 0x00000002 827 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 828 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 829 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 830 #define RCVLPC_STATUS 0x00002004 831 #define RCVLPC_STATUS_CLASS0 0x00000004 832 #define RCVLPC_STATUS_MAPOOR 0x00000008 833 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 834 #define RCVLPC_LOCK 0x00002008 835 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff 836 #define RCVLPC_LOCK_REQ_SHIFT 0 837 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 838 #define RCVLPC_LOCK_GRANT_SHIFT 16 839 #define RCVLPC_NON_EMPTY_BITS 0x0000200c 840 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 841 #define RCVLPC_CONFIG 0x00002010 842 #define RCVLPC_STATSCTRL 0x00002014 843 #define RCVLPC_STATSCTRL_ENABLE 0x00000001 844 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 845 #define RCVLPC_STATS_ENABLE 0x00002018 846 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 847 #define RCVLPC_STATS_INCMASK 0x0000201c 848 /* 0x2020 --> 0x2100 unused */ 849 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 850 #define SELLST_TAIL 0x00000004 851 #define SELLST_CONT 0x00000008 852 #define SELLST_UNUSED 0x0000000c 853 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 854 #define RCVLPC_DROP_FILTER_CNT 0x00002240 855 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 856 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 857 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c 858 #define RCVLPC_IN_DISCARDS_CNT 0x00002250 859 #define RCVLPC_IN_ERRORS_CNT 0x00002254 860 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 861 /* 0x225c --> 0x2400 unused */ 862 863 /* Receive Data and Receive BD Initiator Control */ 864 #define RCVDBDI_MODE 0x00002400 865 #define RCVDBDI_MODE_RESET 0x00000001 866 #define RCVDBDI_MODE_ENABLE 0x00000002 867 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 868 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 869 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 870 #define RCVDBDI_STATUS 0x00002404 871 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 872 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 873 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 874 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 875 /* 0x240c --> 0x2440 unused */ 876 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 877 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 878 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 879 #define RCVDBDI_JUMBO_CON_IDX 0x00002470 880 #define RCVDBDI_STD_CON_IDX 0x00002474 881 #define RCVDBDI_MINI_CON_IDX 0x00002478 882 /* 0x247c --> 0x2480 unused */ 883 #define RCVDBDI_BD_PROD_IDX_0 0x00002480 884 #define RCVDBDI_BD_PROD_IDX_1 0x00002484 885 #define RCVDBDI_BD_PROD_IDX_2 0x00002488 886 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c 887 #define RCVDBDI_BD_PROD_IDX_4 0x00002490 888 #define RCVDBDI_BD_PROD_IDX_5 0x00002494 889 #define RCVDBDI_BD_PROD_IDX_6 0x00002498 890 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c 891 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 892 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 893 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 894 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac 895 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 896 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 897 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 898 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc 899 #define RCVDBDI_HWDIAG 0x000024c0 900 /* 0x24c4 --> 0x2800 unused */ 901 902 /* Receive Data Completion Control */ 903 #define RCVDCC_MODE 0x00002800 904 #define RCVDCC_MODE_RESET 0x00000001 905 #define RCVDCC_MODE_ENABLE 0x00000002 906 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 907 /* 0x2804 --> 0x2c00 unused */ 908 909 /* Receive BD Initiator Control Registers */ 910 #define RCVBDI_MODE 0x00002c00 911 #define RCVBDI_MODE_RESET 0x00000001 912 #define RCVBDI_MODE_ENABLE 0x00000002 913 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 914 #define RCVBDI_STATUS 0x00002c04 915 #define RCVBDI_STATUS_RCB_ATTN 0x00000004 916 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 917 #define RCVBDI_STD_PROD_IDX 0x00002c0c 918 #define RCVBDI_MINI_PROD_IDX 0x00002c10 919 #define RCVBDI_MINI_THRESH 0x00002c14 920 #define RCVBDI_STD_THRESH 0x00002c18 921 #define RCVBDI_JUMBO_THRESH 0x00002c1c 922 /* 0x2c20 --> 0x3000 unused */ 923 924 /* Receive BD Completion Control Registers */ 925 #define RCVCC_MODE 0x00003000 926 #define RCVCC_MODE_RESET 0x00000001 927 #define RCVCC_MODE_ENABLE 0x00000002 928 #define RCVCC_MODE_ATTN_ENABLE 0x00000004 929 #define RCVCC_STATUS 0x00003004 930 #define RCVCC_STATUS_ERROR_ATTN 0x00000004 931 #define RCVCC_JUMP_PROD_IDX 0x00003008 932 #define RCVCC_STD_PROD_IDX 0x0000300c 933 #define RCVCC_MINI_PROD_IDX 0x00003010 934 /* 0x3014 --> 0x3400 unused */ 935 936 /* Receive list selector control registers */ 937 #define RCVLSC_MODE 0x00003400 938 #define RCVLSC_MODE_RESET 0x00000001 939 #define RCVLSC_MODE_ENABLE 0x00000002 940 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 941 #define RCVLSC_STATUS 0x00003404 942 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 943 /* 0x3408 --> 0x3800 unused */ 944 945 /* Mbuf cluster free registers */ 946 #define MBFREE_MODE 0x00003800 947 #define MBFREE_MODE_RESET 0x00000001 948 #define MBFREE_MODE_ENABLE 0x00000002 949 #define MBFREE_STATUS 0x00003804 950 /* 0x3808 --> 0x3c00 unused */ 951 952 /* Host coalescing control registers */ 953 #define HOSTCC_MODE 0x00003c00 954 #define HOSTCC_MODE_RESET 0x00000001 955 #define HOSTCC_MODE_ENABLE 0x00000002 956 #define HOSTCC_MODE_ATTN 0x00000004 957 #define HOSTCC_MODE_NOW 0x00000008 958 #define HOSTCC_MODE_FULL_STATUS 0x00000000 959 #define HOSTCC_MODE_64BYTE 0x00000080 960 #define HOSTCC_MODE_32BYTE 0x00000100 961 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 962 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 963 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 964 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 965 #define HOSTCC_STATUS 0x00003c04 966 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 967 #define HOSTCC_RXCOL_TICKS 0x00003c08 968 #define LOW_RXCOL_TICKS 0x00000032 969 #define DEFAULT_RXCOL_TICKS 0x00000048 970 #define HIGH_RXCOL_TICKS 0x00000096 971 #define HOSTCC_TXCOL_TICKS 0x00003c0c 972 #define LOW_TXCOL_TICKS 0x00000096 973 #define DEFAULT_TXCOL_TICKS 0x0000012c 974 #define HIGH_TXCOL_TICKS 0x00000145 975 #define HOSTCC_RXMAX_FRAMES 0x00003c10 976 #define LOW_RXMAX_FRAMES 0x00000005 977 #define DEFAULT_RXMAX_FRAMES 0x00000008 978 #define HIGH_RXMAX_FRAMES 0x00000012 979 #define HOSTCC_TXMAX_FRAMES 0x00003c14 980 #define LOW_TXMAX_FRAMES 0x00000035 981 #define DEFAULT_TXMAX_FRAMES 0x0000004b 982 #define HIGH_TXMAX_FRAMES 0x00000052 983 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 984 #define DEFAULT_RXCOAL_TICK_INT 0x00000019 985 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 986 #define DEFAULT_TXCOAL_TICK_INT 0x00000019 987 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 988 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 989 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 990 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 991 #define HOSTCC_STAT_COAL_TICKS 0x00003c28 992 #define DEFAULT_STAT_COAL_TICKS 0x000f4240 993 /* 0x3c2c --> 0x3c30 unused */ 994 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 995 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 996 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 997 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 998 #define HOSTCC_FLOW_ATTN 0x00003c48 999 /* 0x3c4c --> 0x3c50 unused */ 1000 #define HOSTCC_JUMBO_CON_IDX 0x00003c50 1001 #define HOSTCC_STD_CON_IDX 0x00003c54 1002 #define HOSTCC_MINI_CON_IDX 0x00003c58 1003 /* 0x3c5c --> 0x3c80 unused */ 1004 #define HOSTCC_RET_PROD_IDX_0 0x00003c80 1005 #define HOSTCC_RET_PROD_IDX_1 0x00003c84 1006 #define HOSTCC_RET_PROD_IDX_2 0x00003c88 1007 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1008 #define HOSTCC_RET_PROD_IDX_4 0x00003c90 1009 #define HOSTCC_RET_PROD_IDX_5 0x00003c94 1010 #define HOSTCC_RET_PROD_IDX_6 0x00003c98 1011 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1012 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1013 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1014 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1015 #define HOSTCC_RET_PROD_IDX_11 0x00003cac 1016 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1017 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1018 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1019 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1020 #define HOSTCC_SND_CON_IDX_0 0x00003cc0 1021 #define HOSTCC_SND_CON_IDX_1 0x00003cc4 1022 #define HOSTCC_SND_CON_IDX_2 0x00003cc8 1023 #define HOSTCC_SND_CON_IDX_3 0x00003ccc 1024 #define HOSTCC_SND_CON_IDX_4 0x00003cd0 1025 #define HOSTCC_SND_CON_IDX_5 0x00003cd4 1026 #define HOSTCC_SND_CON_IDX_6 0x00003cd8 1027 #define HOSTCC_SND_CON_IDX_7 0x00003cdc 1028 #define HOSTCC_SND_CON_IDX_8 0x00003ce0 1029 #define HOSTCC_SND_CON_IDX_9 0x00003ce4 1030 #define HOSTCC_SND_CON_IDX_10 0x00003ce8 1031 #define HOSTCC_SND_CON_IDX_11 0x00003cec 1032 #define HOSTCC_SND_CON_IDX_12 0x00003cf0 1033 #define HOSTCC_SND_CON_IDX_13 0x00003cf4 1034 #define HOSTCC_SND_CON_IDX_14 0x00003cf8 1035 #define HOSTCC_SND_CON_IDX_15 0x00003cfc 1036 /* 0x3d00 --> 0x4000 unused */ 1037 1038 /* Memory arbiter control registers */ 1039 #define MEMARB_MODE 0x00004000 1040 #define MEMARB_MODE_RESET 0x00000001 1041 #define MEMARB_MODE_ENABLE 0x00000002 1042 #define MEMARB_STATUS 0x00004004 1043 #define MEMARB_TRAP_ADDR_LOW 0x00004008 1044 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1045 /* 0x4010 --> 0x4400 unused */ 1046 1047 /* Buffer manager control registers */ 1048 #define BUFMGR_MODE 0x00004400 1049 #define BUFMGR_MODE_RESET 0x00000001 1050 #define BUFMGR_MODE_ENABLE 0x00000002 1051 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1052 #define BUFMGR_MODE_BM_TEST 0x00000008 1053 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1054 #define BUFMGR_STATUS 0x00004404 1055 #define BUFMGR_STATUS_ERROR 0x00000004 1056 #define BUFMGR_STATUS_MBLOW 0x00000010 1057 #define BUFMGR_MB_POOL_ADDR 0x00004408 1058 #define BUFMGR_MB_POOL_SIZE 0x0000440c 1059 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1060 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1061 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1062 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1063 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1064 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1065 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1066 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1067 #define BUFMGR_MB_HIGH_WATER 0x00004418 1068 #define DEFAULT_MB_HIGH_WATER 0x00000060 1069 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1070 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1071 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1072 #define BUFMGR_MB_ALLOC_BIT 0x10000000 1073 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1074 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1075 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1076 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1077 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1078 #define BUFMGR_DMA_LOW_WATER 0x00004434 1079 #define DEFAULT_DMA_LOW_WATER 0x00000005 1080 #define BUFMGR_DMA_HIGH_WATER 0x00004438 1081 #define DEFAULT_DMA_HIGH_WATER 0x0000000a 1082 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1083 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1084 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1085 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1086 #define BUFMGR_HWDIAG_0 0x0000444c 1087 #define BUFMGR_HWDIAG_1 0x00004450 1088 #define BUFMGR_HWDIAG_2 0x00004454 1089 /* 0x4458 --> 0x4800 unused */ 1090 1091 /* Read DMA control registers */ 1092 #define RDMAC_MODE 0x00004800 1093 #define RDMAC_MODE_RESET 0x00000001 1094 #define RDMAC_MODE_ENABLE 0x00000002 1095 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1096 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1097 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1098 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1099 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1100 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1101 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1102 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1103 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1104 #define RDMAC_MODE_SPLIT_RESET 0x00001000 1105 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1106 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1107 #define RDMAC_STATUS 0x00004804 1108 #define RDMAC_STATUS_TGTABORT 0x00000004 1109 #define RDMAC_STATUS_MSTABORT 0x00000008 1110 #define RDMAC_STATUS_PARITYERR 0x00000010 1111 #define RDMAC_STATUS_ADDROFLOW 0x00000020 1112 #define RDMAC_STATUS_FIFOOFLOW 0x00000040 1113 #define RDMAC_STATUS_FIFOURUN 0x00000080 1114 #define RDMAC_STATUS_FIFOOREAD 0x00000100 1115 #define RDMAC_STATUS_LNGREAD 0x00000200 1116 /* 0x4808 --> 0x4c00 unused */ 1117 1118 /* Write DMA control registers */ 1119 #define WDMAC_MODE 0x00004c00 1120 #define WDMAC_MODE_RESET 0x00000001 1121 #define WDMAC_MODE_ENABLE 0x00000002 1122 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1123 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1124 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1125 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1126 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1127 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1128 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1129 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1130 #define WDMAC_MODE_RX_ACCEL 0x00000400 1131 #define WDMAC_STATUS 0x00004c04 1132 #define WDMAC_STATUS_TGTABORT 0x00000004 1133 #define WDMAC_STATUS_MSTABORT 0x00000008 1134 #define WDMAC_STATUS_PARITYERR 0x00000010 1135 #define WDMAC_STATUS_ADDROFLOW 0x00000020 1136 #define WDMAC_STATUS_FIFOOFLOW 0x00000040 1137 #define WDMAC_STATUS_FIFOURUN 0x00000080 1138 #define WDMAC_STATUS_FIFOOREAD 0x00000100 1139 #define WDMAC_STATUS_LNGREAD 0x00000200 1140 /* 0x4c08 --> 0x5000 unused */ 1141 1142 /* Per-cpu register offsets (arm9) */ 1143 #define CPU_MODE 0x00000000 1144 #define CPU_MODE_RESET 0x00000001 1145 #define CPU_MODE_HALT 0x00000400 1146 #define CPU_STATE 0x00000004 1147 #define CPU_EVTMASK 0x00000008 1148 /* 0xc --> 0x1c reserved */ 1149 #define CPU_PC 0x0000001c 1150 #define CPU_INSN 0x00000020 1151 #define CPU_SPAD_UFLOW 0x00000024 1152 #define CPU_WDOG_CLEAR 0x00000028 1153 #define CPU_WDOG_VECTOR 0x0000002c 1154 #define CPU_WDOG_PC 0x00000030 1155 #define CPU_HW_BP 0x00000034 1156 /* 0x38 --> 0x44 unused */ 1157 #define CPU_WDOG_SAVED_STATE 0x00000044 1158 #define CPU_LAST_BRANCH_ADDR 0x00000048 1159 #define CPU_SPAD_UFLOW_SET 0x0000004c 1160 /* 0x50 --> 0x200 unused */ 1161 #define CPU_R0 0x00000200 1162 #define CPU_R1 0x00000204 1163 #define CPU_R2 0x00000208 1164 #define CPU_R3 0x0000020c 1165 #define CPU_R4 0x00000210 1166 #define CPU_R5 0x00000214 1167 #define CPU_R6 0x00000218 1168 #define CPU_R7 0x0000021c 1169 #define CPU_R8 0x00000220 1170 #define CPU_R9 0x00000224 1171 #define CPU_R10 0x00000228 1172 #define CPU_R11 0x0000022c 1173 #define CPU_R12 0x00000230 1174 #define CPU_R13 0x00000234 1175 #define CPU_R14 0x00000238 1176 #define CPU_R15 0x0000023c 1177 #define CPU_R16 0x00000240 1178 #define CPU_R17 0x00000244 1179 #define CPU_R18 0x00000248 1180 #define CPU_R19 0x0000024c 1181 #define CPU_R20 0x00000250 1182 #define CPU_R21 0x00000254 1183 #define CPU_R22 0x00000258 1184 #define CPU_R23 0x0000025c 1185 #define CPU_R24 0x00000260 1186 #define CPU_R25 0x00000264 1187 #define CPU_R26 0x00000268 1188 #define CPU_R27 0x0000026c 1189 #define CPU_R28 0x00000270 1190 #define CPU_R29 0x00000274 1191 #define CPU_R30 0x00000278 1192 #define CPU_R31 0x0000027c 1193 /* 0x280 --> 0x400 unused */ 1194 1195 #define RX_CPU_BASE 0x00005000 1196 #define TX_CPU_BASE 0x00005400 1197 1198 /* Mailboxes */ 1199 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1200 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1201 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1202 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1203 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1204 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1205 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1206 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1207 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1208 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1209 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1210 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1211 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1212 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1213 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1214 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1215 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1216 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1217 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1218 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1219 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1220 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1221 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1222 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1223 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1224 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1225 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1226 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1227 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1228 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1229 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1230 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1231 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1232 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1233 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1234 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1235 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1236 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1237 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1238 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1239 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1240 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1241 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1242 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1243 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1244 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1245 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1246 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1247 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1248 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1249 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1250 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1251 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1252 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1253 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1254 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1255 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1256 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1257 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1258 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1259 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1260 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1261 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1262 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1263 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1264 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1265 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1266 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1267 /* 0x5a10 --> 0x5c00 */ 1268 1269 /* Flow Through queues */ 1270 #define FTQ_RESET 0x00005c00 1271 /* 0x5c04 --> 0x5c10 unused */ 1272 #define FTQ_DMA_NORM_READ_CTL 0x00005c10 1273 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1274 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1275 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1276 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1277 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1278 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1279 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1280 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1281 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1282 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1283 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1284 #define FTQ_SEND_BD_COMP_CTL 0x00005c40 1285 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1286 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1287 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1288 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1289 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1290 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1291 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1292 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1293 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1294 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1295 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1296 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1297 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1298 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1299 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1300 #define FTQ_SWTYPE1_CTL 0x00005c80 1301 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1302 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1303 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1304 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1305 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1306 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1307 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1308 #define FTQ_HOST_COAL_CTL 0x00005ca0 1309 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1310 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1311 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1312 #define FTQ_MAC_TX_CTL 0x00005cb0 1313 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1314 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1315 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1316 #define FTQ_MB_FREE_CTL 0x00005cc0 1317 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1318 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1319 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1320 #define FTQ_RCVBD_COMP_CTL 0x00005cd0 1321 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1322 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1323 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1324 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1325 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1326 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1327 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1328 #define FTQ_RCVDATA_INI_CTL 0x00005cf0 1329 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1330 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1331 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1332 #define FTQ_RCVDATA_COMP_CTL 0x00005d00 1333 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1334 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1335 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1336 #define FTQ_SWTYPE2_CTL 0x00005d10 1337 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1338 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1339 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1340 /* 0x5d20 --> 0x6000 unused */ 1341 1342 /* Message signaled interrupt registers */ 1343 #define MSGINT_MODE 0x00006000 1344 #define MSGINT_MODE_RESET 0x00000001 1345 #define MSGINT_MODE_ENABLE 0x00000002 1346 #define MSGINT_STATUS 0x00006004 1347 #define MSGINT_FIFO 0x00006008 1348 /* 0x600c --> 0x6400 unused */ 1349 1350 /* DMA completion registers */ 1351 #define DMAC_MODE 0x00006400 1352 #define DMAC_MODE_RESET 0x00000001 1353 #define DMAC_MODE_ENABLE 0x00000002 1354 /* 0x6404 --> 0x6800 unused */ 1355 1356 /* GRC registers */ 1357 #define GRC_MODE 0x00006800 1358 #define GRC_MODE_UPD_ON_COAL 0x00000001 1359 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1360 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1361 #define GRC_MODE_BSWAP_DATA 0x00000010 1362 #define GRC_MODE_WSWAP_DATA 0x00000020 1363 #define GRC_MODE_SPLITHDR 0x00000100 1364 #define GRC_MODE_NOFRM_CRACKING 0x00000200 1365 #define GRC_MODE_INCL_CRC 0x00000400 1366 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1367 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1368 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1369 #define GRC_MODE_FORCE_PCI32BIT 0x00008000 1370 #define GRC_MODE_HOST_STACKUP 0x00010000 1371 #define GRC_MODE_HOST_SENDBDS 0x00020000 1372 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1373 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1374 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1375 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1376 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1377 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1378 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1379 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1380 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1381 #define GRC_MISC_CFG 0x00006804 1382 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1383 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1384 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1385 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1386 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1387 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1388 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1389 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1390 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1391 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1392 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1393 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1394 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1395 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1396 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1397 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1398 #define GRC_LOCAL_CTRL 0x00006808 1399 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1400 #define GRC_LCLCTRL_CLEARINT 0x00000002 1401 #define GRC_LCLCTRL_SETINT 0x00000004 1402 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1403 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1404 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1405 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1406 #define GRC_LCLCTRL_GPIO_OE0 0x00000800 1407 #define GRC_LCLCTRL_GPIO_OE1 0x00001000 1408 #define GRC_LCLCTRL_GPIO_OE2 0x00002000 1409 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1410 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1411 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1412 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1413 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1414 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1415 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1416 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1417 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1418 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1419 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1420 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1421 #define GRC_LCLCTRL_BANK_SELECT 0x00200000 1422 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1423 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1424 #define GRC_TIMER 0x0000680c 1425 #define GRC_RX_CPU_EVENT 0x00006810 1426 #define GRC_RX_TIMER_REF 0x00006814 1427 #define GRC_RX_CPU_SEM 0x00006818 1428 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1429 #define GRC_TX_CPU_EVENT 0x00006820 1430 #define GRC_TX_TIMER_REF 0x00006824 1431 #define GRC_TX_CPU_SEM 0x00006828 1432 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1433 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1434 #define GRC_EEPROM_ADDR 0x00006838 1435 #define EEPROM_ADDR_WRITE 0x00000000 1436 #define EEPROM_ADDR_READ 0x80000000 1437 #define EEPROM_ADDR_COMPLETE 0x40000000 1438 #define EEPROM_ADDR_FSM_RESET 0x20000000 1439 #define EEPROM_ADDR_DEVID_MASK 0x1c000000 1440 #define EEPROM_ADDR_DEVID_SHIFT 26 1441 #define EEPROM_ADDR_START 0x02000000 1442 #define EEPROM_ADDR_CLKPERD_SHIFT 16 1443 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1444 #define EEPROM_ADDR_ADDR_SHIFT 0 1445 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1446 #define EEPROM_CHIP_SIZE (64 * 1024) 1447 #define GRC_EEPROM_DATA 0x0000683c 1448 #define GRC_EEPROM_CTRL 0x00006840 1449 #define GRC_MDI_CTRL 0x00006844 1450 #define GRC_SEEPROM_DELAY 0x00006848 1451 /* 0x684c --> 0x6c00 unused */ 1452 1453 /* 0x6c00 --> 0x7000 unused */ 1454 1455 /* NVRAM Control registers */ 1456 #define NVRAM_CMD 0x00007000 1457 #define NVRAM_CMD_RESET 0x00000001 1458 #define NVRAM_CMD_DONE 0x00000008 1459 #define NVRAM_CMD_GO 0x00000010 1460 #define NVRAM_CMD_WR 0x00000020 1461 #define NVRAM_CMD_RD 0x00000000 1462 #define NVRAM_CMD_ERASE 0x00000040 1463 #define NVRAM_CMD_FIRST 0x00000080 1464 #define NVRAM_CMD_LAST 0x00000100 1465 #define NVRAM_STAT 0x00007004 1466 #define NVRAM_WRDATA 0x00007008 1467 #define NVRAM_ADDR 0x0000700c 1468 #define NVRAM_ADDR_MSK 0x00ffffff 1469 #define NVRAM_RDDATA 0x00007010 1470 #define NVRAM_CFG1 0x00007014 1471 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1472 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1473 #define NVRAM_CFG1_PASS_THRU 0x00000004 1474 #define NVRAM_CFG1_BIT_BANG 0x00000008 1475 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1476 #define NVRAM_CFG2 0x00007018 1477 #define NVRAM_CFG3 0x0000701c 1478 #define NVRAM_SWARB 0x00007020 1479 #define SWARB_REQ_SET0 0x00000001 1480 #define SWARB_REQ_SET1 0x00000002 1481 #define SWARB_REQ_SET2 0x00000004 1482 #define SWARB_REQ_SET3 0x00000008 1483 #define SWARB_REQ_CLR0 0x00000010 1484 #define SWARB_REQ_CLR1 0x00000020 1485 #define SWARB_REQ_CLR2 0x00000040 1486 #define SWARB_REQ_CLR3 0x00000080 1487 #define SWARB_GNT0 0x00000100 1488 #define SWARB_GNT1 0x00000200 1489 #define SWARB_GNT2 0x00000400 1490 #define SWARB_GNT3 0x00000800 1491 #define SWARB_REQ0 0x00001000 1492 #define SWARB_REQ1 0x00002000 1493 #define SWARB_REQ2 0x00004000 1494 #define SWARB_REQ3 0x00008000 1495 #define NVRAM_BUFFERED_PAGE_SIZE 264 1496 #define NVRAM_BUFFERED_PAGE_POS 9 1497 /* 0x7024 --> 0x7400 unused */ 1498 1499 /* 0x7400 --> 0x8000 unused */ 1500 1501 /* 32K Window into NIC internal memory */ 1502 #define NIC_SRAM_WIN_BASE 0x00008000 1503 1504 /* Offsets into first 32k of NIC internal memory. */ 1505 #define NIC_SRAM_PAGE_ZERO 0x00000000 1506 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 1507 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 1508 #define NIC_SRAM_STATS_BLK 0x00000300 1509 #define NIC_SRAM_STATUS_BLK 0x00000b00 1510 1511 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 1512 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 1513 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 1514 1515 #define NIC_SRAM_DATA_SIG 0x00000b54 1516 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 1517 1518 #define NIC_SRAM_DATA_CFG 0x00000b58 1519 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 1520 #define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000 1521 #define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004 1522 #define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004 1523 #define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008 1524 #define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008 1525 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 1526 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 1527 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 1528 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 1529 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 1530 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 1531 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 1532 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 1533 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 1534 1535 #define NIC_SRAM_DATA_PHY_ID 0x00000b74 1536 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 1537 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 1538 1539 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 1540 #define FWCMD_NICDRV_ALIVE 0x00000001 1541 #define FWCMD_NICDRV_PAUSE_FW 0x00000002 1542 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 1543 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 1544 #define FWCMD_NICDRV_FIX_DMAR 0x00000005 1545 #define FWCMD_NICDRV_FIX_DMAW 0x00000006 1546 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 1547 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 1548 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 1549 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 1550 #define DRV_STATE_START 0x00000001 1551 #define DRV_STATE_UNLOAD 0x00000002 1552 #define DRV_STATE_WOL 0x00000003 1553 #define DRV_STATE_SUSPEND 0x00000004 1554 1555 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 1556 1557 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 1558 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 1559 1560 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 1561 1562 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 1563 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 1564 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 1565 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 1566 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 1567 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 1568 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 1569 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 1570 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 1571 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 1572 1573 /* Currently this is fixed. */ 1574 #define PHY_ADDR 0x01 1575 1576 /* Tigon3 specific PHY MII registers. */ 1577 #define TG3_BMCR_SPEED1000 0x0040 1578 1579 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ 1580 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100 1581 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200 1582 #define MII_TG3_CTRL_AS_MASTER 0x0800 1583 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 1584 1585 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 1586 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 1587 #define MII_TG3_EXT_CTRL_TBI 0x8000 1588 1589 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 1590 #define MII_TG3_EXT_STAT_LPASS 0x0100 1591 1592 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 1593 1594 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 1595 1596 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ 1597 1598 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ 1599 #define MII_TG3_AUX_STAT_LPASS 0x0004 1600 #define MII_TG3_AUX_STAT_SPDMASK 0x0700 1601 #define MII_TG3_AUX_STAT_10HALF 0x0100 1602 #define MII_TG3_AUX_STAT_10FULL 0x0200 1603 #define MII_TG3_AUX_STAT_100HALF 0x0300 1604 #define MII_TG3_AUX_STAT_100_4 0x0400 1605 #define MII_TG3_AUX_STAT_100FULL 0x0500 1606 #define MII_TG3_AUX_STAT_1000HALF 0x0600 1607 #define MII_TG3_AUX_STAT_1000FULL 0x0700 1608 1609 #define MII_TG3_ISTAT 0x1a /* IRQ status register */ 1610 #define MII_TG3_IMASK 0x1b /* IRQ mask register */ 1611 1612 /* ISTAT/IMASK event bits */ 1613 #define MII_TG3_INT_LINKCHG 0x0002 1614 #define MII_TG3_INT_SPEEDCHG 0x0004 1615 #define MII_TG3_INT_DUPLEXCHG 0x0008 1616 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 1617 1618 /* XXX Add this to mii.h */ 1619 #ifndef ADVERTISE_PAUSE 1620 #define ADVERTISE_PAUSE_CAP 0x0400 1621 #endif 1622 #ifndef ADVERTISE_PAUSE_ASYM 1623 #define ADVERTISE_PAUSE_ASYM 0x0800 1624 #endif 1625 #ifndef LPA_PAUSE 1626 #define LPA_PAUSE_CAP 0x0400 1627 #endif 1628 #ifndef LPA_PAUSE_ASYM 1629 #define LPA_PAUSE_ASYM 0x0800 1630 #endif 1631 1632 /* There are two ways to manage the TX descriptors on the tigon3. 1633 * Either the descriptors are in host DMA'able memory, or they 1634 * exist only in the cards on-chip SRAM. All 16 send bds are under 1635 * the same mode, they may not be configured individually. 1636 * 1637 * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags. 1638 * 1639 * To use host memory TX descriptors: 1640 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 1641 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 1642 * 2) Allocate DMA'able memory. 1643 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 1644 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 1645 * obtained in step 2 1646 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 1647 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 1648 * of TX descriptors. Leave flags field clear. 1649 * 4) Access TX descriptors via host memory. The chip 1650 * will refetch into local SRAM as needed when producer 1651 * index mailboxes are updated. 1652 * 1653 * To use on-chip TX descriptors: 1654 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 1655 * Make sure GRC_MODE_HOST_SENDBDS is clear. 1656 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 1657 * a) Set TG3_BDINFO_HOST_ADDR to zero. 1658 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 1659 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 1660 * 3) Access TX descriptors directly in on-chip SRAM 1661 * using normal {read,write}l(). (and not using 1662 * pointer dereferencing of ioremap()'d memory like 1663 * the broken Broadcom driver does) 1664 * 1665 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 1666 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 1667 */ 1668 struct tg3_tx_buffer_desc { 1669 uint32_t addr_hi; 1670 uint32_t addr_lo; 1671 1672 uint32_t len_flags; 1673 #define TXD_FLAG_TCPUDP_CSUM 0x0001 1674 #define TXD_FLAG_IP_CSUM 0x0002 1675 #define TXD_FLAG_END 0x0004 1676 #define TXD_FLAG_IP_FRAG 0x0008 1677 #define TXD_FLAG_IP_FRAG_END 0x0010 1678 #define TXD_FLAG_VLAN 0x0040 1679 #define TXD_FLAG_COAL_NOW 0x0080 1680 #define TXD_FLAG_CPU_PRE_DMA 0x0100 1681 #define TXD_FLAG_CPU_POST_DMA 0x0200 1682 #define TXD_FLAG_ADD_SRC_ADDR 0x1000 1683 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 1684 #define TXD_FLAG_NO_CRC 0x8000 1685 #define TXD_LEN_SHIFT 16 1686 1687 uint32_t vlan_tag; 1688 #define TXD_VLAN_TAG_SHIFT 0 1689 #define TXD_MSS_SHIFT 16 1690 }; 1691 1692 #define TXD_ADDR 0x00UL /* 64-bit */ 1693 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 1694 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 1695 #define TXD_SIZE 0x10UL 1696 1697 struct tg3_rx_buffer_desc { 1698 uint32_t addr_hi; 1699 uint32_t addr_lo; 1700 1701 uint32_t idx_len; 1702 #define RXD_IDX_MASK 0xffff0000 1703 #define RXD_IDX_SHIFT 16 1704 #define RXD_LEN_MASK 0x0000ffff 1705 #define RXD_LEN_SHIFT 0 1706 1707 uint32_t type_flags; 1708 #define RXD_TYPE_SHIFT 16 1709 #define RXD_FLAGS_SHIFT 0 1710 1711 #define RXD_FLAG_END 0x0004 1712 #define RXD_FLAG_MINI 0x0800 1713 #define RXD_FLAG_JUMBO 0x0020 1714 #define RXD_FLAG_VLAN 0x0040 1715 #define RXD_FLAG_ERROR 0x0400 1716 #define RXD_FLAG_IP_CSUM 0x1000 1717 #define RXD_FLAG_TCPUDP_CSUM 0x2000 1718 #define RXD_FLAG_IS_TCP 0x4000 1719 1720 uint32_t ip_tcp_csum; 1721 #define RXD_IPCSUM_MASK 0xffff0000 1722 #define RXD_IPCSUM_SHIFT 16 1723 #define RXD_TCPCSUM_MASK 0x0000ffff 1724 #define RXD_TCPCSUM_SHIFT 0 1725 1726 uint32_t err_vlan; 1727 1728 #define RXD_VLAN_MASK 0x0000ffff 1729 1730 #define RXD_ERR_BAD_CRC 0x00010000 1731 #define RXD_ERR_COLLISION 0x00020000 1732 #define RXD_ERR_LINK_LOST 0x00040000 1733 #define RXD_ERR_PHY_DECODE 0x00080000 1734 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 1735 #define RXD_ERR_MAC_ABRT 0x00200000 1736 #define RXD_ERR_TOO_SMALL 0x00400000 1737 #define RXD_ERR_NO_RESOURCES 0x00800000 1738 #define RXD_ERR_HUGE_FRAME 0x01000000 1739 #define RXD_ERR_MASK 0xffff0000 1740 1741 uint32_t reserved; 1742 uint32_t opaque; 1743 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff 1744 #define RXD_OPAQUE_INDEX_SHIFT 0 1745 #define RXD_OPAQUE_RING_STD 0x00010000 1746 #define RXD_OPAQUE_RING_JUMBO 0x00020000 1747 #define RXD_OPAQUE_RING_MINI 0x00040000 1748 #define RXD_OPAQUE_RING_MASK 0x00070000 1749 }; 1750 1751 struct tg3_ext_rx_buffer_desc { 1752 struct { 1753 uint32_t addr_hi; 1754 uint32_t addr_lo; 1755 } addrlist[3]; 1756 uint32_t len2_len1; 1757 uint32_t resv_len3; 1758 struct tg3_rx_buffer_desc std; 1759 }; 1760 1761 /* We only use this when testing out the DMA engine 1762 * at probe time. This is the internal format of buffer 1763 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 1764 */ 1765 struct tg3_internal_buffer_desc { 1766 uint32_t addr_hi; 1767 uint32_t addr_lo; 1768 uint32_t nic_mbuf; 1769 /* XXX FIX THIS */ 1770 #if __BYTE_ORDER == __BIG_ENDIAN 1771 uint16_t cqid_sqid; 1772 uint16_t len; 1773 #else 1774 uint16_t len; 1775 uint16_t cqid_sqid; 1776 #endif 1777 uint32_t flags; 1778 uint32_t __cookie1; 1779 uint32_t __cookie2; 1780 uint32_t __cookie3; 1781 }; 1782 1783 #define TG3_HW_STATUS_SIZE 0x50 1784 struct tg3_hw_status { 1785 uint32_t status; 1786 #define SD_STATUS_UPDATED 0x00000001 1787 #define SD_STATUS_LINK_CHG 0x00000002 1788 #define SD_STATUS_ERROR 0x00000004 1789 1790 uint32_t status_tag; 1791 1792 #if __BYTE_ORDER == __BIG_ENDIAN 1793 uint16_t rx_consumer; 1794 uint16_t rx_jumbo_consumer; 1795 #else 1796 uint16_t rx_jumbo_consumer; 1797 uint16_t rx_consumer; 1798 #endif 1799 1800 #if __BYTE_ORDER == __BIG_ENDIAN 1801 uint16_t reserved; 1802 uint16_t rx_mini_consumer; 1803 #else 1804 uint16_t rx_mini_consumer; 1805 uint16_t reserved; 1806 #endif 1807 struct { 1808 #if __BYTE_ORDER == __BIG_ENDIAN 1809 uint16_t tx_consumer; 1810 uint16_t rx_producer; 1811 #else 1812 uint16_t rx_producer; 1813 uint16_t tx_consumer; 1814 #endif 1815 } idx[16]; 1816 }; 1817 1818 typedef struct { 1819 uint32_t high, low; 1820 } tg3_stat64_t; 1821 1822 struct tg3_hw_stats { 1823 uint8_t __reserved0[0x400-0x300]; 1824 1825 /* Statistics maintained by Receive MAC. */ 1826 tg3_stat64_t rx_octets; 1827 uint64_t __reserved1; 1828 tg3_stat64_t rx_fragments; 1829 tg3_stat64_t rx_ucast_packets; 1830 tg3_stat64_t rx_mcast_packets; 1831 tg3_stat64_t rx_bcast_packets; 1832 tg3_stat64_t rx_fcs_errors; 1833 tg3_stat64_t rx_align_errors; 1834 tg3_stat64_t rx_xon_pause_rcvd; 1835 tg3_stat64_t rx_xoff_pause_rcvd; 1836 tg3_stat64_t rx_mac_ctrl_rcvd; 1837 tg3_stat64_t rx_xoff_entered; 1838 tg3_stat64_t rx_frame_too_long_errors; 1839 tg3_stat64_t rx_jabbers; 1840 tg3_stat64_t rx_undersize_packets; 1841 tg3_stat64_t rx_in_length_errors; 1842 tg3_stat64_t rx_out_length_errors; 1843 tg3_stat64_t rx_64_or_less_octet_packets; 1844 tg3_stat64_t rx_65_to_127_octet_packets; 1845 tg3_stat64_t rx_128_to_255_octet_packets; 1846 tg3_stat64_t rx_256_to_511_octet_packets; 1847 tg3_stat64_t rx_512_to_1023_octet_packets; 1848 tg3_stat64_t rx_1024_to_1522_octet_packets; 1849 tg3_stat64_t rx_1523_to_2047_octet_packets; 1850 tg3_stat64_t rx_2048_to_4095_octet_packets; 1851 tg3_stat64_t rx_4096_to_8191_octet_packets; 1852 tg3_stat64_t rx_8192_to_9022_octet_packets; 1853 1854 uint64_t __unused0[37]; 1855 1856 /* Statistics maintained by Transmit MAC. */ 1857 tg3_stat64_t tx_octets; 1858 uint64_t __reserved2; 1859 tg3_stat64_t tx_collisions; 1860 tg3_stat64_t tx_xon_sent; 1861 tg3_stat64_t tx_xoff_sent; 1862 tg3_stat64_t tx_flow_control; 1863 tg3_stat64_t tx_mac_errors; 1864 tg3_stat64_t tx_single_collisions; 1865 tg3_stat64_t tx_mult_collisions; 1866 tg3_stat64_t tx_deferred; 1867 uint64_t __reserved3; 1868 tg3_stat64_t tx_excessive_collisions; 1869 tg3_stat64_t tx_late_collisions; 1870 tg3_stat64_t tx_collide_2times; 1871 tg3_stat64_t tx_collide_3times; 1872 tg3_stat64_t tx_collide_4times; 1873 tg3_stat64_t tx_collide_5times; 1874 tg3_stat64_t tx_collide_6times; 1875 tg3_stat64_t tx_collide_7times; 1876 tg3_stat64_t tx_collide_8times; 1877 tg3_stat64_t tx_collide_9times; 1878 tg3_stat64_t tx_collide_10times; 1879 tg3_stat64_t tx_collide_11times; 1880 tg3_stat64_t tx_collide_12times; 1881 tg3_stat64_t tx_collide_13times; 1882 tg3_stat64_t tx_collide_14times; 1883 tg3_stat64_t tx_collide_15times; 1884 tg3_stat64_t tx_ucast_packets; 1885 tg3_stat64_t tx_mcast_packets; 1886 tg3_stat64_t tx_bcast_packets; 1887 tg3_stat64_t tx_carrier_sense_errors; 1888 tg3_stat64_t tx_discards; 1889 tg3_stat64_t tx_errors; 1890 1891 uint64_t __unused1[31]; 1892 1893 /* Statistics maintained by Receive List Placement. */ 1894 tg3_stat64_t COS_rx_packets[16]; 1895 tg3_stat64_t COS_rx_filter_dropped; 1896 tg3_stat64_t dma_writeq_full; 1897 tg3_stat64_t dma_write_prioq_full; 1898 tg3_stat64_t rxbds_empty; 1899 tg3_stat64_t rx_discards; 1900 tg3_stat64_t rx_errors; 1901 tg3_stat64_t rx_threshold_hit; 1902 1903 uint64_t __unused2[9]; 1904 1905 /* Statistics maintained by Send Data Initiator. */ 1906 tg3_stat64_t COS_out_packets[16]; 1907 tg3_stat64_t dma_readq_full; 1908 tg3_stat64_t dma_read_prioq_full; 1909 tg3_stat64_t tx_comp_queue_full; 1910 1911 /* Statistics maintained by Host Coalescing. */ 1912 tg3_stat64_t ring_set_send_prod_index; 1913 tg3_stat64_t ring_status_update; 1914 tg3_stat64_t nic_irqs; 1915 tg3_stat64_t nic_avoided_irqs; 1916 tg3_stat64_t nic_tx_threshold_hit; 1917 1918 uint8_t __reserved4[0xb00-0x9c0]; 1919 }; 1920 1921 enum phy_led_mode { 1922 led_mode_auto, 1923 led_mode_three_link, 1924 led_mode_link10 1925 }; 1926 1927 #if 0 1928 /* 'mapping' is superfluous as the chip does not write into 1929 * the tx/rx post rings so we could just fetch it from there. 1930 * But the cache behavior is better how we are doing it now. 1931 */ 1932 struct ring_info { 1933 struct sk_buff *skb; 1934 DECLARE_PCI_UNMAP_ADDR(mapping) 1935 }; 1936 1937 struct tx_ring_info { 1938 struct sk_buff *skb; 1939 DECLARE_PCI_UNMAP_ADDR(mapping) 1940 uint32_t prev_vlan_tag; 1941 }; 1942 #endif 1943 1944 struct tg3_config_info { 1945 uint32_t flags; 1946 }; 1947 1948 struct tg3_link_config { 1949 /* Describes what we're trying to get. */ 1950 uint32_t advertising; 1951 #if 0 1952 uint16_t speed; 1953 uint8_t duplex; 1954 uint8_t autoneg; 1955 #define SPEED_INVALID 0xffff 1956 #define DUPLEX_INVALID 0xff 1957 #define AUTONEG_INVALID 0xff 1958 #endif 1959 1960 /* Describes what we actually have. */ 1961 uint8_t active_speed; 1962 uint8_t active_duplex; 1963 1964 /* When we go in and out of low power mode we need 1965 * to swap with this state. 1966 */ 1967 #if 0 1968 int phy_is_low_power; 1969 uint16_t orig_speed; 1970 uint8_t orig_duplex; 1971 uint8_t orig_autoneg; 1972 #endif 1973 }; 1974 1975 struct tg3_bufmgr_config { 1976 uint32_t mbuf_read_dma_low_water; 1977 uint32_t mbuf_mac_rx_low_water; 1978 uint32_t mbuf_high_water; 1979 1980 uint32_t mbuf_read_dma_low_water_jumbo; 1981 uint32_t mbuf_mac_rx_low_water_jumbo; 1982 uint32_t mbuf_high_water_jumbo; 1983 1984 uint32_t dma_low_water; 1985 uint32_t dma_high_water; 1986 }; 1987 1988 struct tg3 { 1989 #if 0 1990 /* SMP locking strategy: 1991 * 1992 * lock: Held during all operations except TX packet 1993 * processing. 1994 * 1995 * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx 1996 * 1997 * If you want to shut up all asynchronous processing you must 1998 * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must 1999 * be disabled to take 'lock' but only softirq disabling is 2000 * necessary for acquisition of 'tx_lock'. 2001 */ 2002 spinlock_t lock; 2003 spinlock_t tx_lock; 2004 #endif 2005 2006 uint32_t tx_prod; 2007 #if 0 2008 uint32_t tx_cons; 2009 #endif 2010 uint32_t rx_rcb_ptr; 2011 uint32_t rx_std_ptr; 2012 #if 0 2013 uint32_t rx_jumbo_ptr; 2014 spinlock_t indirect_lock; 2015 2016 struct net_device_stats net_stats; 2017 struct net_device_stats net_stats_prev; 2018 #endif 2019 unsigned long phy_crc_errors; 2020 2021 #if 0 2022 uint32_t rx_offset; 2023 #endif 2024 uint32_t tg3_flags; 2025 #if 0 2026 #define TG3_FLAG_HOST_TXDS 0x00000001 2027 #endif 2028 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 2029 #define TG3_FLAG_RX_CHECKSUMS 0x00000004 2030 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 2031 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 2032 #define TG3_FLAG_ENABLE_ASF 0x00000020 2033 #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 2034 #define TG3_FLAG_POLL_SERDES 0x00000080 2035 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 2036 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 2037 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400 2038 #define TG3_FLAG_WOL_ENABLE 0x00000800 2039 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 2040 #define TG3_FLAG_NVRAM 0x00002000 2041 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000 2042 #define TG3_FLAG_RX_PAUSE 0x00008000 2043 #define TG3_FLAG_TX_PAUSE 0x00010000 2044 #define TG3_FLAG_PCIX_MODE 0x00020000 2045 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 2046 #define TG3_FLAG_PCI_32BIT 0x00080000 2047 #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000 2048 #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000 2049 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000 2050 #define TG3_FLAG_JUMBO_ENABLE 0x00800000 2051 #define TG3_FLAG_10_100_ONLY 0x01000000 2052 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 2053 #define TG3_FLAG_PAUSE_RX 0x04000000 2054 #define TG3_FLAG_PAUSE_TX 0x08000000 2055 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 2056 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000 2057 #define TG3_FLAG_SPLIT_MODE 0x40000000 2058 #define TG3_FLAG_INIT_COMPLETE 0x80000000 2059 2060 uint32_t tg3_flags2; 2061 #define TG3_FLG2_RESTART_TIMER 0x00000001 2062 #define TG3_FLG2_SUN_5704 0x00000002 2063 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 2064 #define TG3_FLG2_IS_5788 0x00000008 2065 #define TG3_FLG2_MAX_RXPEND_64 0x00000010 2066 #define TG3_FLG2_TSO_CAPABLE 0x00000020 2067 2068 2069 2070 uint32_t split_mode_max_reqs; 2071 #define SPLIT_MODE_5704_MAX_REQ 3 2072 2073 #if 0 2074 struct timer_list timer; 2075 uint16_t timer_counter; 2076 uint16_t timer_multiplier; 2077 uint32_t timer_offset; 2078 uint16_t asf_counter; 2079 uint16_t asf_multiplier; 2080 #endif 2081 2082 struct tg3_link_config link_config; 2083 struct tg3_bufmgr_config bufmgr_config; 2084 2085 #if 0 2086 uint32_t rx_pending; 2087 uint32_t rx_jumbo_pending; 2088 uint32_t tx_pending; 2089 #endif 2090 2091 /* cache h/w values, often passed straight to h/w */ 2092 uint32_t rx_mode; 2093 uint32_t tx_mode; 2094 uint32_t mac_mode; 2095 uint32_t mi_mode; 2096 uint32_t misc_host_ctrl; 2097 uint32_t grc_mode; 2098 uint32_t grc_local_ctrl; 2099 uint32_t dma_rwctrl; 2100 #if 0 2101 uint32_t coalesce_mode; 2102 #endif 2103 2104 /* PCI block */ 2105 uint16_t pci_chip_rev_id; 2106 #if 0 2107 uint8_t pci_cacheline_sz; 2108 uint8_t pci_lat_timer; 2109 uint8_t pci_hdr_type; 2110 uint8_t pci_bist; 2111 #endif 2112 uint32_t pci_cfg_state[64 / sizeof(uint32_t)]; 2113 2114 int pm_cap; 2115 2116 /* PHY info */ 2117 uint32_t phy_id; 2118 #define PHY_ID_MASK 0xfffffff0 2119 #define PHY_ID_BCM5400 0x60008040 2120 #define PHY_ID_BCM5401 0x60008050 2121 #define PHY_ID_BCM5411 0x60008070 2122 #define PHY_ID_BCM5701 0x60008110 2123 #define PHY_ID_BCM5703 0x60008160 2124 #define PHY_ID_BCM5704 0x60008190 2125 #define PHY_ID_BCM5705 0x600081a0 2126 #define PHY_ID_BCM8002 0x60010140 2127 #define PHY_ID_SERDES 0xfeedbee0 2128 #define PHY_ID_INVALID 0xffffffff 2129 #define PHY_ID_REV_MASK 0x0000000f 2130 #define PHY_REV_BCM5401_B0 0x1 2131 #define PHY_REV_BCM5401_B2 0x3 2132 #define PHY_REV_BCM5401_C0 0x6 2133 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ 2134 2135 enum phy_led_mode led_mode; 2136 2137 char board_part_number[24]; 2138 uint32_t nic_sram_data_cfg; 2139 uint32_t pci_clock_ctrl; 2140 #if 0 2141 struct pci_device *pdev_peer; 2142 #endif 2143 2144 /* This macro assumes the passed PHY ID is already masked 2145 * with PHY_ID_MASK. 2146 */ 2147 #define KNOWN_PHY_ID(X) \ 2148 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \ 2149 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \ 2150 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \ 2151 (X) == PHY_ID_BCM5705 || \ 2152 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES) 2153 2154 unsigned long regs; 2155 struct pci_device *pdev; 2156 struct nic *nic; 2157 #if 0 2158 struct net_device *dev; 2159 #endif 2160 #if TG3_VLAN_TAG_USED 2161 struct vlan_group *vlgrp; 2162 #endif 2163 2164 struct tg3_rx_buffer_desc *rx_std; 2165 #if 0 2166 struct ring_info *rx_std_buffers; 2167 dma_addr_t rx_std_mapping; 2168 struct tg3_rx_buffer_desc *rx_jumbo; 2169 struct ring_info *rx_jumbo_buffers; 2170 dma_addr_t rx_jumbo_mapping; 2171 #endif 2172 2173 struct tg3_rx_buffer_desc *rx_rcb; 2174 #if 0 2175 dma_addr_t rx_rcb_mapping; 2176 #endif 2177 2178 /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */ 2179 struct tg3_tx_buffer_desc *tx_ring; 2180 #if 0 2181 struct tx_ring_info *tx_buffers; 2182 dma_addr_t tx_desc_mapping; 2183 #endif 2184 2185 struct tg3_hw_status *hw_status; 2186 #if 0 2187 dma_addr_t status_mapping; 2188 #endif 2189 #if 0 2190 uint32_t msg_enable; 2191 #endif 2192 2193 struct tg3_hw_stats *hw_stats; 2194 #if 0 2195 dma_addr_t stats_mapping; 2196 #endif 2197 2198 int carrier_ok; 2199 uint16_t subsystem_vendor; 2200 uint16_t subsystem_device; 2201 }; 2202 2203 #endif /* !(_T3_H) */ 2204