1*1b8adde7SWilliam Kucharski /* 2*1b8adde7SWilliam Kucharski * Basic support for controlling the 8259 Programmable Interrupt Controllers. 3*1b8adde7SWilliam Kucharski * 4*1b8adde7SWilliam Kucharski * Initially written by Michael Brown (mcb30). 5*1b8adde7SWilliam Kucharski */ 6*1b8adde7SWilliam Kucharski 7*1b8adde7SWilliam Kucharski #ifndef PIC8259_H 8*1b8adde7SWilliam Kucharski #define PIC8259_H 9*1b8adde7SWilliam Kucharski 10*1b8adde7SWilliam Kucharski /* For segoff_t */ 11*1b8adde7SWilliam Kucharski #include <segoff.h> 12*1b8adde7SWilliam Kucharski 13*1b8adde7SWilliam Kucharski #define IRQ_PIC_CUTOFF (8) 14*1b8adde7SWilliam Kucharski 15*1b8adde7SWilliam Kucharski /* 8259 register locations */ 16*1b8adde7SWilliam Kucharski #define PIC1_ICW1 (0x20) 17*1b8adde7SWilliam Kucharski #define PIC1_OCW2 (0x20) 18*1b8adde7SWilliam Kucharski #define PIC1_OCW3 (0x20) 19*1b8adde7SWilliam Kucharski #define PIC1_ICR (0x20) 20*1b8adde7SWilliam Kucharski #define PIC1_IRR (0x20) 21*1b8adde7SWilliam Kucharski #define PIC1_ISR (0x20) 22*1b8adde7SWilliam Kucharski #define PIC1_ICW2 (0x21) 23*1b8adde7SWilliam Kucharski #define PIC1_ICW3 (0x21) 24*1b8adde7SWilliam Kucharski #define PIC1_ICW4 (0x21) 25*1b8adde7SWilliam Kucharski #define PIC1_IMR (0x21) 26*1b8adde7SWilliam Kucharski #define PIC2_ICW1 (0xa0) 27*1b8adde7SWilliam Kucharski #define PIC2_OCW2 (0xa0) 28*1b8adde7SWilliam Kucharski #define PIC2_OCW3 (0xa0) 29*1b8adde7SWilliam Kucharski #define PIC2_ICR (0xa0) 30*1b8adde7SWilliam Kucharski #define PIC2_IRR (0xa0) 31*1b8adde7SWilliam Kucharski #define PIC2_ISR (0xa0) 32*1b8adde7SWilliam Kucharski #define PIC2_ICW2 (0xa1) 33*1b8adde7SWilliam Kucharski #define PIC2_ICW3 (0xa1) 34*1b8adde7SWilliam Kucharski #define PIC2_ICW4 (0xa1) 35*1b8adde7SWilliam Kucharski #define PIC2_IMR (0xa1) 36*1b8adde7SWilliam Kucharski 37*1b8adde7SWilliam Kucharski /* Register command values */ 38*1b8adde7SWilliam Kucharski #define OCW3_ID (0x08) 39*1b8adde7SWilliam Kucharski #define OCW3_READ_IRR (0x03) 40*1b8adde7SWilliam Kucharski #define OCW3_READ_ISR (0x02) 41*1b8adde7SWilliam Kucharski #define ICR_EOI_NON_SPECIFIC (0x20) 42*1b8adde7SWilliam Kucharski #define ICR_EOI_NOP (0x40) 43*1b8adde7SWilliam Kucharski #define ICR_EOI_SPECIFIC (0x60) 44*1b8adde7SWilliam Kucharski #define ICR_EOI_SET_PRIORITY (0xc0) 45*1b8adde7SWilliam Kucharski 46*1b8adde7SWilliam Kucharski /* Macros to enable/disable IRQs */ 47*1b8adde7SWilliam Kucharski #define IMR_REG(x) ( (x) < IRQ_PIC_CUTOFF ? PIC1_IMR : PIC2_IMR ) 48*1b8adde7SWilliam Kucharski #define IMR_BIT(x) ( 1 << ( (x) % IRQ_PIC_CUTOFF ) ) 49*1b8adde7SWilliam Kucharski #define irq_enabled(x) ( ( inb ( IMR_REG(x) ) & IMR_BIT(x) ) == 0 ) 50*1b8adde7SWilliam Kucharski #define enable_irq(x) outb ( inb( IMR_REG(x) ) & ~IMR_BIT(x), IMR_REG(x) ) 51*1b8adde7SWilliam Kucharski #define disable_irq(x) outb ( inb( IMR_REG(x) ) | IMR_BIT(x), IMR_REG(x) ) 52*1b8adde7SWilliam Kucharski 53*1b8adde7SWilliam Kucharski /* Macros for acknowledging IRQs */ 54*1b8adde7SWilliam Kucharski #define ICR_REG(x) ( (x) < IRQ_PIC_CUTOFF ? PIC1_ICR : PIC2_ICR ) 55*1b8adde7SWilliam Kucharski #define ICR_VALUE(x) ( (x) % IRQ_PIC_CUTOFF ) 56*1b8adde7SWilliam Kucharski #define CHAINED_IRQ 2 57*1b8adde7SWilliam Kucharski 58*1b8adde7SWilliam Kucharski /* Utility macros to convert IRQ numbers to INT numbers and INT vectors */ 59*1b8adde7SWilliam Kucharski #define IRQ_INT(x) ( (x)<IRQ_PIC_CUTOFF ? (x)+0x08 : (x)-IRQ_PIC_CUTOFF+0x70 ) 60*1b8adde7SWilliam Kucharski #define INT_VECTOR(x) ( (segoff_t*) phys_to_virt( 4 * (x) ) ) 61*1b8adde7SWilliam Kucharski #define IRQ_VECTOR(x) ( INT_VECTOR ( IRQ_INT(x) ) ) 62*1b8adde7SWilliam Kucharski 63*1b8adde7SWilliam Kucharski /* Other constants */ 64*1b8adde7SWilliam Kucharski typedef uint8_t irq_t; 65*1b8adde7SWilliam Kucharski #define IRQ_MAX (15) 66*1b8adde7SWilliam Kucharski #define IRQ_NONE (0xff) 67*1b8adde7SWilliam Kucharski 68*1b8adde7SWilliam Kucharski /* Labels in assembly code (asm.S) 69*1b8adde7SWilliam Kucharski */ 70*1b8adde7SWilliam Kucharski extern void _undi_irq_handler_start; 71*1b8adde7SWilliam Kucharski extern void _undi_irq_handler ( void ); 72*1b8adde7SWilliam Kucharski extern volatile uint16_t _undi_irq_trigger_count; 73*1b8adde7SWilliam Kucharski extern volatile uint16_t _undi_irq_fail_count; 74*1b8adde7SWilliam Kucharski extern volatile uint16_t _undi_irq_not_ours_count; 75*1b8adde7SWilliam Kucharski extern segoff_t _undi_irq_chain_to; 76*1b8adde7SWilliam Kucharski extern uint8_t _undi_irq_chain; 77*1b8adde7SWilliam Kucharski extern uint8_t _pxenv_undi_irq; 78*1b8adde7SWilliam Kucharski extern segoff_t _pxenv_undi_entrypointsp; 79*1b8adde7SWilliam Kucharski 80*1b8adde7SWilliam Kucharski /* Function prototypes 81*1b8adde7SWilliam Kucharski */ 82*1b8adde7SWilliam Kucharski int install_irq_handler ( irq_t irq, segoff_t *handler, 83*1b8adde7SWilliam Kucharski uint8_t *previously_enabled, 84*1b8adde7SWilliam Kucharski segoff_t *previous_handler ); 85*1b8adde7SWilliam Kucharski int remove_irq_handler ( irq_t irq, segoff_t *handler, 86*1b8adde7SWilliam Kucharski uint8_t *previously_enabled, 87*1b8adde7SWilliam Kucharski segoff_t *previous_handler ); 88*1b8adde7SWilliam Kucharski int install_undi_irq_handler ( irq_t irq, segoff_t ); 89*1b8adde7SWilliam Kucharski int remove_undi_irq_handler ( irq_t irq ); 90*1b8adde7SWilliam Kucharski int undi_irq_triggered ( irq_t irq ); 91*1b8adde7SWilliam Kucharski void send_specific_eoi ( irq_t irq ); 92*1b8adde7SWilliam Kucharski #ifdef DEBUG_IRQ 93*1b8adde7SWilliam Kucharski void dump_irq_status ( void ); 94*1b8adde7SWilliam Kucharski #else 95*1b8adde7SWilliam Kucharski #define dump_irq_status() 96*1b8adde7SWilliam Kucharski #endif 97*1b8adde7SWilliam Kucharski 98*1b8adde7SWilliam Kucharski #endif /* PIC8259_H */ 99