1 /******************************************************************************* 2 3 4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 2 of the License, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 59 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 20 The full GNU General Public License is included in this distribution in the 21 file called LICENSE. 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* e1000_hw.h 30 * Structures, enums, and macros for the MAC 31 */ 32 33 #ifndef _E1000_HW_H_ 34 #define _E1000_HW_H_ 35 36 /* Forward declarations of structures used by the shared code */ 37 struct e1000_hw; 38 struct e1000_hw_stats; 39 40 /* Enumerated types specific to the e1000 hardware */ 41 /* Media Access Controlers */ 42 typedef enum { 43 e1000_undefined = 0, 44 e1000_82542_rev2_0, 45 e1000_82542_rev2_1, 46 e1000_82543, 47 e1000_82544, 48 e1000_82540, 49 e1000_82545, 50 e1000_82545_rev_3, 51 e1000_82546, 52 e1000_82546_rev_3, 53 e1000_82541, 54 e1000_82541_rev_2, 55 e1000_82547, 56 e1000_82547_rev_2, 57 e1000_num_macs 58 } e1000_mac_type; 59 60 typedef enum { 61 e1000_eeprom_uninitialized = 0, 62 e1000_eeprom_spi, 63 e1000_eeprom_microwire, 64 e1000_num_eeprom_types 65 } e1000_eeprom_type; 66 67 /* Media Types */ 68 typedef enum { 69 e1000_media_type_copper = 0, 70 e1000_media_type_fiber = 1, 71 e1000_media_type_internal_serdes = 2, 72 e1000_num_media_types 73 } e1000_media_type; 74 75 typedef enum { 76 e1000_10_half = 0, 77 e1000_10_full = 1, 78 e1000_100_half = 2, 79 e1000_100_full = 3 80 } e1000_speed_duplex_type; 81 82 /* Flow Control Settings */ 83 typedef enum { 84 e1000_fc_none = 0, 85 e1000_fc_rx_pause = 1, 86 e1000_fc_tx_pause = 2, 87 e1000_fc_full = 3, 88 e1000_fc_default = 0xFF 89 } e1000_fc_type; 90 91 /* PCI bus types */ 92 typedef enum { 93 e1000_bus_type_unknown = 0, 94 e1000_bus_type_pci, 95 e1000_bus_type_pcix, 96 e1000_bus_type_reserved 97 } e1000_bus_type; 98 99 /* PCI bus speeds */ 100 typedef enum { 101 e1000_bus_speed_unknown = 0, 102 e1000_bus_speed_33, 103 e1000_bus_speed_66, 104 e1000_bus_speed_100, 105 e1000_bus_speed_120, 106 e1000_bus_speed_133, 107 e1000_bus_speed_reserved 108 } e1000_bus_speed; 109 110 /* PCI bus widths */ 111 typedef enum { 112 e1000_bus_width_unknown = 0, 113 e1000_bus_width_32, 114 e1000_bus_width_64, 115 e1000_bus_width_reserved 116 } e1000_bus_width; 117 118 /* PHY status info structure and supporting enums */ 119 typedef enum { 120 e1000_cable_length_50 = 0, 121 e1000_cable_length_50_80, 122 e1000_cable_length_80_110, 123 e1000_cable_length_110_140, 124 e1000_cable_length_140, 125 e1000_cable_length_undefined = 0xFF 126 } e1000_cable_length; 127 128 typedef enum { 129 e1000_igp_cable_length_10 = 10, 130 e1000_igp_cable_length_20 = 20, 131 e1000_igp_cable_length_30 = 30, 132 e1000_igp_cable_length_40 = 40, 133 e1000_igp_cable_length_50 = 50, 134 e1000_igp_cable_length_60 = 60, 135 e1000_igp_cable_length_70 = 70, 136 e1000_igp_cable_length_80 = 80, 137 e1000_igp_cable_length_90 = 90, 138 e1000_igp_cable_length_100 = 100, 139 e1000_igp_cable_length_110 = 110, 140 e1000_igp_cable_length_120 = 120, 141 e1000_igp_cable_length_130 = 130, 142 e1000_igp_cable_length_140 = 140, 143 e1000_igp_cable_length_150 = 150, 144 e1000_igp_cable_length_160 = 160, 145 e1000_igp_cable_length_170 = 170, 146 e1000_igp_cable_length_180 = 180 147 } e1000_igp_cable_length; 148 149 typedef enum { 150 e1000_10bt_ext_dist_enable_normal = 0, 151 e1000_10bt_ext_dist_enable_lower, 152 e1000_10bt_ext_dist_enable_undefined = 0xFF 153 } e1000_10bt_ext_dist_enable; 154 155 typedef enum { 156 e1000_rev_polarity_normal = 0, 157 e1000_rev_polarity_reversed, 158 e1000_rev_polarity_undefined = 0xFF 159 } e1000_rev_polarity; 160 161 typedef enum { 162 e1000_downshift_normal = 0, 163 e1000_downshift_activated, 164 e1000_downshift_undefined = 0xFF 165 } e1000_downshift; 166 167 typedef enum { 168 e1000_polarity_reversal_enabled = 0, 169 e1000_polarity_reversal_disabled, 170 e1000_polarity_reversal_undefined = 0xFF 171 } e1000_polarity_reversal; 172 173 typedef enum { 174 e1000_auto_x_mode_manual_mdi = 0, 175 e1000_auto_x_mode_manual_mdix, 176 e1000_auto_x_mode_auto1, 177 e1000_auto_x_mode_auto2, 178 e1000_auto_x_mode_undefined = 0xFF 179 } e1000_auto_x_mode; 180 181 typedef enum { 182 e1000_1000t_rx_status_not_ok = 0, 183 e1000_1000t_rx_status_ok, 184 e1000_1000t_rx_status_undefined = 0xFF 185 } e1000_1000t_rx_status; 186 187 typedef enum { 188 e1000_phy_m88 = 0, 189 e1000_phy_igp, 190 e1000_phy_undefined = 0xFF 191 } e1000_phy_type; 192 193 typedef enum { 194 e1000_ms_hw_default = 0, 195 e1000_ms_force_master, 196 e1000_ms_force_slave, 197 e1000_ms_auto 198 } e1000_ms_type; 199 200 typedef enum { 201 e1000_ffe_config_enabled = 0, 202 e1000_ffe_config_active, 203 e1000_ffe_config_blocked 204 } e1000_ffe_config; 205 206 typedef enum { 207 e1000_dsp_config_disabled = 0, 208 e1000_dsp_config_enabled, 209 e1000_dsp_config_activated, 210 e1000_dsp_config_undefined = 0xFF 211 } e1000_dsp_config; 212 213 struct e1000_phy_info { 214 e1000_cable_length cable_length; 215 e1000_10bt_ext_dist_enable extended_10bt_distance; 216 e1000_rev_polarity cable_polarity; 217 e1000_downshift downshift; 218 e1000_polarity_reversal polarity_correction; 219 e1000_auto_x_mode mdix_mode; 220 e1000_1000t_rx_status local_rx; 221 e1000_1000t_rx_status remote_rx; 222 }; 223 224 struct e1000_phy_stats { 225 uint32_t idle_errors; 226 uint32_t receive_errors; 227 }; 228 229 struct e1000_eeprom_info { 230 e1000_eeprom_type type; 231 uint16_t word_size; 232 uint16_t opcode_bits; 233 uint16_t address_bits; 234 uint16_t delay_usec; 235 uint16_t page_size; 236 }; 237 238 239 240 /* Error Codes */ 241 #define E1000_SUCCESS 0 242 #define E1000_ERR_EEPROM 1 243 #define E1000_ERR_PHY 2 244 #define E1000_ERR_CONFIG 3 245 #define E1000_ERR_PARAM 4 246 #define E1000_ERR_MAC_TYPE 5 247 #define E1000_ERR_PHY_TYPE 6 248 #define E1000_ERR_NOLINK 7 249 #define E1000_ERR_TIMEOUT 8 250 251 #define E1000_READ_REG_IO(a, reg) \ 252 e1000_read_reg_io((a), E1000_##reg) 253 #define E1000_WRITE_REG_IO(a, reg, val) \ 254 e1000_write_reg_io((a), E1000_##reg, val) 255 256 /* PCI Device IDs */ 257 #define E1000_DEV_ID_82542 0x1000 258 #define E1000_DEV_ID_82543GC_FIBER 0x1001 259 #define E1000_DEV_ID_82543GC_COPPER 0x1004 260 #define E1000_DEV_ID_82544EI_COPPER 0x1008 261 #define E1000_DEV_ID_82544EI_FIBER 0x1009 262 #define E1000_DEV_ID_82544GC_COPPER 0x100C 263 #define E1000_DEV_ID_82544GC_LOM 0x100D 264 #define E1000_DEV_ID_82540EM 0x100E 265 #define E1000_DEV_ID_82540EM_LOM 0x1015 266 #define E1000_DEV_ID_82540EP_LOM 0x1016 267 #define E1000_DEV_ID_82540EP 0x1017 268 #define E1000_DEV_ID_82540EP_LP 0x101E 269 #define E1000_DEV_ID_82545EM_COPPER 0x100F 270 #define E1000_DEV_ID_82545EM_FIBER 0x1011 271 #define E1000_DEV_ID_82545GM_COPPER 0x1026 272 #define E1000_DEV_ID_82545GM_FIBER 0x1027 273 #define E1000_DEV_ID_82545GM_SERDES 0x1028 274 #define E1000_DEV_ID_82546EB_COPPER 0x1010 275 #define E1000_DEV_ID_82546EB_FIBER 0x1012 276 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 277 #define E1000_DEV_ID_82541EI 0x1013 278 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 279 #define E1000_DEV_ID_82541ER 0x1078 280 #define E1000_DEV_ID_82547GI 0x1075 281 #define E1000_DEV_ID_82541GI 0x1076 282 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 283 #define E1000_DEV_ID_82546GB_COPPER 0x1079 284 #define E1000_DEV_ID_82546GB_FIBER 0x107A 285 #define E1000_DEV_ID_82546GB_SERDES 0x107B 286 #define E1000_DEV_ID_82547EI 0x1019 287 288 #define NODE_ADDRESS_SIZE 6 289 #define ETH_LENGTH_OF_ADDRESS 6 290 291 /* MAC decode size is 128K - This is the size of BAR0 */ 292 #define MAC_DECODE_SIZE (128 * 1024) 293 294 #define E1000_82542_2_0_REV_ID 2 295 #define E1000_82542_2_1_REV_ID 3 296 297 #define SPEED_10 10 298 #define SPEED_100 100 299 #define SPEED_1000 1000 300 #define HALF_DUPLEX 1 301 #define FULL_DUPLEX 2 302 303 /* The sizes (in bytes) of a ethernet packet */ 304 #define ENET_HEADER_SIZE 14 305 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 306 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 307 #define ETHERNET_FCS_SIZE 4 308 #define MAXIMUM_ETHERNET_PACKET_SIZE \ 309 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 310 #define MINIMUM_ETHERNET_PACKET_SIZE \ 311 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 312 #define CRC_LENGTH ETHERNET_FCS_SIZE 313 #define MAX_JUMBO_FRAME_SIZE 0x3F00 314 315 316 /* 802.1q VLAN Packet Sizes */ 317 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 318 319 /* Ethertype field values */ 320 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 321 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 322 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 323 324 /* Packet Header defines */ 325 #define IP_PROTOCOL_TCP 6 326 #define IP_PROTOCOL_UDP 0x11 327 328 /* This defines the bits that are set in the Interrupt Mask 329 * Set/Read Register. Each bit is documented below: 330 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 331 * o RXSEQ = Receive Sequence Error 332 */ 333 #define POLL_IMS_ENABLE_MASK ( \ 334 E1000_IMS_RXDMT0 | \ 335 E1000_IMS_RXSEQ) 336 337 /* This defines the bits that are set in the Interrupt Mask 338 * Set/Read Register. Each bit is documented below: 339 * o RXT0 = Receiver Timer Interrupt (ring 0) 340 * o TXDW = Transmit Descriptor Written Back 341 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 342 * o RXSEQ = Receive Sequence Error 343 * o LSC = Link Status Change 344 */ 345 #define IMS_ENABLE_MASK ( \ 346 E1000_IMS_RXT0 | \ 347 E1000_IMS_TXDW | \ 348 E1000_IMS_RXDMT0 | \ 349 E1000_IMS_RXSEQ | \ 350 E1000_IMS_LSC) 351 352 /* Number of high/low register pairs in the RAR. The RAR (Receive Address 353 * Registers) holds the directed and multicast addresses that we monitor. We 354 * reserve one of these spots for our directed address, allowing us room for 355 * E1000_RAR_ENTRIES - 1 multicast addresses. 356 */ 357 #define E1000_RAR_ENTRIES 15 358 359 #define MIN_NUMBER_OF_DESCRIPTORS 8 360 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 361 362 /* Receive Descriptor */ 363 struct e1000_rx_desc { 364 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 365 uint16_t length; /* Length of data DMAed into data buffer */ 366 uint16_t csum; /* Packet checksum */ 367 uint8_t status; /* Descriptor status */ 368 uint8_t errors; /* Descriptor Errors */ 369 uint16_t special; 370 }; 371 372 /* Receive Decriptor bit definitions */ 373 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 374 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 375 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 376 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 377 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 378 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 379 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 380 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 381 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 382 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 383 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 384 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 385 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 386 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 387 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 388 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 389 #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 390 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 391 #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ 392 393 /* mask to determine if packets should be dropped due to frame errors */ 394 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 395 E1000_RXD_ERR_CE | \ 396 E1000_RXD_ERR_SE | \ 397 E1000_RXD_ERR_SEQ | \ 398 E1000_RXD_ERR_CXE | \ 399 E1000_RXD_ERR_RXE) 400 401 /* Transmit Descriptor */ 402 struct e1000_tx_desc { 403 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 404 union { 405 uint32_t data; 406 struct { 407 uint16_t length; /* Data buffer length */ 408 uint8_t cso; /* Checksum offset */ 409 uint8_t cmd; /* Descriptor control */ 410 } flags; 411 } lower; 412 union { 413 uint32_t data; 414 struct { 415 uint8_t status; /* Descriptor status */ 416 uint8_t css; /* Checksum start */ 417 uint16_t special; 418 } fields; 419 } upper; 420 }; 421 422 /* Transmit Descriptor bit definitions */ 423 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 424 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 425 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 426 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 427 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 428 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 429 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 430 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 431 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 432 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 433 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 434 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 435 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 436 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 437 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 438 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 439 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 440 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 441 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 442 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 443 444 /* Offload Context Descriptor */ 445 struct e1000_context_desc { 446 union { 447 uint32_t ip_config; 448 struct { 449 uint8_t ipcss; /* IP checksum start */ 450 uint8_t ipcso; /* IP checksum offset */ 451 uint16_t ipcse; /* IP checksum end */ 452 } ip_fields; 453 } lower_setup; 454 union { 455 uint32_t tcp_config; 456 struct { 457 uint8_t tucss; /* TCP checksum start */ 458 uint8_t tucso; /* TCP checksum offset */ 459 uint16_t tucse; /* TCP checksum end */ 460 } tcp_fields; 461 } upper_setup; 462 uint32_t cmd_and_length; /* */ 463 union { 464 uint32_t data; 465 struct { 466 uint8_t status; /* Descriptor status */ 467 uint8_t hdr_len; /* Header length */ 468 uint16_t mss; /* Maximum segment size */ 469 } fields; 470 } tcp_seg_setup; 471 }; 472 473 /* Offload data descriptor */ 474 struct e1000_data_desc { 475 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 476 union { 477 uint32_t data; 478 struct { 479 uint16_t length; /* Data buffer length */ 480 uint8_t typ_len_ext; /* */ 481 uint8_t cmd; /* */ 482 } flags; 483 } lower; 484 union { 485 uint32_t data; 486 struct { 487 uint8_t status; /* Descriptor status */ 488 uint8_t popts; /* Packet Options */ 489 uint16_t special; /* */ 490 } fields; 491 } upper; 492 }; 493 494 /* Filters */ 495 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 496 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 497 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 498 499 500 /* Receive Address Register */ 501 struct e1000_rar { 502 volatile uint32_t low; /* receive address low */ 503 volatile uint32_t high; /* receive address high */ 504 }; 505 506 /* Number of entries in the Multicast Table Array (MTA). */ 507 #define E1000_NUM_MTA_REGISTERS 128 508 509 /* IPv4 Address Table Entry */ 510 struct e1000_ipv4_at_entry { 511 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 512 volatile uint32_t reserved; 513 }; 514 515 /* Four wakeup IP addresses are supported */ 516 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 517 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 518 #define E1000_IP6AT_SIZE 1 519 520 /* IPv6 Address Table Entry */ 521 struct e1000_ipv6_at_entry { 522 volatile uint8_t ipv6_addr[16]; 523 }; 524 525 /* Flexible Filter Length Table Entry */ 526 struct e1000_fflt_entry { 527 volatile uint32_t length; /* Flexible Filter Length (RW) */ 528 volatile uint32_t reserved; 529 }; 530 531 /* Flexible Filter Mask Table Entry */ 532 struct e1000_ffmt_entry { 533 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 534 volatile uint32_t reserved; 535 }; 536 537 /* Flexible Filter Value Table Entry */ 538 struct e1000_ffvt_entry { 539 volatile uint32_t value; /* Flexible Filter Value (RW) */ 540 volatile uint32_t reserved; 541 }; 542 543 /* Four Flexible Filters are supported */ 544 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 545 546 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 547 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 548 549 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 550 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 551 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 552 553 /* Register Set. (82543, 82544) 554 * 555 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 556 * These registers are physically located on the NIC, but are mapped into the 557 * host memory address space. 558 * 559 * RW - register is both readable and writable 560 * RO - register is read only 561 * WO - register is write only 562 * R/clr - register is read only and is cleared when read 563 * A - register array 564 */ 565 #define E1000_CTRL 0x00000 /* Device Control - RW */ 566 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 567 #define E1000_STATUS 0x00008 /* Device Status - RO */ 568 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 569 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 570 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 571 #define E1000_FLA 0x0001C /* Flash Access - RW */ 572 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 573 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 574 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 575 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 576 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 577 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 578 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 579 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 580 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 581 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 582 #define E1000_RCTL 0x00100 /* RX Control - RW */ 583 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 584 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 585 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 586 #define E1000_TCTL 0x00400 /* TX Control - RW */ 587 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 588 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 589 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 590 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 591 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 592 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 593 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 594 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 595 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 596 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 597 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 598 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 599 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 600 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 601 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 602 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 603 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 604 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 605 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 606 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 607 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 608 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 609 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 610 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 611 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 612 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 613 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 614 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 615 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 616 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 617 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 618 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 619 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 620 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 621 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 622 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 623 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 624 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 625 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 626 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 627 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 628 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 629 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 630 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 631 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 632 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 633 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 634 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 635 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 636 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 637 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 638 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 639 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 640 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 641 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 642 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 643 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 644 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 645 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 646 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 647 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 648 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 649 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 650 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 651 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 652 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 653 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 654 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 655 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 656 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 657 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 658 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 659 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 660 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 661 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 662 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 663 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 664 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 665 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 666 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 667 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 668 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 669 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 670 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 671 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 672 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 673 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 674 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 675 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 676 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 677 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 678 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 679 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 680 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 681 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 682 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 683 #define E1000_MANC 0x05820 /* Management Control - RW */ 684 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 685 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 686 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 687 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 688 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 689 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 690 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 691 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 692 693 /* Register Set (82542) 694 * 695 * Some of the 82542 registers are located at different offsets than they are 696 * in more current versions of the 8254x. Despite the difference in location, 697 * the registers function in the same manner. 698 */ 699 #define E1000_82542_CTRL E1000_CTRL 700 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP 701 #define E1000_82542_STATUS E1000_STATUS 702 #define E1000_82542_EECD E1000_EECD 703 #define E1000_82542_EERD E1000_EERD 704 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT 705 #define E1000_82542_FLA E1000_FLA 706 #define E1000_82542_MDIC E1000_MDIC 707 #define E1000_82542_FCAL E1000_FCAL 708 #define E1000_82542_FCAH E1000_FCAH 709 #define E1000_82542_FCT E1000_FCT 710 #define E1000_82542_VET E1000_VET 711 #define E1000_82542_RA 0x00040 712 #define E1000_82542_ICR E1000_ICR 713 #define E1000_82542_ITR E1000_ITR 714 #define E1000_82542_ICS E1000_ICS 715 #define E1000_82542_IMS E1000_IMS 716 #define E1000_82542_IMC E1000_IMC 717 #define E1000_82542_RCTL E1000_RCTL 718 #define E1000_82542_RDTR 0x00108 719 #define E1000_82542_RDBAL 0x00110 720 #define E1000_82542_RDBAH 0x00114 721 #define E1000_82542_RDLEN 0x00118 722 #define E1000_82542_RDH 0x00120 723 #define E1000_82542_RDT 0x00128 724 #define E1000_82542_FCRTH 0x00160 725 #define E1000_82542_FCRTL 0x00168 726 #define E1000_82542_FCTTV E1000_FCTTV 727 #define E1000_82542_TXCW E1000_TXCW 728 #define E1000_82542_RXCW E1000_RXCW 729 #define E1000_82542_MTA 0x00200 730 #define E1000_82542_TCTL E1000_TCTL 731 #define E1000_82542_TIPG E1000_TIPG 732 #define E1000_82542_TDBAL 0x00420 733 #define E1000_82542_TDBAH 0x00424 734 #define E1000_82542_TDLEN 0x00428 735 #define E1000_82542_TDH 0x00430 736 #define E1000_82542_TDT 0x00438 737 #define E1000_82542_TIDV 0x00440 738 #define E1000_82542_TBT E1000_TBT 739 #define E1000_82542_AIT E1000_AIT 740 #define E1000_82542_VFTA 0x00600 741 #define E1000_82542_LEDCTL E1000_LEDCTL 742 #define E1000_82542_PBA E1000_PBA 743 #define E1000_82542_RXDCTL E1000_RXDCTL 744 #define E1000_82542_RADV E1000_RADV 745 #define E1000_82542_RSRPD E1000_RSRPD 746 #define E1000_82542_TXDMAC E1000_TXDMAC 747 #define E1000_82542_TDFHS E1000_TDFHS 748 #define E1000_82542_TDFTS E1000_TDFTS 749 #define E1000_82542_TDFPC E1000_TDFPC 750 #define E1000_82542_TXDCTL E1000_TXDCTL 751 #define E1000_82542_TADV E1000_TADV 752 #define E1000_82542_TSPMT E1000_TSPMT 753 #define E1000_82542_CRCERRS E1000_CRCERRS 754 #define E1000_82542_ALGNERRC E1000_ALGNERRC 755 #define E1000_82542_SYMERRS E1000_SYMERRS 756 #define E1000_82542_RXERRC E1000_RXERRC 757 #define E1000_82542_MPC E1000_MPC 758 #define E1000_82542_SCC E1000_SCC 759 #define E1000_82542_ECOL E1000_ECOL 760 #define E1000_82542_MCC E1000_MCC 761 #define E1000_82542_LATECOL E1000_LATECOL 762 #define E1000_82542_COLC E1000_COLC 763 #define E1000_82542_DC E1000_DC 764 #define E1000_82542_TNCRS E1000_TNCRS 765 #define E1000_82542_SEC E1000_SEC 766 #define E1000_82542_CEXTERR E1000_CEXTERR 767 #define E1000_82542_RLEC E1000_RLEC 768 #define E1000_82542_XONRXC E1000_XONRXC 769 #define E1000_82542_XONTXC E1000_XONTXC 770 #define E1000_82542_XOFFRXC E1000_XOFFRXC 771 #define E1000_82542_XOFFTXC E1000_XOFFTXC 772 #define E1000_82542_FCRUC E1000_FCRUC 773 #define E1000_82542_PRC64 E1000_PRC64 774 #define E1000_82542_PRC127 E1000_PRC127 775 #define E1000_82542_PRC255 E1000_PRC255 776 #define E1000_82542_PRC511 E1000_PRC511 777 #define E1000_82542_PRC1023 E1000_PRC1023 778 #define E1000_82542_PRC1522 E1000_PRC1522 779 #define E1000_82542_GPRC E1000_GPRC 780 #define E1000_82542_BPRC E1000_BPRC 781 #define E1000_82542_MPRC E1000_MPRC 782 #define E1000_82542_GPTC E1000_GPTC 783 #define E1000_82542_GORCL E1000_GORCL 784 #define E1000_82542_GORCH E1000_GORCH 785 #define E1000_82542_GOTCL E1000_GOTCL 786 #define E1000_82542_GOTCH E1000_GOTCH 787 #define E1000_82542_RNBC E1000_RNBC 788 #define E1000_82542_RUC E1000_RUC 789 #define E1000_82542_RFC E1000_RFC 790 #define E1000_82542_ROC E1000_ROC 791 #define E1000_82542_RJC E1000_RJC 792 #define E1000_82542_MGTPRC E1000_MGTPRC 793 #define E1000_82542_MGTPDC E1000_MGTPDC 794 #define E1000_82542_MGTPTC E1000_MGTPTC 795 #define E1000_82542_TORL E1000_TORL 796 #define E1000_82542_TORH E1000_TORH 797 #define E1000_82542_TOTL E1000_TOTL 798 #define E1000_82542_TOTH E1000_TOTH 799 #define E1000_82542_TPR E1000_TPR 800 #define E1000_82542_TPT E1000_TPT 801 #define E1000_82542_PTC64 E1000_PTC64 802 #define E1000_82542_PTC127 E1000_PTC127 803 #define E1000_82542_PTC255 E1000_PTC255 804 #define E1000_82542_PTC511 E1000_PTC511 805 #define E1000_82542_PTC1023 E1000_PTC1023 806 #define E1000_82542_PTC1522 E1000_PTC1522 807 #define E1000_82542_MPTC E1000_MPTC 808 #define E1000_82542_BPTC E1000_BPTC 809 #define E1000_82542_TSCTC E1000_TSCTC 810 #define E1000_82542_TSCTFC E1000_TSCTFC 811 #define E1000_82542_RXCSUM E1000_RXCSUM 812 #define E1000_82542_WUC E1000_WUC 813 #define E1000_82542_WUFC E1000_WUFC 814 #define E1000_82542_WUS E1000_WUS 815 #define E1000_82542_MANC E1000_MANC 816 #define E1000_82542_IPAV E1000_IPAV 817 #define E1000_82542_IP4AT E1000_IP4AT 818 #define E1000_82542_IP6AT E1000_IP6AT 819 #define E1000_82542_WUPL E1000_WUPL 820 #define E1000_82542_WUPM E1000_WUPM 821 #define E1000_82542_FFLT E1000_FFLT 822 #define E1000_82542_TDFH 0x08010 823 #define E1000_82542_TDFT 0x08018 824 #define E1000_82542_FFMT E1000_FFMT 825 #define E1000_82542_FFVT E1000_FFVT 826 827 /* Statistics counters collected by the MAC */ 828 struct e1000_hw_stats { 829 uint64_t crcerrs; 830 uint64_t algnerrc; 831 uint64_t symerrs; 832 uint64_t rxerrc; 833 uint64_t mpc; 834 uint64_t scc; 835 uint64_t ecol; 836 uint64_t mcc; 837 uint64_t latecol; 838 uint64_t colc; 839 uint64_t dc; 840 uint64_t tncrs; 841 uint64_t sec; 842 uint64_t cexterr; 843 uint64_t rlec; 844 uint64_t xonrxc; 845 uint64_t xontxc; 846 uint64_t xoffrxc; 847 uint64_t xofftxc; 848 uint64_t fcruc; 849 uint64_t prc64; 850 uint64_t prc127; 851 uint64_t prc255; 852 uint64_t prc511; 853 uint64_t prc1023; 854 uint64_t prc1522; 855 uint64_t gprc; 856 uint64_t bprc; 857 uint64_t mprc; 858 uint64_t gptc; 859 uint64_t gorcl; 860 uint64_t gorch; 861 uint64_t gotcl; 862 uint64_t gotch; 863 uint64_t rnbc; 864 uint64_t ruc; 865 uint64_t rfc; 866 uint64_t roc; 867 uint64_t rjc; 868 uint64_t mgprc; 869 uint64_t mgpdc; 870 uint64_t mgptc; 871 uint64_t torl; 872 uint64_t torh; 873 uint64_t totl; 874 uint64_t toth; 875 uint64_t tpr; 876 uint64_t tpt; 877 uint64_t ptc64; 878 uint64_t ptc127; 879 uint64_t ptc255; 880 uint64_t ptc511; 881 uint64_t ptc1023; 882 uint64_t ptc1522; 883 uint64_t mptc; 884 uint64_t bptc; 885 uint64_t tsctc; 886 uint64_t tsctfc; 887 }; 888 889 /* Structure containing variables used by the shared code (e1000_hw.c) */ 890 struct e1000_hw { 891 struct pci_device *pdev; 892 uint8_t *hw_addr; 893 e1000_mac_type mac_type; 894 e1000_phy_type phy_type; 895 #if 0 896 uint32_t phy_init_script; 897 #endif 898 e1000_media_type media_type; 899 e1000_fc_type fc; 900 #if 0 901 e1000_bus_speed bus_speed; 902 e1000_bus_width bus_width; 903 e1000_bus_type bus_type; 904 #endif 905 struct e1000_eeprom_info eeprom; 906 #if 0 907 e1000_ms_type master_slave; 908 e1000_ms_type original_master_slave; 909 e1000_ffe_config ffe_config_state; 910 #endif 911 uint32_t io_base; 912 uint32_t phy_id; 913 #ifdef LINUX_DRIVER 914 uint32_t phy_revision; 915 #endif 916 uint32_t phy_addr; 917 #if 0 918 uint32_t original_fc; 919 #endif 920 uint32_t txcw; 921 uint32_t autoneg_failed; 922 #if 0 923 uint32_t max_frame_size; 924 uint32_t min_frame_size; 925 uint32_t mc_filter_type; 926 uint32_t num_mc_addrs; 927 uint32_t collision_delta; 928 uint32_t tx_packet_delta; 929 uint32_t ledctl_default; 930 uint32_t ledctl_mode1; 931 uint32_t ledctl_mode2; 932 uint16_t phy_spd_default; 933 #endif 934 uint16_t autoneg_advertised; 935 uint16_t pci_cmd_word; 936 #if 0 937 uint16_t fc_high_water; 938 uint16_t fc_low_water; 939 uint16_t fc_pause_time; 940 uint16_t current_ifs_val; 941 uint16_t ifs_min_val; 942 uint16_t ifs_max_val; 943 uint16_t ifs_step_size; 944 uint16_t ifs_ratio; 945 #endif 946 uint16_t device_id; 947 uint16_t vendor_id; 948 #if 0 949 uint16_t subsystem_id; 950 uint16_t subsystem_vendor_id; 951 #endif 952 uint8_t revision_id; 953 #if 0 954 uint8_t autoneg; 955 uint8_t mdix; 956 uint8_t forced_speed_duplex; 957 uint8_t wait_autoneg_complete; 958 uint8_t dma_fairness; 959 #endif 960 uint8_t mac_addr[NODE_ADDRESS_SIZE]; 961 #if 0 962 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 963 boolean_t disable_polarity_correction; 964 boolean_t speed_downgraded; 965 e1000_dsp_config dsp_config_state; 966 boolean_t get_link_status; 967 boolean_t serdes_link_down; 968 #endif 969 boolean_t tbi_compatibility_en; 970 boolean_t tbi_compatibility_on; 971 #if 0 972 boolean_t phy_reset_disable; 973 boolean_t fc_send_xon; 974 boolean_t fc_strict_ieee; 975 boolean_t report_tx_early; 976 boolean_t adaptive_ifs; 977 boolean_t ifs_params_forced; 978 boolean_t in_ifs_mode; 979 #endif 980 }; 981 982 983 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 984 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 985 986 /* Register Bit Masks */ 987 /* Device Control */ 988 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 989 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 990 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 991 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 992 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 993 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 994 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 995 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 996 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 997 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 998 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 999 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1000 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1001 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1002 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1003 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1004 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1005 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1006 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1007 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1008 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1009 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1010 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1011 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1012 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 1013 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1014 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1015 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1016 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1017 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1018 1019 /* Device Status */ 1020 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1021 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1022 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1023 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1024 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1025 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1026 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1027 #define E1000_STATUS_SPEED_MASK 0x000000C0 1028 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1029 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1030 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1031 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1032 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1033 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1034 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1035 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1036 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1037 1038 /* Constants used to intrepret the masked PCI-X bus speed. */ 1039 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1040 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1041 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1042 1043 /* EEPROM/Flash Control */ 1044 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1045 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1046 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1047 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1048 #define E1000_EECD_FWE_MASK 0x00000030 1049 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1050 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1051 #define E1000_EECD_FWE_SHIFT 4 1052 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1053 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1054 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1055 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1056 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1057 * (0-small, 1-large) */ 1058 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1059 #ifndef E1000_EEPROM_GRANT_ATTEMPTS 1060 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1061 #endif 1062 1063 /* EEPROM Read */ 1064 #define E1000_EERD_START 0x00000001 /* Start Read */ 1065 #define E1000_EERD_DONE 0x00000010 /* Read Done */ 1066 #define E1000_EERD_ADDR_SHIFT 8 1067 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1068 #define E1000_EERD_DATA_SHIFT 16 1069 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1070 1071 /* SPI EEPROM Status Register */ 1072 #define EEPROM_STATUS_RDY_SPI 0x01 1073 #define EEPROM_STATUS_WEN_SPI 0x02 1074 #define EEPROM_STATUS_BP0_SPI 0x04 1075 #define EEPROM_STATUS_BP1_SPI 0x08 1076 #define EEPROM_STATUS_WPEN_SPI 0x80 1077 1078 /* Extended Device Control */ 1079 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1080 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1081 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1082 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1083 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1084 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1085 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1086 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1087 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1088 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1089 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1090 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1091 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1092 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1093 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1094 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1095 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1096 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1097 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1098 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1099 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1100 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 1101 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 1102 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1103 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1104 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1105 1106 /* MDI Control */ 1107 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1108 #define E1000_MDIC_REG_MASK 0x001F0000 1109 #define E1000_MDIC_REG_SHIFT 16 1110 #define E1000_MDIC_PHY_MASK 0x03E00000 1111 #define E1000_MDIC_PHY_SHIFT 21 1112 #define E1000_MDIC_OP_WRITE 0x04000000 1113 #define E1000_MDIC_OP_READ 0x08000000 1114 #define E1000_MDIC_READY 0x10000000 1115 #define E1000_MDIC_INT_EN 0x20000000 1116 #define E1000_MDIC_ERROR 0x40000000 1117 1118 /* LED Control */ 1119 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1120 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 1121 #define E1000_LEDCTL_LED0_IVRT 0x00000040 1122 #define E1000_LEDCTL_LED0_BLINK 0x00000080 1123 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1124 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 1125 #define E1000_LEDCTL_LED1_IVRT 0x00004000 1126 #define E1000_LEDCTL_LED1_BLINK 0x00008000 1127 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1128 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 1129 #define E1000_LEDCTL_LED2_IVRT 0x00400000 1130 #define E1000_LEDCTL_LED2_BLINK 0x00800000 1131 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1132 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 1133 #define E1000_LEDCTL_LED3_IVRT 0x40000000 1134 #define E1000_LEDCTL_LED3_BLINK 0x80000000 1135 1136 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 1137 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 1138 #define E1000_LEDCTL_MODE_LINK_UP 0x2 1139 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 1140 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 1141 #define E1000_LEDCTL_MODE_LINK_10 0x5 1142 #define E1000_LEDCTL_MODE_LINK_100 0x6 1143 #define E1000_LEDCTL_MODE_LINK_1000 0x7 1144 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 1145 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 1146 #define E1000_LEDCTL_MODE_COLLISION 0xA 1147 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 1148 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 1149 #define E1000_LEDCTL_MODE_PAUSED 0xD 1150 #define E1000_LEDCTL_MODE_LED_ON 0xE 1151 #define E1000_LEDCTL_MODE_LED_OFF 0xF 1152 1153 /* Receive Address */ 1154 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1155 1156 /* Interrupt Cause Read */ 1157 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1158 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1159 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1160 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1161 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1162 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1163 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1164 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1165 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1166 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1167 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1168 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1169 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1170 #define E1000_ICR_TXD_LOW 0x00008000 1171 #define E1000_ICR_SRPD 0x00010000 1172 1173 /* Interrupt Cause Set */ 1174 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1175 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1176 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1177 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1178 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1179 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1180 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1181 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1182 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1183 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1184 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1185 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1186 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1187 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1188 #define E1000_ICS_SRPD E1000_ICR_SRPD 1189 1190 /* Interrupt Mask Set */ 1191 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1192 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1193 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1194 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1195 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1196 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1197 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1198 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1199 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1200 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1201 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1202 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1203 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1204 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1205 #define E1000_IMS_SRPD E1000_ICR_SRPD 1206 1207 /* Interrupt Mask Clear */ 1208 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1209 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1210 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1211 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1212 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1213 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1214 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1215 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1216 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1217 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1218 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1219 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1220 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1221 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1222 #define E1000_IMC_SRPD E1000_ICR_SRPD 1223 1224 /* Receive Control */ 1225 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 1226 #define E1000_RCTL_EN 0x00000002 /* enable */ 1227 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1228 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1229 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1230 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1231 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1232 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1233 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1234 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1235 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1236 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1237 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1238 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1239 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1240 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1241 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1242 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1243 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1244 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1245 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1246 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1247 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1248 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1249 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1250 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1251 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1252 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1253 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1254 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1255 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1256 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1257 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1258 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1259 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1260 1261 /* Receive Descriptor */ 1262 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1263 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1264 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1265 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1266 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1267 1268 /* Flow Control */ 1269 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1270 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1271 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1272 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1273 1274 /* Receive Descriptor Control */ 1275 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1276 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1277 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1278 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1279 1280 /* Transmit Descriptor Control */ 1281 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ 1282 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ 1283 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ 1284 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1285 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1286 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1287 1288 /* Transmit Configuration Word */ 1289 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1290 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1291 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1292 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1293 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1294 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1295 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1296 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1297 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1298 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1299 1300 /* Receive Configuration Word */ 1301 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1302 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1303 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1304 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1305 #define E1000_RXCW_C 0x20000000 /* Receive config */ 1306 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1307 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1308 1309 /* Transmit Control */ 1310 #define E1000_TCTL_RST 0x00000001 /* software reset */ 1311 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 1312 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1313 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1314 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1315 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1316 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1317 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1318 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1319 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1320 1321 /* Receive Checksum Control */ 1322 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1323 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1324 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1325 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1326 1327 /* Definitions for power management and wakeup registers */ 1328 /* Wake Up Control */ 1329 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 1330 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1331 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1332 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1333 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 1334 1335 /* Wake Up Filter Control */ 1336 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1337 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1338 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1339 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1340 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1341 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1342 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1343 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1344 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1345 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1346 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1347 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 1348 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 1349 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 1350 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1351 1352 /* Wake Up Status */ 1353 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 1354 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 1355 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 1356 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 1357 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 1358 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 1359 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 1360 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 1361 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 1362 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 1363 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 1364 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 1365 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1366 1367 /* Management Control */ 1368 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 1369 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 1370 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 1371 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 1372 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 1373 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 1374 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 1375 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 1376 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 1377 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 1378 * Filtering */ 1379 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 1380 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 1381 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 1382 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 1383 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 1384 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 1385 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 1386 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 1387 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 1388 1389 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 1390 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 1391 1392 /* Wake Up Packet Length */ 1393 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 1394 1395 #define E1000_MDALIGN 4096 1396 1397 /* EEPROM Commands - Microwire */ 1398 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 1399 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 1400 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 1401 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 1402 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 1403 1404 /* EEPROM Commands - SPI */ 1405 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1406 #define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */ 1407 #define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */ 1408 #define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */ 1409 #define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */ 1410 #define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */ 1411 #define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */ 1412 #define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */ 1413 1414 /* EEPROM Size definitions */ 1415 #define EEPROM_SIZE_16KB 0x1800 1416 #define EEPROM_SIZE_8KB 0x1400 1417 #define EEPROM_SIZE_4KB 0x1000 1418 #define EEPROM_SIZE_2KB 0x0C00 1419 #define EEPROM_SIZE_1KB 0x0800 1420 #define EEPROM_SIZE_512B 0x0400 1421 #define EEPROM_SIZE_128B 0x0000 1422 #define EEPROM_SIZE_MASK 0x1C00 1423 1424 /* EEPROM Word Offsets */ 1425 #define EEPROM_COMPAT 0x0003 1426 #define EEPROM_ID_LED_SETTINGS 0x0004 1427 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 1428 #define EEPROM_INIT_CONTROL1_REG 0x000A 1429 #define EEPROM_INIT_CONTROL2_REG 0x000F 1430 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 1431 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 1432 #define EEPROM_CFG 0x0012 1433 #define EEPROM_FLASH_VERSION 0x0032 1434 #define EEPROM_CHECKSUM_REG 0x003F 1435 1436 /* Word definitions for ID LED Settings */ 1437 #define ID_LED_RESERVED_0000 0x0000 1438 #define ID_LED_RESERVED_FFFF 0xFFFF 1439 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1440 (ID_LED_OFF1_OFF2 << 8) | \ 1441 (ID_LED_DEF1_DEF2 << 4) | \ 1442 (ID_LED_DEF1_DEF2)) 1443 #define ID_LED_DEF1_DEF2 0x1 1444 #define ID_LED_DEF1_ON2 0x2 1445 #define ID_LED_DEF1_OFF2 0x3 1446 #define ID_LED_ON1_DEF2 0x4 1447 #define ID_LED_ON1_ON2 0x5 1448 #define ID_LED_ON1_OFF2 0x6 1449 #define ID_LED_OFF1_DEF2 0x7 1450 #define ID_LED_OFF1_ON2 0x8 1451 #define ID_LED_OFF1_OFF2 0x9 1452 1453 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1454 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1455 #define IGP_LED3_MODE 0x07000000 1456 1457 1458 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 1459 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 1460 1461 /* Mask bits for fields in Word 0x0a of the EEPROM */ 1462 #define EEPROM_WORD0A_ILOS 0x0010 1463 #define EEPROM_WORD0A_SWDPIO 0x01E0 1464 #define EEPROM_WORD0A_LRST 0x0200 1465 #define EEPROM_WORD0A_FD 0x0400 1466 #define EEPROM_WORD0A_66MHZ 0x0800 1467 1468 /* Mask bits for fields in Word 0x0f of the EEPROM */ 1469 #define EEPROM_WORD0F_PAUSE_MASK 0x3000 1470 #define EEPROM_WORD0F_PAUSE 0x1000 1471 #define EEPROM_WORD0F_ASM_DIR 0x2000 1472 #define EEPROM_WORD0F_ANE 0x0800 1473 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 1474 1475 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 1476 #define EEPROM_SUM 0xBABA 1477 1478 /* EEPROM Map defines (WORD OFFSETS)*/ 1479 #define EEPROM_NODE_ADDRESS_BYTE_0 0 1480 #define EEPROM_PBA_BYTE_1 8 1481 1482 #define EEPROM_RESERVED_WORD 0xFFFF 1483 1484 /* EEPROM Map Sizes (Byte Counts) */ 1485 #define PBA_SIZE 4 1486 1487 /* Collision related configuration parameters */ 1488 #define E1000_COLLISION_THRESHOLD 16 1489 #define E1000_CT_SHIFT 4 1490 #define E1000_COLLISION_DISTANCE 64 1491 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 1492 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 1493 #define E1000_COLD_SHIFT 12 1494 1495 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 1496 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 1497 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 1498 1499 /* Default values for the transmit IPG register */ 1500 #define DEFAULT_82542_TIPG_IPGT 10 1501 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 1502 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 1503 1504 #define E1000_TIPG_IPGT_MASK 0x000003FF 1505 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 1506 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 1507 1508 #define DEFAULT_82542_TIPG_IPGR1 2 1509 #define DEFAULT_82543_TIPG_IPGR1 8 1510 #define E1000_TIPG_IPGR1_SHIFT 10 1511 1512 #define DEFAULT_82542_TIPG_IPGR2 10 1513 #define DEFAULT_82543_TIPG_IPGR2 6 1514 #define E1000_TIPG_IPGR2_SHIFT 20 1515 1516 #define E1000_TXDMAC_DPP 0x00000001 1517 1518 /* Adaptive IFS defines */ 1519 #define TX_THRESHOLD_START 8 1520 #define TX_THRESHOLD_INCREMENT 10 1521 #define TX_THRESHOLD_DECREMENT 1 1522 #define TX_THRESHOLD_STOP 190 1523 #define TX_THRESHOLD_DISABLE 0 1524 #define TX_THRESHOLD_TIMER_MS 10000 1525 #define MIN_NUM_XMITS 1000 1526 #define IFS_MAX 80 1527 #define IFS_STEP 10 1528 #define IFS_MIN 40 1529 #define IFS_RATIO 4 1530 1531 /* PBA constants */ 1532 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 1533 #define E1000_PBA_22K 0x0016 1534 #define E1000_PBA_24K 0x0018 1535 #define E1000_PBA_30K 0x001E 1536 #define E1000_PBA_40K 0x0028 1537 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 1538 1539 /* Flow Control Constants */ 1540 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 1541 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 1542 #define FLOW_CONTROL_TYPE 0x8808 1543 1544 /* The historical defaults for the flow control values are given below. */ 1545 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 1546 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 1547 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 1548 1549 /* PCIX Config space */ 1550 #define PCIX_COMMAND_REGISTER 0xE6 1551 #define PCIX_STATUS_REGISTER_LO 0xE8 1552 #define PCIX_STATUS_REGISTER_HI 0xEA 1553 1554 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1555 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1556 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1557 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1558 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1559 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1560 1561 1562 /* Number of bits required to shift right the "pause" bits from the 1563 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 1564 */ 1565 #define PAUSE_SHIFT 5 1566 1567 /* Number of bits required to shift left the "SWDPIO" bits from the 1568 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. 1569 */ 1570 #define SWDPIO_SHIFT 17 1571 1572 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the 1573 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. 1574 */ 1575 #define SWDPIO__EXT_SHIFT 4 1576 1577 /* Number of bits required to shift left the "ILOS" bit from the EEPROM 1578 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. 1579 */ 1580 #define ILOS_SHIFT 3 1581 1582 1583 #define RECEIVE_BUFFER_ALIGN_SIZE (256) 1584 1585 /* Number of milliseconds we wait for auto-negotiation to complete */ 1586 #define LINK_UP_TIMEOUT 500 1587 1588 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 1589 1590 /* The carrier extension symbol, as received by the NIC. */ 1591 #define CARRIER_EXTENSION 0x0F 1592 1593 /* TBI_ACCEPT macro definition: 1594 * 1595 * This macro requires: 1596 * adapter = a pointer to struct e1000_hw 1597 * status = the 8 bit status field of the RX descriptor with EOP set 1598 * error = the 8 bit error field of the RX descriptor with EOP set 1599 * length = the sum of all the length fields of the RX descriptors that 1600 * make up the current frame 1601 * last_byte = the last byte of the frame DMAed by the hardware 1602 * max_frame_length = the maximum frame length we want to accept. 1603 * min_frame_length = the minimum frame length we want to accept. 1604 * 1605 * This macro is a conditional that should be used in the interrupt 1606 * handler's Rx processing routine when RxErrors have been detected. 1607 * 1608 * Typical use: 1609 * ... 1610 * if (TBI_ACCEPT) { 1611 * accept_frame = TRUE; 1612 * e1000_tbi_adjust_stats(adapter, MacAddress); 1613 * frame_length--; 1614 * } else { 1615 * accept_frame = FALSE; 1616 * } 1617 * ... 1618 */ 1619 1620 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ 1621 ((adapter)->tbi_compatibility_on && \ 1622 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 1623 ((last_byte) == CARRIER_EXTENSION) && \ 1624 (((status) & E1000_RXD_STAT_VP) ? \ 1625 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ 1626 ((length) <= ((adapter)->max_frame_size + 1))) : \ 1627 (((length) > (adapter)->min_frame_size) && \ 1628 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 1629 1630 1631 /* Structures, enums, and macros for the PHY */ 1632 1633 /* Bit definitions for the Management Data IO (MDIO) and Management Data 1634 * Clock (MDC) pins in the Device Control Register. 1635 */ 1636 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 1637 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 1638 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 1639 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 1640 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 1641 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 1642 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 1643 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 1644 1645 /* PHY 1000 MII Register/Bit Definitions */ 1646 /* PHY Registers defined by IEEE */ 1647 #define PHY_CTRL 0x00 /* Control Register */ 1648 #define PHY_STATUS 0x01 /* Status Regiser */ 1649 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1650 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1651 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1652 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1653 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1654 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 1655 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1656 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1657 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1658 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1659 1660 /* M88E1000 Specific Registers */ 1661 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1662 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1663 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1664 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 1665 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 1666 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1667 1668 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1669 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 1670 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 1671 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1672 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1673 1674 #define IGP01E1000_IEEE_REGS_PAGE 0x0000 1675 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 1676 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 1677 1678 /* IGP01E1000 Specific Registers */ 1679 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 1680 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 1681 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 1682 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 1683 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 1684 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 1685 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 1686 1687 /* IGP01E1000 AGC Registers - stores the cable length values*/ 1688 #define IGP01E1000_PHY_AGC_A 0x1172 1689 #define IGP01E1000_PHY_AGC_B 0x1272 1690 #define IGP01E1000_PHY_AGC_C 0x1472 1691 #define IGP01E1000_PHY_AGC_D 0x1872 1692 1693 /* IGP01E1000 DSP Reset Register */ 1694 #define IGP01E1000_PHY_DSP_RESET 0x1F33 1695 #define IGP01E1000_PHY_DSP_SET 0x1F71 1696 #define IGP01E1000_PHY_DSP_FFE 0x1F35 1697 1698 #define IGP01E1000_PHY_CHANNEL_NUM 4 1699 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 1700 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 1701 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 1702 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 1703 1704 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 1705 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 1706 1707 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 1708 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 1709 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 1710 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 1711 1712 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 1713 /* IGP01E1000 PCS Initialization register - stores the polarity status when 1714 * speed = 1000 Mbps. */ 1715 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 1716 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 1717 1718 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 1719 1720 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1721 #define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/ 1722 /* PHY Control Register */ 1723 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1724 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1725 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1726 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1727 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1728 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1729 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1730 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1731 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1732 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1733 1734 /* PHY Status Register */ 1735 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1736 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1737 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1738 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1739 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1740 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1741 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1742 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1743 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1744 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1745 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1746 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1747 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1748 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1749 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1750 1751 /* Autoneg Advertisement Register */ 1752 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1753 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1754 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1755 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1756 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1757 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1758 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1759 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1760 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1761 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1762 1763 /* Link Partner Ability Register (Base Page) */ 1764 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1765 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 1766 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 1767 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 1768 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 1769 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1770 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1771 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 1772 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 1773 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 1774 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1775 1776 /* Autoneg Expansion Register */ 1777 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1778 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 1779 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 1780 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 1781 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 1782 1783 /* Next Page TX Register */ 1784 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 1785 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 1786 * of different NP 1787 */ 1788 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 1789 * 0 = cannot comply with msg 1790 */ 1791 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 1792 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 1793 * 0 = sending last NP 1794 */ 1795 1796 /* Link Partner Next Page Register */ 1797 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 1798 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 1799 * of different NP 1800 */ 1801 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 1802 * 0 = cannot comply with msg 1803 */ 1804 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 1805 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 1806 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 1807 * 0 = sending last NP 1808 */ 1809 1810 /* 1000BASE-T Control Register */ 1811 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1812 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1813 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1814 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 1815 /* 0=DTE device */ 1816 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 1817 /* 0=Configure PHY as Slave */ 1818 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 1819 /* 0=Automatic Master/Slave config */ 1820 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1821 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1822 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1823 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1824 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1825 1826 /* 1000BASE-T Status Register */ 1827 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 1828 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 1829 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1830 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1831 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1832 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1833 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 1834 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1835 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 1836 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 1837 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1838 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 1839 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 1840 1841 /* Extended Status Register */ 1842 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 1843 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 1844 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 1845 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 1846 1847 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 1848 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 1849 1850 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 1851 /* (0=enable, 1=disable) */ 1852 1853 /* M88E1000 PHY Specific Control Register */ 1854 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1855 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 1856 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1857 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 1858 * 0=CLK125 toggling 1859 */ 1860 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 1861 /* Manual MDI configuration */ 1862 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1863 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 1864 * 100BASE-TX/10BASE-T: 1865 * MDI Mode 1866 */ 1867 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 1868 * all speeds. 1869 */ 1870 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 1871 /* 1=Enable Extended 10BASE-T distance 1872 * (Lower 10BASE-T RX Threshold) 1873 * 0=Normal 10BASE-T RX Threshold */ 1874 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1875 /* 1=5-Bit interface in 100BASE-TX 1876 * 0=MII interface in 100BASE-TX */ 1877 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1878 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1879 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 1880 1881 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 1882 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 1883 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 1884 1885 /* M88E1000 PHY Specific Status Register */ 1886 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1887 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1888 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1889 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1890 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 1891 * 3=110-140M;4=>140M */ 1892 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1893 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1894 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1895 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1896 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1897 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1898 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1899 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1900 1901 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 1902 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 1903 #define M88E1000_PSSR_MDIX_SHIFT 6 1904 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1905 1906 /* M88E1000 Extended PHY Specific Control Register */ 1907 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1908 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 1909 * Will assert lost lock and bring 1910 * link down if idle not seen 1911 * within 1ms in 1000BASE-T 1912 */ 1913 /* Number of times we will attempt to autonegotiate before downshifting if we 1914 * are the master */ 1915 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1916 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1917 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1918 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1919 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1920 /* Number of times we will attempt to autonegotiate before downshifting if we 1921 * are the slave */ 1922 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1923 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1924 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1925 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1926 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1927 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1928 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1929 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 1930 1931 /* IGP01E1000 Specific Port Config Register - R/W */ 1932 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 1933 #define IGP01E1000_PSCFR_PRE_EN 0x0020 1934 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 1935 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 1936 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 1937 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 1938 1939 /* IGP01E1000 Specific Port Status Register - R/O */ 1940 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 1941 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 1942 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 1943 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 1944 #define IGP01E1000_PSSR_LINK_UP 0x0400 1945 #define IGP01E1000_PSSR_MDIX 0x0800 1946 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 1947 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 1948 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 1949 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 1950 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 1951 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 1952 1953 /* IGP01E1000 Specific Port Control Register - R/W */ 1954 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0001 1955 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 1956 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 1957 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 1958 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 1959 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 1960 1961 /* IGP01E1000 Specific Port Link Health Register */ 1962 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 1963 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 1964 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 1965 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 1966 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 1967 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 1968 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010 1969 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008 1970 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004 1971 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002 1972 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001 1973 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000 1974 1975 /* IGP01E1000 Channel Quality Register */ 1976 #define IGP01E1000_MSE_CHANNEL_D 0x000F 1977 #define IGP01E1000_MSE_CHANNEL_C 0x00F0 1978 #define IGP01E1000_MSE_CHANNEL_B 0x0F00 1979 #define IGP01E1000_MSE_CHANNEL_A 0xF000 1980 1981 /* IGP01E1000 DSP reset macros */ 1982 #define DSP_RESET_ENABLE 0x0 1983 #define DSP_RESET_DISABLE 0x2 1984 #define E1000_MAX_DSP_RESETS 10 1985 1986 /* IGP01E1000 AGC Registers */ 1987 1988 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 1989 1990 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 1991 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 1992 1993 /* The precision of the length is +/- 10 meters */ 1994 #define IGP01E1000_AGC_RANGE 10 1995 1996 /* IGP01E1000 PCS Initialization register */ 1997 /* bits 3:6 in the PCS registers stores the channels polarity */ 1998 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 1999 2000 /* IGP01E1000 GMII FIFO Register */ 2001 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 2002 * on Link-Up */ 2003 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 2004 2005 /* IGP01E1000 Analog Register */ 2006 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 2007 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 2008 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 2009 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 2010 2011 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 2012 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 2013 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 2014 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 2015 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 2016 2017 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 2018 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 2019 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 2020 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 2021 2022 /* Bit definitions for valid PHY IDs. */ 2023 #define M88E1000_E_PHY_ID 0x01410C50 2024 #define M88E1000_I_PHY_ID 0x01410C30 2025 #define M88E1011_I_PHY_ID 0x01410C20 2026 #define IGP01E1000_I_PHY_ID 0x02A80380 2027 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 2028 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 2029 #define M88E1011_I_REV_4 0x04 2030 2031 /* Miscellaneous PHY bit definitions. */ 2032 #define PHY_PREAMBLE 0xFFFFFFFF 2033 #define PHY_SOF 0x01 2034 #define PHY_OP_READ 0x02 2035 #define PHY_OP_WRITE 0x01 2036 #define PHY_TURNAROUND 0x02 2037 #define PHY_PREAMBLE_SIZE 32 2038 #define MII_CR_SPEED_1000 0x0040 2039 #define MII_CR_SPEED_100 0x2000 2040 #define MII_CR_SPEED_10 0x0000 2041 #define E1000_PHY_ADDRESS 0x01 2042 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 2043 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 2044 #define PHY_REVISION_MASK 0xFFFFFFF0 2045 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 2046 #define REG4_SPEED_MASK 0x01E0 2047 #define REG9_SPEED_MASK 0x0300 2048 #define ADVERTISE_10_HALF 0x0001 2049 #define ADVERTISE_10_FULL 0x0002 2050 #define ADVERTISE_100_HALF 0x0004 2051 #define ADVERTISE_100_FULL 0x0008 2052 #define ADVERTISE_1000_HALF 0x0010 2053 #define ADVERTISE_1000_FULL 0x0020 2054 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 2055 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 2056 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 2057 2058 #endif /* _E1000_HW_H_ */ 2059