1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _FABRIC_XLATE_H 26 #define _FABRIC_XLATE_H 27 28 #include <fm/fmd_api.h> 29 #include <sys/fm/protocol.h> 30 #include <sys/nvpair.h> 31 #include <sys/types.h> 32 #include <sys/pcie.h> 33 #include <sys/fm/io/pci.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #define STRCMP(s1, s2) (strcmp((const char *)s1, (const char *)s2) == 0) 40 /* 41 * These values are used for the xxx_tgt_trans value in fab_data_t. They are 42 * originally set in pcie_fault.c and originally defined in pcie_impl.h. 43 */ 44 #define PF_ADDR_DMA (1 << 0) 45 #define PF_ADDR_PIO (1 << 1) 46 #define PF_ADDR_CFG (1 << 2) 47 48 extern fmd_xprt_t *fab_fmd_xprt; /* FMD transport layer handle */ 49 extern char fab_buf[]; 50 51 /* PCI-E config space data for error handling and fabric ereports */ 52 typedef struct fab_data { 53 /* Original ereport NVL */ 54 nvlist_t *nvl; 55 56 /* Device Information */ 57 uint16_t bdf; 58 uint16_t device_id; 59 uint16_t vendor_id; 60 uint8_t rev_id; 61 uint16_t dev_type; 62 uint16_t pcie_off; 63 uint16_t pcix_off; 64 uint16_t aer_off; 65 uint16_t ecc_ver; 66 67 /* Ereport Information */ 68 uint32_t remainder; 69 uint32_t severity; 70 71 /* Error Registers */ 72 uint16_t pci_err_status; /* pci status register */ 73 uint16_t pci_cfg_comm; /* pci command register */ 74 75 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 76 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 77 78 uint16_t pcix_command; /* pcix command register */ 79 uint32_t pcix_status; /* pcix status register */ 80 81 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 82 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 83 84 uint16_t pcix_ecc_control_0; /* pcix ecc control status reg */ 85 uint16_t pcix_ecc_status_0; /* pcix ecc control status reg */ 86 uint32_t pcix_ecc_fst_addr_0; /* pcix ecc first address reg */ 87 uint32_t pcix_ecc_sec_addr_0; /* pcix ecc second address reg */ 88 uint32_t pcix_ecc_attr_0; /* pcix ecc attributes reg */ 89 uint16_t pcix_ecc_control_1; /* pcix ecc control status reg */ 90 uint16_t pcix_ecc_status_1; /* pcix ecc control status reg */ 91 uint32_t pcix_ecc_fst_addr_1; /* pcix ecc first address reg */ 92 uint32_t pcix_ecc_sec_addr_1; /* pcix ecc second address reg */ 93 uint32_t pcix_ecc_attr_1; /* pcix ecc attributes reg */ 94 95 uint16_t pcie_err_status; /* pcie device status register */ 96 uint16_t pcie_err_ctl; /* pcie error control register */ 97 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 98 99 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 100 uint32_t pcie_ue_status; /* pcie ue error status reg */ 101 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 102 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 103 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 104 uint32_t pcie_ce_status; /* pcie ce error status reg */ 105 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 106 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 107 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 108 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from SAER Logs */ 109 boolean_t pcie_ue_no_tgt_erpt; /* Don't send target ereports */ 110 111 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 112 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 113 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 114 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 115 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 116 uint32_t pcie_sue_tgt_trans; /* Fault trans type from AER Logs */ 117 uint64_t pcie_sue_tgt_addr; /* Fault addr from AER Logs */ 118 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 119 120 uint32_t pcie_rp_status; /* root complex status register */ 121 uint16_t pcie_rp_ctl; /* root complex control register */ 122 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 123 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 124 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 125 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 126 127 /* Flags */ 128 boolean_t pcie_rp_send_all; /* need to send ereports on all rps */ 129 } fab_data_t; 130 131 typedef struct fab_erpt_tbl { 132 const char *err_class; /* Final Ereport Class */ 133 uint32_t reg_bit; /* Error Bit Mask */ 134 /* Pointer to function that prepares the ereport body */ 135 const char *tgt_class; /* Target Ereport Class */ 136 } fab_erpt_tbl_t; 137 138 typedef struct fab_err_tbl { 139 fab_erpt_tbl_t *erpt_tbl; /* ereport table */ 140 uint32_t reg_offset; /* sts reg for ereport table offset */ 141 uint32_t reg_size; /* size of the status register */ 142 /* Pointer to function that prepares the ereport body */ 143 int (*fab_prep)(fmd_hdl_t *, fab_data_t *, nvlist_t *, 144 fab_erpt_tbl_t *); 145 } fab_err_tbl_t; 146 147 extern void fab_setup_master_table(); 148 149 /* Main functions for converting "fabric" ereports */ 150 extern void fab_xlate_pcie_erpts(fmd_hdl_t *, fab_data_t *); 151 extern void fab_xlate_fabric_erpts(fmd_hdl_t *, nvlist_t *, const char *); 152 extern void fab_xlate_fire_erpts(fmd_hdl_t *, nvlist_t *, const char *); 153 extern void fab_xlate_epkt_erpts(fmd_hdl_t *, nvlist_t *, const char *); 154 155 /* Common functions for sending translated ereports */ 156 extern int fab_prep_basic_erpt(fmd_hdl_t *, nvlist_t *, nvlist_t *, boolean_t); 157 extern void fab_send_tgt_erpt(fmd_hdl_t *, fab_data_t *, const char *, 158 boolean_t); 159 extern void fab_send_erpt(fmd_hdl_t *hdl, fab_data_t *data, fab_err_tbl_t *tbl); 160 161 /* Misc Functions */ 162 extern void fab_pr(fmd_hdl_t *, fmd_event_t *, nvlist_t *); 163 extern boolean_t fab_get_hcpath(fmd_hdl_t *, nvlist_t *, char **, size_t *); 164 extern boolean_t fab_get_rcpath(fmd_hdl_t *, nvlist_t *, char *); 165 extern char *fab_find_rppath_by_df(fmd_hdl_t *, nvlist_t *, uint8_t); 166 extern char *fab_find_rppath_by_devbdf(fmd_hdl_t *, nvlist_t *, pcie_req_id_t); 167 extern char *fab_find_rppath_by_devpath(fmd_hdl_t *, const char *); 168 extern char *fab_find_addr(fmd_hdl_t *hdl, nvlist_t *nvl, uint64_t addr); 169 extern char *fab_find_bdf(fmd_hdl_t *hdl, nvlist_t *nvl, pcie_req_id_t bdf); 170 extern boolean_t fab_hc2dev(fmd_hdl_t *, const char *, char **); 171 extern boolean_t fab_hc2dev_nvl(fmd_hdl_t *, nvlist_t *, char **); 172 extern char *fab_get_rpdev(fmd_hdl_t *); 173 extern void fab_set_fake_rp(fmd_hdl_t *); 174 extern void fab_send_erpt_all_rps(fmd_hdl_t *, nvlist_t *); 175 176 #ifdef __cplusplus 177 } 178 #endif 179 180 #endif /* _FABRIC_XLATE_H */ 181