1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HYPERVISOR_API_H 28 #define _SYS_HYPERVISOR_API_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * sun4v Hypervisor API 34 * 35 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 36 * io-api.txt version 1.11 dated 10/19/2004 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * Trap types 45 */ 46 #define FAST_TRAP 0x80 /* Function # in %o5 */ 47 #define CPU_TICK_NPT 0x81 48 #define CPU_STICK_NPT 0x82 49 #define MMU_MAP_ADDR 0x83 50 #define MMU_UNMAP_ADDR 0x84 51 52 /* 53 * Error returns in %o0. 54 * (Additional result is returned in %o1.) 55 */ 56 #define H_EOK 0 /* Successful return */ 57 #define H_ENOCPU 1 /* Invalid CPU id */ 58 #define H_ENORADDR 2 /* Invalid real address */ 59 #define H_ENOINTR 3 /* Invalid interrupt id */ 60 #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 61 #define H_EBADTSB 5 /* Invalid TSB description */ 62 #define H_EINVAL 6 /* Invalid argument */ 63 #define H_EBADTRAP 7 /* Invalid function number */ 64 #define H_EBADALIGN 8 /* Invalid address alignment */ 65 #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 66 /* without blocking */ 67 #define H_ENOACCESS 10 /* No access to resource */ 68 #define H_EIO 11 /* I/O error */ 69 #define H_ECPUERROR 12 /* CPU is in error state */ 70 #define H_ENOTSUPPORTED 13 /* Function not supported */ 71 #define H_ENOMAP 14 /* Mapping is not valid, */ 72 /* no translation exists */ 73 74 #define H_BREAK -1 /* Console Break */ 75 #define H_HUP -2 /* Console Break */ 76 77 /* 78 * Mondo CPU ID argument processing. 79 */ 80 #define HV_SEND_MONDO_ENTRYDONE 0xffff 81 82 /* 83 * Function numbers for FAST_TRAP. 84 */ 85 #define HV_MACH_EXIT 0x00 86 #define HV_MACH_DESC 0x01 87 #define HV_CPU_YIELD 0x12 88 #define CPU_QCONF 0x14 89 #define HV_CPU_STATE 0x17 90 #define MMU_TSB_CTX0 0x20 91 #define MMU_TSB_CTXNON0 0x21 92 #define MMU_DEMAP_PAGE 0x22 93 #define MMU_DEMAP_CTX 0x23 94 #define MMU_DEMAP_ALL 0x24 95 #define MAP_PERM_ADDR 0x25 96 #define MMU_SET_INFOPTR 0x26 97 #define UNMAP_PERM_ADDR 0x28 98 #define HV_MEM_SCRUB 0x31 99 #define HV_MEM_SYNC 0x32 100 #define HV_INTR_SEND 0x42 101 #define TOD_GET 0x50 102 #define TOD_SET 0x51 103 #define CONS_READ 0x60 104 #define CONS_WRITE 0x61 105 106 #define SVC_SEND 0x80 107 #define SVC_RECV 0x81 108 #define SVC_GETSTATUS 0x82 109 #define SVC_SETSTATUS 0x83 110 #define SVC_CLRSTATUS 0x84 111 112 #define TTRACE_BUF_CONF 0x90 113 #define TTRACE_BUF_INFO 0x91 114 #define TTRACE_ENABLE 0x92 115 #define TTRACE_FREEZE 0x93 116 117 #define DUMP_BUF_UPDATE 0x94 118 119 #define HVIO_INTR_DEVINO2SYSINO 0xa0 120 #define HVIO_INTR_GETVALID 0xa1 121 #define HVIO_INTR_SETVALID 0xa2 122 #define HVIO_INTR_GETSTATE 0xa3 123 #define HVIO_INTR_SETSTATE 0xa4 124 #define HVIO_INTR_GETTARGET 0xa5 125 #define HVIO_INTR_SETTARGET 0xa6 126 127 #define HVIO_IOMMU_MAP 0xb0 128 #define HVIO_IOMMU_DEMAP 0xb1 129 #define HVIO_IOMMU_GETMAP 0xb2 130 #define HVIO_IOMMU_GETBYPASS 0xb3 131 132 #define HVIO_CONFIG_GET 0xb4 133 #define HVIO_CONFIG_PUT 0xb5 134 135 #define HVIO_PEEK 0xb6 136 #define HVIO_POKE 0xb7 137 138 #define HVIO_DMA_SYNC 0xb8 139 140 #define HVIO_MSIQ_CONF 0xc0 141 #define HVIO_MSIQ_INFO 0xc1 142 #define HVIO_MSIQ_GETVALID 0xc2 143 #define HVIO_MSIQ_SETVALID 0xc3 144 #define HVIO_MSIQ_GETSTATE 0xc4 145 #define HVIO_MSIQ_SETSTATE 0xc5 146 #define HVIO_MSIQ_GETHEAD 0xc6 147 #define HVIO_MSIQ_SETHEAD 0xc7 148 #define HVIO_MSIQ_GETTAIL 0xc8 149 150 #define HVIO_MSI_GETVALID 0xc9 151 #define HVIO_MSI_SETVALID 0xca 152 #define HVIO_MSI_GETMSIQ 0xcb 153 #define HVIO_MSI_SETMSIQ 0xcc 154 #define HVIO_MSI_GETSTATE 0xcd 155 #define HVIO_MSI_SETSTATE 0xce 156 157 #define HVIO_MSG_GETMSIQ 0xd0 158 #define HVIO_MSG_SETMSIQ 0xd1 159 #define HVIO_MSG_GETVALID 0xd2 160 #define HVIO_MSG_SETVALID 0xd3 161 162 #ifdef SET_MMU_STATS 163 #define MMU_STAT_AREA 0xfc 164 #endif /* SET_MMU_STATS */ 165 166 #define HV_NCS_REQUEST 0x110 167 168 #define FIRE_GET_PERFREG 0x120 169 #define FIRE_SET_PERFREG 0x121 170 171 #define HV_RA2PA 0x200 172 #define HV_HPRIV 0x201 173 174 /* 175 * Bits for MMU functions flags argument: 176 * arg3 of MMU_MAP_ADDR 177 * arg3 of MMU_DEMAP_CTX 178 * arg2 of MMU_DEMAP_ALL 179 */ 180 #define MAP_DTLB 0x1 181 #define MAP_ITLB 0x2 182 183 184 /* 185 * Interrupt state manipulation definitions. 186 */ 187 188 #define HV_INTR_IDLE_STATE 0 189 #define HV_INTR_RECEIVED_STATE 1 190 #define HV_INTR_DELIVERED_STATE 2 191 192 #define HV_INTR_NOTVALID 0 193 #define HV_INTR_VALID 1 194 195 #ifndef _ASM 196 197 /* 198 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 199 */ 200 typedef struct hv_tsb_info { 201 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 202 uint16_t hvtsb_assoc; /* TSB associativity */ 203 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 204 uint32_t hvtsb_ctx_index; /* context reg index */ 205 uint32_t hvtsb_pgszs; /* sizes in use */ 206 uint64_t hvtsb_pa; /* real address of TSB base */ 207 uint64_t hvtsb_rsvd; /* reserved */ 208 } hv_tsb_info_t; 209 210 #define HVTSB_SHARE_INDEX ((uint32_t)-1) 211 212 #ifdef SET_MMU_STATS 213 #ifndef TTE4V_NPGSZ 214 #define TTE4V_NPGSZ 8 215 #endif /* TTE4V_NPGSZ */ 216 /* 217 * MMU statistics structure for MMU_STAT_AREA 218 */ 219 struct mmu_stat_one { 220 uint64_t hit_ctx0[TTE4V_NPGSZ]; 221 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 222 uint64_t tsb_miss; 223 uint64_t tlb_miss; /* miss, no TSB set */ 224 uint64_t map_ctx0[TTE4V_NPGSZ]; 225 uint64_t map_ctxn0[TTE4V_NPGSZ]; 226 }; 227 228 struct mmu_stat { 229 struct mmu_stat_one immu_stat; 230 struct mmu_stat_one dmmu_stat; 231 uint64_t set_ctx0; 232 uint64_t set_ctxn0; 233 }; 234 #endif /* SET_MMU_STATS */ 235 236 #endif /* _ASM */ 237 238 /* 239 * CPU States 240 */ 241 #define CPU_STATE_INVALID 0x0 242 #define CPU_STATE_IDLE 0x1 /* cpu not started */ 243 #define CPU_STATE_GUEST 0x2 /* cpu running guest code */ 244 #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 245 #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 246 247 /* 248 * MMU fault status area 249 */ 250 251 #define MMFSA_TYPE_ 0x00 /* fault type */ 252 #define MMFSA_ADDR_ 0x08 /* fault address */ 253 #define MMFSA_CTX_ 0x10 /* fault context */ 254 255 #define MMFSA_I_ 0x00 /* start of fields for I */ 256 #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 257 #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 258 #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 259 260 #define MMFSA_D_ 0x40 /* start of fields for D */ 261 #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 262 #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 263 #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 264 265 #define MMFSA_F_FMISS 1 /* fast miss */ 266 #define MMFSA_F_FPROT 2 /* fast protection */ 267 #define MMFSA_F_MISS 3 /* mmu miss */ 268 #define MMFSA_F_INVRA 4 /* invalid RA */ 269 #define MMFSA_F_PRIV 5 /* privilege violation */ 270 #define MMFSA_F_PROT 6 /* protection violation */ 271 #define MMFSA_F_NFO 7 /* NFO access */ 272 #define MMFSA_F_SOPG 8 /* so page */ 273 #define MMFSA_F_INVVA 9 /* invalid VA */ 274 #define MMFSA_F_INVASI 10 /* invalid ASI */ 275 #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 276 #define MMFSA_F_PRVACT 12 /* privileged action */ 277 #define MMFSA_F_WPT 13 /* watchpoint hit */ 278 #define MMFSA_F_UNALIGN 14 /* unaligned access */ 279 #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 280 281 #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 282 283 /* 284 * MMU fault status - MMFSA_IFS and MMFSA_DFS 285 */ 286 #define MMFS_FV 0x00000001 287 #define MMFS_OW 0x00000002 288 #define MMFS_W 0x00000004 289 #define MMFS_PR 0x00000008 290 #define MMFS_CT 0x00000030 291 #define MMFS_E 0x00000040 292 #define MMFS_FT 0x00003f80 293 #define MMFS_ME 0x00004000 294 #define MMFS_TM 0x00008000 295 #define MMFS_ASI 0x00ff0000 296 #define MMFS_NF 0x01000000 297 298 /* 299 * DMA sync parameter definitions 300 */ 301 #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 302 #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 303 304 /* 305 * Performance counter register definitions. 306 */ 307 #define HVIO_FIRE_PERFREG_JBC_SEL 0 308 #define HVIO_FIRE_PERFREG_JBC_CNT0 1 309 #define HVIO_FIRE_PERFREG_JBC_CNT1 2 310 #define HVIO_FIRE_PERFREG_PCIE_IMU_SEL 3 311 #define HVIO_FIRE_PERFREG_PCIE_IMU_CNT0 4 312 #define HVIO_FIRE_PERFREG_PCIE_IMU_CNT1 5 313 #define HVIO_FIRE_PERFREG_PCIE_MMU_SEL 6 314 #define HVIO_FIRE_PERFREG_PCIE_MMU_CNT0 7 315 #define HVIO_FIRE_PERFREG_PCIE_MMU_CNT1 8 316 #define HVIO_FIRE_PERFREG_PCIE_TLU_SEL 9 317 #define HVIO_FIRE_PERFREG_PCIE_TLU_CNT0 10 318 #define HVIO_FIRE_PERFREG_PCIE_TLU_CNT1 11 319 #define HVIO_FIRE_PERFREG_PCIE_TLU_CNT2 12 320 #define HVIO_FIRE_PERFREG_PCIE_LNK_SEL 13 321 #define HVIO_FIRE_PERFREG_PCIE_LNK_CNT1 14 322 #define HVIO_FIRE_PERFREG_PCIE_LNK_CNT2 15 323 324 #ifndef _ASM 325 326 extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 327 extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 328 extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 329 extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 330 #ifdef SET_MMU_STATS 331 extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 332 #endif /* SET_MMU_STATS */ 333 334 extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 335 extern uint64_t hv_cpu_yield(); 336 337 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 338 extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 339 uint64_t *scrubbed_len); 340 extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 341 uint64_t *flushed_len); 342 343 extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 344 uint64_t size, uint64_t *recv_bytes); 345 extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 346 uint64_t size, uint64_t *send_bytes); 347 extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 348 extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 349 extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 350 351 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 352 353 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 354 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 355 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 356 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 357 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 358 359 extern int64_t hv_cnputchar(uint8_t); 360 extern int64_t hv_cngetchar(uint8_t *); 361 362 extern uint64_t hv_tod_get(uint64_t *seconds); 363 extern uint64_t hv_tod_set(uint64_t); 364 365 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 366 uint64_t *sysino); 367 extern uint64_t hvio_intr_getvalid(uint64_t sysino, 368 int *intr_valid_state); 369 extern uint64_t hvio_intr_setvalid(uint64_t sysino, 370 int intr_valid_state); 371 extern uint64_t hvio_intr_getstate(uint64_t sysino, 372 int *intr_state); 373 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 374 extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 375 extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 376 377 #endif 378 379 #ifdef __cplusplus 380 } 381 #endif 382 383 #endif /* _SYS_HYPERVISOR_API_H */ 384