1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26/* 27 * Hypervisor calls 28 */ 29 30#include <sys/asm_linkage.h> 31#include <sys/machasi.h> 32#include <sys/machparam.h> 33#include <sys/hypervisor_api.h> 34 35#if defined(lint) || defined(__lint) 36 37/*ARGSUSED*/ 38uint64_t 39hv_mach_exit(uint64_t exit_code) 40{ return (0); } 41 42uint64_t 43hv_mach_sir(void) 44{ return (0); } 45 46/*ARGSUSED*/ 47uint64_t 48hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 49{ return (0); } 50 51/*ARGSUSED*/ 52uint64_t 53hv_cpu_stop(uint64_t cpuid) 54{ return (0); } 55 56/*ARGSUSED*/ 57uint64_t 58hv_cpu_set_rtba(uint64_t *rtba) 59{ return (0); } 60 61/*ARGSUSED*/ 62int64_t 63hv_cnputchar(uint8_t ch) 64{ return (0); } 65 66/*ARGSUSED*/ 67int64_t 68hv_cngetchar(uint8_t *ch) 69{ return (0); } 70 71/*ARGSUSED*/ 72uint64_t 73hv_tod_get(uint64_t *seconds) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hv_tod_set(uint64_t seconds) 79{ return (0);} 80 81/*ARGSUSED*/ 82uint64_t 83hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 84{ return (0); } 85 86/*ARGSUSED */ 87uint64_t 88hv_mmu_fault_area_conf(void *raddr) 89{ return (0); } 90 91/*ARGSUSED*/ 92uint64_t 93hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 94{ return (0); } 95 96/*ARGSUSED*/ 97uint64_t 98hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 99{ return (0); } 100 101/*ARGSUSED*/ 102uint64_t 103hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 104{ return (0); } 105 106#ifdef SET_MMU_STATS 107/*ARGSUSED*/ 108uint64_t 109hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 110{ return (0); } 111#endif /* SET_MMU_STATS */ 112 113/*ARGSUSED*/ 114uint64_t 115hv_cpu_qconf(int queue, uint64_t paddr, int size) 116{ return (0); } 117 118/*ARGSUSED*/ 119uint64_t 120hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 121{ return (0); } 122 123/*ARGSUSED*/ 124uint64_t 125hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 126{ return (0); } 127 128/*ARGSUSED*/ 129uint64_t 130hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 131{ return (0); } 132 133/*ARGSUSED*/ 134uint64_t 135hvio_intr_getstate(uint64_t sysino, int *intr_state) 136{ return (0); } 137 138/*ARGSUSED*/ 139uint64_t 140hvio_intr_setstate(uint64_t sysino, int intr_state) 141{ return (0); } 142 143/*ARGSUSED*/ 144uint64_t 145hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 146{ return (0); } 147 148/*ARGSUSED*/ 149uint64_t 150hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 151{ return (0); } 152 153uint64_t 154hv_cpu_yield(void) 155{ return (0); } 156 157/*ARGSUSED*/ 158uint64_t 159hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 160{ return (0); } 161 162/*ARGSUSED*/ 163uint64_t 164hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 165{ return (0); } 166 167/*ARGSUSED*/ 168uint64_t 169hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 170{ return (0); } 171 172/*ARGSUSED*/ 173uint64_t 174hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 175{ return (0); } 176 177/*ARGSUSED*/ 178uint64_t 179hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 180{ return (0); } 181 182/*ARGSUSED*/ 183uint64_t 184hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 185{ return (0); } 186 187/*ARGSUSED*/ 188uint64_t 189hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 190{ return (0); } 191 192/*ARGSUSED*/ 193uint64_t 194hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 195{ return (0); } 196 197/*ARGSUSED*/ 198uint64_t 199hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 200{ return (0); } 201 202/*ARGSUSED*/ 203uint64_t 204hv_ra2pa(uint64_t ra) 205{ return (0); } 206 207/*ARGSUSED*/ 208uint64_t 209hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 210{ return (0); } 211 212/*ARGSUSED*/ 213uint64_t 214hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 215{ return (0); } 216 217/*ARGSUSED*/ 218uint64_t 219hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 220{ return (0); } 221 222/*ARGSUSED*/ 223uint64_t 224hv_ldc_tx_get_state(uint64_t channel, 225 uint64_t *headp, uint64_t *tailp, uint64_t *state) 226{ return (0); } 227 228/*ARGSUSED*/ 229uint64_t 230hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 231{ return (0); } 232 233/*ARGSUSED*/ 234uint64_t 235hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 236{ return (0); } 237 238/*ARGSUSED*/ 239uint64_t 240hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 241{ return (0); } 242 243/*ARGSUSED*/ 244uint64_t 245hv_ldc_rx_get_state(uint64_t channel, 246 uint64_t *headp, uint64_t *tailp, uint64_t *state) 247{ return (0); } 248 249/*ARGSUSED*/ 250uint64_t 251hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 252{ return (0); } 253 254/*ARGSUSED*/ 255uint64_t 256hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 257{ return (0); } 258 259/*ARGSUSED*/ 260uint64_t 261hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 262{ return (0); } 263 264/*ARGSUSED*/ 265uint64_t 266hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 267 uint64_t raddr, uint64_t length, uint64_t *lengthp) 268{ return (0); } 269 270/*ARGSUSED*/ 271uint64_t 272hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 273{ return (0); } 274 275/*ARGSUSED*/ 276uint64_t 277hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 278{ return (0); } 279 280/*ARGSUSED*/ 281uint64_t 282hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 283{ return (0); } 284 285/*ARGSUSED*/ 286uint64_t 287hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 288{ return (0); } 289 290/*ARGSUSED*/ 291uint64_t 292hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 293{ return (0); } 294 295/*ARGSUSED*/ 296uint64_t 297hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 298{ return (0); } 299 300/*ARGSUSED*/ 301uint64_t 302hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 303{ return (0); } 304 305/*ARGSUSED*/ 306uint64_t 307hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 308{ return (0); } 309 310/*ARGSUSED*/ 311uint64_t 312hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 313{ return (0); } 314 315/*ARGSUSED*/ 316uint64_t 317hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 318 uint64_t *supported_minor) 319{ return (0); } 320 321/*ARGSUSED*/ 322uint64_t 323hv_tm_enable(uint64_t enable) 324{ return (0); } 325 326/*ARGSUSED*/ 327uint64_t 328hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 329{ return (0); } 330 331/*ARGSUSED*/ 332int64_t 333hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 334{ return (0); } 335 336/*ARGSUSED*/ 337int64_t 338hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 339{ return (0); } 340 341/*ARGSUSED*/ 342uint64_t 343hv_soft_state_set(uint64_t state, uint64_t string) 344{ return (0); } 345 346/*ARGSUSED*/ 347uint64_t 348hv_soft_state_get(uint64_t string, uint64_t *state) 349{ return (0); }uint64_t 350hv_guest_suspend(void) 351{ return (0); } 352 353/*ARGSUSED*/ 354uint64_t 355hv_tick_set_npt(uint64_t npt) 356{ return (0); } 357 358/*ARGSUSED*/ 359uint64_t 360hv_stick_set_npt(uint64_t npt) 361{ return (0); } 362 363/*ARGSUSED*/ 364uint64_t 365hv_reboot_data_set(uint64_t buffer_ra, uint64_t buffer_len) 366{ return (0); } 367 368#else /* lint || __lint */ 369 370 /* 371 * int hv_mach_exit(uint64_t exit_code) 372 */ 373 ENTRY(hv_mach_exit) 374 mov HV_MACH_EXIT, %o5 375 ta FAST_TRAP 376 retl 377 nop 378 SET_SIZE(hv_mach_exit) 379 380 /* 381 * uint64_t hv_mach_sir(void) 382 */ 383 ENTRY(hv_mach_sir) 384 mov HV_MACH_SIR, %o5 385 ta FAST_TRAP 386 retl 387 nop 388 SET_SIZE(hv_mach_sir) 389 390 /* 391 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 392 * uint64_t arg) 393 */ 394 ENTRY(hv_cpu_start) 395 mov HV_CPU_START, %o5 396 ta FAST_TRAP 397 retl 398 nop 399 SET_SIZE(hv_cpu_start) 400 401 /* 402 * hv_cpu_stop(uint64_t cpuid) 403 */ 404 ENTRY(hv_cpu_stop) 405 mov HV_CPU_STOP, %o5 406 ta FAST_TRAP 407 retl 408 nop 409 SET_SIZE(hv_cpu_stop) 410 411 /* 412 * hv_cpu_set_rtba(uint64_t *rtba) 413 */ 414 ENTRY(hv_cpu_set_rtba) 415 mov %o0, %o2 416 ldx [%o2], %o0 417 mov HV_CPU_SET_RTBA, %o5 418 ta FAST_TRAP 419 stx %o1, [%o2] 420 retl 421 nop 422 SET_SIZE(hv_cpu_set_rtba) 423 424 /* 425 * int64_t hv_cnputchar(uint8_t ch) 426 */ 427 ENTRY(hv_cnputchar) 428 mov CONS_PUTCHAR, %o5 429 ta FAST_TRAP 430 retl 431 nop 432 SET_SIZE(hv_cnputchar) 433 434 /* 435 * int64_t hv_cngetchar(uint8_t *ch) 436 */ 437 ENTRY(hv_cngetchar) 438 mov %o0, %o2 439 mov CONS_GETCHAR, %o5 440 ta FAST_TRAP 441 brnz,a %o0, 1f ! failure, just return error 442 nop 443 444 cmp %o1, H_BREAK 445 be 1f 446 mov %o1, %o0 447 448 cmp %o1, H_HUP 449 be 1f 450 mov %o1, %o0 451 452 stb %o1, [%o2] ! success, save character and return 0 453 mov 0, %o0 4541: 455 retl 456 nop 457 SET_SIZE(hv_cngetchar) 458 459 ENTRY(hv_tod_get) 460 mov %o0, %o4 461 mov TOD_GET, %o5 462 ta FAST_TRAP 463 retl 464 stx %o1, [%o4] 465 SET_SIZE(hv_tod_get) 466 467 ENTRY(hv_tod_set) 468 mov TOD_SET, %o5 469 ta FAST_TRAP 470 retl 471 nop 472 SET_SIZE(hv_tod_set) 473 474 /* 475 * Map permanent address 476 * arg0 vaddr (%o0) 477 * arg1 context (%o1) 478 * arg2 tte (%o2) 479 * arg3 flags (%o3) 0x1=d 0x2=i 480 */ 481 ENTRY(hv_mmu_map_perm_addr) 482 mov MAP_PERM_ADDR, %o5 483 ta FAST_TRAP 484 retl 485 nop 486 SET_SIZE(hv_mmu_map_perm_addr) 487 488 /* 489 * hv_mmu_fault_area_conf(void *raddr) 490 */ 491 ENTRY(hv_mmu_fault_area_conf) 492 mov %o0, %o2 493 ldx [%o2], %o0 494 mov MMU_SET_INFOPTR, %o5 495 ta FAST_TRAP 496 stx %o1, [%o2] 497 retl 498 nop 499 SET_SIZE(hv_mmu_fault_area_conf) 500 501 /* 502 * Unmap permanent address 503 * arg0 vaddr (%o0) 504 * arg1 context (%o1) 505 * arg2 flags (%o2) 0x1=d 0x2=i 506 */ 507 ENTRY(hv_mmu_unmap_perm_addr) 508 mov UNMAP_PERM_ADDR, %o5 509 ta FAST_TRAP 510 retl 511 nop 512 SET_SIZE(hv_mmu_unmap_perm_addr) 513 514 /* 515 * Set TSB for context 0 516 * arg0 ntsb_descriptor (%o0) 517 * arg1 desc_ra (%o1) 518 */ 519 ENTRY(hv_set_ctx0) 520 mov MMU_TSB_CTX0, %o5 521 ta FAST_TRAP 522 retl 523 nop 524 SET_SIZE(hv_set_ctx0) 525 526 /* 527 * Set TSB for context non0 528 * arg0 ntsb_descriptor (%o0) 529 * arg1 desc_ra (%o1) 530 */ 531 ENTRY(hv_set_ctxnon0) 532 mov MMU_TSB_CTXNON0, %o5 533 ta FAST_TRAP 534 retl 535 nop 536 SET_SIZE(hv_set_ctxnon0) 537 538#ifdef SET_MMU_STATS 539 /* 540 * Returns old stat area on success 541 */ 542 ENTRY(hv_mmu_set_stat_area) 543 mov MMU_STAT_AREA, %o5 544 ta FAST_TRAP 545 retl 546 nop 547 SET_SIZE(hv_mmu_set_stat_area) 548#endif /* SET_MMU_STATS */ 549 550 /* 551 * CPU Q Configure 552 * arg0 queue (%o0) 553 * arg1 Base address RA (%o1) 554 * arg2 Size (%o2) 555 */ 556 ENTRY(hv_cpu_qconf) 557 mov HV_CPU_QCONF, %o5 558 ta FAST_TRAP 559 retl 560 nop 561 SET_SIZE(hv_cpu_qconf) 562 563 /* 564 * arg0 - devhandle 565 * arg1 - devino 566 * 567 * ret0 - status 568 * ret1 - sysino 569 */ 570 ENTRY(hvio_intr_devino_to_sysino) 571 mov HVIO_INTR_DEVINO2SYSINO, %o5 572 ta FAST_TRAP 573 brz,a %o0, 1f 574 stx %o1, [%o2] 5751: retl 576 nop 577 SET_SIZE(hvio_intr_devino_to_sysino) 578 579 /* 580 * arg0 - sysino 581 * 582 * ret0 - status 583 * ret1 - intr_valid_state 584 */ 585 ENTRY(hvio_intr_getvalid) 586 mov %o1, %o2 587 mov HVIO_INTR_GETVALID, %o5 588 ta FAST_TRAP 589 brz,a %o0, 1f 590 stuw %o1, [%o2] 5911: retl 592 nop 593 SET_SIZE(hvio_intr_getvalid) 594 595 /* 596 * arg0 - sysino 597 * arg1 - intr_valid_state 598 * 599 * ret0 - status 600 */ 601 ENTRY(hvio_intr_setvalid) 602 mov HVIO_INTR_SETVALID, %o5 603 ta FAST_TRAP 604 retl 605 nop 606 SET_SIZE(hvio_intr_setvalid) 607 608 /* 609 * arg0 - sysino 610 * 611 * ret0 - status 612 * ret1 - intr_state 613 */ 614 ENTRY(hvio_intr_getstate) 615 mov %o1, %o2 616 mov HVIO_INTR_GETSTATE, %o5 617 ta FAST_TRAP 618 brz,a %o0, 1f 619 stuw %o1, [%o2] 6201: retl 621 nop 622 SET_SIZE(hvio_intr_getstate) 623 624 /* 625 * arg0 - sysino 626 * arg1 - intr_state 627 * 628 * ret0 - status 629 */ 630 ENTRY(hvio_intr_setstate) 631 mov HVIO_INTR_SETSTATE, %o5 632 ta FAST_TRAP 633 retl 634 nop 635 SET_SIZE(hvio_intr_setstate) 636 637 /* 638 * arg0 - sysino 639 * 640 * ret0 - status 641 * ret1 - cpu_id 642 */ 643 ENTRY(hvio_intr_gettarget) 644 mov %o1, %o2 645 mov HVIO_INTR_GETTARGET, %o5 646 ta FAST_TRAP 647 brz,a %o0, 1f 648 stuw %o1, [%o2] 6491: retl 650 nop 651 SET_SIZE(hvio_intr_gettarget) 652 653 /* 654 * arg0 - sysino 655 * arg1 - cpu_id 656 * 657 * ret0 - status 658 */ 659 ENTRY(hvio_intr_settarget) 660 mov HVIO_INTR_SETTARGET, %o5 661 ta FAST_TRAP 662 retl 663 nop 664 SET_SIZE(hvio_intr_settarget) 665 666 /* 667 * hv_cpu_yield(void) 668 */ 669 ENTRY(hv_cpu_yield) 670 mov HV_CPU_YIELD, %o5 671 ta FAST_TRAP 672 retl 673 nop 674 SET_SIZE(hv_cpu_yield) 675 676 /* 677 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 678 */ 679 ENTRY(hv_cpu_state) 680 mov %o1, %o4 ! save datap 681 mov HV_CPU_STATE, %o5 682 ta FAST_TRAP 683 brz,a %o0, 1f 684 stx %o1, [%o4] 6851: 686 retl 687 nop 688 SET_SIZE(hv_cpu_state) 689 690 /* 691 * HV state dump zone Configure 692 * arg0 real adrs of dump buffer (%o0) 693 * arg1 size of dump buffer (%o1) 694 * ret0 status (%o0) 695 * ret1 size of buffer on success and min size on EINVAL (%o1) 696 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 697 */ 698 ENTRY(hv_dump_buf_update) 699 mov DUMP_BUF_UPDATE, %o5 700 ta FAST_TRAP 701 retl 702 stx %o1, [%o2] 703 SET_SIZE(hv_dump_buf_update) 704 705 /* 706 * arg0 - timeout value (%o0) 707 * 708 * ret0 - status (%o0) 709 * ret1 - time_remaining (%o1) 710 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 711 */ 712 ENTRY(hv_mach_set_watchdog) 713 mov %o1, %o2 714 mov MACH_SET_WATCHDOG, %o5 715 ta FAST_TRAP 716 retl 717 stx %o1, [%o2] 718 SET_SIZE(hv_mach_set_watchdog) 719 720 /* 721 * For memory scrub 722 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 723 * uint64_t *scrubbed_len); 724 * Retun %o0 -- status 725 * %o1 -- bytes scrubbed 726 */ 727 ENTRY(hv_mem_scrub) 728 mov %o2, %o4 729 mov HV_MEM_SCRUB, %o5 730 ta FAST_TRAP 731 retl 732 stx %o1, [%o4] 733 SET_SIZE(hv_mem_scrub) 734 735 /* 736 * Flush ecache 737 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 738 * uint64_t *flushed_len); 739 * Retun %o0 -- status 740 * %o1 -- bytes flushed 741 */ 742 ENTRY(hv_mem_sync) 743 mov %o2, %o4 744 mov HV_MEM_SYNC, %o5 745 ta FAST_TRAP 746 retl 747 stx %o1, [%o4] 748 SET_SIZE(hv_mem_sync) 749 750 /* 751 * uint64_t hv_tm_enable(uint64_t enable) 752 */ 753 ENTRY(hv_tm_enable) 754 mov HV_TM_ENABLE, %o5 755 ta FAST_TRAP 756 retl 757 nop 758 SET_SIZE(hv_tm_enable) 759 760 /* 761 * TTRACE_BUF_CONF Configure 762 * arg0 RA base of buffer (%o0) 763 * arg1 buf size in no. of entries (%o1) 764 * ret0 status (%o0) 765 * ret1 minimum size in no. of entries on failure, 766 * actual size in no. of entries on success (%o1) 767 */ 768 ENTRY(hv_ttrace_buf_conf) 769 mov TTRACE_BUF_CONF, %o5 770 ta FAST_TRAP 771 retl 772 stx %o1, [%o2] 773 SET_SIZE(hv_ttrace_buf_conf) 774 775 /* 776 * TTRACE_BUF_INFO 777 * ret0 status (%o0) 778 * ret1 RA base of buffer (%o1) 779 * ret2 size in no. of entries (%o2) 780 */ 781 ENTRY(hv_ttrace_buf_info) 782 mov %o0, %o3 783 mov %o1, %o4 784 mov TTRACE_BUF_INFO, %o5 785 ta FAST_TRAP 786 stx %o1, [%o3] 787 retl 788 stx %o2, [%o4] 789 SET_SIZE(hv_ttrace_buf_info) 790 791 /* 792 * TTRACE_ENABLE 793 * arg0 enable/ disable (%o0) 794 * ret0 status (%o0) 795 * ret1 previous enable state (%o1) 796 */ 797 ENTRY(hv_ttrace_enable) 798 mov %o1, %o2 799 mov TTRACE_ENABLE, %o5 800 ta FAST_TRAP 801 retl 802 stx %o1, [%o2] 803 SET_SIZE(hv_ttrace_enable) 804 805 /* 806 * TTRACE_FREEZE 807 * arg0 enable/ freeze (%o0) 808 * ret0 status (%o0) 809 * ret1 previous freeze state (%o1) 810 */ 811 ENTRY(hv_ttrace_freeze) 812 mov %o1, %o2 813 mov TTRACE_FREEZE, %o5 814 ta FAST_TRAP 815 retl 816 stx %o1, [%o2] 817 SET_SIZE(hv_ttrace_freeze) 818 819 /* 820 * MACH_DESC 821 * arg0 buffer real address 822 * arg1 pointer to uint64_t for size of buffer 823 * ret0 status 824 * ret1 return required size of buffer / returned data size 825 */ 826 ENTRY(hv_mach_desc) 827 mov %o1, %o4 ! save datap 828 ldx [%o1], %o1 829 mov HV_MACH_DESC, %o5 830 ta FAST_TRAP 831 retl 832 stx %o1, [%o4] 833 SET_SIZE(hv_mach_desc) 834 835 /* 836 * hv_ra2pa(uint64_t ra) 837 * 838 * MACH_DESC 839 * arg0 Real address to convert 840 * ret0 Returned physical address or -1 on error 841 */ 842 ENTRY(hv_ra2pa) 843 mov HV_RA2PA, %o5 844 ta FAST_TRAP 845 cmp %o0, 0 846 move %xcc, %o1, %o0 847 movne %xcc, -1, %o0 848 retl 849 nop 850 SET_SIZE(hv_ra2pa) 851 852 /* 853 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 854 * 855 * MACH_DESC 856 * arg0 OS function to call 857 * arg1 First arg to OS function 858 * arg2 Second arg to OS function 859 * arg3 Third arg to OS function 860 * ret0 Returned value from function 861 */ 862 863 ENTRY(hv_hpriv) 864 mov HV_HPRIV, %o5 865 ta FAST_TRAP 866 retl 867 nop 868 SET_SIZE(hv_hpriv) 869 870 /* 871 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 872 * uint64_t nentries); 873 */ 874 ENTRY(hv_ldc_tx_qconf) 875 mov LDC_TX_QCONF, %o5 876 ta FAST_TRAP 877 retl 878 nop 879 SET_SIZE(hv_ldc_tx_qconf) 880 881 882 /* 883 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 884 * uint64_t *nentries); 885 */ 886 ENTRY(hv_ldc_tx_qinfo) 887 mov %o1, %g1 888 mov %o2, %g2 889 mov LDC_TX_QINFO, %o5 890 ta FAST_TRAP 891 stx %o1, [%g1] 892 retl 893 stx %o2, [%g2] 894 SET_SIZE(hv_ldc_tx_qinfo) 895 896 897 /* 898 * hv_ldc_tx_get_state(uint64_t channel, 899 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 900 */ 901 ENTRY(hv_ldc_tx_get_state) 902 mov LDC_TX_GET_STATE, %o5 903 mov %o1, %g1 904 mov %o2, %g2 905 mov %o3, %g3 906 ta FAST_TRAP 907 stx %o1, [%g1] 908 stx %o2, [%g2] 909 retl 910 stx %o3, [%g3] 911 SET_SIZE(hv_ldc_tx_get_state) 912 913 914 /* 915 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 916 */ 917 ENTRY(hv_ldc_tx_set_qtail) 918 mov LDC_TX_SET_QTAIL, %o5 919 ta FAST_TRAP 920 retl 921 SET_SIZE(hv_ldc_tx_set_qtail) 922 923 924 /* 925 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 926 * uint64_t nentries); 927 */ 928 ENTRY(hv_ldc_rx_qconf) 929 mov LDC_RX_QCONF, %o5 930 ta FAST_TRAP 931 retl 932 nop 933 SET_SIZE(hv_ldc_rx_qconf) 934 935 936 /* 937 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 938 * uint64_t *nentries); 939 */ 940 ENTRY(hv_ldc_rx_qinfo) 941 mov %o1, %g1 942 mov %o2, %g2 943 mov LDC_RX_QINFO, %o5 944 ta FAST_TRAP 945 stx %o1, [%g1] 946 retl 947 stx %o2, [%g2] 948 SET_SIZE(hv_ldc_rx_qinfo) 949 950 951 /* 952 * hv_ldc_rx_get_state(uint64_t channel, 953 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 954 */ 955 ENTRY(hv_ldc_rx_get_state) 956 mov LDC_RX_GET_STATE, %o5 957 mov %o1, %g1 958 mov %o2, %g2 959 mov %o3, %g3 960 ta FAST_TRAP 961 stx %o1, [%g1] 962 stx %o2, [%g2] 963 retl 964 stx %o3, [%g3] 965 SET_SIZE(hv_ldc_rx_get_state) 966 967 968 /* 969 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 970 */ 971 ENTRY(hv_ldc_rx_set_qhead) 972 mov LDC_RX_SET_QHEAD, %o5 973 ta FAST_TRAP 974 retl 975 SET_SIZE(hv_ldc_rx_set_qhead) 976 977 /* 978 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 979 * uint64_t tbl_entries) 980 */ 981 ENTRY(hv_ldc_set_map_table) 982 mov LDC_SET_MAP_TABLE, %o5 983 ta FAST_TRAP 984 retl 985 nop 986 SET_SIZE(hv_ldc_set_map_table) 987 988 989 /* 990 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 991 * uint64_t *tbl_entries) 992 */ 993 ENTRY(hv_ldc_get_map_table) 994 mov %o1, %g1 995 mov %o2, %g2 996 mov LDC_GET_MAP_TABLE, %o5 997 ta FAST_TRAP 998 stx %o1, [%g1] 999 retl 1000 stx %o2, [%g2] 1001 SET_SIZE(hv_ldc_get_map_table) 1002 1003 1004 /* 1005 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 1006 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 1007 */ 1008 ENTRY(hv_ldc_copy) 1009 mov %o5, %g1 1010 mov LDC_COPY, %o5 1011 ta FAST_TRAP 1012 retl 1013 stx %o1, [%g1] 1014 SET_SIZE(hv_ldc_copy) 1015 1016 1017 /* 1018 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 1019 * uint64_t *perm) 1020 */ 1021 ENTRY(hv_ldc_mapin) 1022 mov %o2, %g1 1023 mov %o3, %g2 1024 mov LDC_MAPIN, %o5 1025 ta FAST_TRAP 1026 stx %o1, [%g1] 1027 retl 1028 stx %o2, [%g2] 1029 SET_SIZE(hv_ldc_mapin) 1030 1031 1032 /* 1033 * hv_ldc_unmap(uint64_t raddr) 1034 */ 1035 ENTRY(hv_ldc_unmap) 1036 mov LDC_UNMAP, %o5 1037 ta FAST_TRAP 1038 retl 1039 nop 1040 SET_SIZE(hv_ldc_unmap) 1041 1042 1043 /* 1044 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1045 * uint64_t revoke_cookie 1046 */ 1047 ENTRY(hv_ldc_revoke) 1048 mov LDC_REVOKE, %o5 1049 ta FAST_TRAP 1050 retl 1051 nop 1052 SET_SIZE(hv_ldc_revoke) 1053 1054 /* 1055 * hv_ldc_mapin_size_max(uint64_t tbl_type, uint64_t *sz) 1056 */ 1057 ENTRY(hv_ldc_mapin_size_max) 1058 mov %o1, %g1 1059 mov LDC_MAPIN_SIZE_MAX, %o5 1060 ta FAST_TRAP 1061 retl 1062 stx %o1, [%g1] 1063 SET_SIZE(hv_ldc_mapin_size_max) 1064 1065 /* 1066 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1067 * uint64_t *cookie); 1068 */ 1069 ENTRY(hvldc_intr_getcookie) 1070 mov %o2, %g1 1071 mov VINTR_GET_COOKIE, %o5 1072 ta FAST_TRAP 1073 retl 1074 stx %o1, [%g1] 1075 SET_SIZE(hvldc_intr_getcookie) 1076 1077 /* 1078 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1079 * uint64_t cookie); 1080 */ 1081 ENTRY(hvldc_intr_setcookie) 1082 mov VINTR_SET_COOKIE, %o5 1083 ta FAST_TRAP 1084 retl 1085 nop 1086 SET_SIZE(hvldc_intr_setcookie) 1087 1088 1089 /* 1090 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1091 * int *intr_valid_state); 1092 */ 1093 ENTRY(hvldc_intr_getvalid) 1094 mov %o2, %g1 1095 mov VINTR_GET_VALID, %o5 1096 ta FAST_TRAP 1097 retl 1098 stuw %o1, [%g1] 1099 SET_SIZE(hvldc_intr_getvalid) 1100 1101 /* 1102 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1103 * int intr_valid_state); 1104 */ 1105 ENTRY(hvldc_intr_setvalid) 1106 mov VINTR_SET_VALID, %o5 1107 ta FAST_TRAP 1108 retl 1109 nop 1110 SET_SIZE(hvldc_intr_setvalid) 1111 1112 /* 1113 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1114 * int *intr_state); 1115 */ 1116 ENTRY(hvldc_intr_getstate) 1117 mov %o2, %g1 1118 mov VINTR_GET_STATE, %o5 1119 ta FAST_TRAP 1120 retl 1121 stuw %o1, [%g1] 1122 SET_SIZE(hvldc_intr_getstate) 1123 1124 /* 1125 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1126 * int intr_state); 1127 */ 1128 ENTRY(hvldc_intr_setstate) 1129 mov VINTR_SET_STATE, %o5 1130 ta FAST_TRAP 1131 retl 1132 nop 1133 SET_SIZE(hvldc_intr_setstate) 1134 1135 /* 1136 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1137 * uint32_t *cpuid); 1138 */ 1139 ENTRY(hvldc_intr_gettarget) 1140 mov %o2, %g1 1141 mov VINTR_GET_TARGET, %o5 1142 ta FAST_TRAP 1143 retl 1144 stuw %o1, [%g1] 1145 SET_SIZE(hvldc_intr_gettarget) 1146 1147 /* 1148 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1149 * uint32_t cpuid); 1150 */ 1151 ENTRY(hvldc_intr_settarget) 1152 mov VINTR_SET_TARGET, %o5 1153 ta FAST_TRAP 1154 retl 1155 nop 1156 SET_SIZE(hvldc_intr_settarget) 1157 1158 /* 1159 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1160 * uint64_t *minorp) 1161 * 1162 * API_GET_VERSION 1163 * arg0 API group 1164 * ret0 status 1165 * ret1 major number 1166 * ret2 minor number 1167 */ 1168 ENTRY(hv_api_get_version) 1169 mov %o1, %o3 1170 mov %o2, %o4 1171 mov API_GET_VERSION, %o5 1172 ta CORE_TRAP 1173 stx %o1, [%o3] 1174 retl 1175 stx %o2, [%o4] 1176 SET_SIZE(hv_api_get_version) 1177 1178 /* 1179 * hv_api_set_version(uint64_t api_group, uint64_t major, 1180 * uint64_t minor, uint64_t *supported_minor) 1181 * 1182 * API_SET_VERSION 1183 * arg0 API group 1184 * arg1 major number 1185 * arg2 requested minor number 1186 * ret0 status 1187 * ret1 actual minor number 1188 */ 1189 ENTRY(hv_api_set_version) 1190 mov %o3, %o4 1191 mov API_SET_VERSION, %o5 1192 ta CORE_TRAP 1193 retl 1194 stx %o1, [%o4] 1195 SET_SIZE(hv_api_set_version) 1196 1197 /* 1198 * %o0 - buffer real address 1199 * %o1 - buffer size 1200 * %o2 - &characters written 1201 * returns 1202 * status 1203 */ 1204 ENTRY(hv_cnwrite) 1205 mov CONS_WRITE, %o5 1206 ta FAST_TRAP 1207 retl 1208 stx %o1, [%o2] 1209 SET_SIZE(hv_cnwrite) 1210 1211 /* 1212 * %o0 character buffer ra 1213 * %o1 buffer size 1214 * %o2 pointer to returned size 1215 * return values: 1216 * 0 success 1217 * hv_errno failure 1218 */ 1219 ENTRY(hv_cnread) 1220 mov CONS_READ, %o5 1221 ta FAST_TRAP 1222 brnz,a %o0, 1f ! failure, just return error 1223 nop 1224 1225 cmp %o1, H_BREAK 1226 be 1f 1227 mov %o1, %o0 1228 1229 cmp %o1, H_HUP 1230 be 1f 1231 mov %o1, %o0 1232 1233 stx %o1, [%o2] ! success, save count and return 0 1234 mov 0, %o0 12351: 1236 retl 1237 nop 1238 SET_SIZE(hv_cnread) 1239 1240 /* 1241 * SOFT_STATE_SET 1242 * arg0 state (%o0) 1243 * arg1 string (%o1) 1244 * ret0 status (%o0) 1245 */ 1246 ENTRY(hv_soft_state_set) 1247 mov SOFT_STATE_SET, %o5 1248 ta FAST_TRAP 1249 retl 1250 nop 1251 SET_SIZE(hv_soft_state_set) 1252 1253 /* 1254 * SOFT_STATE_GET 1255 * arg0 string buffer (%o0) 1256 * ret0 status (%o0) 1257 * ret1 current state (%o1) 1258 */ 1259 ENTRY(hv_soft_state_get) 1260 mov %o1, %o2 1261 mov SOFT_STATE_GET, %o5 1262 ta FAST_TRAP 1263 retl 1264 stx %o1, [%o2] 1265 SET_SIZE(hv_soft_state_get) 1266 1267 ENTRY(hv_guest_suspend) 1268 mov GUEST_SUSPEND, %o5 1269 ta FAST_TRAP 1270 retl 1271 nop 1272 SET_SIZE(hv_guest_suspend) 1273 1274 ENTRY(hv_tick_set_npt) 1275 mov TICK_SET_NPT, %o5 1276 ta FAST_TRAP 1277 retl 1278 nop 1279 SET_SIZE(hv_tick_set_npt) 1280 1281 ENTRY(hv_stick_set_npt) 1282 mov STICK_SET_NPT, %o5 1283 ta FAST_TRAP 1284 retl 1285 nop 1286 SET_SIZE(hv_stick_set_npt) 1287 1288 /* 1289 * REBOOT_DATA_SET 1290 * arg0 buffer real address 1291 * arg1 buffer length 1292 * ret0 status 1293 */ 1294 ENTRY(hv_reboot_data_set) 1295 mov HV_REBOOT_DATA_SET, %o5 1296 ta FAST_TRAP 1297 retl 1298 nop 1299 SET_SIZE(hv_reboot_data_set) 1300 1301#endif /* lint || __lint */ 1302