1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28/* 29 * Hypervisor calls called by px nexus driver. 30*/ 31 32#include <sys/asm_linkage.h> 33#include <sys/hypervisor_api.h> 34#include <px_ioapi.h> 35 36#if defined(lint) || defined(__lint) 37 38/*ARGSUSED*/ 39uint64_t 40hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 41 pci_config_size_t size, pci_cfg_data_t *data_p) 42{ return (0); } 43 44/*ARGSUSED*/ 45uint64_t 46hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 47 pci_config_size_t size, pci_cfg_data_t data) 48{ return (0); } 49 50/*ARGSUSED*/ 51uint64_t 52hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 53 io_attributes_t attr, io_page_list_t *io_page_list_p, 54 pages_t *pages_mapped) 55{ return (0); } 56 57/*ARGSUSED*/ 58uint64_t 59hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 60 pages_t *pages_demapped) 61{ return (0); } 62 63/*ARGSUSED*/ 64uint64_t 65hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p, 66 r_addr_t *r_addr_p) 67{ return (0); } 68 69/*ARGSUSED*/ 70uint64_t 71hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, 72 io_addr_t *io_addr_p) 73{ return (0); } 74 75/*ARGSUSED*/ 76uint64_t 77hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 78 uint64_t *data_p) 79{ return (0); } 80 81/*ARGSUSED*/ 82uint64_t 83hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 84 r_addr_t ra2, uint32_t *rdbk_status) 85{ return (0); } 86 87/*ARGSUSED*/ 88uint64_t 89hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 90 int io_sync_direction, size_t *bytes_synched) 91{ return (0); } 92 93/*ARGSUSED*/ 94uint64_t 95hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 96 uint_t msiq_rec_cnt) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 102 uint_t *msiq_rec_cnt_p) 103{ return (0); } 104 105/*ARGSUSED*/ 106uint64_t 107hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 108 pci_msiq_valid_state_t *msiq_valid_state) 109{ return (0); } 110 111/*ARGSUSED*/ 112uint64_t 113hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 114 pci_msiq_valid_state_t msiq_valid_state) 115{ return (0); } 116 117/*ARGSUSED*/ 118uint64_t 119hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 120 pci_msiq_state_t *msiq_state) 121{ return (0); } 122 123/*ARGSUSED*/ 124uint64_t 125hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 126 pci_msiq_state_t msiq_state) 127{ return (0); } 128 129/*ARGSUSED*/ 130uint64_t 131hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 132 msiqhead_t *msiq_head) 133{ return (0); } 134 135/*ARGSUSED*/ 136uint64_t 137hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 138 msiqhead_t msiq_head) 139{ return (0); } 140 141/*ARGSUSED*/ 142uint64_t 143hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 144 msiqtail_t *msiq_tail) 145{ return (0); } 146 147/*ARGSUSED*/ 148uint64_t 149hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 150 msiqid_t *msiq_id) 151{ return (0); } 152 153/*ARGSUSED*/ 154uint64_t 155hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 156 msiqid_t msiq_id, msi_type_t msitype) 157{ return (0); } 158 159/*ARGSUSED*/ 160uint64_t 161hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 162 pci_msi_valid_state_t *msi_valid_state) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 168 pci_msi_valid_state_t msi_valid_state) 169{ return (0); } 170 171/*ARGSUSED*/ 172uint64_t 173hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 174 pci_msi_state_t *msi_state) 175{ return (0); } 176 177/*ARGSUSED*/ 178uint64_t 179hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 180 pci_msi_state_t msi_state) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 186 msiqid_t *msiq_id) 187{ return (0); } 188 189/*ARGSUSED*/ 190uint64_t 191hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 192 msiqid_t msiq_id) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 198 pcie_msg_valid_state_t *msg_valid_state) 199{ return (0); } 200 201/*ARGSUSED*/ 202uint64_t 203hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 204 pcie_msg_valid_state_t msg_valid_state) 205{ return (0); } 206 207/* 208 * First arg to both of these functions is a dummy, to accomodate how 209 * hv_hpriv() works. 210 */ 211/*ARGSUSED*/ 212int 213px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) 214{ return (0); } 215 216#else /* lint || __lint */ 217 218 /* 219 * arg0 - devhandle 220 * arg1 - pci_device 221 * arg2 - pci_config_offset 222 * arg3 - pci_config_size 223 * 224 * ret0 - status 225 * ret1 - error_flag 226 * ret2 - pci_cfg_data 227 */ 228 ENTRY(hvio_config_get) 229 mov HVIO_CONFIG_GET, %o5 230 ta FAST_TRAP 231 brnz %o0, 1f 232 movrnz %o1, -1, %o2 233 brz,a %o1, 1f 234 stuw %o2, [%o4] 2351: retl 236 nop 237 SET_SIZE(hvio_config_get) 238 239 /* 240 * arg0 - devhandle 241 * arg1 - pci_device 242 * arg2 - pci_config_offset 243 * arg3 - pci_config_size 244 * arg4 - pci_cfg_data 245 * 246 * ret0 - status 247 * ret1 - error_flag 248 */ 249 ENTRY(hvio_config_put) 250 mov HVIO_CONFIG_PUT, %o5 251 ta FAST_TRAP 252 retl 253 nop 254 SET_SIZE(hvio_config_put) 255 256 /* 257 * arg0 - devhandle 258 * arg1 - tsbid 259 * arg2 - pages 260 * arg3 - io_attributes 261 * arg4 - io_page_list_p 262 * 263 * ret1 - pages_mapped 264 */ 265 ENTRY(hvio_iommu_map) 266 save %sp, -SA(MINFRAME64), %sp 267 mov %i0, %o0 268 mov %i1, %o1 269 mov %i2, %o2 270 mov %i3, %o3 271 mov %i4, %o4 272 mov HVIO_IOMMU_MAP, %o5 273 ta FAST_TRAP 274 brnz %o0, 1f 275 mov %o0, %i0 276 stuw %o1, [%i5] 2771: 278 ret 279 restore 280 SET_SIZE(hvio_iommu_map) 281 282 /* 283 * arg0 - devhandle 284 * arg1 - tsbid 285 * arg2 - pages 286 * 287 * ret1 - pages_demapped 288 */ 289 ENTRY(hvio_iommu_demap) 290 mov HVIO_IOMMU_DEMAP, %o5 291 ta FAST_TRAP 292 brz,a %o0, 1f 293 stuw %o1, [%o3] 2941: retl 295 nop 296 SET_SIZE(hvio_iommu_demap) 297 298 /* 299 * arg0 - devhandle 300 * arg1 - tsbid 301 * 302 * 303 * ret0 - status 304 * ret1 - io_attributes 305 * ret2 - r_addr 306 */ 307 ENTRY(hvio_iommu_getmap) 308 mov %o2, %o4 309 mov HVIO_IOMMU_GETMAP, %o5 310 ta FAST_TRAP 311 brnz %o0, 1f 312 nop 313 stx %o2, [%o3] 314 st %o1, [%o4] 3151: 316 retl 317 nop 318 SET_SIZE(hvio_iommu_getmap) 319 320 /* 321 * arg0 - devhandle 322 * arg1 - r_addr 323 * arg2 - io_attributes 324 * 325 * 326 * ret0 - status 327 * ret1 - io_addr 328 */ 329 ENTRY(hvio_iommu_getbypass) 330 mov HVIO_IOMMU_GETBYPASS, %o5 331 ta FAST_TRAP 332 brz,a %o0, 1f 333 stx %o1, [%o3] 3341: retl 335 nop 336 SET_SIZE(hvio_iommu_getbypass) 337 338 /* 339 * arg0 - devhandle 340 * arg1 - r_addr 341 * arg2 - size 342 * 343 * ret1 - error_flag 344 * ret2 - data 345 */ 346 ENTRY(hvio_peek) 347 mov HVIO_PEEK, %o5 348 ta FAST_TRAP 349 brnz %o0, 1f 350 nop 351 stx %o2, [%o4] 352 st %o1, [%o3] 3531: 354 retl 355 nop 356 SET_SIZE(hvio_peek) 357 358 /* 359 * arg0 - devhandle 360 * arg1 - r_addr 361 * arg2 - sizes 362 * arg3 - data 363 * arg4 - r_addr2 364 * 365 * ret1 - error_flag 366 */ 367 ENTRY(hvio_poke) 368 save %sp, -SA(MINFRAME64), %sp 369 mov %i0, %o0 370 mov %i1, %o1 371 mov %i2, %o2 372 mov %i3, %o3 373 mov %i4, %o4 374 mov HVIO_POKE, %o5 375 ta FAST_TRAP 376 brnz %o0, 1f 377 mov %o0, %i0 378 stuw %o1, [%i5] 3791: 380 ret 381 restore 382 SET_SIZE(hvio_poke) 383 384 /* 385 * arg0 - devhandle 386 * arg1 - r_addr 387 * arg2 - num_bytes 388 * arg3 - io_sync_direction 389 * 390 * ret0 - status 391 * ret1 - bytes_synched 392 */ 393 ENTRY(hvio_dma_sync) 394 mov HVIO_DMA_SYNC, %o5 395 ta FAST_TRAP 396 brz,a %o0, 1f 397 stx %o1, [%o4] 3981: retl 399 nop 400 SET_SIZE(hvio_dma_sync) 401 402 /* 403 * arg0 - devhandle 404 * arg1 - msiq_id 405 * arg2 - r_addr 406 * arg3 - nentries 407 * 408 * ret0 - status 409 */ 410 ENTRY(hvio_msiq_conf) 411 mov HVIO_MSIQ_CONF, %o5 412 ta FAST_TRAP 413 retl 414 nop 415 SET_SIZE(hvio_msiq_conf) 416 417 /* 418 * arg0 - devhandle 419 * arg1 - msiq_id 420 * 421 * ret0 - status 422 * ret1 - r_addr 423 * ret1 - nentries 424 */ 425 ENTRY(hvio_msiq_info) 426 mov %o2, %o4 427 mov HVIO_MSIQ_INFO, %o5 428 ta FAST_TRAP 429 brnz 1f 430 nop 431 stx %o1, [%o4] 432 stuw %o2, [%o3] 4331: retl 434 nop 435 SET_SIZE(hvio_msiq_info) 436 437 /* 438 * arg0 - devhandle 439 * arg1 - msiq_id 440 * 441 * ret0 - status 442 * ret1 - msiq_valid_state 443 */ 444 ENTRY(hvio_msiq_getvalid) 445 mov HVIO_MSIQ_GETVALID, %o5 446 ta FAST_TRAP 447 brz,a %o0, 1f 448 stuw %o1, [%o2] 4491: retl 450 nop 451 SET_SIZE(hvio_msiq_getvalid) 452 453 /* 454 * arg0 - devhandle 455 * arg1 - msiq_id 456 * arg2 - msiq_valid_state 457 * 458 * ret0 - status 459 */ 460 ENTRY(hvio_msiq_setvalid) 461 mov HVIO_MSIQ_SETVALID, %o5 462 ta FAST_TRAP 463 retl 464 nop 465 SET_SIZE(hvio_msiq_setvalid) 466 467 /* 468 * arg0 - devhandle 469 * arg1 - msiq_id 470 * 471 * ret0 - status 472 * ret1 - msiq_state 473 */ 474 ENTRY(hvio_msiq_getstate) 475 mov HVIO_MSIQ_GETSTATE, %o5 476 ta FAST_TRAP 477 brz,a %o0, 1f 478 stuw %o1, [%o2] 4791: retl 480 nop 481 SET_SIZE(hvio_msiq_getstate) 482 483 /* 484 * arg0 - devhandle 485 * arg1 - msiq_id 486 * arg2 - msiq_state 487 * 488 * ret0 - status 489 */ 490 ENTRY(hvio_msiq_setstate) 491 mov HVIO_MSIQ_SETSTATE, %o5 492 ta FAST_TRAP 493 retl 494 nop 495 SET_SIZE(hvio_msiq_setstate) 496 497 /* 498 * arg0 - devhandle 499 * arg1 - msiq_id 500 * 501 * ret0 - status 502 * ret1 - msiq_head 503 */ 504 ENTRY(hvio_msiq_gethead) 505 mov HVIO_MSIQ_GETHEAD, %o5 506 ta FAST_TRAP 507 brz,a %o0, 1f 508 stx %o1, [%o2] 5091: retl 510 nop 511 SET_SIZE(hvio_msiq_gethead) 512 513 /* 514 * arg0 - devhandle 515 * arg1 - msiq_id 516 * arg2 - msiq_head 517 * 518 * ret0 - status 519 */ 520 ENTRY(hvio_msiq_sethead) 521 mov HVIO_MSIQ_SETHEAD, %o5 522 ta FAST_TRAP 523 retl 524 nop 525 SET_SIZE(hvio_msiq_sethead) 526 527 /* 528 * arg0 - devhandle 529 * arg1 - msiq_id 530 * 531 * ret0 - status 532 * ret1 - msiq_tail 533 */ 534 ENTRY(hvio_msiq_gettail) 535 mov HVIO_MSIQ_GETTAIL, %o5 536 ta FAST_TRAP 537 brz,a %o0, 1f 538 stx %o1, [%o2] 5391: retl 540 nop 541 SET_SIZE(hvio_msiq_gettail) 542 543 /* 544 * arg0 - devhandle 545 * arg1 - msi_num 546 * 547 * ret0 - status 548 * ret1 - msiq_id 549 */ 550 ENTRY(hvio_msi_getmsiq) 551 mov HVIO_MSI_GETMSIQ, %o5 552 ta FAST_TRAP 553 brz,a %o0, 1f 554 stuw %o1, [%o2] 5551: retl 556 nop 557 SET_SIZE(hvio_msi_getmsiq) 558 559 /* 560 * arg0 - devhandle 561 * arg1 - msi_num 562 * arg2 - msiq_id 563 * arg2 - msitype 564 * 565 * ret0 - status 566 */ 567 ENTRY(hvio_msi_setmsiq) 568 mov HVIO_MSI_SETMSIQ, %o5 569 ta FAST_TRAP 570 retl 571 nop 572 SET_SIZE(hvio_msi_setmsiq) 573 574 /* 575 * arg0 - devhandle 576 * arg1 - msi_num 577 * 578 * ret0 - status 579 * ret1 - msi_valid_state 580 */ 581 ENTRY(hvio_msi_getvalid) 582 mov HVIO_MSI_GETVALID, %o5 583 ta FAST_TRAP 584 brz,a %o0, 1f 585 stuw %o1, [%o2] 5861: retl 587 nop 588 SET_SIZE(hvio_msi_getvalid) 589 590 /* 591 * arg0 - devhandle 592 * arg1 - msi_num 593 * arg2 - msi_valid_state 594 * 595 * ret0 - status 596 */ 597 ENTRY(hvio_msi_setvalid) 598 mov HVIO_MSI_SETVALID, %o5 599 ta FAST_TRAP 600 retl 601 nop 602 SET_SIZE(hvio_msi_setvalid) 603 604 /* 605 * arg0 - devhandle 606 * arg1 - msi_num 607 * 608 * ret0 - status 609 * ret1 - msi_state 610 */ 611 ENTRY(hvio_msi_getstate) 612 mov HVIO_MSI_GETSTATE, %o5 613 ta FAST_TRAP 614 brz,a %o0, 1f 615 stuw %o1, [%o2] 6161: retl 617 nop 618 SET_SIZE(hvio_msi_getstate) 619 620 /* 621 * arg0 - devhandle 622 * arg1 - msi_num 623 * arg2 - msi_state 624 * 625 * ret0 - status 626 */ 627 ENTRY(hvio_msi_setstate) 628 mov HVIO_MSI_SETSTATE, %o5 629 ta FAST_TRAP 630 retl 631 nop 632 SET_SIZE(hvio_msi_setstate) 633 634 /* 635 * arg0 - devhandle 636 * arg1 - msg_type 637 * 638 * ret0 - status 639 * ret1 - msiq_id 640 */ 641 ENTRY(hvio_msg_getmsiq) 642 mov HVIO_MSG_GETMSIQ, %o5 643 ta FAST_TRAP 644 brz,a %o0, 1f 645 stuw %o1, [%o2] 6461: retl 647 nop 648 SET_SIZE(hvio_msg_getmsiq) 649 650 /* 651 * arg0 - devhandle 652 * arg1 - msg_type 653 * arg2 - msiq_id 654 * 655 * ret0 - status 656 */ 657 ENTRY(hvio_msg_setmsiq) 658 mov HVIO_MSG_SETMSIQ, %o5 659 ta FAST_TRAP 660 retl 661 nop 662 SET_SIZE(hvio_msg_setmsiq) 663 664 /* 665 * arg0 - devhandle 666 * arg1 - msg_type 667 * 668 * ret0 - status 669 * ret1 - msg_valid_state 670 */ 671 ENTRY(hvio_msg_getvalid) 672 mov HVIO_MSG_GETVALID, %o5 673 ta FAST_TRAP 674 brz,a %o0, 1f 675 stuw %o1, [%o2] 6761: retl 677 nop 678 SET_SIZE(hvio_msg_getvalid) 679 680 /* 681 * arg0 - devhandle 682 * arg1 - msg_type 683 * arg2 - msg_valid_state 684 * 685 * ret0 - status 686 */ 687 ENTRY(hvio_msg_setvalid) 688 mov HVIO_MSG_SETVALID, %o5 689 ta FAST_TRAP 690 retl 691 nop 692 SET_SIZE(hvio_msg_setvalid) 693 694#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 695 696! px_phys_acc_4v: Do physical address read. 697! 698! After SHIFT_REGS: 699! %o0 is "from" address 700! %o1 is "to" address 701! 702! Assumes 8 byte data and that alignment is correct. 703! 704! Always returns success (0) in %o0 705 706 ! px_phys_acc_4v must not be split across pages. 707 ! 708 ! ATTN: Be sure that the alignment value is larger than the size of 709 ! the px_phys_acc_4v function. 710 ! 711 .align 0x40 712 713 ENTRY(px_phys_acc_4v) 714 715 SHIFT_REGS 716 ldx [%o0], %g1 717 stx %g1, [%o1] 718 membar #Sync ! Make sure the loads take 719 mov %g0, %o0 720 done 721 SET_SIZE(px_phys_acc_4v) 722 723#endif /* lint || __lint */ 724