1*ea1a228cSschwartz /* 2*ea1a228cSschwartz * CDDL HEADER START 3*ea1a228cSschwartz * 4*ea1a228cSschwartz * The contents of this file are subject to the terms of the 5*ea1a228cSschwartz * Common Development and Distribution License (the "License"). 6*ea1a228cSschwartz * You may not use this file except in compliance with the License. 7*ea1a228cSschwartz * 8*ea1a228cSschwartz * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*ea1a228cSschwartz * or http://www.opensolaris.org/os/licensing. 10*ea1a228cSschwartz * See the License for the specific language governing permissions 11*ea1a228cSschwartz * and limitations under the License. 12*ea1a228cSschwartz * 13*ea1a228cSschwartz * When distributing Covered Code, include this CDDL HEADER in each 14*ea1a228cSschwartz * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*ea1a228cSschwartz * If applicable, add the following below this CDDL HEADER, with the 16*ea1a228cSschwartz * fields enclosed by brackets "[]" replaced with your own identifying 17*ea1a228cSschwartz * information: Portions Copyright [yyyy] [name of copyright owner] 18*ea1a228cSschwartz * 19*ea1a228cSschwartz * CDDL HEADER END 20*ea1a228cSschwartz */ 21*ea1a228cSschwartz 22*ea1a228cSschwartz /* 23*ea1a228cSschwartz * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24*ea1a228cSschwartz * Use is subject to license terms. 25*ea1a228cSschwartz */ 26*ea1a228cSschwartz 27*ea1a228cSschwartz #ifndef _N2PIUPC_BITERR_H 28*ea1a228cSschwartz #define _N2PIUPC_BITERR_H 29*ea1a228cSschwartz 30*ea1a228cSschwartz #pragma ident "%Z%%M% %I% %E% SMI" 31*ea1a228cSschwartz 32*ea1a228cSschwartz /* 33*ea1a228cSschwartz * "Virtual register" definitions for the bit error performance counters. 34*ea1a228cSschwartz * 35*ea1a228cSschwartz * The N2 PIU presents two bit error counters. Bit 63 on the first counter 36*ea1a228cSschwartz * serves as an enable for all bit error counters. Bit 62 serves as a clear 37*ea1a228cSschwartz * for all the bit error counters. 38*ea1a228cSschwartz * 39*ea1a228cSschwartz * Busstat doesn't play well with a register that has counters, enable and 40*ea1a228cSschwartz * clear, so this module presents to the rest of the driver and to busstat a 41*ea1a228cSschwartz * new layered set of register interfaces. 42*ea1a228cSschwartz * 43*ea1a228cSschwartz * These are: 44*ea1a228cSschwartz * SW_N2PIU_BITERR_CNT1_DATA Biterr counter 1 data (readonly) 45*ea1a228cSschwartz * Maps directly to HW biterr 46*ea1a228cSschwartz * counter 1. Returns data for 47*ea1a228cSschwartz * bad_dllps, bad_tlps, 48*ea1a228cSschwartz * phys_rcvr_errs 49*ea1a228cSschwartz * 50*ea1a228cSschwartz * SW_N2PIU_BITERR_CNT2_DATA Biterr counter 2 data (readonly) 51*ea1a228cSschwartz * Maps to HW biterr counter 2, but 52*ea1a228cSschwartz * offers evt select of individual 53*ea1a228cSschwartz * lanes 0-7 or all lanes together 54*ea1a228cSschwartz * 55*ea1a228cSschwartz * SW_N2PIU_BITERR_CLR Setting bit 62 here clears all biterr 56*ea1a228cSschwartz * counters (write-only) 57*ea1a228cSschwartz * 58*ea1a228cSschwartz * SW_N2PIU_BITERR_SEL Bit 63 is overall biterr enable. 59*ea1a228cSschwartz * Bits 0-3 are event select for counter 2 60*ea1a228cSschwartz * (read-write) 61*ea1a228cSschwartz * 62*ea1a228cSschwartz * Note: each is assigned an offset similar to the offset of real performance 63*ea1a228cSschwartz * counter registers. Offsets for these registers extend beyond the real reg 64*ea1a228cSschwartz * set. 65*ea1a228cSschwartz */ 66*ea1a228cSschwartz 67*ea1a228cSschwartz #ifdef __cplusplus 68*ea1a228cSschwartz extern "C" { 69*ea1a228cSschwartz #endif 70*ea1a228cSschwartz 71*ea1a228cSschwartz #include <sys/sunddi.h> 72*ea1a228cSschwartz 73*ea1a228cSschwartz /* SW abstractions for the BITERR counters. */ 74*ea1a228cSschwartz 75*ea1a228cSschwartz /* Select register. Select enable for all biterr ctrs, and PIC3 events. */ 76*ea1a228cSschwartz #define SW_N2PIU_BITERR_SEL HVIO_N2PIU_PERFREG_NUM_REGS 77*ea1a228cSschwartz 78*ea1a228cSschwartz /* Clear register. This zeros out all biterr ctrs. */ 79*ea1a228cSschwartz #define SW_N2PIU_BITERR_CLR (HVIO_N2PIU_PERFREG_NUM_REGS + 1) 80*ea1a228cSschwartz 81*ea1a228cSschwartz /* Biterr counter 1. Same as in the PRM. */ 82*ea1a228cSschwartz #define SW_N2PIU_BITERR_CNT1_DATA (HVIO_N2PIU_PERFREG_NUM_REGS + 2) 83*ea1a228cSschwartz 84*ea1a228cSschwartz /* 85*ea1a228cSschwartz * Biterr counter 2. Reports errors for all lanes, or for any individual lane. 86*ea1a228cSschwartz * Select what to report with the SELect register above. Enabled only if the 87*ea1a228cSschwartz * enable for all biterr counters is enabled. 88*ea1a228cSschwartz */ 89*ea1a228cSschwartz #define SW_N2PIU_BITERR_CNT2_DATA (HVIO_N2PIU_PERFREG_NUM_REGS + 3) 90*ea1a228cSschwartz 91*ea1a228cSschwartz /* Biterr counter abstraction functions. */ 92*ea1a228cSschwartz extern int n2piupc_biterr_attach(void **); 93*ea1a228cSschwartz extern void n2piupc_biterr_detach(void *); 94*ea1a228cSschwartz extern int n2piupc_biterr_write(n2piupc_t *n2piupc_p, int regid, uint64_t data); 95*ea1a228cSschwartz extern int n2piupc_biterr_read(n2piupc_t *n2piupc_p, int regid, uint64_t *data); 96*ea1a228cSschwartz 97*ea1a228cSschwartz #ifdef __cplusplus 98*ea1a228cSschwartz } 99*ea1a228cSschwartz #endif 100*ea1a228cSschwartz 101*ea1a228cSschwartz #endif /* _N2PIUPC_BITERR_H */ 102