1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1991-2002 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_REGS_H 28 #define _SYS_PCI_REGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Offsets of registers in the interrupt block: 38 */ 39 40 #define COMMON_IB_UPA0_INTR_MAP_REG_OFFSET 0x6000 41 #define COMMON_IB_UPA1_INTR_MAP_REG_OFFSET 0x8000 42 #define COMMON_IB_SLOT_INTR_STATE_DIAG_REG 0xA800 43 #define COMMON_IB_OBIO_INTR_STATE_DIAG_REG 0xA808 44 #define COMMON_IB_SLOT_CLEAR_INTR_REG_OFFSET 0x1400 45 #define COMMON_IB_INTR_RETRY_TIMER_OFFSET 0x1A00 46 47 /* 48 * Offsets of registers in the ECC block: 49 */ 50 #define COMMON_ECC_CSR_OFFSET 0x20 51 #define COMMON_UE_AFSR_OFFSET 0x30 52 #define COMMON_UE_AFAR_OFFSET 0x38 53 #define COMMON_CE_AFSR_OFFSET 0x40 54 #define COMMON_CE_AFAR_OFFSET 0x48 55 56 /* 57 * Offsets of registers in the iommu block: 58 */ 59 #define COMMON_IOMMU_CTRL_REG_OFFSET 0x00000200 60 #define COMMON_IOMMU_TSB_BASE_ADDR_REG_OFFSET 0x00000208 61 #define COMMON_IOMMU_FLUSH_PAGE_REG_OFFSET 0x00000210 62 63 #define COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET 0x0000A580 64 #define COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET 0x0000A600 65 66 /* 67 * (psycho and schizo) control register bit definitions: 68 */ 69 #define COMMON_CB_CONTROL_STATUS_IGN 0x0007c00000000000ull 70 #define COMMON_CB_CONTROL_STATUS_IGN_SHIFT 46 71 #define COMMON_CB_CONTROL_STATUS_APCKEN 0x0000000000000008ull 72 #define COMMON_CB_CONTROL_STATUS_APERR 0x0000000000000004ull 73 #define COMMON_CB_CONTROL_STATUS_IAP 0x0000000000000002ull 74 75 /* 76 * (psycho and schizo) interrupt mapping register bit definitions: 77 */ 78 #define COMMON_INTR_MAP_REG_VALID 0x0000000080000000ull 79 #define COMMON_INTR_MAP_REG_TID 0x000000007C000000ull 80 #define COMMON_INTR_MAP_REG_IGN 0x00000000000007C0ull 81 #define COMMON_INTR_MAP_REG_INO 0x000000000000003full 82 #define COMMON_INTR_MAP_REG_TID_SHIFT 26 83 #define COMMON_INTR_MAP_REG_IGN_SHIFT 6 84 85 /* 86 * psycho clear interrupt register bit definitions: 87 */ 88 #define COMMON_CLEAR_INTR_REG_MASK 0x0000000000000003ull 89 #define COMMON_CLEAR_INTR_REG_IDLE 0x0000000000000000ull 90 #define COMMON_CLEAR_INTR_REG_RECEIVED 0x0000000000000001ull 91 #define COMMON_CLEAR_INTR_REG_RSVD 0x0000000000000002ull 92 #define COMMON_CLEAR_INTR_REG_PENDING 0x0000000000000003ull 93 94 /* 95 * psycho and schizo ECC control register bit definitions: 96 */ 97 #define COMMON_ECC_CTRL_ECC_EN 0x8000000000000000ull 98 #define COMMON_ECC_CTRL_UE_INTEN 0x4000000000000000ull 99 #define COMMON_ECC_CTRL_CE_INTEN 0x2000000000000000ull 100 101 /* 102 * sabre ECC UE AFSR bit definitions: 103 */ 104 #define SABRE_UE_AFSR_SDTE_SHIFT 57 105 #define SABRE_UE_AFSR_PDTE_SHIFT 56 106 #define SABRE_UE_ARSR_DTE_MASK 0x0000000000000003ull 107 #define SABRE_UE_AFSR_E_SDTE 0x2 108 #define SABRE_UE_AFSR_E_PDTE 0x1 109 110 /* 111 * psycho and schizo ECC UE AFSR bit definitions: 112 */ 113 #define COMMON_ECC_UE_AFSR_PE_SHIFT 61 114 #define COMMON_ECC_UE_AFSR_SE_SHIFT 58 115 #define COMMON_ECC_UE_AFSR_E_MASK 0x0000000000000007ull 116 #define COMMON_ECC_UE_AFSR_E_PIO 0x0000000000000004ull 117 #define COMMON_ECC_UE_AFSR_E_DRD 0x0000000000000002ull 118 #define COMMON_ECC_UE_AFSR_E_DWR 0x0000000000000001ull 119 120 /* 121 * psycho and schizo ECC CE AFSR bit definitions: 122 */ 123 #define COMMON_ECC_CE_AFSR_PE_SHIFT 61 124 #define COMMON_ECC_CE_AFSR_SE_SHIFT 58 125 #define COMMON_ECC_CE_AFSR_E_MASK 0x0000000000000007ull 126 #define COMMON_ECC_CE_AFSR_E_PIO 0x0000000000000004ull 127 #define COMMON_ECC_CE_AFSR_E_DRD 0x0000000000000002ull 128 #define COMMON_ECC_CE_AFSR_E_DWR 0x0000000000000001ull 129 130 /* 131 * psycho and schizo pci control register bits: 132 */ 133 #define COMMON_PCI_CTRL_SBH_ERR 0x0000000800000000ull 134 #define COMMON_PCI_CTRL_SERR 0x0000000400000000ull 135 #define COMMON_PCI_CTRL_SPEED 0x0000000200000000ull 136 137 /* 138 * psycho and schizo PCI diagnostic register bit definitions: 139 */ 140 #define COMMON_PCI_DIAG_DIS_RETRY 0x0000000000000040ull 141 #define COMMON_PCI_DIAG_DIS_INTSYNC 0x0000000000000020ull 142 143 /* 144 * psycho and schizo IOMMU control register bit definitions: 145 */ 146 #define COMMON_IOMMU_CTRL_ENABLE 0x0000000000000001ull 147 #define COMMON_IOMMU_CTRL_DIAG_ENABLE 0x0000000000000002ull 148 #define COMMON_IOMMU_CTRL_TSB_SZ_SHIFT 16 149 #define COMMON_IOMMU_CTRL_TBW_SZ_SHIFT 2 150 #define COMMON_IOMMU_CTRL_LCK_ENABLE 0x0000000000800000ull 151 152 /* 153 * psycho and schizo streaming cache control register bit definitions: 154 */ 155 #define COMMON_SC_CTRL_ENABLE 0x0000000000000001ull 156 #define COMMON_SC_CTRL_DIAG_ENABLE 0x0000000000000002ull 157 #define COMMON_SC_CTRL_RR__DISABLE 0x0000000000000004ull 158 #define COMMON_SC_CTRL_LRU_LE 0x0000000000000008ull 159 160 /* 161 * offsets of PCI address spaces from base address: 162 */ 163 #define PCI_CONFIG 0x001000000ull 164 #define PCI_A_IO 0x002000000ull 165 #define PCI_B_IO 0x002010000ull 166 #define PCI_A_MEMORY 0x100000000ull 167 #define PCI_B_MEMORY 0x180000000ull 168 #define PCI_IO_SIZE 0x000010000ull 169 #define PCI_MEM_SIZE 0x080000000ull 170 171 #ifdef __cplusplus 172 } 173 #endif 174 175 #endif /* _SYS_PCI_REGS_H */ 176